sim/mips/ChangeLog

   1 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
   2
   3         * vr.igen: New file.
   4         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
   5         * mips.igen: Define vr4100 model. Include vr.igen.
   6
   7 start-sanitize-r5900
   8 Tue Jul 14 16:10:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
   9
  10         * r5900.igen (r59fp_overflow): Replace argument ANS with argument
  11         SIGN_P.
  12         (r59fp_zero): Ditto.
  13         (r59fp_store): Update calls.
  14         (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
  15
  16 end-sanitize-r5900
  17 start-sanitize-branchbug4011
  18 Mon Jun 29 09:31:27 1998  Gavin Koch  <gavin@cygnus.com>
  19
  20         * interp.c (OPTION_BRANCH_BUG_4011): Add.
  21         (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
  22         (mips_options): Define the option.
  23         * mips.igen (check_4011_branch_bug): New.
  24         (mark_4011_branch_bug): New.
  25         (all branch insn): Call mark_branch_bug, and check_branch_bug.
  26         * sim-main.h (branchbug4011_option, branchbug4011_last_target,
  27         branchbug4011_last_cia, BRANCHBUG4011_OPTION,
  28         BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
  29         check_branch_bug, mark_branch_bug): Define.
  30
  31 end-sanitize-branchbug4011
  32 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
  33
  34         * mips.igen (check_mf_hilo): Correct check.
  35
  36 start-sanitize-r5900
  37 Fri Jun 19 14:44:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  38
  39         * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
  40         COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
  41         purpose registers, add 8 COP0 break-point registers, add 64 COP0
  42         performance registers.
  43
  44         * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
  45         MFP* instructions.  Just transfer value to/from corresponding
  46         register.
  47
  48         * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
  49         status is always true.
  50         (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
  51         (EI, DI): Set/clear Status-EIE bit.
  52
  53 end-sanitize-r5900
  54 start-sanitize-sky
  55 Fri Jun 19 14:44:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  56
  57         * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
  58         r5900.igen.
  59
  60 end-sanitize-sky
  61 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  62
  63 start-sanitize-sky
  64         * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
  65         ASSERT not assert.
  66         * sky-gdb.c: Include "sim-assert.h".
  67
  68 end-sanitize-sky
  69         * sim-main.h (interrupt_event): Add prototype.
  70
  71 start-sanitize-tx3904
  72         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
  73         register_ptr, register_value.
  74         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
  75
  76 end-sanitize-tx3904
  77         * sim-main.h (tracefh): Make extern.
  78
  79 start-sanitize-tx3904
  80 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
  81
  82         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
  83         Reduce unnecessarily high timer event frequency.
  84         * dv-tx3904cpu.c: Ditto for interrupt event.
  85
  86 end-sanitize-tx3904
  87 start-sanitize-sky
  88 Tue Jun 16 14:12:09 1998  Frank Ch. Eigler  <fche@cygnus.com>
  89
  90         * interp.c (decode_coproc): Removed COP2 branches.
  91         * r5900.igen: Moved COP2 branch instructions here.
  92         * mips.igen: Restricted COPz == COP2 bit pattern to
  93         exclude COP2 branches.
  94
  95 end-sanitize-sky
  96 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
  97
  98         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
  99         to allay warnings.
 100         (interrupt_event): Made non-static.
 101 start-sanitize-tx3904
 102
 103         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 104         interchange of configuration values for external vs. internal
 105         clock dividers.
 106 end-sanitize-tx3904
 107
 108 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 109
 110         * mips.igen (BREAK): Moved code to here for
 111         simulator-reserved break instructions.
 112         * gencode.c (build_instruction): Ditto.
 113         * interp.c (signal_exception): Code moved from here.  Non-
 114         reserved instructions now use exception vector, rather
 115         than halting sim.
 116         * sim-main.h: Moved magic constants to here.
 117
 118 start-sanitize-tx3904
 119 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 120
 121         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 122         register upon non-zero interrupt event level, clear upon zero
 123         event value.
 124         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 125         by passing zero event value.
 126         (*_io_{read,write}_buffer): Endianness fixes.
 127         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 128         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 129
 130         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 131         serial I/O and timer module at base address 0xFFFF0000.
 132
 133 end-sanitize-tx3904
 134 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 135
 136         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 137         and BigEndianCPU.
 138
 139 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 140
 141         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 142         parts.
 143         * configure: Update.
 144
 145 start-sanitize-tx3904
 146 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 147
 148         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 149         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 150         * configure.in: Include tx3904tmr in hw_device list.
 151         * configure: Rebuilt.
 152         * interp.c (sim_open): Instantiate three timer instances.
 153         Fix address typo of tx3904irc instance.
 154
 155 end-sanitize-tx3904
 156 start-sanitize-r5900
 157 Thu Jun  4 16:47:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 158
 159         * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
 160         Select corresponding check_mt_hilo function.
 161         (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
 162         Ditto.
 163
 164         * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
 165         as r5900 specific.
 166
 167 end-sanitize-r5900
 168 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 169
 170         * interp.c (signal_exception): SystemCall exception now uses
 171         the exception vector.
 172
 173 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 174
 175         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 176         to allay warnings.
 177
 178 start-sanitize-r5900
 179 Mon Jun  1 10:28:25 1998  Jeffrey A Law  (law@cygnus.com)
 180
 181         * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
 182         (sqrt.s): Likewise.
 183
 184 end-sanitize-r5900
 185 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 186
 187         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 188
 189 start-sanitize-tx3904
 190 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 191
 192         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 193
 194         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 195         sim-main.h. Declare a struct hw_descriptor instead of struct
 196         hw_device_descriptor.
 197
 198 end-sanitize-tx3904
 199 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 200
 201         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 202         right bits and then re-align left hand bytes to correct byte
 203         lanes.  Fix incorrect computation in do_store_left when loading
 204         bytes from second word.
 205
 206 start-sanitize-tx3904
 207 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 208
 209         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 210         * interp.c (sim_open): Only create a device tree when HW is
 211         enabled.
 212
 213         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 214         * interp.c (signal_exception): Ditto.
 215
 216 end-sanitize-tx3904
 217 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 218
 219         * gencode.c: Mark BEGEZALL as LIKELY.
 220
 221 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 222
 223         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 224         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 225
 226 start-sanitize-r5900
 227 Thu May 21 17:15:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 228
 229         * interp.c (sim_fetch_register): Convert internal r5900 regs to
 230         target byte order
 231
 232 end-sanitize-r5900
 233 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 234
 235         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 236         modules.  Recognize TX39 target with "mips*tx39" pattern.
 237         * configure: Rebuilt.
 238         * sim-main.h (*): Added many macros defining bits in
 239         TX39 control registers.
 240         (SignalInterrupt): Send actual PC instead of NULL.
 241         (SignalNMIReset): New exception type.
 242         * interp.c (board): New variable for future use to identify
 243         a particular board being simulated.
 244         (mips_option_handler,mips_options): Added "--board" option.
 245         (interrupt_event): Send actual PC.
 246         (sim_open): Make memory layout conditional on board setting.
 247         (signal_exception): Initial implementation of hardware interrupt
 248         handling.  Accept another break instruction variant for simulator
 249         exit.
 250         (decode_coproc): Implement RFE instruction for TX39.
 251         (mips.igen): Decode RFE instruction as such.
 252 start-sanitize-tx3904
 253         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 254         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 255         bbegin to implement memory map.
 256         * dv-tx3904cpu.c: New file.
 257         * dv-tx3904irc.c: New file.
 258 end-sanitize-tx3904
 259
 260 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 261
 262         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 263
 264 start-sanitize-r5900
 265 Wed May 13 14:27:53 1998  Gavin Koch  <gavin@cygnus.com>
 266
 267         * r5900.igen: Replace the calls and the definition of the
 268         function check_op_hilo_hi1lo1 with the pair
 269         check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
 270
 271 end-sanitize-r5900
 272 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 273
 274         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 275         with calls to check_div_hilo.
 276
 277 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 278
 279         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 280         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 281         Add special r3900 version of do_mult_hilo.
 282         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 283         with calls to check_mult_hilo.
 284         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 285         with calls to check_div_hilo.
 286
 287 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 288
 289         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 290         Document a replacement.
 291
 292 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 293
 294         * interp.c (sim_monitor): Make mon_printf work.
 295
 296 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 297
 298         * sim-main.h (INSN_NAME): New arg `cpu'.
 299
 300 start-sanitize-sky
 301 Thu Apr 30 18:51:26 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 302
 303         * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
 304         r59fp_mula.
 305
 306 end-sanitize-sky
 307 start-sanitize-r5900
 308 Wed Apr 29 22:54:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 309
 310         * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
 311         * r5900.igen (r59fp_overflow): Use.
 312
 313         * r5900.igen (r59fp_op3): Rename to
 314         (r59fp_mula): This, delete opm argument.
 315         (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
 316         (r59fp_mula): Overflowing product propogates through to result.
 317         (r59fp_mula): ACC to the MAX propogates to result.
 318         (r59fp_mula): Underflow during multiply only sets SU.
 319
 320 end-sanitize-r5900
 321 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 322
 323         * configure: Regenerated to track ../common/aclocal.m4 changes.
 324
 325 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 326
 327         * configure: Regenerated to track ../common/aclocal.m4 changes.
 328         * config.in: Ditto.
 329
 330 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 331
 332         * acconfig.h: New file.
 333         * configure.in: Reverted change of Apr 24; use sinclude again.
 334
 335 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 336
 337         * configure: Regenerated to track ../common/aclocal.m4 changes.
 338         * config.in: Ditto.
 339
 340 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 341
 342         * configure.in: Don't call sinclude.
 343
 344 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 345
 346         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 347
 348 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 349
 350         * mips.igen (ERET): Implement.
 351
 352         * interp.c (decode_coproc): Return sign-extended EPC.
 353
 354         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 355
 356         * interp.c (signal_exception): Do not ignore Trap.
 357         (signal_exception): On TRAP, restart at exception address.
 358         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 359         (signal_exception): Update.
 360         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 361         so that TRAP instructions are caught.
 362
 363 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 364
 365         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 366         contains HI/LO access history.
 367         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 368         (HIACCESS, LOACCESS): Delete, replace with
 369         (HIHISTORY, LOHISTORY): New macros.
 370         (start-sanitize-r5900):
 371         (struct sim_5900_cpu): Make hi1access, lo1access of type
 372         hilo_access.
 373         (HI1ACCESS, LO1ACCESS): Delete, replace with
 374         (HI1HISTORY, LO1HISTORY): New macros.
 375         (end-sanitize-r5900):
 376         (CHECKHILO): Delete all, moved to mips.igen
 377
 378         * gencode.c (build_instruction): Do not generate checks for
 379         correct HI/LO register usage.
 380
 381         * interp.c (old_engine_run): Delete checks for correct HI/LO
 382         register usage.
 383
 384         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 385         check_mf_cycles): New functions.
 386         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 387         do_divu, domultx, do_mult, do_multu): Use.
 388
 389         * tx.igen ("madd", "maddu"): Use.
 390         (start-sanitize-r5900):
 391
 392         r5900.igen: Update all HI/LO checks.
 393         ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
 394         "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
 395         ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
 396         "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
 397         "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
 398         Check HI/LO op.
 399         (end-sanitize-r5900):
 400
 401 start-sanitize-sky
 402 Mon Apr 20 18:39:47 1998  Frank Ch. Eigler  <fche@cygnus.com>
 403
 404         * interp.c (decode_coproc): Correct CMFC2/QMTC2
 405         GPR access.
 406
 407         * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
 408         instead of a single 128-bit access.
 409
 410 end-sanitize-sky
 411 start-sanitize-sky
 412 Fri Apr 17 14:50:39 1998  Frank Ch. Eigler  <fche@cygnus.com>
 413
 414         * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
 415         * interp.c (cop_[ls]q): Fixes corresponding to above.
 416
 417 end-sanitize-sky
 418 start-sanitize-sky
 419 Thu Apr 16 15:24:14 1998  Frank Ch. Eigler  <fche@cygnus.com>
 420
 421         * interp.c (decode_coproc): Adapt COP2 micro interlock to
 422         clarified specs.  Reset "M" bit; exit also on "E" bit.
 423
 424 end-sanitize-sky
 425 start-sanitize-r5900
 426 Thu Apr 16 10:40:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 427
 428         * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
 429         * mips.igen (CFC1, CTC1): R5900 des not use generic version.
 430
 431         * r5900.igen (r59fp_unpack): New function.
 432         (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
 433         RSQRT.S, SQRT.S): Use.
 434         (r59fp_zero): New function.
 435         (r59fp_overflow): Generate r5900 specific overflow value.
 436         (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
 437         to zero.
 438         (CVT.S.W, CVT.W.S): Exchange implementations.
 439
 440         * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
 441
 442 end-sanitize-r5900
 443 start-sanitize-tx19
 444 Thu Apr 16 09:14:44 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 445
 446         * configure.in (tx19, sim_use_gen): Switch to igen.
 447         * configure: Re-build.
 448
 449 end-sanitize-tx19
 450 start-sanitize-sky
 451 Wed Apr 15 12:41:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 452
 453         * interp.c (decode_coproc): Make COP2 branch code compile after
 454         igen signature changes.
 455
 456 end-sanitize-sky
 457 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 458
 459         * mips.igen (DSRAV): Use function do_dsrav.
 460         (SRAV): Use new function do_srav.
 461
 462         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 463         (B): Sign extend 11 bit immediate.
 464         (EXT-B*): Shift 16 bit immediate left by 1.
 465         (ADDIU*): Don't sign extend immediate value.
 466
 467 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 468
 469         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 470
 471 start-sanitize-tx19
 472         * mips.igen (mtc0): Valid tx19 instruction.
 473
 474 end-sanitize-tx19
 475         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 476         functions.
 477
 478         * mips.igen (delayslot32, nullify_next_insn): New functions.
 479         (m16.igen): Always include.
 480         (do_*): Add more tracing.
 481
 482         * m16.igen (delayslot16): Add NIA argument, could be called by a
 483         32 bit MIPS16 instruction.
 484
 485         * interp.c (ifetch16): Move function from here.
 486         * sim-main.c (ifetch16): To here.
 487
 488         * sim-main.c (ifetch16, ifetch32): Update to match current
 489         implementations of LH, LW.
 490         (signal_exception): Don't print out incorrect hex value of illegal
 491         instruction.
 492
 493 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 494
 495         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 496         instruction.
 497
 498         * m16.igen: Implement MIPS16 instructions.
 499
 500         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 501         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 502         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 503         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 504         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 505         bodies of corresponding code from 32 bit insn to these.  Also used
 506         by MIPS16 versions of functions.
 507
 508         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 509         (IMEM16): Drop NR argument from macro.
 510
 511 start-sanitize-sky
 512 Mon Apr 13 16:28:52 1998  Frank Ch. Eigler  <fche@cygnus.com>
 513
 514         * interp.c (decode_coproc): Add proper 1000000 bit-string at top
 515         of VU lower instruction.
 516
 517 end-sanitize-sky
 518 start-sanitize-sky
 519 Thu Apr  9 16:38:23 1998  Frank Ch. Eigler  <fche@cygnus.com>
 520
 521         * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
 522         instead of QUADWORD.
 523
 524         * sim-main.h: Removed attempt at allowing 128-bit access.
 525
 526 end-sanitize-sky
 527 start-sanitize-sky
 528 Wed Apr  8 18:12:13 1998  Frank Ch. Eigler  <fche@cygnus.com>
 529
 530         * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
 531
 532         * interp.c (decode_coproc): Refer to VU CIA as a "special"
 533         register, not as a "misc" register.  Aha.  Add activity
 534         assertions after VCALLMS* instructions.
 535
 536 end-sanitize-sky
 537 start-sanitize-sky
 538 Tue Apr  7 18:32:49 1998  Frank Ch. Eigler  <fche@cygnus.com>
 539
 540         * interp.c (decode_coproc): Do not apply superfluous E (end) flag
 541         to upper code of generated VU instruction.
 542
 543 end-sanitize-sky
 544 start-sanitize-sky
 545 Mon Apr  6 19:55:56 1998  Frank Ch. Eigler  <fche@cygnus.com>
 546
 547         * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
 548
 549         * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
 550         for TARGET_SKY.
 551
 552         * r5900.igen (SQC2): Thinko.
 553
 554 end-sanitize-sky
 555 start-sanitize-sky
 556 Sun Apr  5 12:05:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 557
 558         * interp.c (*): Adapt code to merged VU device & state structs.
 559         (decode_coproc): Execute COP2 each macroinstruction without
 560         pipelining, by stepping VU to completion state.  Adapted to
 561         read_vu_*_reg style of register access.
 562
 563         * mips.igen ([SL]QC2): Removed these COP2 instructions.
 564
 565         * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
 566
 567         * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
 568
 569 end-sanitize-sky
 570 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 571
 572         * Makefile.in (SIM_OBJS): Add sim-main.o.
 573
 574         * sim-main.h (address_translation, load_memory, store_memory,
 575         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 576         as INLINE_SIM_MAIN.
 577         (pr_addr, pr_uword64): Declare.
 578         (sim-main.c): Include when H_REVEALS_MODULE_P.
 579
 580         * interp.c (address_translation, load_memory, store_memory,
 581         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 582         from here.
 583         * sim-main.c: To here. Fix compilation problems.
 584
 585         * configure.in: Enable inlining.
 586         * configure: Re-config.
 587
 588 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 589
 590         * configure: Regenerated to track ../common/aclocal.m4 changes.
 591
 592 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 593
 594         * mips.igen: Include tx.igen.
 595         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 596         * tx.igen: New file, contains MADD and MADDU.
 597
 598         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 599         the hardwired constant `7'.
 600         (store_memory): Ditto.
 601         (LOADDRMASK): Move definition to sim-main.h.
 602
 603         mips.igen (MTC0): Enable for r3900.
 604         (ADDU): Add trace.
 605
 606         mips.igen (do_load_byte): Delete.
 607         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 608         do_store_right): New functions.
 609         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 610
 611         configure.in: Let the tx39 use igen again.
 612         configure: Update.
 613
 614 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 615
 616         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 617         not an address sized quantity.  Return zero for cache sizes.
 618
 619 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 620
 621         * mips.igen (r3900): r3900 does not support 64 bit integer
 622         operations.
 623
 624 start-sanitize-sky
 625 Wed Apr 1 08:20:31 1998  Frank Ch. Eigler  <fche@cygnus.com>
 626
 627         * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
 628
 629 end-sanitize-sky
 630 start-sanitize-sky
 631 Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>
 632
 633         * interp.c (decode_coproc): Continuing COP2 work.
 634         (cop_[ls]q): Make sky-target-only.
 635
 636         * sim-main.h (COP_[LS]Q): Make sky-target-only.
 637 end-sanitize-sky
 638 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 639
 640         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 641         than igen one.
 642         * configure : Rebuild.
 643
 644 start-sanitize-sky
 645 Sun Mar 29 17:50:11       Frank Ch. Eigler  <fche@cygnus.com>
 646
 647         * interp.c (decode_coproc): Added a missing TARGET_SKY check
 648         around COP2 implementation skeleton.
 649
 650 end-sanitize-sky
 651 start-sanitize-sky
 652 Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>
 653
 654         * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
 655
 656         * interp.c (sim_{load,store}_register): Use new vu[01]_device
 657         static to access VU registers.
 658         (decode_coproc): Added skeleton of sky COP2 (VU) instruction
 659         decoding.  Work in progress.
 660
 661         * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
 662         overlapping/redundant bit pattern.
 663         (LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
 664         progress.
 665
 666         * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
 667         status register.
 668
 669         * interp.c (cop_lq, cop_sq): New functions for future 128-bit
 670         access to coprocessor registers.
 671
 672         * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
 673 end-sanitize-sky
 674 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 675
 676         * configure: Regenerated to track ../common/aclocal.m4 changes.
 677
 678 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 679
 680         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 681
 682 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 683
 684         * configure: Regenerated to track ../common/aclocal.m4 changes.
 685         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 686
 687 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 688
 689         * configure: Regenerated to track ../common/aclocal.m4 changes.
 690
 691 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 692
 693         * interp.c (Max, Min): Comment out functions. Not yet used.
 694
 695 start-sanitize-vr4320
 696 Wed Mar 25 10:04:13 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 697
 698         * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
 699
 700 end-sanitize-vr4320
 701 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 702
 703         * configure: Regenerated to track ../common/aclocal.m4 changes.
 704
 705 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 706
 707         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 708         configurable settings for stand-alone simulator.
 709
 710 start-sanitize-sky
 711         * configure.in: Added --with-sim-gpu2 option to specify path of
 712         sky GPU2 library.  Triggers -DSKY_GPU2 for sky-gpuif.c, and
 713         links/compiles stand-alone simulator with this library.
 714
 715         * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
 716 end-sanitize-sky
 717         * configure.in: Added X11 search, just in case.
 718
 719         * configure: Regenerated.
 720
 721 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 722
 723         * interp.c (sim_write, sim_read, load_memory, store_memory):
 724         Replace sim_core_*_map with read_map, write_map, exec_map resp.
 725
 726 start-sanitize-vr4320
 727 Tue Mar 10 10:32:22 1998  Gavin Koch  <gavin@cygnus.com>
 728
 729         * vr4320.igen (clz,dclz) : Added.
 730         (dmac): Replaced 99, with LO.
 731
 732 end-sanitize-vr4320
 733 start-sanitize-vr5400
 734 Fri Mar  6 08:30:58 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 735
 736         * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
 737
 738 end-sanitize-vr5400
 739 start-sanitize-vr4320
 740 Tue Mar  3 11:56:29 1998  Gavin Koch  <gavin@cygnus.com>
 741
 742         * vr4320.igen: New file.
 743         * Makefile.in (vr4320.igen) : Added.
 744         * configure.in (mips64vr4320-*-*): Added.
 745         * configure : Rebuilt.
 746         * mips.igen : Correct the bfd-names in the mips-ISA model entries.
 747         Add the vr4320 model entry and mark the vr4320 insn as necessary.
 748
 749 end-sanitize-vr4320
 750 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 751
 752         * sim-main.h (GETFCC): Return an unsigned value.
 753
 754 start-sanitize-r5900
 755         * r5900.igen: Use an unsigned array index variable `i'.
 756         (QFSRV): Ditto for variable bytes.
 757
 758 end-sanitize-r5900
 759 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 760
 761         * mips.igen (DIV): Fix check for -1 / MIN_INT.
 762         (DADD): Result destination is RD not RT.
 763
 764 start-sanitize-r5900
 765         * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
 766         (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
 767         divide.
 768
 769 end-sanitize-r5900
 770 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 771
 772         * sim-main.h (HIACCESS, LOACCESS): Always define.
 773
 774         * mdmx.igen (Maxi, Mini): Rename Max, Min.
 775
 776         * interp.c (sim_info): Delete.
 777
 778 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
 779
 780         * interp.c (DECLARE_OPTION_HANDLER): Use it.
 781         (mips_option_handler): New argument `cpu'.
 782         (sim_open): Update call to sim_add_option_table.
 783
 784 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 785
 786         * mips.igen (CxC1): Add tracing.
 787
 788 start-sanitize-r5900
 789 Wed Feb 25 13:59:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 790
 791         * r5900.igen (StoreFP): Delete.
 792         (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
 793         New functions.
 794         (rsqrt.s, sqrt.s): Implement.
 795         (r59cond): New function.
 796         (C.COND.S): Call r59cond in assembler line.
 797         (cvt.w.s, cvt.s.w): Implement.
 798
 799         * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
 800         instruction set.
 801
 802         * sim-main.h: Define an enum of r5900 FCSR bit fields.
 803
 804 end-sanitize-r5900
 805 start-sanitize-r5900
 806 Tue Feb 24 14:44:18 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 807
 808         * r5900.igen: Add tracing to all p* instructions.
 809
 810 Tue Feb 24 02:47:33 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 811
 812         * interp.c (sim_store_register, sim_fetch_register): Pull swifty
 813         to get gdb talking to re-aranged sim_cpu register structure.
 814
 815 end-sanitize-r5900
 816 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 817
 818         * sim-main.h (Max, Min): Declare.
 819
 820         * interp.c (Max, Min): New functions.
 821
 822         * mips.igen (BC1): Add tracing.
 823
 824 start-sanitize-vr5400
 825 Fri Feb 20 16:27:17 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 826
 827         * mdmx.igen: Tag all functions as requiring either with mdmx or
 828         vr5400 processor.
 829
 830 end-sanitize-vr5400
 831 start-sanitize-r5900
 832 Fri Feb 20 15:55:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 833
 834         * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
 835         to 32.
 836         (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
 837
 838         * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
 839
 840         * r5900.igen: Rewrite.
 841
 842         * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
 843         struct.
 844         (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
 845         Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
 846
 847 end-sanitize-r5900
 848 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
 849
 850         * interp.c Added memory map for stack in vr4100
 851
 852 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
 853
 854         * interp.c (load_memory): Add missing "break"'s.
 855
 856 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 857
 858         * interp.c (sim_store_register, sim_fetch_register): Pass in
 859         length parameter.  Return -1.
 860
 861 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
 862
 863         * interp.c: Added hardware init hook, fixed warnings.
 864
 865 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 866
 867         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
 868
 869 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 870
 871         * interp.c (ifetch16): New function.
 872
 873         * sim-main.h (IMEM32): Rename IMEM.
 874         (IMEM16_IMMED): Define.
 875         (IMEM16): Define.
 876         (DELAY_SLOT): Update.
 877
 878         * m16run.c (sim_engine_run): New file.
 879
 880         * m16.igen: All instructions except LB.
 881         (LB): Call do_load_byte.
 882         * mips.igen (do_load_byte): New function.
 883         (LB): Call do_load_byte.
 884
 885         * mips.igen: Move spec for insn bit size and high bit from here.
 886         * Makefile.in (tmp-igen, tmp-m16): To here.
 887
 888         * m16.dc: New file, decode mips16 instructions.
 889
 890         * Makefile.in (SIM_NO_ALL): Define.
 891         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
 892
 893 start-sanitize-tx19
 894         * m16.igen: Mark all mips16 insns as being part of the tx19 insn
 895         set.
 896
 897 end-sanitize-tx19
 898 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 899
 900         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
 901         point unit to 32 bit registers.
 902         * configure: Re-generate.
 903
 904 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 905
 906         * configure.in (sim_use_gen): Make IGEN the default simulator
 907         generator for generic 32 and 64 bit mips targets.
 908         * configure: Re-generate.
 909
 910 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 911
 912         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
 913         bitsize.
 914
 915         * interp.c (sim_fetch_register, sim_store_register): Read/write
 916         FGR from correct location.
 917         (sim_open): Set size of FGR's according to
 918         WITH_TARGET_FLOATING_POINT_BITSIZE.
 919
 920         * sim-main.h (FGR): Store floating point registers in a separate
 921         array.
 922
 923 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 924
 925         * configure: Regenerated to track ../common/aclocal.m4 changes.
 926
 927 start-sanitize-vr5400
 928         * mdmx.igen: Mark all instructions as 64bit/fp specific.
 929
 930 end-sanitize-vr5400
 931 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 932
 933         * interp.c (ColdReset): Call PENDING_INVALIDATE.
 934
 935         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
 936
 937         * interp.c (pending_tick): New function.  Deliver pending writes.
 938
 939         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
 940         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
 941         it can handle mixed sized quantites and single bits.
 942
 943 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 944
 945         * interp.c (oengine.h): Do not include when building with IGEN.
 946         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
 947         (sim_info): Ditto for PROCESSOR_64BIT.
 948         (sim_monitor): Replace ut_reg with unsigned_word.
 949         (*): Ditto for t_reg.
 950         (LOADDRMASK): Define.
 951         (sim_open): Remove defunct check that host FP is IEEE compliant,
 952         using software to emulate floating point.
 953         (value_fpr, ...): Always compile, was conditional on HASFPU.
 954
 955 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 956
 957         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
 958         size.
 959
 960         * interp.c (SD, CPU): Define.
 961         (mips_option_handler): Set flags in each CPU.
 962         (interrupt_event): Assume CPU 0 is the one being iterrupted.
 963         (sim_close): Do not clear STATE, deleted anyway.
 964         (sim_write, sim_read): Assume CPU zero's vm should be used for
 965         data transfers.
 966         (sim_create_inferior): Set the PC for all processors.
 967         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
 968         argument.
 969         (mips16_entry): Pass correct nr of args to store_word, load_word.
 970         (ColdReset): Cold reset all cpu's.
 971         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
 972         (sim_monitor, load_memory, store_memory, signal_exception): Use
 973         `CPU' instead of STATE_CPU.
 974
 975
 976         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
 977         SD or CPU_.
 978
 979         * sim-main.h (signal_exception): Add sim_cpu arg.
 980         (SignalException*): Pass both SD and CPU to signal_exception.
 981         * interp.c (signal_exception): Update.
 982
 983         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
 984         Ditto
 985         (sync_operation, prefetch, cache_op, store_memory, load_memory,
 986         address_translation): Ditto
 987         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
 988
 989 start-sanitize-vr5400
 990         * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
 991         `sd'.
 992         (ByteAlign): Use StoreFPR, pass args in correct order.
 993
 994 end-sanitize-vr5400
 995 start-sanitize-r5900
 996 Sun Feb  1 10:59:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 997
 998         * configure.in (sim_igen_filter): For r5900, configure as SMP.
 999
1000 end-sanitize-r5900
1001 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1002
1003         * configure: Regenerated to track ../common/aclocal.m4 changes.
1004
1005 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1006
1007 start-sanitize-r5900
1008         * configure.in (sim_igen_filter): For r5900, use igen.
1009         * configure: Re-generate.
1010
1011 end-sanitize-r5900
1012         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1013
1014         * mips.igen (model): Map processor names onto BFD name.
1015
1016         * sim-main.h (CPU_CIA): Delete.
1017         (SET_CIA, GET_CIA): Define
1018
1019 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1020
1021         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1022         regiser.
1023
1024         * configure.in (default_endian): Configure a big-endian simulator
1025         by default.
1026         * configure: Re-generate.
1027
1028 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1029
1030         * configure: Regenerated to track ../common/aclocal.m4 changes.
1031
1032 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1033
1034         * interp.c (sim_monitor): Handle Densan monitor outbyte
1035         and inbyte functions.
1036
1037 1997-12-29  Felix Lee  <flee@cygnus.com>
1038
1039         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1040
1041 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1042
1043         * Makefile.in (tmp-igen): Arrange for $zero to always be
1044         reset to zero after every instruction.
1045
1046 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1047
1048         * configure: Regenerated to track ../common/aclocal.m4 changes.
1049         * config.in: Ditto.
1050
1051 start-sanitize-vr5400
1052 Sat Dec 13 15:18:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1053
1054         * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1055         bit values.
1056
1057 end-sanitize-vr5400
1058 start-sanitize-vr5400
1059 Fri Dec 12 12:26:07 1997  Jeffrey A Law  (law@cygnus.com)
1060
1061         * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1062         vr5400 with the vr5000 as the default.
1063
1064 end-sanitize-vr5400
1065 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1066
1067         * mips.igen (MSUB): Fix to work like MADD.
1068         * gencode.c (MSUB): Similarly.
1069
1070 start-sanitize-vr5400
1071 Tue Dec  9 12:02:12 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1072
1073         * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1074         vr5400.
1075
1076 end-sanitize-vr5400
1077 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1078
1079         * configure: Regenerated to track ../common/aclocal.m4 changes.
1080
1081 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1082
1083         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1084
1085 start-sanitize-vr5400
1086         * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1087         (value_cc, store_cc): Implement.
1088
1089         * sim-main.h: Add 8*3*8 bit accumulator.
1090
1091         * vr5400.igen: Move mdmx instructins from here
1092         * mdmx.igen: To here - new file. Add/fix missing instructions.
1093         * mips.igen: Include mdmx.igen.
1094         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1095
1096 end-sanitize-vr5400
1097 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1098
1099         * sim-main.h (sim-fpu.h): Include.
1100
1101         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1102         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1103         using host independant sim_fpu module.
1104
1105 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1106
1107         * interp.c (signal_exception): Report internal errors with SIGABRT
1108         not SIGQUIT.
1109
1110         * sim-main.h (C0_CONFIG): New register.
1111         (signal.h): No longer include.
1112
1113         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1114
1115 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1116
1117         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1118
1119 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1120
1121         * mips.igen: Tag vr5000 instructions.
1122         (ANDI): Was missing mipsIV model, fix assembler syntax.
1123         (do_c_cond_fmt): New function.
1124         (C.cond.fmt): Handle mips I-III which do not support CC field
1125         separatly.
1126         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1127         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1128         in IV3.2 spec.
1129         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1130         vr5000 which saves LO in a GPR separatly.
1131
1132         * configure.in (enable-sim-igen): For vr5000, select vr5000
1133         specific instructions.
1134         * configure: Re-generate.
1135
1136 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1137
1138         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1139
1140         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1141         fmt_uninterpreted_64 bit cases to switch.  Convert to
1142         fmt_formatted,
1143
1144         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1145
1146         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1147         as specified in IV3.2 spec.
1148         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1149
1150 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1151
1152         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1153         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1154         (start-sanitize-r5900):
1155         (LWXC1, SWXC1): Delete from r5900 instruction set.
1156         (end-sanitize-r5900):
1157         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1158         PENDING_FILL versions of instructions.  Simplify.
1159         (X): New function.
1160         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1161         instructions.
1162         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1163         a signed value.
1164         (MTHI, MFHI): Disable code checking HI-LO.
1165
1166         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1167         global.
1168         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1169
1170 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1171
1172         * gencode.c (build_mips16_operands): Replace IPC with cia.
1173
1174         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1175         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1176         IPC to `cia'.
1177         (UndefinedResult): Replace function with macro/function
1178         combination.
1179         (sim_engine_run): Don't save PC in IPC.
1180
1181         * sim-main.h (IPC): Delete.
1182
1183         start-sanitize-vr5400
1184         * vr5400.igen (vr): Add missing cia argument to value_fpr.
1185         (do_select): Rename function select.
1186         end-sanitize-vr5400
1187
1188         * interp.c (signal_exception, store_word, load_word,
1189         address_translation, load_memory, store_memory, cache_op,
1190         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1191         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1192         current instruction address - cia - argument.
1193         (sim_read, sim_write): Call address_translation directly.
1194         (sim_engine_run): Rename variable vaddr to cia.
1195         (signal_exception): Pass cia to sim_monitor
1196
1197         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1198         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1199         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1200
1201         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1202         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1203         SIM_ASSERT.
1204
1205         * interp.c (signal_exception): Pass restart address to
1206         sim_engine_restart.
1207
1208         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1209         idecode.o): Add dependency.
1210
1211         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1212         Delete definitions
1213         (DELAY_SLOT): Update NIA not PC with branch address.
1214         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1215
1216         * mips.igen: Use CIA not PC in branch calculations.
1217         (illegal): Call SignalException.
1218         (BEQ, ADDIU): Fix assembler.
1219
1220 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1221
1222         * m16.igen (JALX): Was missing.
1223
1224         * configure.in (enable-sim-igen): New configuration option.
1225         * configure: Re-generate.
1226
1227         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1228
1229         * interp.c (load_memory, store_memory): Delete parameter RAW.
1230         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1231         bypassing {load,store}_memory.
1232
1233         * sim-main.h (ByteSwapMem): Delete definition.
1234
1235         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1236
1237         * interp.c (sim_do_command, sim_commands): Delete mips specific
1238         commands.  Handled by module sim-options.
1239
1240         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1241         (WITH_MODULO_MEMORY): Define.
1242
1243         * interp.c (sim_info): Delete code printing memory size.
1244
1245         * interp.c (mips_size): Nee sim_size, delete function.
1246         (power2): Delete.
1247         (monitor, monitor_base, monitor_size): Delete global variables.
1248         (sim_open, sim_close): Delete code creating monitor and other
1249         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1250         manage memory regions.
1251         (load_memory, store_memory): Use sim-core for memory model.
1252
1253         * interp.c (address_translation): Delete all memory map code
1254         except line forcing 32 bit addresses.
1255
1256 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1257
1258         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1259         trace options.
1260
1261         * interp.c (logfh, logfile): Delete globals.
1262         (sim_open, sim_close): Delete code opening & closing log file.
1263         (mips_option_handler): Delete -l and -n options.
1264         (OPTION mips_options): Ditto.
1265
1266         * interp.c (OPTION mips_options): Rename option trace to dinero.
1267         (mips_option_handler): Update.
1268
1269 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1270
1271         * interp.c (fetch_str): New function.
1272         (sim_monitor): Rewrite using sim_read & sim_write.
1273         (sim_open): Check magic number.
1274         (sim_open): Write monitor vectors into memory using sim_write.
1275         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1276         (sim_read, sim_write): Simplify - transfer data one byte at a
1277         time.
1278         (load_memory, store_memory): Clarify meaning of parameter RAW.
1279
1280         * sim-main.h (isHOST): Defete definition.
1281         (isTARGET): Mark as depreciated.
1282         (address_translation): Delete parameter HOST.
1283
1284         * interp.c (address_translation): Delete parameter HOST.
1285
1286 start-sanitize-tx49
1287 Wed Oct 29 14:21:32 1997  Gavin Koch  <gavin@cygnus.com>
1288
1289         * gencode.c: Add tx49 configury and insns.
1290         * configure.in: Add tx49 configury.
1291         * configure: Update.
1292
1293 end-sanitize-tx49
1294 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1295
1296         * mips.igen:
1297
1298         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1299         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1300
1301 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1302
1303         * mips.igen: Add model filter field to records.
1304
1305 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1306
1307         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1308
1309         interp.c (sim_engine_run): Do not compile function sim_engine_run
1310         when WITH_IGEN == 1.
1311
1312         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1313         target architecture.
1314
1315         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1316         igen. Replace with configuration variables sim_igen_flags /
1317         sim_m16_flags.
1318
1319         start-sanitize-r5900
1320         * r5900.igen: New file. Copy r5900 insns here.
1321         end-sanitize-r5900
1322         start-sanitize-vr5400
1323         * vr5400.igen: New file.
1324         end-sanitize-vr5400
1325         * m16.igen: New file.  Copy mips16 insns here.
1326         * mips.igen: From here.
1327
1328 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1329
1330         start-sanitize-vr5400
1331         * mips.igen: Tag all mipsIV instructions with vr5400 model.
1332
1333         * configure.in: Add mips64vr5400 target.
1334         * configure: Re-generate.
1335
1336         end-sanitize-vr5400
1337         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1338         to top.
1339         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1340
1341 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1342
1343         * gencode.c (build_instruction): Follow sim_write's lead in using
1344         BigEndianMem instead of !ByteSwapMem.
1345
1346 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1347
1348         * configure.in (sim_gen): Dependent on target, select type of
1349         generator.  Always select old style generator.
1350
1351         configure: Re-generate.
1352
1353         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1354         targets.
1355         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1356         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1357         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1358         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1359         SIM_@sim_gen@_*, set by autoconf.
1360
1361 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1362
1363         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1364
1365         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1366         CURRENT_FLOATING_POINT instead.
1367
1368         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1369         (address_translation): Raise exception InstructionFetch when
1370         translation fails and isINSTRUCTION.
1371
1372         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1373         sim_engine_run): Change type of of vaddr and paddr to
1374         address_word.
1375         (address_translation, prefetch, load_memory, store_memory,
1376         cache_op): Change type of vAddr and pAddr to address_word.
1377
1378         * gencode.c (build_instruction): Change type of vaddr and paddr to
1379         address_word.
1380
1381 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1382
1383         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1384         macro to obtain result of ALU op.
1385
1386 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1387
1388         * interp.c (sim_info): Call profile_print.
1389
1390 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1391
1392         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1393
1394         * sim-main.h (WITH_PROFILE): Do not define, defined in
1395         common/sim-config.h.  Use sim-profile module.
1396         (simPROFILE): Delete defintion.
1397
1398         * interp.c (PROFILE): Delete definition.
1399         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1400         (sim_close): Delete code writing profile histogram.
1401         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1402         Delete.
1403         (sim_engine_run): Delete code profiling the PC.
1404
1405 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1406
1407         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1408
1409         * interp.c (sim_monitor): Make register pointers of type
1410         unsigned_word*.
1411
1412         * sim-main.h: Make registers of type unsigned_word not
1413         signed_word.
1414
1415 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1416
1417 start-sanitize-r5900
1418         * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1419         ...): Move to sim-main.h
1420
1421 end-sanitize-r5900
1422         * interp.c (sync_operation): Rename from SyncOperation, make
1423         global, add SD argument.
1424         (prefetch): Rename from Prefetch, make global, add SD argument.
1425         (decode_coproc): Make global.
1426
1427         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1428
1429         * gencode.c (build_instruction): Generate DecodeCoproc not
1430         decode_coproc calls.
1431
1432         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1433         (SizeFGR): Move to sim-main.h
1434         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1435         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1436         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1437         sim-main.h.
1438         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1439         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1440         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1441         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1442         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1443         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1444
1445         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1446         exception.
1447         (sim-alu.h): Include.
1448         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1449         (sim_cia): Typedef to instruction_address.
1450
1451 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1452
1453         * Makefile.in (interp.o): Rename generated file engine.c to
1454         oengine.c.
1455
1456         * interp.c: Update.
1457
1458 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1459
1460         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1461
1462 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1463
1464         * gencode.c (build_instruction): For "FPSQRT", output correct
1465         number of arguments to Recip.
1466
1467 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1468
1469         * Makefile.in (interp.o): Depends on sim-main.h
1470
1471         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1472
1473         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1474         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1475         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1476         STATE, DSSTATE): Define
1477         (GPR, FGRIDX, ..): Define.
1478
1479         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1480         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1481         (GPR, FGRIDX, ...): Delete macros.
1482
1483         * interp.c: Update names to match defines from sim-main.h
1484
1485 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1486
1487         * interp.c (sim_monitor): Add SD argument.
1488         (sim_warning): Delete.  Replace calls with calls to
1489         sim_io_eprintf.
1490         (sim_error): Delete. Replace calls with sim_io_error.
1491         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1492         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1493         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1494         argument.
1495         (mips_size): Rename from sim_size. Add SD argument.
1496
1497         * interp.c (simulator): Delete global variable.
1498         (callback): Delete global variable.
1499         (mips_option_handler, sim_open, sim_write, sim_read,
1500         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1501         sim_size,sim_monitor): Use sim_io_* not callback->*.
1502         (sim_open): ZALLOC simulator struct.
1503         (PROFILE): Do not define.
1504
1505 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1506
1507         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1508         support.h with corresponding code.
1509
1510         * sim-main.h (word64, uword64), support.h: Move definition to
1511         sim-main.h.
1512         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1513
1514         * support.h: Delete
1515         * Makefile.in: Update dependencies
1516         * interp.c: Do not include.
1517
1518 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1519
1520         * interp.c (address_translation, load_memory, store_memory,
1521         cache_op): Rename to from AddressTranslation et.al., make global,
1522         add SD argument
1523
1524         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1525         CacheOp): Define.
1526
1527         * interp.c (SignalException): Rename to signal_exception, make
1528         global.
1529
1530         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1531
1532         * sim-main.h (SignalException, SignalExceptionInterrupt,
1533         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1534         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1535         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1536         Define.
1537
1538         * interp.c, support.h: Use.
1539
1540 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1541
1542         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1543         to value_fpr / store_fpr. Add SD argument.
1544         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1545         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1546
1547         * sim-main.h (ValueFPR, StoreFPR): Define.
1548
1549 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1550
1551         * interp.c (sim_engine_run): Check consistency between configure
1552         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1553         and HASFPU.
1554
1555         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1556         (mips_fpu): Configure WITH_FLOATING_POINT.
1557         (mips_endian): Configure WITH_TARGET_ENDIAN.
1558         * configure: Update.
1559
1560 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1561
1562         * configure: Regenerated to track ../common/aclocal.m4 changes.
1563
1564 start-sanitize-r5900
1565 Mon Aug 25 19:11:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1566
1567         * interp.c (MAX_REG): Allow up-to 128 registers.
1568         (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1569         (REGISTER_SA): Ditto.
1570         (sim_open): Initialize register_widths for r5900 specific
1571         registers.
1572         (sim_fetch_register, sim_store_register): Check for request of
1573         r5900 specific SA register.  Check for request for hi 64 bits of
1574         r5900 specific registers.
1575
1576 end-sanitize-r5900
1577 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1578
1579         * configure: Regenerated.
1580
1581 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1582
1583         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1584
1585 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1586
1587         * gencode.c (print_igen_insn_models): Assume certain architectures
1588         include all mips* instructions.
1589         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1590         instruction.
1591
1592         * Makefile.in (tmp.igen): Add target. Generate igen input from
1593         gencode file.
1594
1595         * gencode.c (FEATURE_IGEN): Define.
1596         (main): Add --igen option.  Generate output in igen format.
1597         (process_instructions): Format output according to igen option.
1598         (print_igen_insn_format): New function.
1599         (print_igen_insn_models): New function.
1600         (process_instructions): Only issue warnings and ignore
1601         instructions when no FEATURE_IGEN.
1602
1603 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1604
1605         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1606         MIPS targets.
1607
1608 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1609
1610         * configure: Regenerated to track ../common/aclocal.m4 changes.
1611
1612 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1613
1614         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1615         SIM_RESERVED_BITS): Delete, moved to common.
1616         (SIM_EXTRA_CFLAGS): Update.
1617
1618 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1619
1620         * configure.in: Configure non-strict memory alignment.
1621         * configure: Regenerated to track ../common/aclocal.m4 changes.
1622
1623 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1624
1625         * configure: Regenerated to track ../common/aclocal.m4 changes.
1626
1627 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1628
1629         * gencode.c (SDBBP,DERET): Added (3900) insns.
1630         (RFE): Turn on for 3900.
1631         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1632         (dsstate): Made global.
1633         (SUBTARGET_R3900): Added.
1634         (CANCELDELAYSLOT): New.
1635         (SignalException): Ignore SystemCall rather than ignore and
1636         terminate.  Add DebugBreakPoint handling.
1637         (decode_coproc): New insns RFE, DERET; and new registers Debug
1638         and DEPC protected by SUBTARGET_R3900.
1639         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1640         bits explicitly.
1641         * Makefile.in,configure.in: Add mips subtarget option.
1642         * configure: Update.
1643
1644 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1645
1646         * gencode.c: Add r3900 (tx39).
1647
1648 start-sanitize-tx19
1649         * gencode.c: Fix some configuration problems by improving
1650         the relationship between tx19 and tx39.
1651 end-sanitize-tx19
1652
1653 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1654
1655         * gencode.c (build_instruction): Don't need to subtract 4 for
1656         JALR, just 2.
1657
1658 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1659
1660         * interp.c: Correct some HASFPU problems.
1661
1662 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1663
1664         * configure: Regenerated to track ../common/aclocal.m4 changes.
1665
1666 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1667
1668         * interp.c (mips_options): Fix samples option short form, should
1669         be `x'.
1670
1671 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1672
1673         * interp.c (sim_info): Enable info code.  Was just returning.
1674
1675 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1676
1677         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1678         MFC0.
1679
1680 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1681
1682         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1683         constants.
1684         (build_instruction): Ditto for LL.
1685
1686 start-sanitize-tx19
1687 Sun Sep  7 16:05:46 1997  Gavin Koch  <gavin@cygnus.com>
1688
1689         * mips/configure.in, mips/gencode: Add tx19/r1900.
1690
1691 end-sanitize-tx19
1692 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1693
1694         * configure: Regenerated to track ../common/aclocal.m4 changes.
1695
1696 start-sanitize-r5900
1697 Mon Sep  1 18:43:30 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1698
1699         * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1700         for overflow due to ABS of MININT, set result to MAXINT.
1701         (build_instruction): For "psrlvw", signextend bit 31.
1702
1703 end-sanitize-r5900
1704 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1705
1706         * configure: Regenerated to track ../common/aclocal.m4 changes.
1707         * config.in: Ditto.
1708
1709 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1710
1711         * interp.c (sim_open): Add call to sim_analyze_program, update
1712         call to sim_config.
1713
1714 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1715
1716         * interp.c (sim_kill): Delete.
1717         (sim_create_inferior): Add ABFD argument. Set PC from same.
1718         (sim_load): Move code initializing trap handlers from here.
1719         (sim_open): To here.
1720         (sim_load): Delete, use sim-hload.c.
1721
1722         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1723
1724 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1725
1726         * configure: Regenerated to track ../common/aclocal.m4 changes.
1727         * config.in: Ditto.
1728
1729 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1730
1731         * interp.c (sim_open): Add ABFD argument.
1732         (sim_load): Move call to sim_config from here.
1733         (sim_open): To here.  Check return status.
1734
1735 start-sanitize-r5900
1736         * gencode.c (build_instruction): Do not define x8000000000000000,
1737         x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1738
1739 end-sanitize-r5900
1740 start-sanitize-r5900
1741 Mon Jul 28 19:49:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1742
1743         * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1744         "pdivuw" check for overflow due to signed divide by -1.
1745
1746 end-sanitize-r5900
1747 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1748
1749         * gencode.c (build_instruction): Two arg MADD should
1750         not assign result to $0.
1751
1752 start-sanitize-r5900
1753 Thu Jul 10 11:58:48 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1754
1755         * gencode.c (build_instruction): For "ppac5" use unsigned
1756         arrithmetic so that the sign bit doesn't smear when right shifted.
1757         (build_instruction): For "pdiv" perform sign extension when
1758         storing results in HI and LO.
1759         (build_instructions): For "pdiv" and "pdivbw" check for
1760         divide-by-zero.
1761         (build_instruction): For "pmfhl.slw" update hi part of dest
1762         register as well as low part.
1763         (build_instruction): For "pmfhl" portably handle long long values.
1764         (build_instruction): For "pmfhl.sh" correctly negative values.
1765         Store half words 2 and three in the correct place.
1766         (build_instruction): For "psllvw", sign extend value after shift.
1767
1768 end-sanitize-r5900
1769 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1770
1771         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1772         * sim/mips/configure.in: Regenerate.
1773
1774 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1775
1776         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1777         signed8, unsigned8 et.al. types.
1778
1779 start-sanitize-r5900
1780         * gencode.c (build_instruction): For PMULTU* do not sign extend
1781         registers.  Make generated code easier to debug.
1782
1783 end-sanitize-r5900
1784         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1785         hosts when selecting subreg.
1786
1787 start-sanitize-r5900
1788 Tue Jul  8 18:07:20 1997  Andrew Cagney  <cagney@andros.cygnus.com>
1789
1790         * gencode.c (type_for_data_len): For 32bit operations concerned
1791         with overflow, perform op using 64bits.
1792         (build_instruction): For PADD, always compute operation using type
1793         returned by type_for_data_len.
1794         (build_instruction): For PSUBU, when overflow, saturate to zero as
1795         actually underflow.
1796
1797 end-sanitize-r5900
1798 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1799
1800 start-sanitize-r5900
1801         * gencode.c (build_instruction): Handle "pext5" according to
1802         version 1.95 of the r5900 ISA.
1803
1804         * gencode.c (build_instruction): Handle "ppac5" according to
1805         version 1.95 of the r5900 ISA.
1806
1807 end-sanitize-r5900
1808         * interp.c (sim_engine_run): Reset the ZERO register to zero
1809         regardless of FEATURE_WARN_ZERO.
1810         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1811
1812 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1813
1814         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1815         (SignalException): For BreakPoints ignore any mode bits and just
1816         save the PC.
1817         (SignalException): Always set the CAUSE register.
1818
1819 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1820
1821         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1822         exception has been taken.
1823
1824         * interp.c: Implement the ERET and mt/f sr instructions.
1825
1826 start-sanitize-r5900
1827 Mon Jun  2 23:28:19 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1828
1829         * gencode.c (build_instruction): For paddu, extract unsigned
1830         sub-fields.
1831
1832         * gencode.c (build_instruction): Saturate padds instead of padd
1833         instructions.
1834
1835 end-sanitize-r5900
1836 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1837
1838         * interp.c (SignalException): Don't bother restarting an
1839         interrupt.
1840
1841 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1842
1843         * interp.c (SignalException): Really take an interrupt.
1844         (interrupt_event): Only deliver interrupts when enabled.
1845
1846 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1847
1848         * interp.c (sim_info): Only print info when verbose.
1849         (sim_info) Use sim_io_printf for output.
1850
1851 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1852
1853         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1854         mips architectures.
1855
1856 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1857
1858         * interp.c (sim_do_command): Check for common commands if a
1859         simulator specific command fails.
1860
1861 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1862
1863         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1864         and simBE when DEBUG is defined.
1865
1866 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1867
1868         * interp.c (interrupt_event): New function.  Pass exception event
1869         onto exception handler.
1870
1871         * configure.in: Check for stdlib.h.
1872         * configure: Regenerate.
1873
1874         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1875         variable declaration.
1876         (build_instruction): Initialize memval1.
1877         (build_instruction): Add UNUSED attribute to byte, bigend,
1878         reverse.
1879         (build_operands): Ditto.
1880
1881         * interp.c: Fix GCC warnings.
1882         (sim_get_quit_code): Delete.
1883
1884         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1885         * Makefile.in: Ditto.
1886         * configure: Re-generate.
1887
1888         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1889
1890 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1891
1892         * interp.c (mips_option_handler): New function parse argumes using
1893         sim-options.
1894         (myname): Replace with STATE_MY_NAME.
1895         (sim_open): Delete check for host endianness - performed by
1896         sim_config.
1897         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1898         (sim_open): Move much of the initialization from here.
1899         (sim_load): To here.  After the image has been loaded and
1900         endianness set.
1901         (sim_open): Move ColdReset from here.
1902         (sim_create_inferior): To here.
1903         (sim_open): Make FP check less dependant on host endianness.
1904
1905         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1906         run.
1907         * interp.c (sim_set_callbacks): Delete.
1908
1909         * interp.c (membank, membank_base, membank_size): Replace with
1910         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1911         (sim_open): Remove call to callback->init. gdb/run do this.
1912
1913         * interp.c: Update
1914
1915         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1916
1917         * interp.c (big_endian_p): Delete, replaced by
1918         current_target_byte_order.
1919
1920 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1921
1922         * interp.c (host_read_long, host_read_word, host_swap_word,
1923         host_swap_long): Delete. Using common sim-endian.
1924         (sim_fetch_register, sim_store_register): Use H2T.
1925         (pipeline_ticks): Delete.  Handled by sim-events.
1926         (sim_info): Update.
1927         (sim_engine_run): Update.
1928
1929 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1930
1931         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1932         reason from here.
1933         (SignalException): To here. Signal using sim_engine_halt.
1934         (sim_stop_reason): Delete, moved to common.
1935
1936 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1937
1938         * interp.c (sim_open): Add callback argument.
1939         (sim_set_callbacks): Delete SIM_DESC argument.
1940         (sim_size): Ditto.
1941
1942 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1943
1944         * Makefile.in (SIM_OBJS): Add common modules.
1945
1946         * interp.c (sim_set_callbacks): Also set SD callback.
1947         (set_endianness, xfer_*, swap_*): Delete.
1948         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1949         Change to functions using sim-endian macros.
1950         (control_c, sim_stop): Delete, use common version.
1951         (simulate): Convert into.
1952         (sim_engine_run): This function.
1953         (sim_resume): Delete.
1954
1955         * interp.c (simulation): New variable - the simulator object.
1956         (sim_kind): Delete global - merged into simulation.
1957         (sim_load): Cleanup.  Move PC assignment from here.
1958         (sim_create_inferior): To here.
1959
1960         * sim-main.h: New file.
1961         * interp.c (sim-main.h): Include.
1962
1963 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1964
1965         * configure: Regenerated to track ../common/aclocal.m4 changes.
1966
1967 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1968
1969         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1970
1971 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1972
1973         * gencode.c (build_instruction): DIV instructions: check
1974         for division by zero and integer overflow before using
1975         host's division operation.
1976
1977 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1978
1979         * Makefile.in (SIM_OBJS): Add sim-load.o.
1980         * interp.c: #include bfd.h.
1981         (target_byte_order): Delete.
1982         (sim_kind, myname, big_endian_p): New static locals.
1983         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1984         after argument parsing.  Recognize -E arg, set endianness accordingly.
1985         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1986         load file into simulator.  Set PC from bfd.
1987         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1988         (set_endianness): Use big_endian_p instead of target_byte_order.
1989
1990 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1991
1992         * interp.c (sim_size): Delete prototype - conflicts with
1993         definition in remote-sim.h.  Correct definition.
1994
1995 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1996
1997         * configure: Regenerated to track ../common/aclocal.m4 changes.
1998         * config.in: Ditto.
1999
2000 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2001
2002         * interp.c (sim_open): New arg `kind'.
2003
2004         * configure: Regenerated to track ../common/aclocal.m4 changes.
2005
2006 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2007
2008         * configure: Regenerated to track ../common/aclocal.m4 changes.
2009
2010 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2011
2012         * interp.c (sim_open): Set optind to 0 before calling getopt.
2013
2014 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2015
2016         * configure: Regenerated to track ../common/aclocal.m4 changes.
2017
2018 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2019
2020         * interp.c : Replace uses of pr_addr with pr_uword64
2021         where the bit length is always 64 independent of SIM_ADDR.
2022         (pr_uword64) : added.
2023
2024 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2025
2026         * configure: Re-generate.
2027
2028 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2029
2030         * configure: Regenerate to track ../common/aclocal.m4 changes.
2031
2032 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2033
2034         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2035         in argv form.
2036         (other sim_*): New SIM_DESC argument.
2037
2038 start-sanitize-r5900
2039 Wed Feb 26 18:32:21 1997  Gavin Koch  <gavin@cygnus.com>
2040
2041         * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2042         Change values to avoid overloading DOUBLEWORD which is tested
2043         for all insns.
2044         * gencode.c: reinstate "offending code".
2045
2046 end-sanitize-r5900
2047 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2048
2049         * interp.c: Fix printing of addresses for non-64-bit targets.
2050         (pr_addr): Add function to print address based on size.
2051 start-sanitize-r5900
2052         * gencode.c: #ifdef out offending code until a permanent fix
2053         can be added.  Code is causing build errors for non-5900 mips targets.
2054 end-sanitize-r5900
2055
2056 start-sanitize-r5900
2057 Thu Feb 20 10:40:24 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2058
2059         * gencode.c (process_instructions): Correct test for ISA dependent
2060         architecture bits in isa field of MIPS_DECODE.
2061
2062 end-sanitize-r5900
2063 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2064
2065         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2066
2067 start-sanitize-r5900
2068 Tue Feb 18 17:03:47 1997  Gavin Koch  <gavin@cygnus.com>
2069
2070         * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2071         PMADDUW.
2072
2073 end-sanitize-r5900
2074 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2075
2076         * gencode.c (build_mips16_operands): Correct computation of base
2077         address for extended PC relative instruction.
2078
2079 start-sanitize-r5900
2080 Fri Feb  7 11:12:44 1997  Gavin Koch  <gavin@cygnus.com>
2081
2082         * Makefile.in, configure, configure.in, gencode.c,
2083         interp.c, support.h: add r5900.
2084
2085 end-sanitize-r5900
2086 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2087
2088         * interp.c (mips16_entry): Add support for floating point cases.
2089         (SignalException): Pass floating point cases to mips16_entry.
2090         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2091         registers.
2092         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2093         or fmt_word.
2094         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2095         and then set the state to fmt_uninterpreted.
2096         (COP_SW): Temporarily set the state to fmt_word while calling
2097         ValueFPR.
2098
2099 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2100
2101         * gencode.c (build_instruction): The high order may be set in the
2102         comparison flags at any ISA level, not just ISA 4.
2103
2104 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2105
2106         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2107         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2108         * configure.in: sinclude ../common/aclocal.m4.
2109         * configure: Regenerated.
2110
2111 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2112
2113         * configure: Rebuild after change to aclocal.m4.
2114
2115 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2116
2117         * configure configure.in Makefile.in:  Update to new configure
2118         scheme which is more compatible with WinGDB builds.
2119         * configure.in:  Improve comment on how to run autoconf.
2120         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2121         * Makefile.in:  Use autoconf substitution to install common
2122         makefile fragment.
2123
2124 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2125
2126         * gencode.c (build_instruction): Use BigEndianCPU instead of
2127         ByteSwapMem.
2128
2129 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2130
2131         * interp.c (sim_monitor): Make output to stdout visible in
2132         wingdb's I/O log window.
2133
2134 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2135
2136         * support.h: Undo previous change to SIGTRAP
2137         and SIGQUIT values.
2138
2139 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2140
2141         * interp.c (store_word, load_word): New static functions.
2142         (mips16_entry): New static function.
2143         (SignalException): Look for mips16 entry and exit instructions.
2144         (simulate): Use the correct index when setting fpr_state after
2145         doing a pending move.
2146
2147 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2148
2149         * interp.c: Fix byte-swapping code throughout to work on
2150         both little- and big-endian hosts.
2151
2152 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2153
2154         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2155         with gdb/config/i386/xm-windows.h.
2156
2157 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2158
2159         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2160         that messes up arithmetic shifts.
2161
2162 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2163
2164         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2165         SIGTRAP and SIGQUIT for _WIN32.
2166
2167 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2168
2169         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2170         force a 64 bit multiplication.
2171         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2172         destination register is 0, since that is the default mips16 nop
2173         instruction.
2174
2175 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2176
2177         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2178         (build_endian_shift): Don't check proc64.
2179         (build_instruction): Always set memval to uword64.  Cast op2 to
2180         uword64 when shifting it left in memory instructions.  Always use
2181         the same code for stores--don't special case proc64.
2182
2183         * gencode.c (build_mips16_operands): Fix base PC value for PC
2184         relative operands.
2185         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2186         jal instruction.
2187         * interp.c (simJALDELAYSLOT): Define.
2188         (JALDELAYSLOT): Define.
2189         (INDELAYSLOT, INJALDELAYSLOT): Define.
2190         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2191
2192 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2193
2194         * interp.c (sim_open): add flush_cache as a PMON routine
2195         (sim_monitor): handle flush_cache by ignoring it
2196
2197 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2198
2199         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2200         BigEndianMem.
2201         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2202         (BigEndianMem): Rename to ByteSwapMem and change sense.
2203         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2204         BigEndianMem references to !ByteSwapMem.
2205         (set_endianness): New function, with prototype.
2206         (sim_open): Call set_endianness.
2207         (sim_info): Use simBE instead of BigEndianMem.
2208         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2209         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2210         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2211         ifdefs, keeping the prototype declaration.
2212         (swap_word): Rewrite correctly.
2213         (ColdReset): Delete references to CONFIG.  Delete endianness related
2214         code; moved to set_endianness.
2215
2216 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2217
2218         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2219         * interp.c (CHECKHILO): Define away.
2220         (simSIGINT): New macro.
2221         (membank_size): Increase from 1MB to 2MB.
2222         (control_c): New function.
2223         (sim_resume): Rename parameter signal to signal_number.  Add local
2224         variable prev.  Call signal before and after simulate.
2225         (sim_stop_reason): Add simSIGINT support.
2226         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2227         functions always.
2228         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2229         if logfh is NULL.
2230         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2231         a call to sim_warning.
2232
2233 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2234
2235         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2236         16 bit instructions.
2237
2238 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2239
2240         Add support for mips16 (16 bit MIPS implementation):
2241         * gencode.c (inst_type): Add mips16 instruction encoding types.
2242         (GETDATASIZEINSN): Define.
2243         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2244         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2245         mtlo.
2246         (MIPS16_DECODE): New table, for mips16 instructions.
2247         (bitmap_val): New static function.
2248         (struct mips16_op): Define.
2249         (mips16_op_table): New table, for mips16 operands.
2250         (build_mips16_operands): New static function.
2251         (process_instructions): If PC is odd, decode a mips16
2252         instruction.  Break out instruction handling into new
2253         build_instruction function.
2254         (build_instruction): New static function, broken out of
2255         process_instructions.  Check modifiers rather than flags for SHIFT
2256         bit count and m[ft]{hi,lo} direction.
2257         (usage): Pass program name to fprintf.
2258         (main): Remove unused variable this_option_optind.  Change
2259         ``*loptarg++'' to ``loptarg++''.
2260         (my_strtoul): Parenthesize && within ||.
2261         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2262         (simulate): If PC is odd, fetch a 16 bit instruction, and
2263         increment PC by 2 rather than 4.
2264         * configure.in: Add case for mips16*-*-*.
2265         * configure: Rebuild.
2266
2267 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2268
2269         * interp.c: Allow -t to enable tracing in standalone simulator.
2270         Fix garbage output in trace file and error messages.
2271
2272 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2273
2274         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2275         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2276         * configure.in: Simplify using macros in ../common/aclocal.m4.
2277         * configure: Regenerated.
2278         * tconfig.in: New file.
2279
2280 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2281
2282         * interp.c: Fix bugs in 64-bit port.
2283         Use ansi function declarations for msvc compiler.
2284         Initialize and test file pointer in trace code.
2285         Prevent duplicate definition of LAST_EMED_REGNUM.
2286
2287 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2288
2289         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2290
2291 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2292
2293         * interp.c (SignalException): Check for explicit terminating
2294         breakpoint value.
2295         * gencode.c: Pass instruction value through SignalException()
2296         calls for Trap, Breakpoint and Syscall.
2297
2298 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2299
2300         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2301         only used on those hosts that provide it.
2302         * configure.in: Add sqrt() to list of functions to be checked for.
2303         * config.in: Re-generated.
2304         * configure: Re-generated.
2305
2306 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2307
2308         * gencode.c (process_instructions): Call build_endian_shift when
2309         expanding STORE RIGHT, to fix swr.
2310         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2311         clear the high bits.
2312         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2313         Fix float to int conversions to produce signed values.
2314
2315 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2316
2317         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2318         (process_instructions): Correct handling of nor instruction.
2319         Correct shift count for 32 bit shift instructions. Correct sign
2320         extension for arithmetic shifts to not shift the number of bits in
2321         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2322         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2323         Fix madd.
2324         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2325         It's OK to have a mult follow a mult.  What's not OK is to have a
2326         mult follow an mfhi.
2327         (Convert): Comment out incorrect rounding code.
2328
2329 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2330
2331         * interp.c (sim_monitor): Improved monitor printf
2332         simulation. Tidied up simulator warnings, and added "--log" option
2333         for directing warning message output.
2334         * gencode.c: Use sim_warning() rather than WARNING macro.
2335
2336 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2337
2338         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2339         getopt1.o, rather than on gencode.c.  Link objects together.
2340         Don't link against -liberty.
2341         (gencode.o, getopt.o, getopt1.o): New targets.
2342         * gencode.c: Include <ctype.h> and "ansidecl.h".
2343         (AND): Undefine after including "ansidecl.h".
2344         (ULONG_MAX): Define if not defined.
2345         (OP_*): Don't define macros; now defined in opcode/mips.h.
2346         (main): Call my_strtoul rather than strtoul.
2347         (my_strtoul): New static function.
2348
2349 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2350
2351         * gencode.c (process_instructions):  Generate word64 and uword64
2352         instead of `long long' and `unsigned long long' data types.
2353         * interp.c:  #include sysdep.h to get signals, and define default
2354         for SIGBUS.
2355         * (Convert):  Work around for Visual-C++ compiler bug with type
2356         conversion.
2357         * support.h:  Make things compile under Visual-C++ by using
2358         __int64 instead of `long long'.  Change many refs to long long
2359         into word64/uword64 typedefs.
2360
2361 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2362
2363         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2364         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2365         (docdir): Removed.
2366         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2367         (AC_PROG_INSTALL): Added.
2368         (AC_PROG_CC): Moved to before configure.host call.
2369         * configure: Rebuilt.
2370
2371 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2372
2373         * configure.in: Define @SIMCONF@ depending on mips target.
2374         * configure: Rebuild.
2375         * Makefile.in (run): Add @SIMCONF@ to control simulator
2376         construction.
2377         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2378         * interp.c: Remove some debugging, provide more detailed error
2379         messages, update memory accesses to use LOADDRMASK.
2380
2381 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2382
2383         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2384         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2385         stamp-h.
2386         * configure: Rebuild.
2387         * config.in: New file, generated by autoheader.
2388         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2389         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2390         HAVE_ANINT and HAVE_AINT, as appropriate.
2391         * Makefile.in (run): Use @LIBS@ rather than -lm.
2392         (interp.o): Depend upon config.h.
2393         (Makefile): Just rebuild Makefile.
2394         (clean): Remove stamp-h.
2395         (mostlyclean): Make the same as clean, not as distclean.
2396         (config.h, stamp-h): New targets.
2397
2398 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2399
2400         * interp.c (ColdReset): Fix boolean test. Make all simulator
2401         globals static.
2402
2403 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2404
2405         * interp.c (xfer_direct_word, xfer_direct_long,
2406         swap_direct_word, swap_direct_long, xfer_big_word,
2407         xfer_big_long, xfer_little_word, xfer_little_long,
2408         swap_word,swap_long): Added.
2409         * interp.c (ColdReset): Provide function indirection to
2410         host<->simulated_target transfer routines.
2411         * interp.c (sim_store_register, sim_fetch_register): Updated to
2412         make use of indirected transfer routines.
2413
2414 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2415
2416         * gencode.c (process_instructions): Ensure FP ABS instruction
2417         recognised.
2418         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2419         system call support.
2420
2421 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2422
2423         * interp.c (sim_do_command): Complain if callback structure not
2424         initialised.
2425
2426 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2427
2428         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2429         support for Sun hosts.
2430         * Makefile.in (gencode): Ensure the host compiler and libraries
2431         used for cross-hosted build.
2432
2433 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2434
2435         * interp.c, gencode.c: Some more (TODO) tidying.
2436
2437 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2438
2439         * gencode.c, interp.c: Replaced explicit long long references with
2440         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2441         * support.h (SET64LO, SET64HI): Macros added.
2442
2443 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2444
2445         * configure: Regenerate with autoconf 2.7.
2446
2447 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2448
2449         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2450         * support.h: Remove superfluous "1" from #if.
2451         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2452
2453 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2454
2455         * interp.c (StoreFPR): Control UndefinedResult() call on
2456         WARN_RESULT manifest.
2457
2458 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2459
2460         * gencode.c: Tidied instruction decoding, and added FP instruction
2461         support.
2462
2463         * interp.c: Added dineroIII, and BSD profiling support. Also
2464         run-time FP handling.
2465
2466 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2467
2468         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2469         gencode.c, interp.c, support.h: created.