1 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
3 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
5 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
7 * mips.igen (ERET): Implement.
9 * interp.c (decode_coproc): Return sign-extended EPC.
11 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
13 * interp.c (signal_exception): Do not ignore Trap.
14 (signal_exception): On TRAP, restart at exception address.
15 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
16 (signal_exception): Update.
17 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
18 so that TRAP instructions are caught.
20 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
22 * sim-main.h (struct hilo_access, struct hilo_history): Define,
23 contains HI/LO access history.
24 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
25 (HIACCESS, LOACCESS): Delete, replace with
26 (HIHISTORY, LOHISTORY): New macros.
27 (start-sanitize-r5900):
28 (struct sim_5900_cpu): Make hi1access, lo1access of type
30 (HI1ACCESS, LO1ACCESS): Delete, replace with
31 (HI1HISTORY, LO1HISTORY): New macros.
33 (CHECKHILO): Delete all, moved to mips.igen
35 * gencode.c (build_instruction): Do not generate checks for
36 correct HI/LO register usage.
38 * interp.c (old_engine_run): Delete checks for correct HI/LO
41 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
42 check_mf_cycles): New functions.
43 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
44 do_divu, domultx, do_mult, do_multu): Use.
46 * tx.igen ("madd", "maddu"): Use.
47 (start-sanitize-r5900):
49 r5900.igen: Update all HI/LO checks.
50 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
51 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
52 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
53 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
54 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
59 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
61 * interp.c (decode_coproc): Correct CMFC2/QMTC2
64 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
65 instead of a single 128-bit access.
69 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
71 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
72 * interp.c (cop_[ls]q): Fixes corresponding to above.
76 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
78 * interp.c (decode_coproc): Adapt COP2 micro interlock to
79 clarified specs. Reset "M" bit; exit also on "E" bit.
83 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
85 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
86 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
88 * r5900.igen (r59fp_unpack): New function.
89 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
90 RSQRT.S, SQRT.S): Use.
91 (r59fp_zero): New function.
92 (r59fp_overflow): Generate r5900 specific overflow value.
93 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
95 (CVT.S.W, CVT.W.S): Exchange implementations.
97 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
101 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
103 * configure.in (tx19, sim_use_gen): Switch to igen.
104 * configure: Re-build.
108 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
110 * interp.c (decode_coproc): Make COP2 branch code compile after
111 igen signature changes.
114 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
116 * mips.igen (DSRAV): Use function do_dsrav.
117 (SRAV): Use new function do_srav.
119 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
120 (B): Sign extend 11 bit immediate.
121 (EXT-B*): Shift 16 bit immediate left by 1.
122 (ADDIU*): Don't sign extend immediate value.
124 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
126 * m16run.c (sim_engine_run): Restore CIA after handling an event.
129 * mips.igen (mtc0): Valid tx19 instruction.
132 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
135 * mips.igen (delayslot32, nullify_next_insn): New functions.
136 (m16.igen): Always include.
137 (do_*): Add more tracing.
139 * m16.igen (delayslot16): Add NIA argument, could be called by a
140 32 bit MIPS16 instruction.
142 * interp.c (ifetch16): Move function from here.
143 * sim-main.c (ifetch16): To here.
145 * sim-main.c (ifetch16, ifetch32): Update to match current
146 implementations of LH, LW.
147 (signal_exception): Don't print out incorrect hex value of illegal
150 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
152 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
155 * m16.igen: Implement MIPS16 instructions.
157 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
158 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
159 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
160 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
161 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
162 bodies of corresponding code from 32 bit insn to these. Also used
163 by MIPS16 versions of functions.
165 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
166 (IMEM16): Drop NR argument from macro.
169 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
171 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
172 of VU lower instruction.
176 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
178 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
181 * sim-main.h: Removed attempt at allowing 128-bit access.
185 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
187 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
189 * interp.c (decode_coproc): Refer to VU CIA as a "special"
190 register, not as a "misc" register. Aha. Add activity
191 assertions after VCALLMS* instructions.
195 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
197 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
198 to upper code of generated VU instruction.
202 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
204 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
206 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
209 * r5900.igen (SQC2): Thinko.
213 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
215 * interp.c (*): Adapt code to merged VU device & state structs.
216 (decode_coproc): Execute COP2 each macroinstruction without
217 pipelining, by stepping VU to completion state. Adapted to
218 read_vu_*_reg style of register access.
220 * mips.igen ([SL]QC2): Removed these COP2 instructions.
222 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
224 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
227 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
229 * Makefile.in (SIM_OBJS): Add sim-main.o.
231 * sim-main.h (address_translation, load_memory, store_memory,
232 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
234 (pr_addr, pr_uword64): Declare.
235 (sim-main.c): Include when H_REVEALS_MODULE_P.
237 * interp.c (address_translation, load_memory, store_memory,
238 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
240 * sim-main.c: To here. Fix compilation problems.
242 * configure.in: Enable inlining.
243 * configure: Re-config.
245 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
247 * configure: Regenerated to track ../common/aclocal.m4 changes.
249 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
251 * mips.igen: Include tx.igen.
252 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
253 * tx.igen: New file, contains MADD and MADDU.
255 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
256 the hardwired constant `7'.
257 (store_memory): Ditto.
258 (LOADDRMASK): Move definition to sim-main.h.
260 mips.igen (MTC0): Enable for r3900.
263 mips.igen (do_load_byte): Delete.
264 (do_load, do_store, do_load_left, do_load_write, do_store_left,
265 do_store_right): New functions.
266 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
268 configure.in: Let the tx39 use igen again.
271 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
273 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
274 not an address sized quantity. Return zero for cache sizes.
276 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
278 * mips.igen (r3900): r3900 does not support 64 bit integer
282 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
284 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
288 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
290 * interp.c (decode_coproc): Continuing COP2 work.
291 (cop_[ls]q): Make sky-target-only.
293 * sim-main.h (COP_[LS]Q): Make sky-target-only.
295 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
297 * configure.in (mipstx39*-*-*): Use gencode simulator rather
299 * configure : Rebuild.
302 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
304 * interp.c (decode_coproc): Added a missing TARGET_SKY check
305 around COP2 implementation skeleton.
309 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
311 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
313 * interp.c (sim_{load,store}_register): Use new vu[01]_device
314 static to access VU registers.
315 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
316 decoding. Work in progress.
318 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
319 overlapping/redundant bit pattern.
320 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
323 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
326 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
327 access to coprocessor registers.
329 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
331 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
333 * configure: Regenerated to track ../common/aclocal.m4 changes.
335 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
337 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
339 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
341 * configure: Regenerated to track ../common/aclocal.m4 changes.
342 * config.in: Regenerated to track ../common/aclocal.m4 changes.
344 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
346 * configure: Regenerated to track ../common/aclocal.m4 changes.
348 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
350 * interp.c (Max, Min): Comment out functions. Not yet used.
352 start-sanitize-vr4320
353 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
355 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
358 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
360 * configure: Regenerated to track ../common/aclocal.m4 changes.
362 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
364 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
365 configurable settings for stand-alone simulator.
368 * configure.in: Added --with-sim-gpu2 option to specify path of
369 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
370 links/compiles stand-alone simulator with this library.
372 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
374 * configure.in: Added X11 search, just in case.
376 * configure: Regenerated.
378 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
380 * interp.c (sim_write, sim_read, load_memory, store_memory):
381 Replace sim_core_*_map with read_map, write_map, exec_map resp.
383 start-sanitize-vr4320
384 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
386 * vr4320.igen (clz,dclz) : Added.
387 (dmac): Replaced 99, with LO.
390 start-sanitize-vr5400
391 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
393 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
396 start-sanitize-vr4320
397 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
399 * vr4320.igen: New file.
400 * Makefile.in (vr4320.igen) : Added.
401 * configure.in (mips64vr4320-*-*): Added.
402 * configure : Rebuilt.
403 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
404 Add the vr4320 model entry and mark the vr4320 insn as necessary.
407 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
409 * sim-main.h (GETFCC): Return an unsigned value.
412 * r5900.igen: Use an unsigned array index variable `i'.
413 (QFSRV): Ditto for variable bytes.
416 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
418 * mips.igen (DIV): Fix check for -1 / MIN_INT.
419 (DADD): Result destination is RD not RT.
422 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
423 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
427 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
429 * sim-main.h (HIACCESS, LOACCESS): Always define.
431 * mdmx.igen (Maxi, Mini): Rename Max, Min.
433 * interp.c (sim_info): Delete.
435 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
437 * interp.c (DECLARE_OPTION_HANDLER): Use it.
438 (mips_option_handler): New argument `cpu'.
439 (sim_open): Update call to sim_add_option_table.
441 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
443 * mips.igen (CxC1): Add tracing.
446 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
448 * r5900.igen (StoreFP): Delete.
449 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
451 (rsqrt.s, sqrt.s): Implement.
452 (r59cond): New function.
453 (C.COND.S): Call r59cond in assembler line.
454 (cvt.w.s, cvt.s.w): Implement.
456 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
459 * sim-main.h: Define an enum of r5900 FCSR bit fields.
463 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
465 * r5900.igen: Add tracing to all p* instructions.
467 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
469 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
470 to get gdb talking to re-aranged sim_cpu register structure.
473 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
475 * sim-main.h (Max, Min): Declare.
477 * interp.c (Max, Min): New functions.
479 * mips.igen (BC1): Add tracing.
481 start-sanitize-vr5400
482 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
484 * mdmx.igen: Tag all functions as requiring either with mdmx or
489 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
491 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
493 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
495 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
497 * r5900.igen: Rewrite.
499 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
501 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
502 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
505 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
507 * interp.c Added memory map for stack in vr4100
509 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
511 * interp.c (load_memory): Add missing "break"'s.
513 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
515 * interp.c (sim_store_register, sim_fetch_register): Pass in
516 length parameter. Return -1.
518 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
520 * interp.c: Added hardware init hook, fixed warnings.
522 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
524 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
526 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
528 * interp.c (ifetch16): New function.
530 * sim-main.h (IMEM32): Rename IMEM.
531 (IMEM16_IMMED): Define.
533 (DELAY_SLOT): Update.
535 * m16run.c (sim_engine_run): New file.
537 * m16.igen: All instructions except LB.
538 (LB): Call do_load_byte.
539 * mips.igen (do_load_byte): New function.
540 (LB): Call do_load_byte.
542 * mips.igen: Move spec for insn bit size and high bit from here.
543 * Makefile.in (tmp-igen, tmp-m16): To here.
545 * m16.dc: New file, decode mips16 instructions.
547 * Makefile.in (SIM_NO_ALL): Define.
548 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
551 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
555 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
557 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
558 point unit to 32 bit registers.
559 * configure: Re-generate.
561 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
563 * configure.in (sim_use_gen): Make IGEN the default simulator
564 generator for generic 32 and 64 bit mips targets.
565 * configure: Re-generate.
567 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
569 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
572 * interp.c (sim_fetch_register, sim_store_register): Read/write
573 FGR from correct location.
574 (sim_open): Set size of FGR's according to
575 WITH_TARGET_FLOATING_POINT_BITSIZE.
577 * sim-main.h (FGR): Store floating point registers in a separate
580 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
582 * configure: Regenerated to track ../common/aclocal.m4 changes.
584 start-sanitize-vr5400
585 * mdmx.igen: Mark all instructions as 64bit/fp specific.
588 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
590 * interp.c (ColdReset): Call PENDING_INVALIDATE.
592 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
594 * interp.c (pending_tick): New function. Deliver pending writes.
596 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
597 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
598 it can handle mixed sized quantites and single bits.
600 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
602 * interp.c (oengine.h): Do not include when building with IGEN.
603 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
604 (sim_info): Ditto for PROCESSOR_64BIT.
605 (sim_monitor): Replace ut_reg with unsigned_word.
606 (*): Ditto for t_reg.
607 (LOADDRMASK): Define.
608 (sim_open): Remove defunct check that host FP is IEEE compliant,
609 using software to emulate floating point.
610 (value_fpr, ...): Always compile, was conditional on HASFPU.
612 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
614 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
617 * interp.c (SD, CPU): Define.
618 (mips_option_handler): Set flags in each CPU.
619 (interrupt_event): Assume CPU 0 is the one being iterrupted.
620 (sim_close): Do not clear STATE, deleted anyway.
621 (sim_write, sim_read): Assume CPU zero's vm should be used for
623 (sim_create_inferior): Set the PC for all processors.
624 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
626 (mips16_entry): Pass correct nr of args to store_word, load_word.
627 (ColdReset): Cold reset all cpu's.
628 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
629 (sim_monitor, load_memory, store_memory, signal_exception): Use
630 `CPU' instead of STATE_CPU.
633 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
636 * sim-main.h (signal_exception): Add sim_cpu arg.
637 (SignalException*): Pass both SD and CPU to signal_exception.
638 * interp.c (signal_exception): Update.
640 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
642 (sync_operation, prefetch, cache_op, store_memory, load_memory,
643 address_translation): Ditto
644 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
646 start-sanitize-vr5400
647 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
649 (ByteAlign): Use StoreFPR, pass args in correct order.
653 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
655 * configure.in (sim_igen_filter): For r5900, configure as SMP.
658 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
660 * configure: Regenerated to track ../common/aclocal.m4 changes.
662 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
665 * configure.in (sim_igen_filter): For r5900, use igen.
666 * configure: Re-generate.
669 * interp.c (sim_engine_run): Add `nr_cpus' argument.
671 * mips.igen (model): Map processor names onto BFD name.
673 * sim-main.h (CPU_CIA): Delete.
674 (SET_CIA, GET_CIA): Define
676 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
678 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
681 * configure.in (default_endian): Configure a big-endian simulator
683 * configure: Re-generate.
685 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
687 * configure: Regenerated to track ../common/aclocal.m4 changes.
689 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
691 * interp.c (sim_monitor): Handle Densan monitor outbyte
692 and inbyte functions.
694 1997-12-29 Felix Lee <flee@cygnus.com>
696 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
698 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
700 * Makefile.in (tmp-igen): Arrange for $zero to always be
701 reset to zero after every instruction.
703 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
705 * configure: Regenerated to track ../common/aclocal.m4 changes.
708 start-sanitize-vr5400
709 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
711 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
715 start-sanitize-vr5400
716 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
718 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
719 vr5400 with the vr5000 as the default.
722 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
724 * mips.igen (MSUB): Fix to work like MADD.
725 * gencode.c (MSUB): Similarly.
727 start-sanitize-vr5400
728 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
730 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
734 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
736 * configure: Regenerated to track ../common/aclocal.m4 changes.
738 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
740 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
742 start-sanitize-vr5400
743 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
744 (value_cc, store_cc): Implement.
746 * sim-main.h: Add 8*3*8 bit accumulator.
748 * vr5400.igen: Move mdmx instructins from here
749 * mdmx.igen: To here - new file. Add/fix missing instructions.
750 * mips.igen: Include mdmx.igen.
751 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
754 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
756 * sim-main.h (sim-fpu.h): Include.
758 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
759 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
760 using host independant sim_fpu module.
762 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
764 * interp.c (signal_exception): Report internal errors with SIGABRT
767 * sim-main.h (C0_CONFIG): New register.
768 (signal.h): No longer include.
770 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
772 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
774 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
776 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
778 * mips.igen: Tag vr5000 instructions.
779 (ANDI): Was missing mipsIV model, fix assembler syntax.
780 (do_c_cond_fmt): New function.
781 (C.cond.fmt): Handle mips I-III which do not support CC field
783 (bc1): Handle mips IV which do not have a delaed FCC separatly.
784 (SDR): Mask paddr when BigEndianMem, not the converse as specified
786 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
787 vr5000 which saves LO in a GPR separatly.
789 * configure.in (enable-sim-igen): For vr5000, select vr5000
790 specific instructions.
791 * configure: Re-generate.
793 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
795 * Makefile.in (SIM_OBJS): Add sim-fpu module.
797 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
798 fmt_uninterpreted_64 bit cases to switch. Convert to
801 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
803 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
804 as specified in IV3.2 spec.
805 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
807 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
809 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
810 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
811 (start-sanitize-r5900):
812 (LWXC1, SWXC1): Delete from r5900 instruction set.
813 (end-sanitize-r5900):
814 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
815 PENDING_FILL versions of instructions. Simplify.
817 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
819 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
821 (MTHI, MFHI): Disable code checking HI-LO.
823 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
825 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
827 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
829 * gencode.c (build_mips16_operands): Replace IPC with cia.
831 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
832 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
834 (UndefinedResult): Replace function with macro/function
836 (sim_engine_run): Don't save PC in IPC.
838 * sim-main.h (IPC): Delete.
840 start-sanitize-vr5400
841 * vr5400.igen (vr): Add missing cia argument to value_fpr.
842 (do_select): Rename function select.
845 * interp.c (signal_exception, store_word, load_word,
846 address_translation, load_memory, store_memory, cache_op,
847 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
848 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
849 current instruction address - cia - argument.
850 (sim_read, sim_write): Call address_translation directly.
851 (sim_engine_run): Rename variable vaddr to cia.
852 (signal_exception): Pass cia to sim_monitor
854 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
855 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
856 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
858 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
859 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
862 * interp.c (signal_exception): Pass restart address to
865 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
866 idecode.o): Add dependency.
868 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
870 (DELAY_SLOT): Update NIA not PC with branch address.
871 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
873 * mips.igen: Use CIA not PC in branch calculations.
874 (illegal): Call SignalException.
875 (BEQ, ADDIU): Fix assembler.
877 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
879 * m16.igen (JALX): Was missing.
881 * configure.in (enable-sim-igen): New configuration option.
882 * configure: Re-generate.
884 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
886 * interp.c (load_memory, store_memory): Delete parameter RAW.
887 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
888 bypassing {load,store}_memory.
890 * sim-main.h (ByteSwapMem): Delete definition.
892 * Makefile.in (SIM_OBJS): Add sim-memopt module.
894 * interp.c (sim_do_command, sim_commands): Delete mips specific
895 commands. Handled by module sim-options.
897 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
898 (WITH_MODULO_MEMORY): Define.
900 * interp.c (sim_info): Delete code printing memory size.
902 * interp.c (mips_size): Nee sim_size, delete function.
904 (monitor, monitor_base, monitor_size): Delete global variables.
905 (sim_open, sim_close): Delete code creating monitor and other
906 memory regions. Use sim-memopts module, via sim_do_commandf, to
907 manage memory regions.
908 (load_memory, store_memory): Use sim-core for memory model.
910 * interp.c (address_translation): Delete all memory map code
911 except line forcing 32 bit addresses.
913 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
915 * sim-main.h (WITH_TRACE): Delete definition. Enables common
918 * interp.c (logfh, logfile): Delete globals.
919 (sim_open, sim_close): Delete code opening & closing log file.
920 (mips_option_handler): Delete -l and -n options.
921 (OPTION mips_options): Ditto.
923 * interp.c (OPTION mips_options): Rename option trace to dinero.
924 (mips_option_handler): Update.
926 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
928 * interp.c (fetch_str): New function.
929 (sim_monitor): Rewrite using sim_read & sim_write.
930 (sim_open): Check magic number.
931 (sim_open): Write monitor vectors into memory using sim_write.
932 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
933 (sim_read, sim_write): Simplify - transfer data one byte at a
935 (load_memory, store_memory): Clarify meaning of parameter RAW.
937 * sim-main.h (isHOST): Defete definition.
938 (isTARGET): Mark as depreciated.
939 (address_translation): Delete parameter HOST.
941 * interp.c (address_translation): Delete parameter HOST.
944 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
946 * gencode.c: Add tx49 configury and insns.
947 * configure.in: Add tx49 configury.
951 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
955 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
956 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
958 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
960 * mips.igen: Add model filter field to records.
962 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
964 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
966 interp.c (sim_engine_run): Do not compile function sim_engine_run
969 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
972 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
973 igen. Replace with configuration variables sim_igen_flags /
977 * r5900.igen: New file. Copy r5900 insns here.
979 start-sanitize-vr5400
980 * vr5400.igen: New file.
982 * m16.igen: New file. Copy mips16 insns here.
983 * mips.igen: From here.
985 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
987 start-sanitize-vr5400
988 * mips.igen: Tag all mipsIV instructions with vr5400 model.
990 * configure.in: Add mips64vr5400 target.
991 * configure: Re-generate.
994 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
996 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
998 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1000 * gencode.c (build_instruction): Follow sim_write's lead in using
1001 BigEndianMem instead of !ByteSwapMem.
1003 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1005 * configure.in (sim_gen): Dependent on target, select type of
1006 generator. Always select old style generator.
1008 configure: Re-generate.
1010 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1012 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1013 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1014 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1015 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1016 SIM_@sim_gen@_*, set by autoconf.
1018 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1020 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1022 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1023 CURRENT_FLOATING_POINT instead.
1025 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1026 (address_translation): Raise exception InstructionFetch when
1027 translation fails and isINSTRUCTION.
1029 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1030 sim_engine_run): Change type of of vaddr and paddr to
1032 (address_translation, prefetch, load_memory, store_memory,
1033 cache_op): Change type of vAddr and pAddr to address_word.
1035 * gencode.c (build_instruction): Change type of vaddr and paddr to
1038 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1040 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1041 macro to obtain result of ALU op.
1043 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1045 * interp.c (sim_info): Call profile_print.
1047 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1049 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1051 * sim-main.h (WITH_PROFILE): Do not define, defined in
1052 common/sim-config.h. Use sim-profile module.
1053 (simPROFILE): Delete defintion.
1055 * interp.c (PROFILE): Delete definition.
1056 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1057 (sim_close): Delete code writing profile histogram.
1058 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1060 (sim_engine_run): Delete code profiling the PC.
1062 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1064 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1066 * interp.c (sim_monitor): Make register pointers of type
1069 * sim-main.h: Make registers of type unsigned_word not
1072 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1074 start-sanitize-r5900
1075 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1076 ...): Move to sim-main.h
1079 * interp.c (sync_operation): Rename from SyncOperation, make
1080 global, add SD argument.
1081 (prefetch): Rename from Prefetch, make global, add SD argument.
1082 (decode_coproc): Make global.
1084 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1086 * gencode.c (build_instruction): Generate DecodeCoproc not
1087 decode_coproc calls.
1089 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1090 (SizeFGR): Move to sim-main.h
1091 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1092 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1093 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1095 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1096 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1097 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1098 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1099 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1100 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1102 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1104 (sim-alu.h): Include.
1105 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1106 (sim_cia): Typedef to instruction_address.
1108 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1110 * Makefile.in (interp.o): Rename generated file engine.c to
1115 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1117 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1119 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1121 * gencode.c (build_instruction): For "FPSQRT", output correct
1122 number of arguments to Recip.
1124 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1126 * Makefile.in (interp.o): Depends on sim-main.h
1128 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1130 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1131 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1132 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1133 STATE, DSSTATE): Define
1134 (GPR, FGRIDX, ..): Define.
1136 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1137 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1138 (GPR, FGRIDX, ...): Delete macros.
1140 * interp.c: Update names to match defines from sim-main.h
1142 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1144 * interp.c (sim_monitor): Add SD argument.
1145 (sim_warning): Delete. Replace calls with calls to
1147 (sim_error): Delete. Replace calls with sim_io_error.
1148 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1149 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1150 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1152 (mips_size): Rename from sim_size. Add SD argument.
1154 * interp.c (simulator): Delete global variable.
1155 (callback): Delete global variable.
1156 (mips_option_handler, sim_open, sim_write, sim_read,
1157 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1158 sim_size,sim_monitor): Use sim_io_* not callback->*.
1159 (sim_open): ZALLOC simulator struct.
1160 (PROFILE): Do not define.
1162 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1164 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1165 support.h with corresponding code.
1167 * sim-main.h (word64, uword64), support.h: Move definition to
1169 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1172 * Makefile.in: Update dependencies
1173 * interp.c: Do not include.
1175 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1177 * interp.c (address_translation, load_memory, store_memory,
1178 cache_op): Rename to from AddressTranslation et.al., make global,
1181 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1184 * interp.c (SignalException): Rename to signal_exception, make
1187 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1189 * sim-main.h (SignalException, SignalExceptionInterrupt,
1190 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1191 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1192 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1195 * interp.c, support.h: Use.
1197 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1199 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1200 to value_fpr / store_fpr. Add SD argument.
1201 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1202 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1204 * sim-main.h (ValueFPR, StoreFPR): Define.
1206 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1208 * interp.c (sim_engine_run): Check consistency between configure
1209 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1212 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1213 (mips_fpu): Configure WITH_FLOATING_POINT.
1214 (mips_endian): Configure WITH_TARGET_ENDIAN.
1215 * configure: Update.
1217 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219 * configure: Regenerated to track ../common/aclocal.m4 changes.
1221 start-sanitize-r5900
1222 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1224 * interp.c (MAX_REG): Allow up-to 128 registers.
1225 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1226 (REGISTER_SA): Ditto.
1227 (sim_open): Initialize register_widths for r5900 specific
1229 (sim_fetch_register, sim_store_register): Check for request of
1230 r5900 specific SA register. Check for request for hi 64 bits of
1231 r5900 specific registers.
1234 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1236 * configure: Regenerated.
1238 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1240 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1242 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1244 * gencode.c (print_igen_insn_models): Assume certain architectures
1245 include all mips* instructions.
1246 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1249 * Makefile.in (tmp.igen): Add target. Generate igen input from
1252 * gencode.c (FEATURE_IGEN): Define.
1253 (main): Add --igen option. Generate output in igen format.
1254 (process_instructions): Format output according to igen option.
1255 (print_igen_insn_format): New function.
1256 (print_igen_insn_models): New function.
1257 (process_instructions): Only issue warnings and ignore
1258 instructions when no FEATURE_IGEN.
1260 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1262 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1265 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1267 * configure: Regenerated to track ../common/aclocal.m4 changes.
1269 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1271 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1272 SIM_RESERVED_BITS): Delete, moved to common.
1273 (SIM_EXTRA_CFLAGS): Update.
1275 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1277 * configure.in: Configure non-strict memory alignment.
1278 * configure: Regenerated to track ../common/aclocal.m4 changes.
1280 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1282 * configure: Regenerated to track ../common/aclocal.m4 changes.
1284 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1286 * gencode.c (SDBBP,DERET): Added (3900) insns.
1287 (RFE): Turn on for 3900.
1288 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1289 (dsstate): Made global.
1290 (SUBTARGET_R3900): Added.
1291 (CANCELDELAYSLOT): New.
1292 (SignalException): Ignore SystemCall rather than ignore and
1293 terminate. Add DebugBreakPoint handling.
1294 (decode_coproc): New insns RFE, DERET; and new registers Debug
1295 and DEPC protected by SUBTARGET_R3900.
1296 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1298 * Makefile.in,configure.in: Add mips subtarget option.
1299 * configure: Update.
1301 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1303 * gencode.c: Add r3900 (tx39).
1306 * gencode.c: Fix some configuration problems by improving
1307 the relationship between tx19 and tx39.
1310 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1312 * gencode.c (build_instruction): Don't need to subtract 4 for
1315 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1317 * interp.c: Correct some HASFPU problems.
1319 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1321 * configure: Regenerated to track ../common/aclocal.m4 changes.
1323 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1325 * interp.c (mips_options): Fix samples option short form, should
1328 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1330 * interp.c (sim_info): Enable info code. Was just returning.
1332 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1337 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1339 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1341 (build_instruction): Ditto for LL.
1344 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1346 * mips/configure.in, mips/gencode: Add tx19/r1900.
1349 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1351 * configure: Regenerated to track ../common/aclocal.m4 changes.
1353 start-sanitize-r5900
1354 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1357 for overflow due to ABS of MININT, set result to MAXINT.
1358 (build_instruction): For "psrlvw", signextend bit 31.
1361 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1363 * configure: Regenerated to track ../common/aclocal.m4 changes.
1366 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1368 * interp.c (sim_open): Add call to sim_analyze_program, update
1371 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1373 * interp.c (sim_kill): Delete.
1374 (sim_create_inferior): Add ABFD argument. Set PC from same.
1375 (sim_load): Move code initializing trap handlers from here.
1376 (sim_open): To here.
1377 (sim_load): Delete, use sim-hload.c.
1379 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1381 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1383 * configure: Regenerated to track ../common/aclocal.m4 changes.
1386 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1388 * interp.c (sim_open): Add ABFD argument.
1389 (sim_load): Move call to sim_config from here.
1390 (sim_open): To here. Check return status.
1392 start-sanitize-r5900
1393 * gencode.c (build_instruction): Do not define x8000000000000000,
1394 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1397 start-sanitize-r5900
1398 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1401 "pdivuw" check for overflow due to signed divide by -1.
1404 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1406 * gencode.c (build_instruction): Two arg MADD should
1407 not assign result to $0.
1409 start-sanitize-r5900
1410 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1412 * gencode.c (build_instruction): For "ppac5" use unsigned
1413 arrithmetic so that the sign bit doesn't smear when right shifted.
1414 (build_instruction): For "pdiv" perform sign extension when
1415 storing results in HI and LO.
1416 (build_instructions): For "pdiv" and "pdivbw" check for
1418 (build_instruction): For "pmfhl.slw" update hi part of dest
1419 register as well as low part.
1420 (build_instruction): For "pmfhl" portably handle long long values.
1421 (build_instruction): For "pmfhl.sh" correctly negative values.
1422 Store half words 2 and three in the correct place.
1423 (build_instruction): For "psllvw", sign extend value after shift.
1426 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1428 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1429 * sim/mips/configure.in: Regenerate.
1431 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1433 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1434 signed8, unsigned8 et.al. types.
1436 start-sanitize-r5900
1437 * gencode.c (build_instruction): For PMULTU* do not sign extend
1438 registers. Make generated code easier to debug.
1441 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1442 hosts when selecting subreg.
1444 start-sanitize-r5900
1445 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1447 * gencode.c (type_for_data_len): For 32bit operations concerned
1448 with overflow, perform op using 64bits.
1449 (build_instruction): For PADD, always compute operation using type
1450 returned by type_for_data_len.
1451 (build_instruction): For PSUBU, when overflow, saturate to zero as
1455 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1457 start-sanitize-r5900
1458 * gencode.c (build_instruction): Handle "pext5" according to
1459 version 1.95 of the r5900 ISA.
1461 * gencode.c (build_instruction): Handle "ppac5" according to
1462 version 1.95 of the r5900 ISA.
1465 * interp.c (sim_engine_run): Reset the ZERO register to zero
1466 regardless of FEATURE_WARN_ZERO.
1467 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1469 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1471 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1472 (SignalException): For BreakPoints ignore any mode bits and just
1474 (SignalException): Always set the CAUSE register.
1476 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1478 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1479 exception has been taken.
1481 * interp.c: Implement the ERET and mt/f sr instructions.
1483 start-sanitize-r5900
1484 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1486 * gencode.c (build_instruction): For paddu, extract unsigned
1489 * gencode.c (build_instruction): Saturate padds instead of padd
1493 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495 * interp.c (SignalException): Don't bother restarting an
1498 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500 * interp.c (SignalException): Really take an interrupt.
1501 (interrupt_event): Only deliver interrupts when enabled.
1503 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1505 * interp.c (sim_info): Only print info when verbose.
1506 (sim_info) Use sim_io_printf for output.
1508 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1513 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1515 * interp.c (sim_do_command): Check for common commands if a
1516 simulator specific command fails.
1518 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1520 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1521 and simBE when DEBUG is defined.
1523 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525 * interp.c (interrupt_event): New function. Pass exception event
1526 onto exception handler.
1528 * configure.in: Check for stdlib.h.
1529 * configure: Regenerate.
1531 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1532 variable declaration.
1533 (build_instruction): Initialize memval1.
1534 (build_instruction): Add UNUSED attribute to byte, bigend,
1536 (build_operands): Ditto.
1538 * interp.c: Fix GCC warnings.
1539 (sim_get_quit_code): Delete.
1541 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1542 * Makefile.in: Ditto.
1543 * configure: Re-generate.
1545 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1547 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1549 * interp.c (mips_option_handler): New function parse argumes using
1551 (myname): Replace with STATE_MY_NAME.
1552 (sim_open): Delete check for host endianness - performed by
1554 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1555 (sim_open): Move much of the initialization from here.
1556 (sim_load): To here. After the image has been loaded and
1558 (sim_open): Move ColdReset from here.
1559 (sim_create_inferior): To here.
1560 (sim_open): Make FP check less dependant on host endianness.
1562 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1564 * interp.c (sim_set_callbacks): Delete.
1566 * interp.c (membank, membank_base, membank_size): Replace with
1567 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1568 (sim_open): Remove call to callback->init. gdb/run do this.
1572 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1574 * interp.c (big_endian_p): Delete, replaced by
1575 current_target_byte_order.
1577 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1579 * interp.c (host_read_long, host_read_word, host_swap_word,
1580 host_swap_long): Delete. Using common sim-endian.
1581 (sim_fetch_register, sim_store_register): Use H2T.
1582 (pipeline_ticks): Delete. Handled by sim-events.
1584 (sim_engine_run): Update.
1586 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1590 (SignalException): To here. Signal using sim_engine_halt.
1591 (sim_stop_reason): Delete, moved to common.
1593 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1595 * interp.c (sim_open): Add callback argument.
1596 (sim_set_callbacks): Delete SIM_DESC argument.
1599 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601 * Makefile.in (SIM_OBJS): Add common modules.
1603 * interp.c (sim_set_callbacks): Also set SD callback.
1604 (set_endianness, xfer_*, swap_*): Delete.
1605 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1606 Change to functions using sim-endian macros.
1607 (control_c, sim_stop): Delete, use common version.
1608 (simulate): Convert into.
1609 (sim_engine_run): This function.
1610 (sim_resume): Delete.
1612 * interp.c (simulation): New variable - the simulator object.
1613 (sim_kind): Delete global - merged into simulation.
1614 (sim_load): Cleanup. Move PC assignment from here.
1615 (sim_create_inferior): To here.
1617 * sim-main.h: New file.
1618 * interp.c (sim-main.h): Include.
1620 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1622 * configure: Regenerated to track ../common/aclocal.m4 changes.
1624 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1626 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1628 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1630 * gencode.c (build_instruction): DIV instructions: check
1631 for division by zero and integer overflow before using
1632 host's division operation.
1634 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1636 * Makefile.in (SIM_OBJS): Add sim-load.o.
1637 * interp.c: #include bfd.h.
1638 (target_byte_order): Delete.
1639 (sim_kind, myname, big_endian_p): New static locals.
1640 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1641 after argument parsing. Recognize -E arg, set endianness accordingly.
1642 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1643 load file into simulator. Set PC from bfd.
1644 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1645 (set_endianness): Use big_endian_p instead of target_byte_order.
1647 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649 * interp.c (sim_size): Delete prototype - conflicts with
1650 definition in remote-sim.h. Correct definition.
1652 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1654 * configure: Regenerated to track ../common/aclocal.m4 changes.
1657 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1659 * interp.c (sim_open): New arg `kind'.
1661 * configure: Regenerated to track ../common/aclocal.m4 changes.
1663 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1665 * configure: Regenerated to track ../common/aclocal.m4 changes.
1667 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1669 * interp.c (sim_open): Set optind to 0 before calling getopt.
1671 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1673 * configure: Regenerated to track ../common/aclocal.m4 changes.
1675 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1677 * interp.c : Replace uses of pr_addr with pr_uword64
1678 where the bit length is always 64 independent of SIM_ADDR.
1679 (pr_uword64) : added.
1681 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1683 * configure: Re-generate.
1685 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1687 * configure: Regenerate to track ../common/aclocal.m4 changes.
1689 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1691 * interp.c (sim_open): New SIM_DESC result. Argument is now
1693 (other sim_*): New SIM_DESC argument.
1695 start-sanitize-r5900
1696 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1698 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1699 Change values to avoid overloading DOUBLEWORD which is tested
1701 * gencode.c: reinstate "offending code".
1704 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1706 * interp.c: Fix printing of addresses for non-64-bit targets.
1707 (pr_addr): Add function to print address based on size.
1708 start-sanitize-r5900
1709 * gencode.c: #ifdef out offending code until a permanent fix
1710 can be added. Code is causing build errors for non-5900 mips targets.
1713 start-sanitize-r5900
1714 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1716 * gencode.c (process_instructions): Correct test for ISA dependent
1717 architecture bits in isa field of MIPS_DECODE.
1720 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1722 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1724 start-sanitize-r5900
1725 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1727 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1731 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1733 * gencode.c (build_mips16_operands): Correct computation of base
1734 address for extended PC relative instruction.
1736 start-sanitize-r5900
1737 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1739 * Makefile.in, configure, configure.in, gencode.c,
1740 interp.c, support.h: add r5900.
1743 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1745 * interp.c (mips16_entry): Add support for floating point cases.
1746 (SignalException): Pass floating point cases to mips16_entry.
1747 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1749 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1751 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1752 and then set the state to fmt_uninterpreted.
1753 (COP_SW): Temporarily set the state to fmt_word while calling
1756 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1758 * gencode.c (build_instruction): The high order may be set in the
1759 comparison flags at any ISA level, not just ISA 4.
1761 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1763 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1764 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1765 * configure.in: sinclude ../common/aclocal.m4.
1766 * configure: Regenerated.
1768 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1770 * configure: Rebuild after change to aclocal.m4.
1772 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1774 * configure configure.in Makefile.in: Update to new configure
1775 scheme which is more compatible with WinGDB builds.
1776 * configure.in: Improve comment on how to run autoconf.
1777 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1778 * Makefile.in: Use autoconf substitution to install common
1781 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1783 * gencode.c (build_instruction): Use BigEndianCPU instead of
1786 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1788 * interp.c (sim_monitor): Make output to stdout visible in
1789 wingdb's I/O log window.
1791 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1793 * support.h: Undo previous change to SIGTRAP
1796 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1798 * interp.c (store_word, load_word): New static functions.
1799 (mips16_entry): New static function.
1800 (SignalException): Look for mips16 entry and exit instructions.
1801 (simulate): Use the correct index when setting fpr_state after
1802 doing a pending move.
1804 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1806 * interp.c: Fix byte-swapping code throughout to work on
1807 both little- and big-endian hosts.
1809 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1811 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1812 with gdb/config/i386/xm-windows.h.
1814 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1816 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1817 that messes up arithmetic shifts.
1819 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1821 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1822 SIGTRAP and SIGQUIT for _WIN32.
1824 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1826 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1827 force a 64 bit multiplication.
1828 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1829 destination register is 0, since that is the default mips16 nop
1832 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1834 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1835 (build_endian_shift): Don't check proc64.
1836 (build_instruction): Always set memval to uword64. Cast op2 to
1837 uword64 when shifting it left in memory instructions. Always use
1838 the same code for stores--don't special case proc64.
1840 * gencode.c (build_mips16_operands): Fix base PC value for PC
1842 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1844 * interp.c (simJALDELAYSLOT): Define.
1845 (JALDELAYSLOT): Define.
1846 (INDELAYSLOT, INJALDELAYSLOT): Define.
1847 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1849 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1851 * interp.c (sim_open): add flush_cache as a PMON routine
1852 (sim_monitor): handle flush_cache by ignoring it
1854 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1856 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1858 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1859 (BigEndianMem): Rename to ByteSwapMem and change sense.
1860 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1861 BigEndianMem references to !ByteSwapMem.
1862 (set_endianness): New function, with prototype.
1863 (sim_open): Call set_endianness.
1864 (sim_info): Use simBE instead of BigEndianMem.
1865 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1866 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1867 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1868 ifdefs, keeping the prototype declaration.
1869 (swap_word): Rewrite correctly.
1870 (ColdReset): Delete references to CONFIG. Delete endianness related
1871 code; moved to set_endianness.
1873 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1875 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1876 * interp.c (CHECKHILO): Define away.
1877 (simSIGINT): New macro.
1878 (membank_size): Increase from 1MB to 2MB.
1879 (control_c): New function.
1880 (sim_resume): Rename parameter signal to signal_number. Add local
1881 variable prev. Call signal before and after simulate.
1882 (sim_stop_reason): Add simSIGINT support.
1883 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1885 (sim_warning): Delete call to SignalException. Do call printf_filtered
1887 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1888 a call to sim_warning.
1890 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1892 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1893 16 bit instructions.
1895 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1897 Add support for mips16 (16 bit MIPS implementation):
1898 * gencode.c (inst_type): Add mips16 instruction encoding types.
1899 (GETDATASIZEINSN): Define.
1900 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1901 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1903 (MIPS16_DECODE): New table, for mips16 instructions.
1904 (bitmap_val): New static function.
1905 (struct mips16_op): Define.
1906 (mips16_op_table): New table, for mips16 operands.
1907 (build_mips16_operands): New static function.
1908 (process_instructions): If PC is odd, decode a mips16
1909 instruction. Break out instruction handling into new
1910 build_instruction function.
1911 (build_instruction): New static function, broken out of
1912 process_instructions. Check modifiers rather than flags for SHIFT
1913 bit count and m[ft]{hi,lo} direction.
1914 (usage): Pass program name to fprintf.
1915 (main): Remove unused variable this_option_optind. Change
1916 ``*loptarg++'' to ``loptarg++''.
1917 (my_strtoul): Parenthesize && within ||.
1918 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1919 (simulate): If PC is odd, fetch a 16 bit instruction, and
1920 increment PC by 2 rather than 4.
1921 * configure.in: Add case for mips16*-*-*.
1922 * configure: Rebuild.
1924 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1926 * interp.c: Allow -t to enable tracing in standalone simulator.
1927 Fix garbage output in trace file and error messages.
1929 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1931 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1932 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1933 * configure.in: Simplify using macros in ../common/aclocal.m4.
1934 * configure: Regenerated.
1935 * tconfig.in: New file.
1937 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1939 * interp.c: Fix bugs in 64-bit port.
1940 Use ansi function declarations for msvc compiler.
1941 Initialize and test file pointer in trace code.
1942 Prevent duplicate definition of LAST_EMED_REGNUM.
1944 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1946 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1948 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1950 * interp.c (SignalException): Check for explicit terminating
1952 * gencode.c: Pass instruction value through SignalException()
1953 calls for Trap, Breakpoint and Syscall.
1955 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1957 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1958 only used on those hosts that provide it.
1959 * configure.in: Add sqrt() to list of functions to be checked for.
1960 * config.in: Re-generated.
1961 * configure: Re-generated.
1963 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1965 * gencode.c (process_instructions): Call build_endian_shift when
1966 expanding STORE RIGHT, to fix swr.
1967 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1968 clear the high bits.
1969 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1970 Fix float to int conversions to produce signed values.
1972 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1974 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1975 (process_instructions): Correct handling of nor instruction.
1976 Correct shift count for 32 bit shift instructions. Correct sign
1977 extension for arithmetic shifts to not shift the number of bits in
1978 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1979 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1981 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1982 It's OK to have a mult follow a mult. What's not OK is to have a
1983 mult follow an mfhi.
1984 (Convert): Comment out incorrect rounding code.
1986 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1988 * interp.c (sim_monitor): Improved monitor printf
1989 simulation. Tidied up simulator warnings, and added "--log" option
1990 for directing warning message output.
1991 * gencode.c: Use sim_warning() rather than WARNING macro.
1993 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1995 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1996 getopt1.o, rather than on gencode.c. Link objects together.
1997 Don't link against -liberty.
1998 (gencode.o, getopt.o, getopt1.o): New targets.
1999 * gencode.c: Include <ctype.h> and "ansidecl.h".
2000 (AND): Undefine after including "ansidecl.h".
2001 (ULONG_MAX): Define if not defined.
2002 (OP_*): Don't define macros; now defined in opcode/mips.h.
2003 (main): Call my_strtoul rather than strtoul.
2004 (my_strtoul): New static function.
2006 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2008 * gencode.c (process_instructions): Generate word64 and uword64
2009 instead of `long long' and `unsigned long long' data types.
2010 * interp.c: #include sysdep.h to get signals, and define default
2012 * (Convert): Work around for Visual-C++ compiler bug with type
2014 * support.h: Make things compile under Visual-C++ by using
2015 __int64 instead of `long long'. Change many refs to long long
2016 into word64/uword64 typedefs.
2018 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2020 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2021 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2023 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2024 (AC_PROG_INSTALL): Added.
2025 (AC_PROG_CC): Moved to before configure.host call.
2026 * configure: Rebuilt.
2028 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2030 * configure.in: Define @SIMCONF@ depending on mips target.
2031 * configure: Rebuild.
2032 * Makefile.in (run): Add @SIMCONF@ to control simulator
2034 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2035 * interp.c: Remove some debugging, provide more detailed error
2036 messages, update memory accesses to use LOADDRMASK.
2038 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2040 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2041 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2043 * configure: Rebuild.
2044 * config.in: New file, generated by autoheader.
2045 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2046 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2047 HAVE_ANINT and HAVE_AINT, as appropriate.
2048 * Makefile.in (run): Use @LIBS@ rather than -lm.
2049 (interp.o): Depend upon config.h.
2050 (Makefile): Just rebuild Makefile.
2051 (clean): Remove stamp-h.
2052 (mostlyclean): Make the same as clean, not as distclean.
2053 (config.h, stamp-h): New targets.
2055 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2057 * interp.c (ColdReset): Fix boolean test. Make all simulator
2060 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2062 * interp.c (xfer_direct_word, xfer_direct_long,
2063 swap_direct_word, swap_direct_long, xfer_big_word,
2064 xfer_big_long, xfer_little_word, xfer_little_long,
2065 swap_word,swap_long): Added.
2066 * interp.c (ColdReset): Provide function indirection to
2067 host<->simulated_target transfer routines.
2068 * interp.c (sim_store_register, sim_fetch_register): Updated to
2069 make use of indirected transfer routines.
2071 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2073 * gencode.c (process_instructions): Ensure FP ABS instruction
2075 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2076 system call support.
2078 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2080 * interp.c (sim_do_command): Complain if callback structure not
2083 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2085 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2086 support for Sun hosts.
2087 * Makefile.in (gencode): Ensure the host compiler and libraries
2088 used for cross-hosted build.
2090 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2092 * interp.c, gencode.c: Some more (TODO) tidying.
2094 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2096 * gencode.c, interp.c: Replaced explicit long long references with
2097 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2098 * support.h (SET64LO, SET64HI): Macros added.
2100 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2102 * configure: Regenerate with autoconf 2.7.
2104 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2106 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2107 * support.h: Remove superfluous "1" from #if.
2108 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2110 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2112 * interp.c (StoreFPR): Control UndefinedResult() call on
2113 WARN_RESULT manifest.
2115 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2117 * gencode.c: Tidied instruction decoding, and added FP instruction
2120 * interp.c: Added dineroIII, and BSD profiling support. Also
2121 run-time FP handling.
2123 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2125 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2126 gencode.c, interp.c, support.h: created.