sim/mips/ChangeLog

   1 2007-05-15  Thiemo Seufer  <ths@mips.com>
   2
   3         * mips3264r2.igen (DSHD): Fix compile warning.
   4
   5 2007-05-14  Thiemo Seufer  <ths@mips.com>
   6
   7         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
   8         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
   9         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
  10         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
  11         for mips32r2.
  12
  13 2007-03-01  Thiemo Seufer  <ths@mips.com>
  14
  15         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
  16         and mips64.
  17
  18 2007-02-20  Thiemo Seufer  <ths@mips.com>
  19
  20         * dsp.igen: Update copyright notice.
  21         * dsp2.igen: Fix copyright notice.
  22
  23 2007-02-20  Thiemo Seufer  <ths@mips.com>
  24             Chao-Ying Fu  <fu@mips.com>
  25
  26         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
  27         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  28         Add dsp2 to sim_igen_machine.
  29         * configure: Regenerate.
  30         * dsp.igen (do_ph_op): Add MUL support when op = 2.
  31         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
  32         (mulq_rs.ph): Use do_ph_mulq.
  33         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
  34         * mips.igen: Add dsp2 model and include dsp2.igen.
  35         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
  36         for *mips32r2, *mips64r2, *dsp.
  37         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
  38         for *mips32r2, *mips64r2, *dsp2.
  39         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
  40
  41 2007-02-19  Thiemo Seufer  <ths@mips.com>
  42             Nigel Stephens  <nigel@mips.com>
  43
  44         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
  45         jumps with hazard barrier.
  46
  47 2007-02-19  Thiemo Seufer  <ths@mips.com>
  48             Nigel Stephens  <nigel@mips.com>
  49
  50         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
  51         after each call to sim_io_write.
  52
  53 2007-02-19  Thiemo Seufer  <ths@mips.com>
  54             Nigel Stephens  <nigel@mips.com>
  55
  56         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
  57         supported by this simulator.
  58         (decode_coproc): Recognise additional CP0 Config registers
  59         correctly.
  60
  61 2007-02-19  Thiemo Seufer  <ths@mips.com>
  62             Nigel Stephens  <nigel@mips.com>
  63             David Ung  <davidu@mips.com>
  64
  65         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
  66         uninterpreted formats. If fmt is one of the uninterpreted types
  67         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
  68         fmt_word, and fmt_uninterpreted_64 like fmt_long.
  69         (store_fpr): When writing an invalid odd register, set the
  70         matching even register to fmt_unknown, not the following register.
  71         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
  72         the the memory window at offset 0 set by --memory-size command
  73         line option.
  74         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
  75         point register.
  76         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
  77         register.
  78         (sim_monitor): When returning the memory size to the MIPS
  79         application, use the value in STATE_MEM_SIZE, not an arbitrary
  80         hardcoded value.
  81         (cop_lw): Don' mess around with FPR_STATE, just pass
  82         fmt_uninterpreted_32 to StoreFPR.
  83         (cop_sw): Similarly.
  84         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
  85         (cop_sd): Similarly.
  86         * mips.igen (not_word_value): Single version for mips32, mips64
  87         and mips16.
  88
  89 2007-02-19  Thiemo Seufer <ths@mips.com>
  90             Nigel Stephens  <nigel@mips.com>
  91
  92         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
  93         MBytes.
  94
  95 2007-02-17  Thiemo Seufer  <ths@mips.com>
  96
  97         * configure.ac (mips*-sde-elf*): Move in front of generic machine
  98         configuration.
  99         * configure: Regenerate.
 100
 101 2007-02-17  Thiemo Seufer  <ths@mips.com>
 102
 103         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 104         Add mdmx to sim_igen_machine.
 105         (mipsisa64*-*-*): Likewise. Remove dsp.
 106         (mipsisa32*-*-*): Remove dsp.
 107         * configure: Regenerate.
 108
 109 2007-02-13  Thiemo Seufer  <ths@mips.com>
 110
 111         * configure.ac: Add mips*-sde-elf* target.
 112         * configure: Regenerate.
 113
 114 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 115
 116         * acconfig.h: Remove.
 117         * config.in, configure: Regenerate.
 118
 119 2006-11-07  Thiemo Seufer  <ths@mips.com>
 120
 121         * dsp.igen (do_w_op): Fix compiler warning.
 122
 123 2006-08-29  Thiemo Seufer  <ths@mips.com>
 124             David Ung  <davidu@mips.com>
 125
 126         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 127         sim_igen_machine.
 128         * configure: Regenerate.
 129         * mips.igen (model): Add smartmips.
 130         (MADDU): Increment ACX if carry.
 131         (do_mult): Clear ACX.
 132         (ROR,RORV): Add smartmips.
 133         (include): Include smartmips.igen.
 134         * sim-main.h (ACX): Set to REGISTERS[89].
 135         * smartmips.igen: New file.
 136
 137 2006-08-29  Thiemo Seufer  <ths@mips.com>
 138             David Ung  <davidu@mips.com>
 139
 140         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 141         mips3264r2.igen. Add missing dependency rules.
 142         * m16e.igen: Support for mips16e save/restore instructions.
 143
 144 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 145
 146         * configure: Regenerated.
 147
 148 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 149
 150         * configure: Regenerated.
 151
 152 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 153
 154         * configure: Regenerated.
 155
 156 2006-05-15 Chao-ying Fu  <fu@mips.com>
 157
 158         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 159
 160 2006-04-18  Nick Clifton  <nickc@redhat.com>
 161
 162         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 163         statement.
 164
 165 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 166
 167         * configure: Regenerate.
 168
 169 2005-12-14  Chao-ying Fu  <fu@mips.com>
 170
 171         * Makefile.in (SIM_OBJS): Add dsp.o.
 172         (dsp.o): New dependency.
 173         (IGEN_INCLUDE): Add dsp.igen.
 174         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 175         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 176         * configure: Regenerate.
 177         * mips.igen: Add dsp model and include dsp.igen.
 178         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 179         because these instructions are extended in DSP ASE.
 180         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 181         adding 6 DSP accumulator registers and 1 DSP control register.
 182         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 183         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 184         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 185         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 186         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 187         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 188         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 189         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 190         DSPCR_CCOND_SMASK): New define.
 191         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 192         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 193
 194 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 195
 196         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 197
 198 2005-06-16  David Ung  <davidu@mips.com>
 199             Nigel Stephens  <nigel@mips.com>
 200
 201         * mips.igen: New mips16e model and include m16e.igen.
 202         (check_u64): Add mips16e tag.
 203         * m16e.igen: New file for MIPS16e instructions.
 204         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 205         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 206         models.
 207         * configure: Regenerate.
 208
 209 2005-05-26  David Ung  <davidu@mips.com>
 210
 211         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 212         tags to all instructions which are applicable to the new ISAs.
 213         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 214         vr.igen.
 215         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 216         instructions.
 217         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 218         to mips.igen.
 219         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 220         * configure: Regenerate.
 221
 222 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 223
 224         * configure: Regenerate.
 225
 226 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 227
 228         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 229         explicit call to AC_CONFIG_HEADER.
 230         * configure: Regenerate.
 231
 232 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 233
 234         * configure.ac: Update to use ../common/common.m4.
 235         * configure: Re-generate.
 236
 237 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 238
 239         * configure: Regenerated to track ../common/aclocal.m4 changes.
 240
 241 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 242
 243         * configure.ac: Rename configure.in, require autoconf 2.59.
 244         * configure: Re-generate.
 245
 246 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 247
 248         * configure: Regenerate for ../common/aclocal.m4 update.
 249
 250 2004-09-24  Monika Chaddha  <monika@acmet.com>
 251
 252         Committed by Andrew Cagney.
 253         * m16.igen (CMP, CMPI): Fix assembler.
 254
 255 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 256
 257         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 258         * configure: Regenerate.
 259
 260 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 261
 262         * configure.in (sim_m16_machine): Include mipsIII.
 263         * configure: Regenerate.
 264
 265 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 266
 267         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 268         from COP0_BADVADDR.
 269         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 270
 271 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 272
 273         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 274
 275 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 276
 277         * mips.igen (check_fmt): Remove.
 278         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 279         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 280         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 281         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 282         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 283         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 284         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 285         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 286         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 287         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 288
 289 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 290
 291         * sb1.igen (check_sbx): New function.
 292         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 293
 294 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 295             Richard Sandiford  <rsandifo@redhat.com>
 296
 297         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 298         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 299         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 300         separate implementations for mipsIV and mipsV.  Use new macros to
 301         determine whether the restrictions apply.
 302
 303 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 304
 305         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 306         (check_mult_hilo): Improve comments.
 307         (check_div_hilo): Likewise.  Also, fork off a new version
 308         to handle mips32/mips64 (since there are no hazards to check
 309         in MIPS32/MIPS64).
 310
 311 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 312
 313         * mips.igen (do_dmultx): Fix check for negative operands.
 314
 315 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 316
 317         * Makefile.in (SHELL): Make sure this is defined.
 318         (various): Use $(SHELL) whenever we invoke move-if-change.
 319
 320 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 321
 322         * cp1.c: Tweak attribution slightly.
 323         * cp1.h: Likewise.
 324         * mdmx.c: Likewise.
 325         * mdmx.igen: Likewise.
 326         * mips3d.igen: Likewise.
 327         * sb1.igen: Likewise.
 328
 329 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 330
 331         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 332         unsigned operands.
 333
 334 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 335
 336         * interp.c (sim_open): Rename _bfd to bfd.
 337         (sim_create_inferior): Ditto.
 338
 339 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 340
 341         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 342
 343 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 344
 345         * mips.igen (EI, DI): Remove.
 346
 347 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 348
 349         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 350
 351 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 352             Andrew Cagney  <ac131313@redhat.com>
 353             Gavin Romig-Koch  <gavin@redhat.com>
 354             Graydon Hoare  <graydon@redhat.com>
 355             Aldy Hernandez  <aldyh@redhat.com>
 356             Dave Brolley  <brolley@redhat.com>
 357             Chris Demetriou  <cgd@broadcom.com>
 358
 359         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 360         (sim_mach_default): New variable.
 361         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 362         Add a new simulator generator, MULTI.
 363         * configure: Regenerate.
 364         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 365         (multi-run.o): New dependency.
 366         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 367         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 368         (tmp-multi): Combine them.
 369         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 370         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 371         (distclean-extra): New rule.
 372         * sim-main.h: Include bfd.h.
 373         (MIPS_MACH): New macro.
 374         * mips.igen (vr4120, vr5400, vr5500): New models.
 375         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 376         * vr.igen: Replace with new version.
 377
 378 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 379
 380         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 381         * configure: Regenerate.
 382
 383 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 386         * mips.igen: Remove all invocations of check_branch_bug and
 387         mark_branch_bug.
 388
 389 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 390
 391         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 392
 393 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 394
 395         * mips.igen (do_load_double, do_store_double): New functions.
 396         (LDC1, SDC1): Rename to...
 397         (LDC1b, SDC1b): respectively.
 398         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 399
 400 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 401
 402         * cp1.c (fp_recip2): Modify initialization expression so that
 403         GCC will recognize it as constant.
 404
 405 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 406
 407         * mdmx.c (SD_): Delete.
 408         (Unpredictable): Re-define, for now, to directly invoke
 409         unpredictable_action().
 410         (mdmx_acc_op): Fix error in .ob immediate handling.
 411
 412 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 413
 414         * interp.c (sim_firmware_command): Initialize `address'.
 415
 416 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 417
 418         * configure: Regenerated to track ../common/aclocal.m4 changes.
 419
 420 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 421             Ed Satterthwaite  <ehs@broadcom.com>
 422
 423         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 424         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 425         * mips.igen: Include mips3d.igen.
 426         (mips3d): New model name for MIPS-3D ASE instructions.
 427         (CVT.W.fmt): Don't use this instruction for word (source) format
 428         instructions.
 429         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 430         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 431         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 432         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 433         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 434         (RSquareRoot1, RSquareRoot2): New macros.
 435         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 436         (fp_rsqrt2): New functions.
 437         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 438         * configure: Regenerate.
 439
 440 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 441             Ed Satterthwaite  <ehs@broadcom.com>
 442
 443         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 444         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 445         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 446         (convert): Note that this function is not used for paired-single
 447         format conversions.
 448         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 449         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 450         (check_fmt_p): Enable paired-single support.
 451         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 452         (PUU.PS): New instructions.
 453         (CVT.S.fmt): Don't use this instruction for paired-single format
 454         destinations.
 455         * sim-main.h (FP_formats): New value 'fmt_ps.'
 456         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 457         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 458
 459 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 460
 461         * mips.igen: Fix formatting of function calls in
 462         many FP operations.
 463
 464 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 465
 466         * mips.igen (MOVN, MOVZ): Trace result.
 467         (TNEI): Print "tnei" as the opcode name in traces.
 468         (CEIL.W): Add disassembly string for traces.
 469         (RSQRT.fmt): Make location of disassembly string consistent
 470         with other instructions.
 471
 472 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 473
 474         * mips.igen (X): Delete unused function.
 475
 476 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 477
 478         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 479
 480 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 481             Ed Satterthwaite  <ehs@broadcom.com>
 482
 483         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 484         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 485         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 486         (fp_nmsub): New prototypes.
 487         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 488         (NegMultiplySub): New defines.
 489         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 490         (MADD.D, MADD.S): Replace with...
 491         (MADD.fmt): New instruction.
 492         (MSUB.D, MSUB.S): Replace with...
 493         (MSUB.fmt): New instruction.
 494         (NMADD.D, NMADD.S): Replace with...
 495         (NMADD.fmt): New instruction.
 496         (NMSUB.D, MSUB.S): Replace with...
 497         (NMSUB.fmt): New instruction.
 498
 499 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 500             Ed Satterthwaite  <ehs@broadcom.com>
 501
 502         * cp1.c: Fix more comment spelling and formatting.
 503         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 504         (denorm_mode): New function.
 505         (fpu_unary, fpu_binary): Round results after operation, collect
 506         status from rounding operations, and update the FCSR.
 507         (convert): Collect status from integer conversions and rounding
 508         operations, and update the FCSR.  Adjust NaN values that result
 509         from conversions.  Convert to use sim_io_eprintf rather than
 510         fprintf, and remove some debugging code.
 511         * cp1.h (fenr_FS): New define.
 512
 513 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 514
 515         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 516         rounding mode to sim FP rounding mode flag conversion code into...
 517         (rounding_mode): New function.
 518
 519 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 520
 521         * cp1.c: Clean up formatting of a few comments.
 522         (value_fpr): Reformat switch statement.
 523
 524 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 525             Ed Satterthwaite  <ehs@broadcom.com>
 526
 527         * cp1.h: New file.
 528         * sim-main.h: Include cp1.h.
 529         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 530         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 531         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 532         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 533         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 534         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 535         * cp1.c: Don't include sim-fpu.h; already included by
 536         sim-main.h.  Clean up formatting of some comments.
 537         (NaN, Equal, Less): Remove.
 538         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 539         (fp_cmp): New functions.
 540         * mips.igen (do_c_cond_fmt): Remove.
 541         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 542         Compare.  Add result tracing.
 543         (CxC1): Remove, replace with...
 544         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 545         (DMxC1): Remove, replace with...
 546         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 547         (MxC1): Remove, replace with...
 548         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 549
 550 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 551
 552         * sim-main.h (FGRIDX): Remove, replace all uses with...
 553         (FGR_BASE): New macro.
 554         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 555         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 556         (NR_FGR, FGR): Likewise.
 557         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 558         * mips.igen: Likewise.
 559
 560 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 561
 562         * cp1.c: Add an FSF Copyright notice to this file.
 563
 564 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 565             Ed Satterthwaite  <ehs@broadcom.com>
 566
 567         * cp1.c (Infinity): Remove.
 568         * sim-main.h (Infinity): Likewise.
 569
 570         * cp1.c (fp_unary, fp_binary): New functions.
 571         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 572         (fp_sqrt): New functions, implemented in terms of the above.
 573         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 574         (Recip, SquareRoot): Remove (replaced by functions above).
 575         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 576         (fp_recip, fp_sqrt): New prototypes.
 577         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 578         (Recip, SquareRoot): Replace prototypes with #defines which
 579         invoke the functions above.
 580
 581 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 582
 583         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 584         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 585         file, remove PARAMS from prototypes.
 586         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 587         simulator state arguments.
 588         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 589         pass simulator state arguments.
 590         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 591         (store_fpr, convert): Remove 'sd' argument.
 592         (value_fpr): Likewise.  Convert to use 'SD' instead.
 593
 594 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 595
 596         * cp1.c (Min, Max): Remove #if 0'd functions.
 597         * sim-main.h (Min, Max): Remove.
 598
 599 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 600
 601         * cp1.c: fix formatting of switch case and default labels.
 602         * interp.c: Likewise.
 603         * sim-main.c: Likewise.
 604
 605 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 606
 607         * cp1.c: Clean up comments which describe FP formats.
 608          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 609
 610 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 611             Ed Satterthwaite  <ehs@broadcom.com>
 612
 613         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 614         Broadcom SiByte SB-1 processor configurations.
 615         * configure: Regenerate.
 616         * sb1.igen: New file.
 617         * mips.igen: Include sb1.igen.
 618         (sb1): New model.
 619         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 620         * mdmx.igen: Add "sb1" model to all appropriate functions and
 621         instructions.
 622         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 623         (ob_func, ob_acc): Reference the above.
 624         (qh_acc): Adjust to keep the same size as ob_acc.
 625         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 626         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 627
 628 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 629
 630         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 631
 632 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 633             Ed Satterthwaite  <ehs@broadcom.com>
 634
 635         * mips.igen (mdmx): New (pseudo-)model.
 636         * mdmx.c, mdmx.igen: New files.
 637         * Makefile.in (SIM_OBJS): Add mdmx.o.
 638         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 639         New typedefs.
 640         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 641         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 642         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 643         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 644         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 645         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 646         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 647         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 648         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 649         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 650         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 651         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 652         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 653         (qh_fmtsel): New macros.
 654         (_sim_cpu): New member "acc".
 655         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 656         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 657
 658 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 659
 660         * interp.c: Use 'deprecated' rather than 'depreciated.'
 661         * sim-main.h: Likewise.
 662
 663 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 664
 665         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 666         which wouldn't compile anyway.
 667         * sim-main.h (unpredictable_action): New function prototype.
 668         (Unpredictable): Define to call igen function unpredictable().
 669         (NotWordValue): New macro to call igen function not_word_value().
 670         (UndefinedResult): Remove.
 671         * interp.c (undefined_result): Remove.
 672         (unpredictable_action): New function.
 673         * mips.igen (not_word_value, unpredictable): New functions.
 674         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 675         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 676         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 677         NotWordValue() to check for unpredictable inputs, then
 678         Unpredictable() to handle them.
 679
 680 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 681
 682         * mips.igen: Fix formatting of calls to Unpredictable().
 683
 684 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 685
 686         * interp.c (sim_open): Revert previous change.
 687
 688 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 689
 690         * interp.c (sim_open): Disable chunk of code that wrote code in
 691         vector table entries.
 692
 693 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 694
 695         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 696         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 697         unused definitions.
 698
 699 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 700
 701         * cp1.c: Fix many formatting issues.
 702
 703 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 704
 705         * cp1.c (fpu_format_name): New function to replace...
 706         (DOFMT): This.  Delete, and update all callers.
 707         (fpu_rounding_mode_name): New function to replace...
 708         (RMMODE): This.  Delete, and update all callers.
 709
 710 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 711
 712         * interp.c: Move FPU support routines from here to...
 713         * cp1.c: Here.  New file.
 714         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 715         (cp1.o): New target.
 716
 717 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 718
 719         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 720         * mips.igen (mips32, mips64): New models, add to all instructions
 721         and functions as appropriate.
 722         (loadstore_ea, check_u64): New variant for model mips64.
 723         (check_fmt_p): New variant for models mipsV and mips64, remove
 724         mipsV model marking fro other variant.
 725         (SLL) Rename to...
 726         (SLLa) this.
 727         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 728         for mips32 and mips64.
 729         (DCLO, DCLZ): New instructions for mips64.
 730
 731 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 732
 733         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 734         immediate or code as a hex value with the "%#lx" format.
 735         (ANDI): Likewise, and fix printed instruction name.
 736
 737 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 738
 739         * sim-main.h (UndefinedResult, Unpredictable): New macros
 740         which currently do nothing.
 741
 742 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 743
 744         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 745         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 746         (status_CU3): New definitions.
 747
 748         * sim-main.h (ExceptionCause): Add new values for MIPS32
 749         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 750         for DebugBreakPoint and NMIReset to note their status in
 751         MIPS32 and MIPS64.
 752         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 753         (SignalExceptionCacheErr): New exception macros.
 754
 755 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 756
 757         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 758         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 759         is always enabled.
 760         (SignalExceptionCoProcessorUnusable): Take as argument the
 761         unusable coprocessor number.
 762
 763 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 764
 765         * mips.igen: Fix formatting of all SignalException calls.
 766
 767 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 768
 769         * sim-main.h (SIGNEXTEND): Remove.
 770
 771 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 772
 773         * mips.igen: Remove gencode comment from top of file, fix
 774         spelling in another comment.
 775
 776 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 777
 778         * mips.igen (check_fmt, check_fmt_p): New functions to check
 779         whether specific floating point formats are usable.
 780         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 781         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 782         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 783         Use the new functions.
 784         (do_c_cond_fmt): Remove format checks...
 785         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 786
 787 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 788
 789         * mips.igen: Fix formatting of check_fpu calls.
 790
 791 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 792
 793         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 794
 795 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 796
 797         * mips.igen: Remove whitespace at end of lines.
 798
 799 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 800
 801         * mips.igen (loadstore_ea): New function to do effective
 802         address calculations.
 803         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 804         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 805         CACHE): Use loadstore_ea to do effective address computations.
 806
 807 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 808
 809         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 810         * mips.igen (LL, CxC1, MxC1): Likewise.
 811
 812 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 813
 814         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 815         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 816         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 817         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 818         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 819         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 820         Don't split opcode fields by hand, use the opcode field values
 821         provided by igen.
 822
 823 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 824
 825         * mips.igen (do_divu): Fix spacing.
 826
 827         * mips.igen (do_dsllv): Move to be right before DSLLV,
 828         to match the rest of the do_<shift> functions.
 829
 830 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 831
 832         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 833         DSRL32, do_dsrlv): Trace inputs and results.
 834
 835 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 836
 837         * mips.igen (CACHE): Provide instruction-printing string.
 838
 839         * interp.c (signal_exception): Comment tokens after #endif.
 840
 841 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 842
 843         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 844         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 845         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 846         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 847         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 848         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 849         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 850         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 851
 852 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 853
 854         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 855         instruction-printing string.
 856         (LWU): Use '64' as the filter flag.
 857
 858 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 859
 860         * mips.igen (SDXC1): Fix instruction-printing string.
 861
 862 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 863
 864         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 865         filter flags "32,f".
 866
 867 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 868
 869         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 870         as the filter flag.
 871
 872 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 873
 874         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 875         add a comma) so that it more closely match the MIPS ISA
 876         documentation opcode partitioning.
 877         (PREF): Put useful names on opcode fields, and include
 878         instruction-printing string.
 879
 880 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 881
 882         * mips.igen (check_u64): New function which in the future will
 883         check whether 64-bit instructions are usable and signal an
 884         exception if not.  Currently a no-op.
 885         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 886         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 887         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 888         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 889
 890         * mips.igen (check_fpu): New function which in the future will
 891         check whether FPU instructions are usable and signal an exception
 892         if not.  Currently a no-op.
 893         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 894         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 895         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 896         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 897         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 898         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 899         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 900         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 901
 902 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 903
 904         * mips.igen (do_load_left, do_load_right): Move to be immediately
 905         following do_load.
 906         (do_store_left, do_store_right): Move to be immediately following
 907         do_store.
 908
 909 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 910
 911         * mips.igen (mipsV): New model name.  Also, add it to
 912         all instructions and functions where it is appropriate.
 913
 914 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 915
 916         * mips.igen: For all functions and instructions, list model
 917         names that support that instruction one per line.
 918
 919 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 920
 921         * mips.igen: Add some additional comments about supported
 922         models, and about which instructions go where.
 923         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 924         order as is used in the rest of the file.
 925
 926 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 927
 928         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 929         indicating that ALU32_END or ALU64_END are there to check
 930         for overflow.
 931         (DADD): Likewise, but also remove previous comment about
 932         overflow checking.
 933
 934 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 935
 936         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 937         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 938         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 939         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 940         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 941         fields (i.e., add and move commas) so that they more closely
 942         match the MIPS ISA documentation opcode partitioning.
 943
 944 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 945
 946         * mips.igen (ADDI): Print immediate value.
 947         (BREAK): Print code.
 948         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 949         (SLL): Print "nop" specially, and don't run the code
 950         that does the shift for the "nop" case.
 951
 952 2001-11-17  Fred Fish  <fnf@redhat.com>
 953
 954         * sim-main.h (float_operation): Move enum declaration outside
 955         of _sim_cpu struct declaration.
 956
 957 2001-04-12  Jim Blandy  <jimb@redhat.com>
 958
 959         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 960         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 961         set of the FCSR.
 962         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 963         PENDING_FILL, and you can get the intended effect gracefully by
 964         calling PENDING_SCHED directly.
 965
 966 2001-02-23  Ben Elliston  <bje@redhat.com>
 967
 968         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 969         already defined elsewhere.
 970
 971 2001-02-19  Ben Elliston  <bje@redhat.com>
 972
 973         * sim-main.h (sim_monitor): Return an int.
 974         * interp.c (sim_monitor): Add return values.
 975         (signal_exception): Handle error conditions from sim_monitor.
 976
 977 2001-02-08  Ben Elliston  <bje@redhat.com>
 978
 979         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 980         (store_memory): Likewise, pass cia to sim_core_write*.
 981
 982 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 983
 984         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 985         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 986
 987 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 988
 989         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 990         * Makefile.in: Don't delete *.igen when cleaning directory.
 991
 992 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 993
 994         * m16.igen (break): Call SignalException not sim_engine_halt.
 995
 996 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 997
 998         From Jason Eckhardt:
 999         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1000
1001 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1002
1003         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1004
1005 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1006
1007         * mips.igen (do_dmultx): Fix typo.
1008
1009 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1010
1011         * configure: Regenerated to track ../common/aclocal.m4 changes.
1012
1013 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1014
1015         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1016
1017 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1018
1019         * sim-main.h (GPR_CLEAR): Define macro.
1020
1021 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1022
1023         * interp.c (decode_coproc): Output long using %lx and not %s.
1024
1025 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1026
1027         * interp.c (sim_open): Sort & extend dummy memory regions for
1028         --board=jmr3904 for eCos.
1029
1030 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1031
1032         * configure: Regenerated.
1033
1034 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1035
1036         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1037         calls, conditional on the simulator being in verbose mode.
1038
1039 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1040
1041         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1042         cache don't get ReservedInstruction traps.
1043
1044 1999-11-29  Mark Salter  <msalter@cygnus.com>
1045
1046         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1047         to clear status bits in sdisr register. This is how the hardware works.
1048
1049         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1050         being used by cygmon.
1051
1052 1999-11-11  Andrew Haley  <aph@cygnus.com>
1053
1054         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1055         instructions.
1056
1057 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1058
1059         * mips.igen (MULT): Correct previous mis-applied patch.
1060
1061 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1062
1063         * mips.igen (delayslot32): Handle sequence like
1064         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1065         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1066         (MULT): Actually pass the third register...
1067
1068 1999-09-03  Mark Salter  <msalter@cygnus.com>
1069
1070         * interp.c (sim_open): Added more memory aliases for additional
1071         hardware being touched by cygmon on jmr3904 board.
1072
1073 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1074
1075         * configure: Regenerated to track ../common/aclocal.m4 changes.
1076
1077 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1078
1079         * interp.c (sim_store_register): Handle case where client - GDB -
1080         specifies that a 4 byte register is 8 bytes in size.
1081         (sim_fetch_register): Ditto.
1082
1083 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1084
1085         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1086         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1087         (idt_monitor_base): Base address for IDT monitor traps.
1088         (pmon_monitor_base): Ditto for PMON.
1089         (lsipmon_monitor_base): Ditto for LSI PMON.
1090         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1091         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1092         (sim_firmware_command): New function.
1093         (mips_option_handler): Call it for OPTION_FIRMWARE.
1094         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1095         option was given, add no monitor by default.  Add BREAK hooks only if
1096         monitors are also there.
1097
1098 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1099
1100         * interp.c (sim_monitor): Flush output before reading input.
1101
1102 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1103
1104         * tconfig.in (SIM_HANDLES_LMA): Always define.
1105
1106 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1107
1108         From Mark Salter <msalter@cygnus.com>:
1109         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1110         (sim_open): Add setup for BSP board.
1111
1112 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1113
1114         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1115         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1116         them as unimplemented.
1117
1118 1999-05-08  Felix Lee  <flee@cygnus.com>
1119
1120         * configure: Regenerated to track ../common/aclocal.m4 changes.
1121
1122 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1123
1124         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1125
1126 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1127
1128         * configure.in: Any mips64vr5*-*-* target should have
1129         -DTARGET_ENABLE_FR=1.
1130         (default_endian): Any mips64vr*el-*-* target should default to
1131         LITTLE_ENDIAN.
1132         * configure: Re-generate.
1133
1134 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1135
1136         * mips.igen (ldl): Extend from _16_, not 32.
1137
1138 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1139
1140         * interp.c (sim_store_register): Force registers written to by GDB
1141         into an un-interpreted state.
1142
1143 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1144
1145         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1146         CPU, start periodic background I/O polls.
1147         (tx3904sio_poll): New function: periodic I/O poller.
1148
1149 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1150
1151         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1152
1153 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1154
1155         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1156         case statement.
1157
1158 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1159
1160         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1161         (load_word): Call SIM_CORE_SIGNAL hook on error.
1162         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1163         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1164         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1165         * sim-main.h (COP0_BADVADDR): Define.
1166         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1167         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1168         (_sim_cpu): Add exc_* fields to store register value snapshots.
1169         * mips.igen (*): Replace memory-related SignalException* calls
1170         with references to SIM_CORE_SIGNAL hook.
1171
1172         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1173         fix.
1174         * sim-main.c (*): Minor warning cleanups.
1175
1176 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1177
1178         * m16.igen (DADDIU5): Correct type-o.
1179
1180 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1181
1182         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1183         variables.
1184
1185 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1186
1187         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1188         to include path.
1189         (interp.o): Add dependency on itable.h
1190         (oengine.c, gencode): Delete remaining references.
1191         (BUILT_SRC_FROM_GEN): Clean up.
1192
1193 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1194
1195         * vr4run.c: New.
1196         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1197         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1198         tmp-run-hack) : New.
1199         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1200         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1201         Drop the "64" qualifier to get the HACK generator working.
1202         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1203         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1204         qualifier to get the hack generator working.
1205         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1206         (DSLL): Use do_dsll.
1207         (DSLLV): Use do_dsllv.
1208         (DSRA): Use do_dsra.
1209         (DSRL): Use do_dsrl.
1210         (DSRLV): Use do_dsrlv.
1211         (BC1): Move *vr4100 to get the HACK generator working.
1212         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1213         get the HACK generator working.
1214         (MACC) Rename to get the HACK generator working.
1215         (DMACC,MACCS,DMACCS): Add the 64.
1216
1217 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1218
1219         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1220         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1221
1222 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1223
1224     * mips/interp.c (DEBUG): Cleanups.
1225
1226 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1227
1228         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1229         (tx3904sio_tickle): fflush after a stdout character output.
1230
1231 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1232
1233         * interp.c (sim_close): Uninstall modules.
1234
1235 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1236
1237         * sim-main.h, interp.c (sim_monitor): Change to global
1238         function.
1239
1240 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1241
1242         * configure.in (vr4100): Only include vr4100 instructions in
1243         simulator.
1244         * configure: Re-generate.
1245         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1246
1247 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1248
1249         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1250         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1251         true alternative.
1252
1253         * configure.in (sim_default_gen, sim_use_gen): Replace with
1254         sim_gen.
1255         (--enable-sim-igen): Delete config option. Always using IGEN.
1256         * configure: Re-generate.
1257
1258         * Makefile.in (gencode): Kill, kill, kill.
1259         * gencode.c: Ditto.
1260
1261 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1262
1263         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1264         bit mips16 igen simulator.
1265         * configure: Re-generate.
1266
1267         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1268         as part of vr4100 ISA.
1269         * vr.igen: Mark all instructions as 64 bit only.
1270
1271 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1272
1273         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1274         Pacify GCC.
1275
1276 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1277
1278         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1279         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1280         * configure: Re-generate.
1281
1282         * m16.igen (BREAK): Define breakpoint instruction.
1283         (JALX32): Mark instruction as mips16 and not r3900.
1284         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1285
1286         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1287
1288 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1289
1290         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1291         insn as a debug breakpoint.
1292
1293         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1294         pending.slot_size.
1295         (PENDING_SCHED): Clean up trace statement.
1296         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1297         (PENDING_FILL): Delay write by only one cycle.
1298         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1299
1300         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1301         of pending writes.
1302         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1303         32 & 64.
1304         (pending_tick): Move incrementing of index to FOR statement.
1305         (pending_tick): Only update PENDING_OUT after a write has occured.
1306
1307         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1308         build simulator.
1309         * configure: Re-generate.
1310
1311         * interp.c (sim_engine_run OLD): Delete explicit call to
1312         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1313
1314 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1315
1316         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1317         interrupt level number to match changed SignalExceptionInterrupt
1318         macro.
1319
1320 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1321
1322         * interp.c: #include "itable.h" if WITH_IGEN.
1323         (get_insn_name): New function.
1324         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1325         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1326
1327 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1328
1329         * configure: Rebuilt to inhale new common/aclocal.m4.
1330
1331 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1332
1333         * dv-tx3904sio.c: Include sim-assert.h.
1334
1335 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1336
1337         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1338         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1339         Reorganize target-specific sim-hardware checks.
1340         * configure: rebuilt.
1341         * interp.c (sim_open): For tx39 target boards, set
1342         OPERATING_ENVIRONMENT, add tx3904sio devices.
1343         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1344         ROM executables.  Install dv-sockser into sim-modules list.
1345
1346         * dv-tx3904irc.c: Compiler warning clean-up.
1347         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1348         frequent hw-trace messages.
1349
1350 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1351
1352         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1353
1354 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1355
1356         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1357
1358         * vr.igen: New file.
1359         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1360         * mips.igen: Define vr4100 model. Include vr.igen.
1361 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1362
1363         * mips.igen (check_mf_hilo): Correct check.
1364
1365 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1366
1367         * sim-main.h (interrupt_event): Add prototype.
1368
1369         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1370         register_ptr, register_value.
1371         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1372
1373         * sim-main.h (tracefh): Make extern.
1374
1375 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1376
1377         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1378         Reduce unnecessarily high timer event frequency.
1379         * dv-tx3904cpu.c: Ditto for interrupt event.
1380
1381 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1382
1383         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1384         to allay warnings.
1385         (interrupt_event): Made non-static.
1386
1387         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1388         interchange of configuration values for external vs. internal
1389         clock dividers.
1390
1391 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1392
1393         * mips.igen (BREAK): Moved code to here for
1394         simulator-reserved break instructions.
1395         * gencode.c (build_instruction): Ditto.
1396         * interp.c (signal_exception): Code moved from here.  Non-
1397         reserved instructions now use exception vector, rather
1398         than halting sim.
1399         * sim-main.h: Moved magic constants to here.
1400
1401 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1402
1403         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1404         register upon non-zero interrupt event level, clear upon zero
1405         event value.
1406         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1407         by passing zero event value.
1408         (*_io_{read,write}_buffer): Endianness fixes.
1409         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1410         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1411
1412         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1413         serial I/O and timer module at base address 0xFFFF0000.
1414
1415 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1416
1417         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1418         and BigEndianCPU.
1419
1420 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1421
1422         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1423         parts.
1424         * configure: Update.
1425
1426 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1427
1428         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1429         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1430         * configure.in: Include tx3904tmr in hw_device list.
1431         * configure: Rebuilt.
1432         * interp.c (sim_open): Instantiate three timer instances.
1433         Fix address typo of tx3904irc instance.
1434
1435 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1436
1437         * interp.c (signal_exception): SystemCall exception now uses
1438         the exception vector.
1439
1440 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1441
1442         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1443         to allay warnings.
1444
1445 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1446
1447         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1448
1449 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1450
1451         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1452
1453         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1454         sim-main.h. Declare a struct hw_descriptor instead of struct
1455         hw_device_descriptor.
1456
1457 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1458
1459         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1460         right bits and then re-align left hand bytes to correct byte
1461         lanes.  Fix incorrect computation in do_store_left when loading
1462         bytes from second word.
1463
1464 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1465
1466         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1467         * interp.c (sim_open): Only create a device tree when HW is
1468         enabled.
1469
1470         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1471         * interp.c (signal_exception): Ditto.
1472
1473 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1474
1475         * gencode.c: Mark BEGEZALL as LIKELY.
1476
1477 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1478
1479         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1480         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1481
1482 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1483
1484         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1485         modules.  Recognize TX39 target with "mips*tx39" pattern.
1486         * configure: Rebuilt.
1487         * sim-main.h (*): Added many macros defining bits in
1488         TX39 control registers.
1489         (SignalInterrupt): Send actual PC instead of NULL.
1490         (SignalNMIReset): New exception type.
1491         * interp.c (board): New variable for future use to identify
1492         a particular board being simulated.
1493         (mips_option_handler,mips_options): Added "--board" option.
1494         (interrupt_event): Send actual PC.
1495         (sim_open): Make memory layout conditional on board setting.
1496         (signal_exception): Initial implementation of hardware interrupt
1497         handling.  Accept another break instruction variant for simulator
1498         exit.
1499         (decode_coproc): Implement RFE instruction for TX39.
1500         (mips.igen): Decode RFE instruction as such.
1501         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1502         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1503         bbegin to implement memory map.
1504         * dv-tx3904cpu.c: New file.
1505         * dv-tx3904irc.c: New file.
1506
1507 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1508
1509         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1510
1511 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1512
1513         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1514         with calls to check_div_hilo.
1515
1516 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1517
1518         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1519         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1520         Add special r3900 version of do_mult_hilo.
1521         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1522         with calls to check_mult_hilo.
1523         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1524         with calls to check_div_hilo.
1525
1526 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1527
1528         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1529         Document a replacement.
1530
1531 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1532
1533         * interp.c (sim_monitor): Make mon_printf work.
1534
1535 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1536
1537         * sim-main.h (INSN_NAME): New arg `cpu'.
1538
1539 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1540
1541         * configure: Regenerated to track ../common/aclocal.m4 changes.
1542
1543 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1544
1545         * configure: Regenerated to track ../common/aclocal.m4 changes.
1546         * config.in: Ditto.
1547
1548 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1549
1550         * acconfig.h: New file.
1551         * configure.in: Reverted change of Apr 24; use sinclude again.
1552
1553 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1554
1555         * configure: Regenerated to track ../common/aclocal.m4 changes.
1556         * config.in: Ditto.
1557
1558 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1559
1560         * configure.in: Don't call sinclude.
1561
1562 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1563
1564         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1565
1566 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1567
1568         * mips.igen (ERET): Implement.
1569
1570         * interp.c (decode_coproc): Return sign-extended EPC.
1571
1572         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1573
1574         * interp.c (signal_exception): Do not ignore Trap.
1575         (signal_exception): On TRAP, restart at exception address.
1576         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1577         (signal_exception): Update.
1578         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1579         so that TRAP instructions are caught.
1580
1581 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1582
1583         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1584         contains HI/LO access history.
1585         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1586         (HIACCESS, LOACCESS): Delete, replace with
1587         (HIHISTORY, LOHISTORY): New macros.
1588         (CHECKHILO): Delete all, moved to mips.igen
1589
1590         * gencode.c (build_instruction): Do not generate checks for
1591         correct HI/LO register usage.
1592
1593         * interp.c (old_engine_run): Delete checks for correct HI/LO
1594         register usage.
1595
1596         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1597         check_mf_cycles): New functions.
1598         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1599         do_divu, domultx, do_mult, do_multu): Use.
1600
1601         * tx.igen ("madd", "maddu"): Use.
1602
1603 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1604
1605         * mips.igen (DSRAV): Use function do_dsrav.
1606         (SRAV): Use new function do_srav.
1607
1608         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1609         (B): Sign extend 11 bit immediate.
1610         (EXT-B*): Shift 16 bit immediate left by 1.
1611         (ADDIU*): Don't sign extend immediate value.
1612
1613 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1614
1615         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1616
1617         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1618         functions.
1619
1620         * mips.igen (delayslot32, nullify_next_insn): New functions.
1621         (m16.igen): Always include.
1622         (do_*): Add more tracing.
1623
1624         * m16.igen (delayslot16): Add NIA argument, could be called by a
1625         32 bit MIPS16 instruction.
1626
1627         * interp.c (ifetch16): Move function from here.
1628         * sim-main.c (ifetch16): To here.
1629
1630         * sim-main.c (ifetch16, ifetch32): Update to match current
1631         implementations of LH, LW.
1632         (signal_exception): Don't print out incorrect hex value of illegal
1633         instruction.
1634
1635 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1636
1637         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1638         instruction.
1639
1640         * m16.igen: Implement MIPS16 instructions.
1641
1642         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1643         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1644         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1645         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1646         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1647         bodies of corresponding code from 32 bit insn to these.  Also used
1648         by MIPS16 versions of functions.
1649
1650         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1651         (IMEM16): Drop NR argument from macro.
1652
1653 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * Makefile.in (SIM_OBJS): Add sim-main.o.
1656
1657         * sim-main.h (address_translation, load_memory, store_memory,
1658         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1659         as INLINE_SIM_MAIN.
1660         (pr_addr, pr_uword64): Declare.
1661         (sim-main.c): Include when H_REVEALS_MODULE_P.
1662
1663         * interp.c (address_translation, load_memory, store_memory,
1664         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1665         from here.
1666         * sim-main.c: To here. Fix compilation problems.
1667
1668         * configure.in: Enable inlining.
1669         * configure: Re-config.
1670
1671 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1672
1673         * configure: Regenerated to track ../common/aclocal.m4 changes.
1674
1675 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1676
1677         * mips.igen: Include tx.igen.
1678         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1679         * tx.igen: New file, contains MADD and MADDU.
1680
1681         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1682         the hardwired constant `7'.
1683         (store_memory): Ditto.
1684         (LOADDRMASK): Move definition to sim-main.h.
1685
1686         mips.igen (MTC0): Enable for r3900.
1687         (ADDU): Add trace.
1688
1689         mips.igen (do_load_byte): Delete.
1690         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1691         do_store_right): New functions.
1692         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1693
1694         configure.in: Let the tx39 use igen again.
1695         configure: Update.
1696
1697 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1698
1699         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1700         not an address sized quantity.  Return zero for cache sizes.
1701
1702 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1703
1704         * mips.igen (r3900): r3900 does not support 64 bit integer
1705         operations.
1706
1707 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1708
1709         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1710         than igen one.
1711         * configure : Rebuild.
1712
1713 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1714
1715         * configure: Regenerated to track ../common/aclocal.m4 changes.
1716
1717 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1718
1719         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1720
1721 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1722
1723         * configure: Regenerated to track ../common/aclocal.m4 changes.
1724         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1725
1726 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1727
1728         * configure: Regenerated to track ../common/aclocal.m4 changes.
1729
1730 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1731
1732         * interp.c (Max, Min): Comment out functions. Not yet used.
1733
1734 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * configure: Regenerated to track ../common/aclocal.m4 changes.
1737
1738 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1739
1740         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1741         configurable settings for stand-alone simulator.
1742
1743         * configure.in: Added X11 search, just in case.
1744
1745         * configure: Regenerated.
1746
1747 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1748
1749         * interp.c (sim_write, sim_read, load_memory, store_memory):
1750         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1751
1752 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1753
1754         * sim-main.h (GETFCC): Return an unsigned value.
1755
1756 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1757
1758         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1759         (DADD): Result destination is RD not RT.
1760
1761 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1762
1763         * sim-main.h (HIACCESS, LOACCESS): Always define.
1764
1765         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1766
1767         * interp.c (sim_info): Delete.
1768
1769 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1770
1771         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1772         (mips_option_handler): New argument `cpu'.
1773         (sim_open): Update call to sim_add_option_table.
1774
1775 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1776
1777         * mips.igen (CxC1): Add tracing.
1778
1779 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1780
1781         * sim-main.h (Max, Min): Declare.
1782
1783         * interp.c (Max, Min): New functions.
1784
1785         * mips.igen (BC1): Add tracing.
1786
1787 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1788
1789         * interp.c Added memory map for stack in vr4100
1790
1791 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1792
1793         * interp.c (load_memory): Add missing "break"'s.
1794
1795 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1796
1797         * interp.c (sim_store_register, sim_fetch_register): Pass in
1798         length parameter.  Return -1.
1799
1800 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1801
1802         * interp.c: Added hardware init hook, fixed warnings.
1803
1804 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1805
1806         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1807
1808 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1809
1810         * interp.c (ifetch16): New function.
1811
1812         * sim-main.h (IMEM32): Rename IMEM.
1813         (IMEM16_IMMED): Define.
1814         (IMEM16): Define.
1815         (DELAY_SLOT): Update.
1816
1817         * m16run.c (sim_engine_run): New file.
1818
1819         * m16.igen: All instructions except LB.
1820         (LB): Call do_load_byte.
1821         * mips.igen (do_load_byte): New function.
1822         (LB): Call do_load_byte.
1823
1824         * mips.igen: Move spec for insn bit size and high bit from here.
1825         * Makefile.in (tmp-igen, tmp-m16): To here.
1826
1827         * m16.dc: New file, decode mips16 instructions.
1828
1829         * Makefile.in (SIM_NO_ALL): Define.
1830         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1831
1832 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1833
1834         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1835         point unit to 32 bit registers.
1836         * configure: Re-generate.
1837
1838 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1839
1840         * configure.in (sim_use_gen): Make IGEN the default simulator
1841         generator for generic 32 and 64 bit mips targets.
1842         * configure: Re-generate.
1843
1844 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1845
1846         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1847         bitsize.
1848
1849         * interp.c (sim_fetch_register, sim_store_register): Read/write
1850         FGR from correct location.
1851         (sim_open): Set size of FGR's according to
1852         WITH_TARGET_FLOATING_POINT_BITSIZE.
1853
1854         * sim-main.h (FGR): Store floating point registers in a separate
1855         array.
1856
1857 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1858
1859         * configure: Regenerated to track ../common/aclocal.m4 changes.
1860
1861 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1862
1863         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1864
1865         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1866
1867         * interp.c (pending_tick): New function.  Deliver pending writes.
1868
1869         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1870         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1871         it can handle mixed sized quantites and single bits.
1872
1873 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1874
1875         * interp.c (oengine.h): Do not include when building with IGEN.
1876         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1877         (sim_info): Ditto for PROCESSOR_64BIT.
1878         (sim_monitor): Replace ut_reg with unsigned_word.
1879         (*): Ditto for t_reg.
1880         (LOADDRMASK): Define.
1881         (sim_open): Remove defunct check that host FP is IEEE compliant,
1882         using software to emulate floating point.
1883         (value_fpr, ...): Always compile, was conditional on HASFPU.
1884
1885 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1886
1887         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1888         size.
1889
1890         * interp.c (SD, CPU): Define.
1891         (mips_option_handler): Set flags in each CPU.
1892         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1893         (sim_close): Do not clear STATE, deleted anyway.
1894         (sim_write, sim_read): Assume CPU zero's vm should be used for
1895         data transfers.
1896         (sim_create_inferior): Set the PC for all processors.
1897         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1898         argument.
1899         (mips16_entry): Pass correct nr of args to store_word, load_word.
1900         (ColdReset): Cold reset all cpu's.
1901         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1902         (sim_monitor, load_memory, store_memory, signal_exception): Use
1903         `CPU' instead of STATE_CPU.
1904
1905
1906         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1907         SD or CPU_.
1908
1909         * sim-main.h (signal_exception): Add sim_cpu arg.
1910         (SignalException*): Pass both SD and CPU to signal_exception.
1911         * interp.c (signal_exception): Update.
1912
1913         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1914         Ditto
1915         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1916         address_translation): Ditto
1917         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1918
1919 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1920
1921         * configure: Regenerated to track ../common/aclocal.m4 changes.
1922
1923 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1924
1925         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1926
1927         * mips.igen (model): Map processor names onto BFD name.
1928
1929         * sim-main.h (CPU_CIA): Delete.
1930         (SET_CIA, GET_CIA): Define
1931
1932 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1935         regiser.
1936
1937         * configure.in (default_endian): Configure a big-endian simulator
1938         by default.
1939         * configure: Re-generate.
1940
1941 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1942
1943         * configure: Regenerated to track ../common/aclocal.m4 changes.
1944
1945 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1946
1947         * interp.c (sim_monitor): Handle Densan monitor outbyte
1948         and inbyte functions.
1949
1950 1997-12-29  Felix Lee  <flee@cygnus.com>
1951
1952         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1953
1954 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1955
1956         * Makefile.in (tmp-igen): Arrange for $zero to always be
1957         reset to zero after every instruction.
1958
1959 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1960
1961         * configure: Regenerated to track ../common/aclocal.m4 changes.
1962         * config.in: Ditto.
1963
1964 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1965
1966         * mips.igen (MSUB): Fix to work like MADD.
1967         * gencode.c (MSUB): Similarly.
1968
1969 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1970
1971         * configure: Regenerated to track ../common/aclocal.m4 changes.
1972
1973 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1974
1975         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1976
1977 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1978
1979         * sim-main.h (sim-fpu.h): Include.
1980
1981         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1982         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1983         using host independant sim_fpu module.
1984
1985 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1986
1987         * interp.c (signal_exception): Report internal errors with SIGABRT
1988         not SIGQUIT.
1989
1990         * sim-main.h (C0_CONFIG): New register.
1991         (signal.h): No longer include.
1992
1993         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1994
1995 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1996
1997         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1998
1999 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2000
2001         * mips.igen: Tag vr5000 instructions.
2002         (ANDI): Was missing mipsIV model, fix assembler syntax.
2003         (do_c_cond_fmt): New function.
2004         (C.cond.fmt): Handle mips I-III which do not support CC field
2005         separatly.
2006         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2007         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2008         in IV3.2 spec.
2009         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2010         vr5000 which saves LO in a GPR separatly.
2011
2012         * configure.in (enable-sim-igen): For vr5000, select vr5000
2013         specific instructions.
2014         * configure: Re-generate.
2015
2016 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2017
2018         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2019
2020         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2021         fmt_uninterpreted_64 bit cases to switch.  Convert to
2022         fmt_formatted,
2023
2024         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2025
2026         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2027         as specified in IV3.2 spec.
2028         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2029
2030 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2031
2032         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2033         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2034         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2035         PENDING_FILL versions of instructions.  Simplify.
2036         (X): New function.
2037         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2038         instructions.
2039         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2040         a signed value.
2041         (MTHI, MFHI): Disable code checking HI-LO.
2042
2043         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2044         global.
2045         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2046
2047 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2048
2049         * gencode.c (build_mips16_operands): Replace IPC with cia.
2050
2051         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2052         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2053         IPC to `cia'.
2054         (UndefinedResult): Replace function with macro/function
2055         combination.
2056         (sim_engine_run): Don't save PC in IPC.
2057
2058         * sim-main.h (IPC): Delete.
2059
2060
2061         * interp.c (signal_exception, store_word, load_word,
2062         address_translation, load_memory, store_memory, cache_op,
2063         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2064         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2065         current instruction address - cia - argument.
2066         (sim_read, sim_write): Call address_translation directly.
2067         (sim_engine_run): Rename variable vaddr to cia.
2068         (signal_exception): Pass cia to sim_monitor
2069
2070         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2071         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2072         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2073
2074         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2075         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2076         SIM_ASSERT.
2077
2078         * interp.c (signal_exception): Pass restart address to
2079         sim_engine_restart.
2080
2081         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2082         idecode.o): Add dependency.
2083
2084         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2085         Delete definitions
2086         (DELAY_SLOT): Update NIA not PC with branch address.
2087         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2088
2089         * mips.igen: Use CIA not PC in branch calculations.
2090         (illegal): Call SignalException.
2091         (BEQ, ADDIU): Fix assembler.
2092
2093 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2094
2095         * m16.igen (JALX): Was missing.
2096
2097         * configure.in (enable-sim-igen): New configuration option.
2098         * configure: Re-generate.
2099
2100         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2101
2102         * interp.c (load_memory, store_memory): Delete parameter RAW.
2103         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2104         bypassing {load,store}_memory.
2105
2106         * sim-main.h (ByteSwapMem): Delete definition.
2107
2108         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2109
2110         * interp.c (sim_do_command, sim_commands): Delete mips specific
2111         commands.  Handled by module sim-options.
2112
2113         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2114         (WITH_MODULO_MEMORY): Define.
2115
2116         * interp.c (sim_info): Delete code printing memory size.
2117
2118         * interp.c (mips_size): Nee sim_size, delete function.
2119         (power2): Delete.
2120         (monitor, monitor_base, monitor_size): Delete global variables.
2121         (sim_open, sim_close): Delete code creating monitor and other
2122         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2123         manage memory regions.
2124         (load_memory, store_memory): Use sim-core for memory model.
2125
2126         * interp.c (address_translation): Delete all memory map code
2127         except line forcing 32 bit addresses.
2128
2129 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2130
2131         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2132         trace options.
2133
2134         * interp.c (logfh, logfile): Delete globals.
2135         (sim_open, sim_close): Delete code opening & closing log file.
2136         (mips_option_handler): Delete -l and -n options.
2137         (OPTION mips_options): Ditto.
2138
2139         * interp.c (OPTION mips_options): Rename option trace to dinero.
2140         (mips_option_handler): Update.
2141
2142 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2143
2144         * interp.c (fetch_str): New function.
2145         (sim_monitor): Rewrite using sim_read & sim_write.
2146         (sim_open): Check magic number.
2147         (sim_open): Write monitor vectors into memory using sim_write.
2148         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2149         (sim_read, sim_write): Simplify - transfer data one byte at a
2150         time.
2151         (load_memory, store_memory): Clarify meaning of parameter RAW.
2152
2153         * sim-main.h (isHOST): Defete definition.
2154         (isTARGET): Mark as depreciated.
2155         (address_translation): Delete parameter HOST.
2156
2157         * interp.c (address_translation): Delete parameter HOST.
2158
2159 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2160
2161         * mips.igen:
2162
2163         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2164         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2165
2166 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2167
2168         * mips.igen: Add model filter field to records.
2169
2170 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2171
2172         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2173
2174         interp.c (sim_engine_run): Do not compile function sim_engine_run
2175         when WITH_IGEN == 1.
2176
2177         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2178         target architecture.
2179
2180         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2181         igen. Replace with configuration variables sim_igen_flags /
2182         sim_m16_flags.
2183
2184         * m16.igen: New file.  Copy mips16 insns here.
2185         * mips.igen: From here.
2186
2187 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2188
2189         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2190         to top.
2191         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2192
2193 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2194
2195         * gencode.c (build_instruction): Follow sim_write's lead in using
2196         BigEndianMem instead of !ByteSwapMem.
2197
2198 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2199
2200         * configure.in (sim_gen): Dependent on target, select type of
2201         generator.  Always select old style generator.
2202
2203         configure: Re-generate.
2204
2205         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2206         targets.
2207         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2208         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2209         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2210         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2211         SIM_@sim_gen@_*, set by autoconf.
2212
2213 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2214
2215         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2216
2217         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2218         CURRENT_FLOATING_POINT instead.
2219
2220         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2221         (address_translation): Raise exception InstructionFetch when
2222         translation fails and isINSTRUCTION.
2223
2224         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2225         sim_engine_run): Change type of of vaddr and paddr to
2226         address_word.
2227         (address_translation, prefetch, load_memory, store_memory,
2228         cache_op): Change type of vAddr and pAddr to address_word.
2229
2230         * gencode.c (build_instruction): Change type of vaddr and paddr to
2231         address_word.
2232
2233 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2234
2235         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2236         macro to obtain result of ALU op.
2237
2238 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2239
2240         * interp.c (sim_info): Call profile_print.
2241
2242 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2243
2244         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2245
2246         * sim-main.h (WITH_PROFILE): Do not define, defined in
2247         common/sim-config.h.  Use sim-profile module.
2248         (simPROFILE): Delete defintion.
2249
2250         * interp.c (PROFILE): Delete definition.
2251         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2252         (sim_close): Delete code writing profile histogram.
2253         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2254         Delete.
2255         (sim_engine_run): Delete code profiling the PC.
2256
2257 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2258
2259         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2260
2261         * interp.c (sim_monitor): Make register pointers of type
2262         unsigned_word*.
2263
2264         * sim-main.h: Make registers of type unsigned_word not
2265         signed_word.
2266
2267 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2268
2269         * interp.c (sync_operation): Rename from SyncOperation, make
2270         global, add SD argument.
2271         (prefetch): Rename from Prefetch, make global, add SD argument.
2272         (decode_coproc): Make global.
2273
2274         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2275
2276         * gencode.c (build_instruction): Generate DecodeCoproc not
2277         decode_coproc calls.
2278
2279         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2280         (SizeFGR): Move to sim-main.h
2281         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2282         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2283         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2284         sim-main.h.
2285         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2286         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2287         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2288         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2289         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2290         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2291
2292         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2293         exception.
2294         (sim-alu.h): Include.
2295         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2296         (sim_cia): Typedef to instruction_address.
2297
2298 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2299
2300         * Makefile.in (interp.o): Rename generated file engine.c to
2301         oengine.c.
2302
2303         * interp.c: Update.
2304
2305 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2306
2307         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2308
2309 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2310
2311         * gencode.c (build_instruction): For "FPSQRT", output correct
2312         number of arguments to Recip.
2313
2314 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2315
2316         * Makefile.in (interp.o): Depends on sim-main.h
2317
2318         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2319
2320         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2321         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2322         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2323         STATE, DSSTATE): Define
2324         (GPR, FGRIDX, ..): Define.
2325
2326         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2327         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2328         (GPR, FGRIDX, ...): Delete macros.
2329
2330         * interp.c: Update names to match defines from sim-main.h
2331
2332 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2333
2334         * interp.c (sim_monitor): Add SD argument.
2335         (sim_warning): Delete.  Replace calls with calls to
2336         sim_io_eprintf.
2337         (sim_error): Delete. Replace calls with sim_io_error.
2338         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2339         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2340         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2341         argument.
2342         (mips_size): Rename from sim_size. Add SD argument.
2343
2344         * interp.c (simulator): Delete global variable.
2345         (callback): Delete global variable.
2346         (mips_option_handler, sim_open, sim_write, sim_read,
2347         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2348         sim_size,sim_monitor): Use sim_io_* not callback->*.
2349         (sim_open): ZALLOC simulator struct.
2350         (PROFILE): Do not define.
2351
2352 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2353
2354         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2355         support.h with corresponding code.
2356
2357         * sim-main.h (word64, uword64), support.h: Move definition to
2358         sim-main.h.
2359         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2360
2361         * support.h: Delete
2362         * Makefile.in: Update dependencies
2363         * interp.c: Do not include.
2364
2365 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2366
2367         * interp.c (address_translation, load_memory, store_memory,
2368         cache_op): Rename to from AddressTranslation et.al., make global,
2369         add SD argument
2370
2371         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2372         CacheOp): Define.
2373
2374         * interp.c (SignalException): Rename to signal_exception, make
2375         global.
2376
2377         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2378
2379         * sim-main.h (SignalException, SignalExceptionInterrupt,
2380         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2381         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2382         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2383         Define.
2384
2385         * interp.c, support.h: Use.
2386
2387 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2388
2389         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2390         to value_fpr / store_fpr. Add SD argument.
2391         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2392         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2393
2394         * sim-main.h (ValueFPR, StoreFPR): Define.
2395
2396 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2397
2398         * interp.c (sim_engine_run): Check consistency between configure
2399         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2400         and HASFPU.
2401
2402         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2403         (mips_fpu): Configure WITH_FLOATING_POINT.
2404         (mips_endian): Configure WITH_TARGET_ENDIAN.
2405         * configure: Update.
2406
2407 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2408
2409         * configure: Regenerated to track ../common/aclocal.m4 changes.
2410
2411 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2412
2413         * configure: Regenerated.
2414
2415 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2416
2417         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2418
2419 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2420
2421         * gencode.c (print_igen_insn_models): Assume certain architectures
2422         include all mips* instructions.
2423         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2424         instruction.
2425
2426         * Makefile.in (tmp.igen): Add target. Generate igen input from
2427         gencode file.
2428
2429         * gencode.c (FEATURE_IGEN): Define.
2430         (main): Add --igen option.  Generate output in igen format.
2431         (process_instructions): Format output according to igen option.
2432         (print_igen_insn_format): New function.
2433         (print_igen_insn_models): New function.
2434         (process_instructions): Only issue warnings and ignore
2435         instructions when no FEATURE_IGEN.
2436
2437 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2438
2439         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2440         MIPS targets.
2441
2442 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2443
2444         * configure: Regenerated to track ../common/aclocal.m4 changes.
2445
2446 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2447
2448         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2449         SIM_RESERVED_BITS): Delete, moved to common.
2450         (SIM_EXTRA_CFLAGS): Update.
2451
2452 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2453
2454         * configure.in: Configure non-strict memory alignment.
2455         * configure: Regenerated to track ../common/aclocal.m4 changes.
2456
2457 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2458
2459         * configure: Regenerated to track ../common/aclocal.m4 changes.
2460
2461 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2462
2463         * gencode.c (SDBBP,DERET): Added (3900) insns.
2464         (RFE): Turn on for 3900.
2465         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2466         (dsstate): Made global.
2467         (SUBTARGET_R3900): Added.
2468         (CANCELDELAYSLOT): New.
2469         (SignalException): Ignore SystemCall rather than ignore and
2470         terminate.  Add DebugBreakPoint handling.
2471         (decode_coproc): New insns RFE, DERET; and new registers Debug
2472         and DEPC protected by SUBTARGET_R3900.
2473         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2474         bits explicitly.
2475         * Makefile.in,configure.in: Add mips subtarget option.
2476         * configure: Update.
2477
2478 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2479
2480         * gencode.c: Add r3900 (tx39).
2481
2482
2483 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2484
2485         * gencode.c (build_instruction): Don't need to subtract 4 for
2486         JALR, just 2.
2487
2488 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2489
2490         * interp.c: Correct some HASFPU problems.
2491
2492 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2493
2494         * configure: Regenerated to track ../common/aclocal.m4 changes.
2495
2496 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2497
2498         * interp.c (mips_options): Fix samples option short form, should
2499         be `x'.
2500
2501 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2502
2503         * interp.c (sim_info): Enable info code.  Was just returning.
2504
2505 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2506
2507         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2508         MFC0.
2509
2510 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2511
2512         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2513         constants.
2514         (build_instruction): Ditto for LL.
2515
2516 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2517
2518         * configure: Regenerated to track ../common/aclocal.m4 changes.
2519
2520 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2521
2522         * configure: Regenerated to track ../common/aclocal.m4 changes.
2523         * config.in: Ditto.
2524
2525 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2526
2527         * interp.c (sim_open): Add call to sim_analyze_program, update
2528         call to sim_config.
2529
2530 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2531
2532         * interp.c (sim_kill): Delete.
2533         (sim_create_inferior): Add ABFD argument. Set PC from same.
2534         (sim_load): Move code initializing trap handlers from here.
2535         (sim_open): To here.
2536         (sim_load): Delete, use sim-hload.c.
2537
2538         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2539
2540 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2541
2542         * configure: Regenerated to track ../common/aclocal.m4 changes.
2543         * config.in: Ditto.
2544
2545 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2546
2547         * interp.c (sim_open): Add ABFD argument.
2548         (sim_load): Move call to sim_config from here.
2549         (sim_open): To here.  Check return status.
2550
2551 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2552
2553         * gencode.c (build_instruction): Two arg MADD should
2554         not assign result to $0.
2555
2556 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2557
2558         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2559         * sim/mips/configure.in: Regenerate.
2560
2561 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2562
2563         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2564         signed8, unsigned8 et.al. types.
2565
2566         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2567         hosts when selecting subreg.
2568
2569 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2570
2571         * interp.c (sim_engine_run): Reset the ZERO register to zero
2572         regardless of FEATURE_WARN_ZERO.
2573         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2574
2575 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2576
2577         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2578         (SignalException): For BreakPoints ignore any mode bits and just
2579         save the PC.
2580         (SignalException): Always set the CAUSE register.
2581
2582 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2583
2584         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2585         exception has been taken.
2586
2587         * interp.c: Implement the ERET and mt/f sr instructions.
2588
2589 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2590
2591         * interp.c (SignalException): Don't bother restarting an
2592         interrupt.
2593
2594 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2595
2596         * interp.c (SignalException): Really take an interrupt.
2597         (interrupt_event): Only deliver interrupts when enabled.
2598
2599 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2600
2601         * interp.c (sim_info): Only print info when verbose.
2602         (sim_info) Use sim_io_printf for output.
2603
2604 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2605
2606         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2607         mips architectures.
2608
2609 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2610
2611         * interp.c (sim_do_command): Check for common commands if a
2612         simulator specific command fails.
2613
2614 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2615
2616         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2617         and simBE when DEBUG is defined.
2618
2619 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2620
2621         * interp.c (interrupt_event): New function.  Pass exception event
2622         onto exception handler.
2623
2624         * configure.in: Check for stdlib.h.
2625         * configure: Regenerate.
2626
2627         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2628         variable declaration.
2629         (build_instruction): Initialize memval1.
2630         (build_instruction): Add UNUSED attribute to byte, bigend,
2631         reverse.
2632         (build_operands): Ditto.
2633
2634         * interp.c: Fix GCC warnings.
2635         (sim_get_quit_code): Delete.
2636
2637         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2638         * Makefile.in: Ditto.
2639         * configure: Re-generate.
2640
2641         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2642
2643 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2644
2645         * interp.c (mips_option_handler): New function parse argumes using
2646         sim-options.
2647         (myname): Replace with STATE_MY_NAME.
2648         (sim_open): Delete check for host endianness - performed by
2649         sim_config.
2650         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2651         (sim_open): Move much of the initialization from here.
2652         (sim_load): To here.  After the image has been loaded and
2653         endianness set.
2654         (sim_open): Move ColdReset from here.
2655         (sim_create_inferior): To here.
2656         (sim_open): Make FP check less dependant on host endianness.
2657
2658         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2659         run.
2660         * interp.c (sim_set_callbacks): Delete.
2661
2662         * interp.c (membank, membank_base, membank_size): Replace with
2663         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2664         (sim_open): Remove call to callback->init. gdb/run do this.
2665
2666         * interp.c: Update
2667
2668         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2669
2670         * interp.c (big_endian_p): Delete, replaced by
2671         current_target_byte_order.
2672
2673 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2674
2675         * interp.c (host_read_long, host_read_word, host_swap_word,
2676         host_swap_long): Delete. Using common sim-endian.
2677         (sim_fetch_register, sim_store_register): Use H2T.
2678         (pipeline_ticks): Delete.  Handled by sim-events.
2679         (sim_info): Update.
2680         (sim_engine_run): Update.
2681
2682 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2683
2684         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2685         reason from here.
2686         (SignalException): To here. Signal using sim_engine_halt.
2687         (sim_stop_reason): Delete, moved to common.
2688
2689 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2690
2691         * interp.c (sim_open): Add callback argument.
2692         (sim_set_callbacks): Delete SIM_DESC argument.
2693         (sim_size): Ditto.
2694
2695 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2696
2697         * Makefile.in (SIM_OBJS): Add common modules.
2698
2699         * interp.c (sim_set_callbacks): Also set SD callback.
2700         (set_endianness, xfer_*, swap_*): Delete.
2701         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2702         Change to functions using sim-endian macros.
2703         (control_c, sim_stop): Delete, use common version.
2704         (simulate): Convert into.
2705         (sim_engine_run): This function.
2706         (sim_resume): Delete.
2707
2708         * interp.c (simulation): New variable - the simulator object.
2709         (sim_kind): Delete global - merged into simulation.
2710         (sim_load): Cleanup.  Move PC assignment from here.
2711         (sim_create_inferior): To here.
2712
2713         * sim-main.h: New file.
2714         * interp.c (sim-main.h): Include.
2715
2716 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2717
2718         * configure: Regenerated to track ../common/aclocal.m4 changes.
2719
2720 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2721
2722         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2723
2724 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2725
2726         * gencode.c (build_instruction): DIV instructions: check
2727         for division by zero and integer overflow before using
2728         host's division operation.
2729
2730 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2731
2732         * Makefile.in (SIM_OBJS): Add sim-load.o.
2733         * interp.c: #include bfd.h.
2734         (target_byte_order): Delete.
2735         (sim_kind, myname, big_endian_p): New static locals.
2736         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2737         after argument parsing.  Recognize -E arg, set endianness accordingly.
2738         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2739         load file into simulator.  Set PC from bfd.
2740         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2741         (set_endianness): Use big_endian_p instead of target_byte_order.
2742
2743 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2744
2745         * interp.c (sim_size): Delete prototype - conflicts with
2746         definition in remote-sim.h.  Correct definition.
2747
2748 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2749
2750         * configure: Regenerated to track ../common/aclocal.m4 changes.
2751         * config.in: Ditto.
2752
2753 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2754
2755         * interp.c (sim_open): New arg `kind'.
2756
2757         * configure: Regenerated to track ../common/aclocal.m4 changes.
2758
2759 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2760
2761         * configure: Regenerated to track ../common/aclocal.m4 changes.
2762
2763 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2764
2765         * interp.c (sim_open): Set optind to 0 before calling getopt.
2766
2767 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2768
2769         * configure: Regenerated to track ../common/aclocal.m4 changes.
2770
2771 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2772
2773         * interp.c : Replace uses of pr_addr with pr_uword64
2774         where the bit length is always 64 independent of SIM_ADDR.
2775         (pr_uword64) : added.
2776
2777 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2778
2779         * configure: Re-generate.
2780
2781 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2782
2783         * configure: Regenerate to track ../common/aclocal.m4 changes.
2784
2785 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2786
2787         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2788         in argv form.
2789         (other sim_*): New SIM_DESC argument.
2790
2791 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2792
2793         * interp.c: Fix printing of addresses for non-64-bit targets.
2794         (pr_addr): Add function to print address based on size.
2795
2796 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2797
2798         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2799
2800 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2801
2802         * gencode.c (build_mips16_operands): Correct computation of base
2803         address for extended PC relative instruction.
2804
2805 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2806
2807         * interp.c (mips16_entry): Add support for floating point cases.
2808         (SignalException): Pass floating point cases to mips16_entry.
2809         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2810         registers.
2811         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2812         or fmt_word.
2813         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2814         and then set the state to fmt_uninterpreted.
2815         (COP_SW): Temporarily set the state to fmt_word while calling
2816         ValueFPR.
2817
2818 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2819
2820         * gencode.c (build_instruction): The high order may be set in the
2821         comparison flags at any ISA level, not just ISA 4.
2822
2823 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2824
2825         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2826         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2827         * configure.in: sinclude ../common/aclocal.m4.
2828         * configure: Regenerated.
2829
2830 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2831
2832         * configure: Rebuild after change to aclocal.m4.
2833
2834 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2835
2836         * configure configure.in Makefile.in:  Update to new configure
2837         scheme which is more compatible with WinGDB builds.
2838         * configure.in:  Improve comment on how to run autoconf.
2839         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2840         * Makefile.in:  Use autoconf substitution to install common
2841         makefile fragment.
2842
2843 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2844
2845         * gencode.c (build_instruction): Use BigEndianCPU instead of
2846         ByteSwapMem.
2847
2848 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2849
2850         * interp.c (sim_monitor): Make output to stdout visible in
2851         wingdb's I/O log window.
2852
2853 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2854
2855         * support.h: Undo previous change to SIGTRAP
2856         and SIGQUIT values.
2857
2858 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2859
2860         * interp.c (store_word, load_word): New static functions.
2861         (mips16_entry): New static function.
2862         (SignalException): Look for mips16 entry and exit instructions.
2863         (simulate): Use the correct index when setting fpr_state after
2864         doing a pending move.
2865
2866 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2867
2868         * interp.c: Fix byte-swapping code throughout to work on
2869         both little- and big-endian hosts.
2870
2871 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2872
2873         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2874         with gdb/config/i386/xm-windows.h.
2875
2876 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2877
2878         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2879         that messes up arithmetic shifts.
2880
2881 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2882
2883         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2884         SIGTRAP and SIGQUIT for _WIN32.
2885
2886 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2887
2888         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2889         force a 64 bit multiplication.
2890         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2891         destination register is 0, since that is the default mips16 nop
2892         instruction.
2893
2894 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2895
2896         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2897         (build_endian_shift): Don't check proc64.
2898         (build_instruction): Always set memval to uword64.  Cast op2 to
2899         uword64 when shifting it left in memory instructions.  Always use
2900         the same code for stores--don't special case proc64.
2901
2902         * gencode.c (build_mips16_operands): Fix base PC value for PC
2903         relative operands.
2904         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2905         jal instruction.
2906         * interp.c (simJALDELAYSLOT): Define.
2907         (JALDELAYSLOT): Define.
2908         (INDELAYSLOT, INJALDELAYSLOT): Define.
2909         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2910
2911 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2912
2913         * interp.c (sim_open): add flush_cache as a PMON routine
2914         (sim_monitor): handle flush_cache by ignoring it
2915
2916 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2917
2918         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2919         BigEndianMem.
2920         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2921         (BigEndianMem): Rename to ByteSwapMem and change sense.
2922         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2923         BigEndianMem references to !ByteSwapMem.
2924         (set_endianness): New function, with prototype.
2925         (sim_open): Call set_endianness.
2926         (sim_info): Use simBE instead of BigEndianMem.
2927         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2928         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2929         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2930         ifdefs, keeping the prototype declaration.
2931         (swap_word): Rewrite correctly.
2932         (ColdReset): Delete references to CONFIG.  Delete endianness related
2933         code; moved to set_endianness.
2934
2935 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2936
2937         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2938         * interp.c (CHECKHILO): Define away.
2939         (simSIGINT): New macro.
2940         (membank_size): Increase from 1MB to 2MB.
2941         (control_c): New function.
2942         (sim_resume): Rename parameter signal to signal_number.  Add local
2943         variable prev.  Call signal before and after simulate.
2944         (sim_stop_reason): Add simSIGINT support.
2945         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2946         functions always.
2947         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2948         if logfh is NULL.
2949         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2950         a call to sim_warning.
2951
2952 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2953
2954         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2955         16 bit instructions.
2956
2957 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2958
2959         Add support for mips16 (16 bit MIPS implementation):
2960         * gencode.c (inst_type): Add mips16 instruction encoding types.
2961         (GETDATASIZEINSN): Define.
2962         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2963         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2964         mtlo.
2965         (MIPS16_DECODE): New table, for mips16 instructions.
2966         (bitmap_val): New static function.
2967         (struct mips16_op): Define.
2968         (mips16_op_table): New table, for mips16 operands.
2969         (build_mips16_operands): New static function.
2970         (process_instructions): If PC is odd, decode a mips16
2971         instruction.  Break out instruction handling into new
2972         build_instruction function.
2973         (build_instruction): New static function, broken out of
2974         process_instructions.  Check modifiers rather than flags for SHIFT
2975         bit count and m[ft]{hi,lo} direction.
2976         (usage): Pass program name to fprintf.
2977         (main): Remove unused variable this_option_optind.  Change
2978         ``*loptarg++'' to ``loptarg++''.
2979         (my_strtoul): Parenthesize && within ||.
2980         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2981         (simulate): If PC is odd, fetch a 16 bit instruction, and
2982         increment PC by 2 rather than 4.
2983         * configure.in: Add case for mips16*-*-*.
2984         * configure: Rebuild.
2985
2986 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2987
2988         * interp.c: Allow -t to enable tracing in standalone simulator.
2989         Fix garbage output in trace file and error messages.
2990
2991 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2992
2993         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2994         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2995         * configure.in: Simplify using macros in ../common/aclocal.m4.
2996         * configure: Regenerated.
2997         * tconfig.in: New file.
2998
2999 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
3000
3001         * interp.c: Fix bugs in 64-bit port.
3002         Use ansi function declarations for msvc compiler.
3003         Initialize and test file pointer in trace code.
3004         Prevent duplicate definition of LAST_EMED_REGNUM.
3005
3006 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3007
3008         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3009
3010 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3011
3012         * interp.c (SignalException): Check for explicit terminating
3013         breakpoint value.
3014         * gencode.c: Pass instruction value through SignalException()
3015         calls for Trap, Breakpoint and Syscall.
3016
3017 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3018
3019         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3020         only used on those hosts that provide it.
3021         * configure.in: Add sqrt() to list of functions to be checked for.
3022         * config.in: Re-generated.
3023         * configure: Re-generated.
3024
3025 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3026
3027         * gencode.c (process_instructions): Call build_endian_shift when
3028         expanding STORE RIGHT, to fix swr.
3029         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3030         clear the high bits.
3031         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3032         Fix float to int conversions to produce signed values.
3033
3034 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3035
3036         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3037         (process_instructions): Correct handling of nor instruction.
3038         Correct shift count for 32 bit shift instructions. Correct sign
3039         extension for arithmetic shifts to not shift the number of bits in
3040         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3041         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3042         Fix madd.
3043         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3044         It's OK to have a mult follow a mult.  What's not OK is to have a
3045         mult follow an mfhi.
3046         (Convert): Comment out incorrect rounding code.
3047
3048 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3049
3050         * interp.c (sim_monitor): Improved monitor printf
3051         simulation. Tidied up simulator warnings, and added "--log" option
3052         for directing warning message output.
3053         * gencode.c: Use sim_warning() rather than WARNING macro.
3054
3055 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3056
3057         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3058         getopt1.o, rather than on gencode.c.  Link objects together.
3059         Don't link against -liberty.
3060         (gencode.o, getopt.o, getopt1.o): New targets.
3061         * gencode.c: Include <ctype.h> and "ansidecl.h".
3062         (AND): Undefine after including "ansidecl.h".
3063         (ULONG_MAX): Define if not defined.
3064         (OP_*): Don't define macros; now defined in opcode/mips.h.
3065         (main): Call my_strtoul rather than strtoul.
3066         (my_strtoul): New static function.
3067
3068 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3069
3070         * gencode.c (process_instructions):  Generate word64 and uword64
3071         instead of `long long' and `unsigned long long' data types.
3072         * interp.c:  #include sysdep.h to get signals, and define default
3073         for SIGBUS.
3074         * (Convert):  Work around for Visual-C++ compiler bug with type
3075         conversion.
3076         * support.h:  Make things compile under Visual-C++ by using
3077         __int64 instead of `long long'.  Change many refs to long long
3078         into word64/uword64 typedefs.
3079
3080 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3081
3082         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3083         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3084         (docdir): Removed.
3085         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3086         (AC_PROG_INSTALL): Added.
3087         (AC_PROG_CC): Moved to before configure.host call.
3088         * configure: Rebuilt.
3089
3090 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3091
3092         * configure.in: Define @SIMCONF@ depending on mips target.
3093         * configure: Rebuild.
3094         * Makefile.in (run): Add @SIMCONF@ to control simulator
3095         construction.
3096         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3097         * interp.c: Remove some debugging, provide more detailed error
3098         messages, update memory accesses to use LOADDRMASK.
3099
3100 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3101
3102         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3103         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3104         stamp-h.
3105         * configure: Rebuild.
3106         * config.in: New file, generated by autoheader.
3107         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3108         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3109         HAVE_ANINT and HAVE_AINT, as appropriate.
3110         * Makefile.in (run): Use @LIBS@ rather than -lm.
3111         (interp.o): Depend upon config.h.
3112         (Makefile): Just rebuild Makefile.
3113         (clean): Remove stamp-h.
3114         (mostlyclean): Make the same as clean, not as distclean.
3115         (config.h, stamp-h): New targets.
3116
3117 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3118
3119         * interp.c (ColdReset): Fix boolean test. Make all simulator
3120         globals static.
3121
3122 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3123
3124         * interp.c (xfer_direct_word, xfer_direct_long,
3125         swap_direct_word, swap_direct_long, xfer_big_word,
3126         xfer_big_long, xfer_little_word, xfer_little_long,
3127         swap_word,swap_long): Added.
3128         * interp.c (ColdReset): Provide function indirection to
3129         host<->simulated_target transfer routines.
3130         * interp.c (sim_store_register, sim_fetch_register): Updated to
3131         make use of indirected transfer routines.
3132
3133 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3134
3135         * gencode.c (process_instructions): Ensure FP ABS instruction
3136         recognised.
3137         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3138         system call support.
3139
3140 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3141
3142         * interp.c (sim_do_command): Complain if callback structure not
3143         initialised.
3144
3145 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3146
3147         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3148         support for Sun hosts.
3149         * Makefile.in (gencode): Ensure the host compiler and libraries
3150         used for cross-hosted build.
3151
3152 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3153
3154         * interp.c, gencode.c: Some more (TODO) tidying.
3155
3156 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3157
3158         * gencode.c, interp.c: Replaced explicit long long references with
3159         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3160         * support.h (SET64LO, SET64HI): Macros added.
3161
3162 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3163
3164         * configure: Regenerate with autoconf 2.7.
3165
3166 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3167
3168         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3169         * support.h: Remove superfluous "1" from #if.
3170         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3171
3172 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3173
3174         * interp.c (StoreFPR): Control UndefinedResult() call on
3175         WARN_RESULT manifest.
3176
3177 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3178
3179         * gencode.c: Tidied instruction decoding, and added FP instruction
3180         support.
3181
3182         * interp.c: Added dineroIII, and BSD profiling support. Also
3183         run-time FP handling.
3184
3185 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3186
3187         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3188         gencode.c, interp.c, support.h: created.