sim/mips/ChangeLog

   1 2005-06-16  David Ung  <davidu@mips.com>
   2             Nigel Stephens  <nigel@mips.com>
   3
   4         * mips.igen: New mips16e model and include m16e.igen.
   5         (check_u64): Add mips16e tag.
   6         * m16e.igen: New file for MIPS16e instructions.
   7         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
   8         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
   9         models.
  10         * configure: Regenerate.
  11
  12 2005-05-26  David Ung  <davidu@mips.com>
  13
  14         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
  15         tags to all instructions which are applicable to the new ISAs.
  16         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
  17         vr.igen.
  18         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
  19         instructions.
  20         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
  21         to mips.igen.
  22         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
  23         * configure: Regenerate.
  24
  25 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
  26
  27         * configure: Regenerate.
  28
  29 2005-01-14  Andrew Cagney  <cagney@gnu.org>
  30
  31         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
  32         explicit call to AC_CONFIG_HEADER.
  33         * configure: Regenerate.
  34
  35 2005-01-12  Andrew Cagney  <cagney@gnu.org>
  36
  37         * configure.ac: Update to use ../common/common.m4.
  38         * configure: Re-generate.
  39
  40 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
  41
  42         * configure: Regenerated to track ../common/aclocal.m4 changes.
  43
  44 2005-01-07  Andrew Cagney  <cagney@gnu.org>
  45
  46         * configure.ac: Rename configure.in, require autoconf 2.59.
  47         * configure: Re-generate.
  48
  49 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
  50
  51         * configure: Regenerate for ../common/aclocal.m4 update.
  52
  53 2004-09-24  Monika Chaddha  <monika@acmet.com>
  54
  55         Committed by Andrew Cagney.
  56         * m16.igen (CMP, CMPI): Fix assembler.
  57
  58 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
  59
  60         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
  61         * configure: Regenerate.
  62
  63 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
  64
  65         * configure.in (sim_m16_machine): Include mipsIII.
  66         * configure: Regenerate.
  67
  68 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
  69
  70         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
  71         from COP0_BADVADDR.
  72         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
  73
  74 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
  75
  76         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
  77
  78 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
  79
  80         * mips.igen (check_fmt): Remove.
  81         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
  82         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
  83         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
  84         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
  85         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
  86         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
  87         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
  88         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
  89         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
  90         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
  91
  92 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
  93
  94         * sb1.igen (check_sbx): New function.
  95         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
  96
  97 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
  98             Richard Sandiford  <rsandifo@redhat.com>
  99
 100         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 101         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 102         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 103         separate implementations for mipsIV and mipsV.  Use new macros to
 104         determine whether the restrictions apply.
 105
 106 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 107
 108         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 109         (check_mult_hilo): Improve comments.
 110         (check_div_hilo): Likewise.  Also, fork off a new version
 111         to handle mips32/mips64 (since there are no hazards to check
 112         in MIPS32/MIPS64).
 113
 114 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 115
 116         * mips.igen (do_dmultx): Fix check for negative operands.
 117
 118 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 119
 120         * Makefile.in (SHELL): Make sure this is defined.
 121         (various): Use $(SHELL) whenever we invoke move-if-change.
 122
 123 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 124
 125         * cp1.c: Tweak attribution slightly.
 126         * cp1.h: Likewise.
 127         * mdmx.c: Likewise.
 128         * mdmx.igen: Likewise.
 129         * mips3d.igen: Likewise.
 130         * sb1.igen: Likewise.
 131
 132 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 133
 134         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 135         unsigned operands.
 136
 137 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 138
 139         * interp.c (sim_open): Rename _bfd to bfd.
 140         (sim_create_inferior): Ditto.
 141
 142 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 143
 144         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 145
 146 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 147
 148         * mips.igen (EI, DI): Remove.
 149
 150 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 151
 152         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 153
 154 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 155             Andrew Cagney  <ac131313@redhat.com>
 156             Gavin Romig-Koch  <gavin@redhat.com>
 157             Graydon Hoare  <graydon@redhat.com>
 158             Aldy Hernandez  <aldyh@redhat.com>
 159             Dave Brolley  <brolley@redhat.com>
 160             Chris Demetriou  <cgd@broadcom.com>
 161
 162         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 163         (sim_mach_default): New variable.
 164         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 165         Add a new simulator generator, MULTI.
 166         * configure: Regenerate.
 167         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 168         (multi-run.o): New dependency.
 169         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 170         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 171         (tmp-multi): Combine them.
 172         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 173         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 174         (distclean-extra): New rule.
 175         * sim-main.h: Include bfd.h.
 176         (MIPS_MACH): New macro.
 177         * mips.igen (vr4120, vr5400, vr5500): New models.
 178         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 179         * vr.igen: Replace with new version.
 180
 181 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 182
 183         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 184         * configure: Regenerate.
 185
 186 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 187
 188         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 189         * mips.igen: Remove all invocations of check_branch_bug and
 190         mark_branch_bug.
 191
 192 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 193
 194         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 195
 196 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 197
 198         * mips.igen (do_load_double, do_store_double): New functions.
 199         (LDC1, SDC1): Rename to...
 200         (LDC1b, SDC1b): respectively.
 201         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 202
 203 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 204
 205         * cp1.c (fp_recip2): Modify initialization expression so that
 206         GCC will recognize it as constant.
 207
 208 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 209
 210         * mdmx.c (SD_): Delete.
 211         (Unpredictable): Re-define, for now, to directly invoke
 212         unpredictable_action().
 213         (mdmx_acc_op): Fix error in .ob immediate handling.
 214
 215 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 216
 217         * interp.c (sim_firmware_command): Initialize `address'.
 218
 219 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 220
 221         * configure: Regenerated to track ../common/aclocal.m4 changes.
 222
 223 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 224             Ed Satterthwaite  <ehs@broadcom.com>
 225
 226         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 227         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 228         * mips.igen: Include mips3d.igen.
 229         (mips3d): New model name for MIPS-3D ASE instructions.
 230         (CVT.W.fmt): Don't use this instruction for word (source) format
 231         instructions.
 232         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 233         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 234         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 235         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 236         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 237         (RSquareRoot1, RSquareRoot2): New macros.
 238         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 239         (fp_rsqrt2): New functions.
 240         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 241         * configure: Regenerate.
 242
 243 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 244             Ed Satterthwaite  <ehs@broadcom.com>
 245
 246         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 247         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 248         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 249         (convert): Note that this function is not used for paired-single
 250         format conversions.
 251         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 252         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 253         (check_fmt_p): Enable paired-single support.
 254         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 255         (PUU.PS): New instructions.
 256         (CVT.S.fmt): Don't use this instruction for paired-single format
 257         destinations.
 258         * sim-main.h (FP_formats): New value 'fmt_ps.'
 259         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 260         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 261
 262 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 263
 264         * mips.igen: Fix formatting of function calls in
 265         many FP operations.
 266
 267 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 268
 269         * mips.igen (MOVN, MOVZ): Trace result.
 270         (TNEI): Print "tnei" as the opcode name in traces.
 271         (CEIL.W): Add disassembly string for traces.
 272         (RSQRT.fmt): Make location of disassembly string consistent
 273         with other instructions.
 274
 275 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 276
 277         * mips.igen (X): Delete unused function.
 278
 279 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 280
 281         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 282
 283 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 284             Ed Satterthwaite  <ehs@broadcom.com>
 285
 286         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 287         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 288         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 289         (fp_nmsub): New prototypes.
 290         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 291         (NegMultiplySub): New defines.
 292         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 293         (MADD.D, MADD.S): Replace with...
 294         (MADD.fmt): New instruction.
 295         (MSUB.D, MSUB.S): Replace with...
 296         (MSUB.fmt): New instruction.
 297         (NMADD.D, NMADD.S): Replace with...
 298         (NMADD.fmt): New instruction.
 299         (NMSUB.D, MSUB.S): Replace with...
 300         (NMSUB.fmt): New instruction.
 301
 302 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 303             Ed Satterthwaite  <ehs@broadcom.com>
 304
 305         * cp1.c: Fix more comment spelling and formatting.
 306         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 307         (denorm_mode): New function.
 308         (fpu_unary, fpu_binary): Round results after operation, collect
 309         status from rounding operations, and update the FCSR.
 310         (convert): Collect status from integer conversions and rounding
 311         operations, and update the FCSR.  Adjust NaN values that result
 312         from conversions.  Convert to use sim_io_eprintf rather than
 313         fprintf, and remove some debugging code.
 314         * cp1.h (fenr_FS): New define.
 315
 316 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 317
 318         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 319         rounding mode to sim FP rounding mode flag conversion code into...
 320         (rounding_mode): New function.
 321
 322 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 323
 324         * cp1.c: Clean up formatting of a few comments.
 325         (value_fpr): Reformat switch statement.
 326
 327 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 328             Ed Satterthwaite  <ehs@broadcom.com>
 329
 330         * cp1.h: New file.
 331         * sim-main.h: Include cp1.h.
 332         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 333         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 334         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 335         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 336         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 337         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 338         * cp1.c: Don't include sim-fpu.h; already included by
 339         sim-main.h.  Clean up formatting of some comments.
 340         (NaN, Equal, Less): Remove.
 341         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 342         (fp_cmp): New functions.
 343         * mips.igen (do_c_cond_fmt): Remove.
 344         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 345         Compare.  Add result tracing.
 346         (CxC1): Remove, replace with...
 347         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 348         (DMxC1): Remove, replace with...
 349         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 350         (MxC1): Remove, replace with...
 351         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 352
 353 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 354
 355         * sim-main.h (FGRIDX): Remove, replace all uses with...
 356         (FGR_BASE): New macro.
 357         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 358         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 359         (NR_FGR, FGR): Likewise.
 360         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 361         * mips.igen: Likewise.
 362
 363 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 364
 365         * cp1.c: Add an FSF Copyright notice to this file.
 366
 367 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 368             Ed Satterthwaite  <ehs@broadcom.com>
 369
 370         * cp1.c (Infinity): Remove.
 371         * sim-main.h (Infinity): Likewise.
 372
 373         * cp1.c (fp_unary, fp_binary): New functions.
 374         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 375         (fp_sqrt): New functions, implemented in terms of the above.
 376         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 377         (Recip, SquareRoot): Remove (replaced by functions above).
 378         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 379         (fp_recip, fp_sqrt): New prototypes.
 380         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 381         (Recip, SquareRoot): Replace prototypes with #defines which
 382         invoke the functions above.
 383
 384 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 385
 386         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 387         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 388         file, remove PARAMS from prototypes.
 389         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 390         simulator state arguments.
 391         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 392         pass simulator state arguments.
 393         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 394         (store_fpr, convert): Remove 'sd' argument.
 395         (value_fpr): Likewise.  Convert to use 'SD' instead.
 396
 397 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 398
 399         * cp1.c (Min, Max): Remove #if 0'd functions.
 400         * sim-main.h (Min, Max): Remove.
 401
 402 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 403
 404         * cp1.c: fix formatting of switch case and default labels.
 405         * interp.c: Likewise.
 406         * sim-main.c: Likewise.
 407
 408 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 409
 410         * cp1.c: Clean up comments which describe FP formats.
 411          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 412
 413 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 414             Ed Satterthwaite  <ehs@broadcom.com>
 415
 416         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 417         Broadcom SiByte SB-1 processor configurations.
 418         * configure: Regenerate.
 419         * sb1.igen: New file.
 420         * mips.igen: Include sb1.igen.
 421         (sb1): New model.
 422         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 423         * mdmx.igen: Add "sb1" model to all appropriate functions and
 424         instructions.
 425         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 426         (ob_func, ob_acc): Reference the above.
 427         (qh_acc): Adjust to keep the same size as ob_acc.
 428         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 429         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 430
 431 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 432
 433         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 434
 435 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 436             Ed Satterthwaite  <ehs@broadcom.com>
 437
 438         * mips.igen (mdmx): New (pseudo-)model.
 439         * mdmx.c, mdmx.igen: New files.
 440         * Makefile.in (SIM_OBJS): Add mdmx.o.
 441         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 442         New typedefs.
 443         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 444         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 445         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 446         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 447         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 448         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 449         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 450         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 451         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 452         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 453         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 454         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 455         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 456         (qh_fmtsel): New macros.
 457         (_sim_cpu): New member "acc".
 458         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 459         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 460
 461 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 462
 463         * interp.c: Use 'deprecated' rather than 'depreciated.'
 464         * sim-main.h: Likewise.
 465
 466 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 467
 468         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 469         which wouldn't compile anyway.
 470         * sim-main.h (unpredictable_action): New function prototype.
 471         (Unpredictable): Define to call igen function unpredictable().
 472         (NotWordValue): New macro to call igen function not_word_value().
 473         (UndefinedResult): Remove.
 474         * interp.c (undefined_result): Remove.
 475         (unpredictable_action): New function.
 476         * mips.igen (not_word_value, unpredictable): New functions.
 477         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 478         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 479         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 480         NotWordValue() to check for unpredictable inputs, then
 481         Unpredictable() to handle them.
 482
 483 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 484
 485         * mips.igen: Fix formatting of calls to Unpredictable().
 486
 487 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 488
 489         * interp.c (sim_open): Revert previous change.
 490
 491 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 492
 493         * interp.c (sim_open): Disable chunk of code that wrote code in
 494         vector table entries.
 495
 496 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 497
 498         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 499         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 500         unused definitions.
 501
 502 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 503
 504         * cp1.c: Fix many formatting issues.
 505
 506 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 507
 508         * cp1.c (fpu_format_name): New function to replace...
 509         (DOFMT): This.  Delete, and update all callers.
 510         (fpu_rounding_mode_name): New function to replace...
 511         (RMMODE): This.  Delete, and update all callers.
 512
 513 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 514
 515         * interp.c: Move FPU support routines from here to...
 516         * cp1.c: Here.  New file.
 517         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 518         (cp1.o): New target.
 519
 520 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 521
 522         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 523         * mips.igen (mips32, mips64): New models, add to all instructions
 524         and functions as appropriate.
 525         (loadstore_ea, check_u64): New variant for model mips64.
 526         (check_fmt_p): New variant for models mipsV and mips64, remove
 527         mipsV model marking fro other variant.
 528         (SLL) Rename to...
 529         (SLLa) this.
 530         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 531         for mips32 and mips64.
 532         (DCLO, DCLZ): New instructions for mips64.
 533
 534 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 535
 536         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 537         immediate or code as a hex value with the "%#lx" format.
 538         (ANDI): Likewise, and fix printed instruction name.
 539
 540 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 541
 542         * sim-main.h (UndefinedResult, Unpredictable): New macros
 543         which currently do nothing.
 544
 545 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 546
 547         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 548         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 549         (status_CU3): New definitions.
 550
 551         * sim-main.h (ExceptionCause): Add new values for MIPS32
 552         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 553         for DebugBreakPoint and NMIReset to note their status in
 554         MIPS32 and MIPS64.
 555         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 556         (SignalExceptionCacheErr): New exception macros.
 557
 558 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 559
 560         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 561         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 562         is always enabled.
 563         (SignalExceptionCoProcessorUnusable): Take as argument the
 564         unusable coprocessor number.
 565
 566 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 567
 568         * mips.igen: Fix formatting of all SignalException calls.
 569
 570 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 571
 572         * sim-main.h (SIGNEXTEND): Remove.
 573
 574 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 575
 576         * mips.igen: Remove gencode comment from top of file, fix
 577         spelling in another comment.
 578
 579 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 580
 581         * mips.igen (check_fmt, check_fmt_p): New functions to check
 582         whether specific floating point formats are usable.
 583         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 584         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 585         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 586         Use the new functions.
 587         (do_c_cond_fmt): Remove format checks...
 588         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 589
 590 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 591
 592         * mips.igen: Fix formatting of check_fpu calls.
 593
 594 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 595
 596         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 597
 598 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 599
 600         * mips.igen: Remove whitespace at end of lines.
 601
 602 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 603
 604         * mips.igen (loadstore_ea): New function to do effective
 605         address calculations.
 606         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 607         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 608         CACHE): Use loadstore_ea to do effective address computations.
 609
 610 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 611
 612         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 613         * mips.igen (LL, CxC1, MxC1): Likewise.
 614
 615 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 616
 617         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 618         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 619         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 620         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 621         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 622         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 623         Don't split opcode fields by hand, use the opcode field values
 624         provided by igen.
 625
 626 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 627
 628         * mips.igen (do_divu): Fix spacing.
 629
 630         * mips.igen (do_dsllv): Move to be right before DSLLV,
 631         to match the rest of the do_<shift> functions.
 632
 633 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 634
 635         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 636         DSRL32, do_dsrlv): Trace inputs and results.
 637
 638 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 639
 640         * mips.igen (CACHE): Provide instruction-printing string.
 641
 642         * interp.c (signal_exception): Comment tokens after #endif.
 643
 644 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 645
 646         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 647         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 648         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 649         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 650         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 651         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 652         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 653         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 654
 655 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 656
 657         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 658         instruction-printing string.
 659         (LWU): Use '64' as the filter flag.
 660
 661 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 662
 663         * mips.igen (SDXC1): Fix instruction-printing string.
 664
 665 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 666
 667         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 668         filter flags "32,f".
 669
 670 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 671
 672         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 673         as the filter flag.
 674
 675 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 676
 677         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 678         add a comma) so that it more closely match the MIPS ISA
 679         documentation opcode partitioning.
 680         (PREF): Put useful names on opcode fields, and include
 681         instruction-printing string.
 682
 683 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 684
 685         * mips.igen (check_u64): New function which in the future will
 686         check whether 64-bit instructions are usable and signal an
 687         exception if not.  Currently a no-op.
 688         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 689         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 690         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 691         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 692
 693         * mips.igen (check_fpu): New function which in the future will
 694         check whether FPU instructions are usable and signal an exception
 695         if not.  Currently a no-op.
 696         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 697         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 698         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 699         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 700         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 701         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 702         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 703         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 704
 705 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 706
 707         * mips.igen (do_load_left, do_load_right): Move to be immediately
 708         following do_load.
 709         (do_store_left, do_store_right): Move to be immediately following
 710         do_store.
 711
 712 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 713
 714         * mips.igen (mipsV): New model name.  Also, add it to
 715         all instructions and functions where it is appropriate.
 716
 717 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 718
 719         * mips.igen: For all functions and instructions, list model
 720         names that support that instruction one per line.
 721
 722 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 723
 724         * mips.igen: Add some additional comments about supported
 725         models, and about which instructions go where.
 726         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 727         order as is used in the rest of the file.
 728
 729 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 730
 731         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 732         indicating that ALU32_END or ALU64_END are there to check
 733         for overflow.
 734         (DADD): Likewise, but also remove previous comment about
 735         overflow checking.
 736
 737 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 738
 739         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 740         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 741         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 742         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 743         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 744         fields (i.e., add and move commas) so that they more closely
 745         match the MIPS ISA documentation opcode partitioning.
 746
 747 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 748
 749         * mips.igen (ADDI): Print immediate value.
 750         (BREAK): Print code.
 751         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 752         (SLL): Print "nop" specially, and don't run the code
 753         that does the shift for the "nop" case.
 754
 755 2001-11-17  Fred Fish  <fnf@redhat.com>
 756
 757         * sim-main.h (float_operation): Move enum declaration outside
 758         of _sim_cpu struct declaration.
 759
 760 2001-04-12  Jim Blandy  <jimb@redhat.com>
 761
 762         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 763         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 764         set of the FCSR.
 765         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 766         PENDING_FILL, and you can get the intended effect gracefully by
 767         calling PENDING_SCHED directly.
 768
 769 2001-02-23  Ben Elliston  <bje@redhat.com>
 770
 771         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 772         already defined elsewhere.
 773
 774 2001-02-19  Ben Elliston  <bje@redhat.com>
 775
 776         * sim-main.h (sim_monitor): Return an int.
 777         * interp.c (sim_monitor): Add return values.
 778         (signal_exception): Handle error conditions from sim_monitor.
 779
 780 2001-02-08  Ben Elliston  <bje@redhat.com>
 781
 782         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 783         (store_memory): Likewise, pass cia to sim_core_write*.
 784
 785 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 786
 787         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 788         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 789
 790 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 791
 792         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 793         * Makefile.in: Don't delete *.igen when cleaning directory.
 794
 795 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 796
 797         * m16.igen (break): Call SignalException not sim_engine_halt.
 798
 799 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 800
 801         From Jason Eckhardt:
 802         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 803
 804 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 805
 806         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 807
 808 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 809
 810         * mips.igen (do_dmultx): Fix typo.
 811
 812 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 813
 814         * configure: Regenerated to track ../common/aclocal.m4 changes.
 815
 816 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 817
 818         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 819
 820 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 821
 822         * sim-main.h (GPR_CLEAR): Define macro.
 823
 824 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 825
 826         * interp.c (decode_coproc): Output long using %lx and not %s.
 827
 828 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 829
 830         * interp.c (sim_open): Sort & extend dummy memory regions for
 831         --board=jmr3904 for eCos.
 832
 833 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 834
 835         * configure: Regenerated.
 836
 837 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 838
 839         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 840         calls, conditional on the simulator being in verbose mode.
 841
 842 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 843
 844         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 845         cache don't get ReservedInstruction traps.
 846
 847 1999-11-29  Mark Salter  <msalter@cygnus.com>
 848
 849         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 850         to clear status bits in sdisr register. This is how the hardware works.
 851
 852         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 853         being used by cygmon.
 854
 855 1999-11-11  Andrew Haley  <aph@cygnus.com>
 856
 857         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 858         instructions.
 859
 860 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 861
 862         * mips.igen (MULT): Correct previous mis-applied patch.
 863
 864 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 865
 866         * mips.igen (delayslot32): Handle sequence like
 867         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 868         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 869         (MULT): Actually pass the third register...
 870
 871 1999-09-03  Mark Salter  <msalter@cygnus.com>
 872
 873         * interp.c (sim_open): Added more memory aliases for additional
 874         hardware being touched by cygmon on jmr3904 board.
 875
 876 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 877
 878         * configure: Regenerated to track ../common/aclocal.m4 changes.
 879
 880 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 881
 882         * interp.c (sim_store_register): Handle case where client - GDB -
 883         specifies that a 4 byte register is 8 bytes in size.
 884         (sim_fetch_register): Ditto.
 885
 886 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 887
 888         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 889         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 890         (idt_monitor_base): Base address for IDT monitor traps.
 891         (pmon_monitor_base): Ditto for PMON.
 892         (lsipmon_monitor_base): Ditto for LSI PMON.
 893         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 894         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 895         (sim_firmware_command): New function.
 896         (mips_option_handler): Call it for OPTION_FIRMWARE.
 897         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 898         option was given, add no monitor by default.  Add BREAK hooks only if
 899         monitors are also there.
 900
 901 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 902
 903         * interp.c (sim_monitor): Flush output before reading input.
 904
 905 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 906
 907         * tconfig.in (SIM_HANDLES_LMA): Always define.
 908
 909 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 910
 911         From Mark Salter <msalter@cygnus.com>:
 912         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 913         (sim_open): Add setup for BSP board.
 914
 915 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 916
 917         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 918         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 919         them as unimplemented.
 920
 921 1999-05-08  Felix Lee  <flee@cygnus.com>
 922
 923         * configure: Regenerated to track ../common/aclocal.m4 changes.
 924
 925 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 926
 927         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 928
 929 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 930
 931         * configure.in: Any mips64vr5*-*-* target should have
 932         -DTARGET_ENABLE_FR=1.
 933         (default_endian): Any mips64vr*el-*-* target should default to
 934         LITTLE_ENDIAN.
 935         * configure: Re-generate.
 936
 937 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 938
 939         * mips.igen (ldl): Extend from _16_, not 32.
 940
 941 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 942
 943         * interp.c (sim_store_register): Force registers written to by GDB
 944         into an un-interpreted state.
 945
 946 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 947
 948         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 949         CPU, start periodic background I/O polls.
 950         (tx3904sio_poll): New function: periodic I/O poller.
 951
 952 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 953
 954         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 955
 956 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 957
 958         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 959         case statement.
 960
 961 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 962
 963         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 964         (load_word): Call SIM_CORE_SIGNAL hook on error.
 965         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 966         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 967         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 968         * sim-main.h (COP0_BADVADDR): Define.
 969         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 970         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 971         (_sim_cpu): Add exc_* fields to store register value snapshots.
 972         * mips.igen (*): Replace memory-related SignalException* calls
 973         with references to SIM_CORE_SIGNAL hook.
 974
 975         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 976         fix.
 977         * sim-main.c (*): Minor warning cleanups.
 978
 979 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 980
 981         * m16.igen (DADDIU5): Correct type-o.
 982
 983 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 984
 985         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 986         variables.
 987
 988 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 989
 990         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 991         to include path.
 992         (interp.o): Add dependency on itable.h
 993         (oengine.c, gencode): Delete remaining references.
 994         (BUILT_SRC_FROM_GEN): Clean up.
 995
 996 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 997
 998         * vr4run.c: New.
 999         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1000         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1001         tmp-run-hack) : New.
1002         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1003         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1004         Drop the "64" qualifier to get the HACK generator working.
1005         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1006         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1007         qualifier to get the hack generator working.
1008         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1009         (DSLL): Use do_dsll.
1010         (DSLLV): Use do_dsllv.
1011         (DSRA): Use do_dsra.
1012         (DSRL): Use do_dsrl.
1013         (DSRLV): Use do_dsrlv.
1014         (BC1): Move *vr4100 to get the HACK generator working.
1015         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1016         get the HACK generator working.
1017         (MACC) Rename to get the HACK generator working.
1018         (DMACC,MACCS,DMACCS): Add the 64.
1019
1020 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1021
1022         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1023         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1024
1025 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1026
1027     * mips/interp.c (DEBUG): Cleanups.
1028
1029 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1030
1031         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1032         (tx3904sio_tickle): fflush after a stdout character output.
1033
1034 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1035
1036         * interp.c (sim_close): Uninstall modules.
1037
1038 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1039
1040         * sim-main.h, interp.c (sim_monitor): Change to global
1041         function.
1042
1043 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1044
1045         * configure.in (vr4100): Only include vr4100 instructions in
1046         simulator.
1047         * configure: Re-generate.
1048         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1049
1050 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1051
1052         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1053         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1054         true alternative.
1055
1056         * configure.in (sim_default_gen, sim_use_gen): Replace with
1057         sim_gen.
1058         (--enable-sim-igen): Delete config option. Always using IGEN.
1059         * configure: Re-generate.
1060
1061         * Makefile.in (gencode): Kill, kill, kill.
1062         * gencode.c: Ditto.
1063
1064 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1065
1066         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1067         bit mips16 igen simulator.
1068         * configure: Re-generate.
1069
1070         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1071         as part of vr4100 ISA.
1072         * vr.igen: Mark all instructions as 64 bit only.
1073
1074 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1075
1076         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1077         Pacify GCC.
1078
1079 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1080
1081         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1082         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1083         * configure: Re-generate.
1084
1085         * m16.igen (BREAK): Define breakpoint instruction.
1086         (JALX32): Mark instruction as mips16 and not r3900.
1087         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1088
1089         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1090
1091 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1092
1093         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1094         insn as a debug breakpoint.
1095
1096         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1097         pending.slot_size.
1098         (PENDING_SCHED): Clean up trace statement.
1099         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1100         (PENDING_FILL): Delay write by only one cycle.
1101         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1102
1103         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1104         of pending writes.
1105         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1106         32 & 64.
1107         (pending_tick): Move incrementing of index to FOR statement.
1108         (pending_tick): Only update PENDING_OUT after a write has occured.
1109
1110         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1111         build simulator.
1112         * configure: Re-generate.
1113
1114         * interp.c (sim_engine_run OLD): Delete explicit call to
1115         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1116
1117 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1118
1119         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1120         interrupt level number to match changed SignalExceptionInterrupt
1121         macro.
1122
1123 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1124
1125         * interp.c: #include "itable.h" if WITH_IGEN.
1126         (get_insn_name): New function.
1127         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1128         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1129
1130 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1131
1132         * configure: Rebuilt to inhale new common/aclocal.m4.
1133
1134 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1135
1136         * dv-tx3904sio.c: Include sim-assert.h.
1137
1138 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1139
1140         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1141         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1142         Reorganize target-specific sim-hardware checks.
1143         * configure: rebuilt.
1144         * interp.c (sim_open): For tx39 target boards, set
1145         OPERATING_ENVIRONMENT, add tx3904sio devices.
1146         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1147         ROM executables.  Install dv-sockser into sim-modules list.
1148
1149         * dv-tx3904irc.c: Compiler warning clean-up.
1150         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1151         frequent hw-trace messages.
1152
1153 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1154
1155         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1156
1157 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1158
1159         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1160
1161         * vr.igen: New file.
1162         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1163         * mips.igen: Define vr4100 model. Include vr.igen.
1164 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1165
1166         * mips.igen (check_mf_hilo): Correct check.
1167
1168 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1169
1170         * sim-main.h (interrupt_event): Add prototype.
1171
1172         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1173         register_ptr, register_value.
1174         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1175
1176         * sim-main.h (tracefh): Make extern.
1177
1178 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1179
1180         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1181         Reduce unnecessarily high timer event frequency.
1182         * dv-tx3904cpu.c: Ditto for interrupt event.
1183
1184 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1185
1186         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1187         to allay warnings.
1188         (interrupt_event): Made non-static.
1189
1190         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1191         interchange of configuration values for external vs. internal
1192         clock dividers.
1193
1194 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1195
1196         * mips.igen (BREAK): Moved code to here for
1197         simulator-reserved break instructions.
1198         * gencode.c (build_instruction): Ditto.
1199         * interp.c (signal_exception): Code moved from here.  Non-
1200         reserved instructions now use exception vector, rather
1201         than halting sim.
1202         * sim-main.h: Moved magic constants to here.
1203
1204 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1205
1206         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1207         register upon non-zero interrupt event level, clear upon zero
1208         event value.
1209         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1210         by passing zero event value.
1211         (*_io_{read,write}_buffer): Endianness fixes.
1212         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1213         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1214
1215         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1216         serial I/O and timer module at base address 0xFFFF0000.
1217
1218 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1219
1220         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1221         and BigEndianCPU.
1222
1223 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1224
1225         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1226         parts.
1227         * configure: Update.
1228
1229 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1230
1231         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1232         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1233         * configure.in: Include tx3904tmr in hw_device list.
1234         * configure: Rebuilt.
1235         * interp.c (sim_open): Instantiate three timer instances.
1236         Fix address typo of tx3904irc instance.
1237
1238 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1239
1240         * interp.c (signal_exception): SystemCall exception now uses
1241         the exception vector.
1242
1243 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1244
1245         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1246         to allay warnings.
1247
1248 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1249
1250         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1251
1252 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1253
1254         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1255
1256         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1257         sim-main.h. Declare a struct hw_descriptor instead of struct
1258         hw_device_descriptor.
1259
1260 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1261
1262         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1263         right bits and then re-align left hand bytes to correct byte
1264         lanes.  Fix incorrect computation in do_store_left when loading
1265         bytes from second word.
1266
1267 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1268
1269         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1270         * interp.c (sim_open): Only create a device tree when HW is
1271         enabled.
1272
1273         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1274         * interp.c (signal_exception): Ditto.
1275
1276 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1277
1278         * gencode.c: Mark BEGEZALL as LIKELY.
1279
1280 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1281
1282         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1283         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1284
1285 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1286
1287         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1288         modules.  Recognize TX39 target with "mips*tx39" pattern.
1289         * configure: Rebuilt.
1290         * sim-main.h (*): Added many macros defining bits in
1291         TX39 control registers.
1292         (SignalInterrupt): Send actual PC instead of NULL.
1293         (SignalNMIReset): New exception type.
1294         * interp.c (board): New variable for future use to identify
1295         a particular board being simulated.
1296         (mips_option_handler,mips_options): Added "--board" option.
1297         (interrupt_event): Send actual PC.
1298         (sim_open): Make memory layout conditional on board setting.
1299         (signal_exception): Initial implementation of hardware interrupt
1300         handling.  Accept another break instruction variant for simulator
1301         exit.
1302         (decode_coproc): Implement RFE instruction for TX39.
1303         (mips.igen): Decode RFE instruction as such.
1304         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1305         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1306         bbegin to implement memory map.
1307         * dv-tx3904cpu.c: New file.
1308         * dv-tx3904irc.c: New file.
1309
1310 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1311
1312         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1313
1314 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1315
1316         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1317         with calls to check_div_hilo.
1318
1319 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1320
1321         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1322         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1323         Add special r3900 version of do_mult_hilo.
1324         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1325         with calls to check_mult_hilo.
1326         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1327         with calls to check_div_hilo.
1328
1329 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1332         Document a replacement.
1333
1334 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1335
1336         * interp.c (sim_monitor): Make mon_printf work.
1337
1338 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1339
1340         * sim-main.h (INSN_NAME): New arg `cpu'.
1341
1342 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1343
1344         * configure: Regenerated to track ../common/aclocal.m4 changes.
1345
1346 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1347
1348         * configure: Regenerated to track ../common/aclocal.m4 changes.
1349         * config.in: Ditto.
1350
1351 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1352
1353         * acconfig.h: New file.
1354         * configure.in: Reverted change of Apr 24; use sinclude again.
1355
1356 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1357
1358         * configure: Regenerated to track ../common/aclocal.m4 changes.
1359         * config.in: Ditto.
1360
1361 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1362
1363         * configure.in: Don't call sinclude.
1364
1365 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1366
1367         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1368
1369 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1370
1371         * mips.igen (ERET): Implement.
1372
1373         * interp.c (decode_coproc): Return sign-extended EPC.
1374
1375         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1376
1377         * interp.c (signal_exception): Do not ignore Trap.
1378         (signal_exception): On TRAP, restart at exception address.
1379         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1380         (signal_exception): Update.
1381         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1382         so that TRAP instructions are caught.
1383
1384 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1385
1386         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1387         contains HI/LO access history.
1388         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1389         (HIACCESS, LOACCESS): Delete, replace with
1390         (HIHISTORY, LOHISTORY): New macros.
1391         (CHECKHILO): Delete all, moved to mips.igen
1392
1393         * gencode.c (build_instruction): Do not generate checks for
1394         correct HI/LO register usage.
1395
1396         * interp.c (old_engine_run): Delete checks for correct HI/LO
1397         register usage.
1398
1399         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1400         check_mf_cycles): New functions.
1401         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1402         do_divu, domultx, do_mult, do_multu): Use.
1403
1404         * tx.igen ("madd", "maddu"): Use.
1405
1406 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1407
1408         * mips.igen (DSRAV): Use function do_dsrav.
1409         (SRAV): Use new function do_srav.
1410
1411         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1412         (B): Sign extend 11 bit immediate.
1413         (EXT-B*): Shift 16 bit immediate left by 1.
1414         (ADDIU*): Don't sign extend immediate value.
1415
1416 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1417
1418         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1419
1420         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1421         functions.
1422
1423         * mips.igen (delayslot32, nullify_next_insn): New functions.
1424         (m16.igen): Always include.
1425         (do_*): Add more tracing.
1426
1427         * m16.igen (delayslot16): Add NIA argument, could be called by a
1428         32 bit MIPS16 instruction.
1429
1430         * interp.c (ifetch16): Move function from here.
1431         * sim-main.c (ifetch16): To here.
1432
1433         * sim-main.c (ifetch16, ifetch32): Update to match current
1434         implementations of LH, LW.
1435         (signal_exception): Don't print out incorrect hex value of illegal
1436         instruction.
1437
1438 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1439
1440         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1441         instruction.
1442
1443         * m16.igen: Implement MIPS16 instructions.
1444
1445         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1446         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1447         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1448         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1449         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1450         bodies of corresponding code from 32 bit insn to these.  Also used
1451         by MIPS16 versions of functions.
1452
1453         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1454         (IMEM16): Drop NR argument from macro.
1455
1456 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1457
1458         * Makefile.in (SIM_OBJS): Add sim-main.o.
1459
1460         * sim-main.h (address_translation, load_memory, store_memory,
1461         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1462         as INLINE_SIM_MAIN.
1463         (pr_addr, pr_uword64): Declare.
1464         (sim-main.c): Include when H_REVEALS_MODULE_P.
1465
1466         * interp.c (address_translation, load_memory, store_memory,
1467         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1468         from here.
1469         * sim-main.c: To here. Fix compilation problems.
1470
1471         * configure.in: Enable inlining.
1472         * configure: Re-config.
1473
1474 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1475
1476         * configure: Regenerated to track ../common/aclocal.m4 changes.
1477
1478 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1479
1480         * mips.igen: Include tx.igen.
1481         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1482         * tx.igen: New file, contains MADD and MADDU.
1483
1484         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1485         the hardwired constant `7'.
1486         (store_memory): Ditto.
1487         (LOADDRMASK): Move definition to sim-main.h.
1488
1489         mips.igen (MTC0): Enable for r3900.
1490         (ADDU): Add trace.
1491
1492         mips.igen (do_load_byte): Delete.
1493         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1494         do_store_right): New functions.
1495         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1496
1497         configure.in: Let the tx39 use igen again.
1498         configure: Update.
1499
1500 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1501
1502         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1503         not an address sized quantity.  Return zero for cache sizes.
1504
1505 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1506
1507         * mips.igen (r3900): r3900 does not support 64 bit integer
1508         operations.
1509
1510 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1511
1512         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1513         than igen one.
1514         * configure : Rebuild.
1515
1516 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1517
1518         * configure: Regenerated to track ../common/aclocal.m4 changes.
1519
1520 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1521
1522         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1523
1524 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1525
1526         * configure: Regenerated to track ../common/aclocal.m4 changes.
1527         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1528
1529 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1530
1531         * configure: Regenerated to track ../common/aclocal.m4 changes.
1532
1533 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1534
1535         * interp.c (Max, Min): Comment out functions. Not yet used.
1536
1537 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1538
1539         * configure: Regenerated to track ../common/aclocal.m4 changes.
1540
1541 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1542
1543         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1544         configurable settings for stand-alone simulator.
1545
1546         * configure.in: Added X11 search, just in case.
1547
1548         * configure: Regenerated.
1549
1550 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1551
1552         * interp.c (sim_write, sim_read, load_memory, store_memory):
1553         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1554
1555 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1556
1557         * sim-main.h (GETFCC): Return an unsigned value.
1558
1559 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1560
1561         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1562         (DADD): Result destination is RD not RT.
1563
1564 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1565
1566         * sim-main.h (HIACCESS, LOACCESS): Always define.
1567
1568         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1569
1570         * interp.c (sim_info): Delete.
1571
1572 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1573
1574         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1575         (mips_option_handler): New argument `cpu'.
1576         (sim_open): Update call to sim_add_option_table.
1577
1578 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1579
1580         * mips.igen (CxC1): Add tracing.
1581
1582 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1583
1584         * sim-main.h (Max, Min): Declare.
1585
1586         * interp.c (Max, Min): New functions.
1587
1588         * mips.igen (BC1): Add tracing.
1589
1590 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1591
1592         * interp.c Added memory map for stack in vr4100
1593
1594 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1595
1596         * interp.c (load_memory): Add missing "break"'s.
1597
1598 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1599
1600         * interp.c (sim_store_register, sim_fetch_register): Pass in
1601         length parameter.  Return -1.
1602
1603 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1604
1605         * interp.c: Added hardware init hook, fixed warnings.
1606
1607 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1608
1609         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1610
1611 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1612
1613         * interp.c (ifetch16): New function.
1614
1615         * sim-main.h (IMEM32): Rename IMEM.
1616         (IMEM16_IMMED): Define.
1617         (IMEM16): Define.
1618         (DELAY_SLOT): Update.
1619
1620         * m16run.c (sim_engine_run): New file.
1621
1622         * m16.igen: All instructions except LB.
1623         (LB): Call do_load_byte.
1624         * mips.igen (do_load_byte): New function.
1625         (LB): Call do_load_byte.
1626
1627         * mips.igen: Move spec for insn bit size and high bit from here.
1628         * Makefile.in (tmp-igen, tmp-m16): To here.
1629
1630         * m16.dc: New file, decode mips16 instructions.
1631
1632         * Makefile.in (SIM_NO_ALL): Define.
1633         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1634
1635 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1636
1637         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1638         point unit to 32 bit registers.
1639         * configure: Re-generate.
1640
1641 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1642
1643         * configure.in (sim_use_gen): Make IGEN the default simulator
1644         generator for generic 32 and 64 bit mips targets.
1645         * configure: Re-generate.
1646
1647 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1648
1649         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1650         bitsize.
1651
1652         * interp.c (sim_fetch_register, sim_store_register): Read/write
1653         FGR from correct location.
1654         (sim_open): Set size of FGR's according to
1655         WITH_TARGET_FLOATING_POINT_BITSIZE.
1656
1657         * sim-main.h (FGR): Store floating point registers in a separate
1658         array.
1659
1660 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1661
1662         * configure: Regenerated to track ../common/aclocal.m4 changes.
1663
1664 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1665
1666         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1667
1668         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1669
1670         * interp.c (pending_tick): New function.  Deliver pending writes.
1671
1672         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1673         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1674         it can handle mixed sized quantites and single bits.
1675
1676 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1677
1678         * interp.c (oengine.h): Do not include when building with IGEN.
1679         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1680         (sim_info): Ditto for PROCESSOR_64BIT.
1681         (sim_monitor): Replace ut_reg with unsigned_word.
1682         (*): Ditto for t_reg.
1683         (LOADDRMASK): Define.
1684         (sim_open): Remove defunct check that host FP is IEEE compliant,
1685         using software to emulate floating point.
1686         (value_fpr, ...): Always compile, was conditional on HASFPU.
1687
1688 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1689
1690         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1691         size.
1692
1693         * interp.c (SD, CPU): Define.
1694         (mips_option_handler): Set flags in each CPU.
1695         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1696         (sim_close): Do not clear STATE, deleted anyway.
1697         (sim_write, sim_read): Assume CPU zero's vm should be used for
1698         data transfers.
1699         (sim_create_inferior): Set the PC for all processors.
1700         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1701         argument.
1702         (mips16_entry): Pass correct nr of args to store_word, load_word.
1703         (ColdReset): Cold reset all cpu's.
1704         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1705         (sim_monitor, load_memory, store_memory, signal_exception): Use
1706         `CPU' instead of STATE_CPU.
1707
1708
1709         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1710         SD or CPU_.
1711
1712         * sim-main.h (signal_exception): Add sim_cpu arg.
1713         (SignalException*): Pass both SD and CPU to signal_exception.
1714         * interp.c (signal_exception): Update.
1715
1716         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1717         Ditto
1718         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1719         address_translation): Ditto
1720         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1721
1722 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1723
1724         * configure: Regenerated to track ../common/aclocal.m4 changes.
1725
1726 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1727
1728         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1729
1730         * mips.igen (model): Map processor names onto BFD name.
1731
1732         * sim-main.h (CPU_CIA): Delete.
1733         (SET_CIA, GET_CIA): Define
1734
1735 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1736
1737         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1738         regiser.
1739
1740         * configure.in (default_endian): Configure a big-endian simulator
1741         by default.
1742         * configure: Re-generate.
1743
1744 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1745
1746         * configure: Regenerated to track ../common/aclocal.m4 changes.
1747
1748 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1749
1750         * interp.c (sim_monitor): Handle Densan monitor outbyte
1751         and inbyte functions.
1752
1753 1997-12-29  Felix Lee  <flee@cygnus.com>
1754
1755         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1756
1757 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1758
1759         * Makefile.in (tmp-igen): Arrange for $zero to always be
1760         reset to zero after every instruction.
1761
1762 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1763
1764         * configure: Regenerated to track ../common/aclocal.m4 changes.
1765         * config.in: Ditto.
1766
1767 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1768
1769         * mips.igen (MSUB): Fix to work like MADD.
1770         * gencode.c (MSUB): Similarly.
1771
1772 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1773
1774         * configure: Regenerated to track ../common/aclocal.m4 changes.
1775
1776 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1777
1778         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1779
1780 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1781
1782         * sim-main.h (sim-fpu.h): Include.
1783
1784         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1785         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1786         using host independant sim_fpu module.
1787
1788 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1789
1790         * interp.c (signal_exception): Report internal errors with SIGABRT
1791         not SIGQUIT.
1792
1793         * sim-main.h (C0_CONFIG): New register.
1794         (signal.h): No longer include.
1795
1796         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1797
1798 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1799
1800         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1801
1802 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1803
1804         * mips.igen: Tag vr5000 instructions.
1805         (ANDI): Was missing mipsIV model, fix assembler syntax.
1806         (do_c_cond_fmt): New function.
1807         (C.cond.fmt): Handle mips I-III which do not support CC field
1808         separatly.
1809         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1810         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1811         in IV3.2 spec.
1812         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1813         vr5000 which saves LO in a GPR separatly.
1814
1815         * configure.in (enable-sim-igen): For vr5000, select vr5000
1816         specific instructions.
1817         * configure: Re-generate.
1818
1819 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1820
1821         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1822
1823         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1824         fmt_uninterpreted_64 bit cases to switch.  Convert to
1825         fmt_formatted,
1826
1827         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1828
1829         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1830         as specified in IV3.2 spec.
1831         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1832
1833 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1834
1835         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1836         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1837         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1838         PENDING_FILL versions of instructions.  Simplify.
1839         (X): New function.
1840         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1841         instructions.
1842         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1843         a signed value.
1844         (MTHI, MFHI): Disable code checking HI-LO.
1845
1846         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1847         global.
1848         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1849
1850 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1851
1852         * gencode.c (build_mips16_operands): Replace IPC with cia.
1853
1854         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1855         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1856         IPC to `cia'.
1857         (UndefinedResult): Replace function with macro/function
1858         combination.
1859         (sim_engine_run): Don't save PC in IPC.
1860
1861         * sim-main.h (IPC): Delete.
1862
1863
1864         * interp.c (signal_exception, store_word, load_word,
1865         address_translation, load_memory, store_memory, cache_op,
1866         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1867         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1868         current instruction address - cia - argument.
1869         (sim_read, sim_write): Call address_translation directly.
1870         (sim_engine_run): Rename variable vaddr to cia.
1871         (signal_exception): Pass cia to sim_monitor
1872
1873         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1874         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1875         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1876
1877         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1878         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1879         SIM_ASSERT.
1880
1881         * interp.c (signal_exception): Pass restart address to
1882         sim_engine_restart.
1883
1884         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1885         idecode.o): Add dependency.
1886
1887         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1888         Delete definitions
1889         (DELAY_SLOT): Update NIA not PC with branch address.
1890         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1891
1892         * mips.igen: Use CIA not PC in branch calculations.
1893         (illegal): Call SignalException.
1894         (BEQ, ADDIU): Fix assembler.
1895
1896 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1897
1898         * m16.igen (JALX): Was missing.
1899
1900         * configure.in (enable-sim-igen): New configuration option.
1901         * configure: Re-generate.
1902
1903         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1904
1905         * interp.c (load_memory, store_memory): Delete parameter RAW.
1906         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1907         bypassing {load,store}_memory.
1908
1909         * sim-main.h (ByteSwapMem): Delete definition.
1910
1911         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1912
1913         * interp.c (sim_do_command, sim_commands): Delete mips specific
1914         commands.  Handled by module sim-options.
1915
1916         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1917         (WITH_MODULO_MEMORY): Define.
1918
1919         * interp.c (sim_info): Delete code printing memory size.
1920
1921         * interp.c (mips_size): Nee sim_size, delete function.
1922         (power2): Delete.
1923         (monitor, monitor_base, monitor_size): Delete global variables.
1924         (sim_open, sim_close): Delete code creating monitor and other
1925         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1926         manage memory regions.
1927         (load_memory, store_memory): Use sim-core for memory model.
1928
1929         * interp.c (address_translation): Delete all memory map code
1930         except line forcing 32 bit addresses.
1931
1932 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1935         trace options.
1936
1937         * interp.c (logfh, logfile): Delete globals.
1938         (sim_open, sim_close): Delete code opening & closing log file.
1939         (mips_option_handler): Delete -l and -n options.
1940         (OPTION mips_options): Ditto.
1941
1942         * interp.c (OPTION mips_options): Rename option trace to dinero.
1943         (mips_option_handler): Update.
1944
1945 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1946
1947         * interp.c (fetch_str): New function.
1948         (sim_monitor): Rewrite using sim_read & sim_write.
1949         (sim_open): Check magic number.
1950         (sim_open): Write monitor vectors into memory using sim_write.
1951         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1952         (sim_read, sim_write): Simplify - transfer data one byte at a
1953         time.
1954         (load_memory, store_memory): Clarify meaning of parameter RAW.
1955
1956         * sim-main.h (isHOST): Defete definition.
1957         (isTARGET): Mark as depreciated.
1958         (address_translation): Delete parameter HOST.
1959
1960         * interp.c (address_translation): Delete parameter HOST.
1961
1962 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1963
1964         * mips.igen:
1965
1966         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1967         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1968
1969 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1970
1971         * mips.igen: Add model filter field to records.
1972
1973 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1974
1975         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1976
1977         interp.c (sim_engine_run): Do not compile function sim_engine_run
1978         when WITH_IGEN == 1.
1979
1980         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1981         target architecture.
1982
1983         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1984         igen. Replace with configuration variables sim_igen_flags /
1985         sim_m16_flags.
1986
1987         * m16.igen: New file.  Copy mips16 insns here.
1988         * mips.igen: From here.
1989
1990 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1991
1992         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1993         to top.
1994         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1995
1996 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1997
1998         * gencode.c (build_instruction): Follow sim_write's lead in using
1999         BigEndianMem instead of !ByteSwapMem.
2000
2001 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2002
2003         * configure.in (sim_gen): Dependent on target, select type of
2004         generator.  Always select old style generator.
2005
2006         configure: Re-generate.
2007
2008         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2009         targets.
2010         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2011         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2012         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2013         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2014         SIM_@sim_gen@_*, set by autoconf.
2015
2016 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2017
2018         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2019
2020         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2021         CURRENT_FLOATING_POINT instead.
2022
2023         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2024         (address_translation): Raise exception InstructionFetch when
2025         translation fails and isINSTRUCTION.
2026
2027         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2028         sim_engine_run): Change type of of vaddr and paddr to
2029         address_word.
2030         (address_translation, prefetch, load_memory, store_memory,
2031         cache_op): Change type of vAddr and pAddr to address_word.
2032
2033         * gencode.c (build_instruction): Change type of vaddr and paddr to
2034         address_word.
2035
2036 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2037
2038         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2039         macro to obtain result of ALU op.
2040
2041 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2042
2043         * interp.c (sim_info): Call profile_print.
2044
2045 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2046
2047         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2048
2049         * sim-main.h (WITH_PROFILE): Do not define, defined in
2050         common/sim-config.h.  Use sim-profile module.
2051         (simPROFILE): Delete defintion.
2052
2053         * interp.c (PROFILE): Delete definition.
2054         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2055         (sim_close): Delete code writing profile histogram.
2056         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2057         Delete.
2058         (sim_engine_run): Delete code profiling the PC.
2059
2060 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2061
2062         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2063
2064         * interp.c (sim_monitor): Make register pointers of type
2065         unsigned_word*.
2066
2067         * sim-main.h: Make registers of type unsigned_word not
2068         signed_word.
2069
2070 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2071
2072         * interp.c (sync_operation): Rename from SyncOperation, make
2073         global, add SD argument.
2074         (prefetch): Rename from Prefetch, make global, add SD argument.
2075         (decode_coproc): Make global.
2076
2077         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2078
2079         * gencode.c (build_instruction): Generate DecodeCoproc not
2080         decode_coproc calls.
2081
2082         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2083         (SizeFGR): Move to sim-main.h
2084         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2085         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2086         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2087         sim-main.h.
2088         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2089         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2090         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2091         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2092         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2093         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2094
2095         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2096         exception.
2097         (sim-alu.h): Include.
2098         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2099         (sim_cia): Typedef to instruction_address.
2100
2101 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2102
2103         * Makefile.in (interp.o): Rename generated file engine.c to
2104         oengine.c.
2105
2106         * interp.c: Update.
2107
2108 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2109
2110         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2111
2112 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2113
2114         * gencode.c (build_instruction): For "FPSQRT", output correct
2115         number of arguments to Recip.
2116
2117 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2118
2119         * Makefile.in (interp.o): Depends on sim-main.h
2120
2121         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2122
2123         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2124         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2125         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2126         STATE, DSSTATE): Define
2127         (GPR, FGRIDX, ..): Define.
2128
2129         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2130         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2131         (GPR, FGRIDX, ...): Delete macros.
2132
2133         * interp.c: Update names to match defines from sim-main.h
2134
2135 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2136
2137         * interp.c (sim_monitor): Add SD argument.
2138         (sim_warning): Delete.  Replace calls with calls to
2139         sim_io_eprintf.
2140         (sim_error): Delete. Replace calls with sim_io_error.
2141         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2142         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2143         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2144         argument.
2145         (mips_size): Rename from sim_size. Add SD argument.
2146
2147         * interp.c (simulator): Delete global variable.
2148         (callback): Delete global variable.
2149         (mips_option_handler, sim_open, sim_write, sim_read,
2150         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2151         sim_size,sim_monitor): Use sim_io_* not callback->*.
2152         (sim_open): ZALLOC simulator struct.
2153         (PROFILE): Do not define.
2154
2155 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2156
2157         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2158         support.h with corresponding code.
2159
2160         * sim-main.h (word64, uword64), support.h: Move definition to
2161         sim-main.h.
2162         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2163
2164         * support.h: Delete
2165         * Makefile.in: Update dependencies
2166         * interp.c: Do not include.
2167
2168 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2169
2170         * interp.c (address_translation, load_memory, store_memory,
2171         cache_op): Rename to from AddressTranslation et.al., make global,
2172         add SD argument
2173
2174         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2175         CacheOp): Define.
2176
2177         * interp.c (SignalException): Rename to signal_exception, make
2178         global.
2179
2180         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2181
2182         * sim-main.h (SignalException, SignalExceptionInterrupt,
2183         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2184         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2185         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2186         Define.
2187
2188         * interp.c, support.h: Use.
2189
2190 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2191
2192         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2193         to value_fpr / store_fpr. Add SD argument.
2194         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2195         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2196
2197         * sim-main.h (ValueFPR, StoreFPR): Define.
2198
2199 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2200
2201         * interp.c (sim_engine_run): Check consistency between configure
2202         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2203         and HASFPU.
2204
2205         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2206         (mips_fpu): Configure WITH_FLOATING_POINT.
2207         (mips_endian): Configure WITH_TARGET_ENDIAN.
2208         * configure: Update.
2209
2210 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2211
2212         * configure: Regenerated to track ../common/aclocal.m4 changes.
2213
2214 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2215
2216         * configure: Regenerated.
2217
2218 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2219
2220         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2221
2222 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2223
2224         * gencode.c (print_igen_insn_models): Assume certain architectures
2225         include all mips* instructions.
2226         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2227         instruction.
2228
2229         * Makefile.in (tmp.igen): Add target. Generate igen input from
2230         gencode file.
2231
2232         * gencode.c (FEATURE_IGEN): Define.
2233         (main): Add --igen option.  Generate output in igen format.
2234         (process_instructions): Format output according to igen option.
2235         (print_igen_insn_format): New function.
2236         (print_igen_insn_models): New function.
2237         (process_instructions): Only issue warnings and ignore
2238         instructions when no FEATURE_IGEN.
2239
2240 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2241
2242         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2243         MIPS targets.
2244
2245 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2246
2247         * configure: Regenerated to track ../common/aclocal.m4 changes.
2248
2249 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2250
2251         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2252         SIM_RESERVED_BITS): Delete, moved to common.
2253         (SIM_EXTRA_CFLAGS): Update.
2254
2255 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2256
2257         * configure.in: Configure non-strict memory alignment.
2258         * configure: Regenerated to track ../common/aclocal.m4 changes.
2259
2260 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2261
2262         * configure: Regenerated to track ../common/aclocal.m4 changes.
2263
2264 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2265
2266         * gencode.c (SDBBP,DERET): Added (3900) insns.
2267         (RFE): Turn on for 3900.
2268         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2269         (dsstate): Made global.
2270         (SUBTARGET_R3900): Added.
2271         (CANCELDELAYSLOT): New.
2272         (SignalException): Ignore SystemCall rather than ignore and
2273         terminate.  Add DebugBreakPoint handling.
2274         (decode_coproc): New insns RFE, DERET; and new registers Debug
2275         and DEPC protected by SUBTARGET_R3900.
2276         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2277         bits explicitly.
2278         * Makefile.in,configure.in: Add mips subtarget option.
2279         * configure: Update.
2280
2281 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2282
2283         * gencode.c: Add r3900 (tx39).
2284
2285
2286 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2287
2288         * gencode.c (build_instruction): Don't need to subtract 4 for
2289         JALR, just 2.
2290
2291 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2292
2293         * interp.c: Correct some HASFPU problems.
2294
2295 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2296
2297         * configure: Regenerated to track ../common/aclocal.m4 changes.
2298
2299 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2300
2301         * interp.c (mips_options): Fix samples option short form, should
2302         be `x'.
2303
2304 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2305
2306         * interp.c (sim_info): Enable info code.  Was just returning.
2307
2308 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2309
2310         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2311         MFC0.
2312
2313 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2314
2315         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2316         constants.
2317         (build_instruction): Ditto for LL.
2318
2319 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2320
2321         * configure: Regenerated to track ../common/aclocal.m4 changes.
2322
2323 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2324
2325         * configure: Regenerated to track ../common/aclocal.m4 changes.
2326         * config.in: Ditto.
2327
2328 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2329
2330         * interp.c (sim_open): Add call to sim_analyze_program, update
2331         call to sim_config.
2332
2333 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2334
2335         * interp.c (sim_kill): Delete.
2336         (sim_create_inferior): Add ABFD argument. Set PC from same.
2337         (sim_load): Move code initializing trap handlers from here.
2338         (sim_open): To here.
2339         (sim_load): Delete, use sim-hload.c.
2340
2341         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2342
2343 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2344
2345         * configure: Regenerated to track ../common/aclocal.m4 changes.
2346         * config.in: Ditto.
2347
2348 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2349
2350         * interp.c (sim_open): Add ABFD argument.
2351         (sim_load): Move call to sim_config from here.
2352         (sim_open): To here.  Check return status.
2353
2354 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2355
2356         * gencode.c (build_instruction): Two arg MADD should
2357         not assign result to $0.
2358
2359 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2360
2361         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2362         * sim/mips/configure.in: Regenerate.
2363
2364 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2365
2366         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2367         signed8, unsigned8 et.al. types.
2368
2369         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2370         hosts when selecting subreg.
2371
2372 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2373
2374         * interp.c (sim_engine_run): Reset the ZERO register to zero
2375         regardless of FEATURE_WARN_ZERO.
2376         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2377
2378 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2379
2380         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2381         (SignalException): For BreakPoints ignore any mode bits and just
2382         save the PC.
2383         (SignalException): Always set the CAUSE register.
2384
2385 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2386
2387         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2388         exception has been taken.
2389
2390         * interp.c: Implement the ERET and mt/f sr instructions.
2391
2392 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2393
2394         * interp.c (SignalException): Don't bother restarting an
2395         interrupt.
2396
2397 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2398
2399         * interp.c (SignalException): Really take an interrupt.
2400         (interrupt_event): Only deliver interrupts when enabled.
2401
2402 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2403
2404         * interp.c (sim_info): Only print info when verbose.
2405         (sim_info) Use sim_io_printf for output.
2406
2407 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2408
2409         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2410         mips architectures.
2411
2412 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2413
2414         * interp.c (sim_do_command): Check for common commands if a
2415         simulator specific command fails.
2416
2417 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2418
2419         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2420         and simBE when DEBUG is defined.
2421
2422 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2423
2424         * interp.c (interrupt_event): New function.  Pass exception event
2425         onto exception handler.
2426
2427         * configure.in: Check for stdlib.h.
2428         * configure: Regenerate.
2429
2430         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2431         variable declaration.
2432         (build_instruction): Initialize memval1.
2433         (build_instruction): Add UNUSED attribute to byte, bigend,
2434         reverse.
2435         (build_operands): Ditto.
2436
2437         * interp.c: Fix GCC warnings.
2438         (sim_get_quit_code): Delete.
2439
2440         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2441         * Makefile.in: Ditto.
2442         * configure: Re-generate.
2443
2444         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2445
2446 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2447
2448         * interp.c (mips_option_handler): New function parse argumes using
2449         sim-options.
2450         (myname): Replace with STATE_MY_NAME.
2451         (sim_open): Delete check for host endianness - performed by
2452         sim_config.
2453         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2454         (sim_open): Move much of the initialization from here.
2455         (sim_load): To here.  After the image has been loaded and
2456         endianness set.
2457         (sim_open): Move ColdReset from here.
2458         (sim_create_inferior): To here.
2459         (sim_open): Make FP check less dependant on host endianness.
2460
2461         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2462         run.
2463         * interp.c (sim_set_callbacks): Delete.
2464
2465         * interp.c (membank, membank_base, membank_size): Replace with
2466         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2467         (sim_open): Remove call to callback->init. gdb/run do this.
2468
2469         * interp.c: Update
2470
2471         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2472
2473         * interp.c (big_endian_p): Delete, replaced by
2474         current_target_byte_order.
2475
2476 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2477
2478         * interp.c (host_read_long, host_read_word, host_swap_word,
2479         host_swap_long): Delete. Using common sim-endian.
2480         (sim_fetch_register, sim_store_register): Use H2T.
2481         (pipeline_ticks): Delete.  Handled by sim-events.
2482         (sim_info): Update.
2483         (sim_engine_run): Update.
2484
2485 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2486
2487         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2488         reason from here.
2489         (SignalException): To here. Signal using sim_engine_halt.
2490         (sim_stop_reason): Delete, moved to common.
2491
2492 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2493
2494         * interp.c (sim_open): Add callback argument.
2495         (sim_set_callbacks): Delete SIM_DESC argument.
2496         (sim_size): Ditto.
2497
2498 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2499
2500         * Makefile.in (SIM_OBJS): Add common modules.
2501
2502         * interp.c (sim_set_callbacks): Also set SD callback.
2503         (set_endianness, xfer_*, swap_*): Delete.
2504         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2505         Change to functions using sim-endian macros.
2506         (control_c, sim_stop): Delete, use common version.
2507         (simulate): Convert into.
2508         (sim_engine_run): This function.
2509         (sim_resume): Delete.
2510
2511         * interp.c (simulation): New variable - the simulator object.
2512         (sim_kind): Delete global - merged into simulation.
2513         (sim_load): Cleanup.  Move PC assignment from here.
2514         (sim_create_inferior): To here.
2515
2516         * sim-main.h: New file.
2517         * interp.c (sim-main.h): Include.
2518
2519 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2520
2521         * configure: Regenerated to track ../common/aclocal.m4 changes.
2522
2523 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2524
2525         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2526
2527 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2528
2529         * gencode.c (build_instruction): DIV instructions: check
2530         for division by zero and integer overflow before using
2531         host's division operation.
2532
2533 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2534
2535         * Makefile.in (SIM_OBJS): Add sim-load.o.
2536         * interp.c: #include bfd.h.
2537         (target_byte_order): Delete.
2538         (sim_kind, myname, big_endian_p): New static locals.
2539         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2540         after argument parsing.  Recognize -E arg, set endianness accordingly.
2541         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2542         load file into simulator.  Set PC from bfd.
2543         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2544         (set_endianness): Use big_endian_p instead of target_byte_order.
2545
2546 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2547
2548         * interp.c (sim_size): Delete prototype - conflicts with
2549         definition in remote-sim.h.  Correct definition.
2550
2551 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2552
2553         * configure: Regenerated to track ../common/aclocal.m4 changes.
2554         * config.in: Ditto.
2555
2556 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2557
2558         * interp.c (sim_open): New arg `kind'.
2559
2560         * configure: Regenerated to track ../common/aclocal.m4 changes.
2561
2562 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2563
2564         * configure: Regenerated to track ../common/aclocal.m4 changes.
2565
2566 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2567
2568         * interp.c (sim_open): Set optind to 0 before calling getopt.
2569
2570 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2571
2572         * configure: Regenerated to track ../common/aclocal.m4 changes.
2573
2574 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2575
2576         * interp.c : Replace uses of pr_addr with pr_uword64
2577         where the bit length is always 64 independent of SIM_ADDR.
2578         (pr_uword64) : added.
2579
2580 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2581
2582         * configure: Re-generate.
2583
2584 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2585
2586         * configure: Regenerate to track ../common/aclocal.m4 changes.
2587
2588 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2589
2590         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2591         in argv form.
2592         (other sim_*): New SIM_DESC argument.
2593
2594 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2595
2596         * interp.c: Fix printing of addresses for non-64-bit targets.
2597         (pr_addr): Add function to print address based on size.
2598
2599 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2600
2601         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2602
2603 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2604
2605         * gencode.c (build_mips16_operands): Correct computation of base
2606         address for extended PC relative instruction.
2607
2608 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2609
2610         * interp.c (mips16_entry): Add support for floating point cases.
2611         (SignalException): Pass floating point cases to mips16_entry.
2612         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2613         registers.
2614         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2615         or fmt_word.
2616         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2617         and then set the state to fmt_uninterpreted.
2618         (COP_SW): Temporarily set the state to fmt_word while calling
2619         ValueFPR.
2620
2621 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2622
2623         * gencode.c (build_instruction): The high order may be set in the
2624         comparison flags at any ISA level, not just ISA 4.
2625
2626 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2627
2628         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2629         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2630         * configure.in: sinclude ../common/aclocal.m4.
2631         * configure: Regenerated.
2632
2633 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2634
2635         * configure: Rebuild after change to aclocal.m4.
2636
2637 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2638
2639         * configure configure.in Makefile.in:  Update to new configure
2640         scheme which is more compatible with WinGDB builds.
2641         * configure.in:  Improve comment on how to run autoconf.
2642         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2643         * Makefile.in:  Use autoconf substitution to install common
2644         makefile fragment.
2645
2646 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2647
2648         * gencode.c (build_instruction): Use BigEndianCPU instead of
2649         ByteSwapMem.
2650
2651 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2652
2653         * interp.c (sim_monitor): Make output to stdout visible in
2654         wingdb's I/O log window.
2655
2656 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2657
2658         * support.h: Undo previous change to SIGTRAP
2659         and SIGQUIT values.
2660
2661 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2662
2663         * interp.c (store_word, load_word): New static functions.
2664         (mips16_entry): New static function.
2665         (SignalException): Look for mips16 entry and exit instructions.
2666         (simulate): Use the correct index when setting fpr_state after
2667         doing a pending move.
2668
2669 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2670
2671         * interp.c: Fix byte-swapping code throughout to work on
2672         both little- and big-endian hosts.
2673
2674 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2675
2676         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2677         with gdb/config/i386/xm-windows.h.
2678
2679 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2680
2681         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2682         that messes up arithmetic shifts.
2683
2684 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2685
2686         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2687         SIGTRAP and SIGQUIT for _WIN32.
2688
2689 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2690
2691         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2692         force a 64 bit multiplication.
2693         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2694         destination register is 0, since that is the default mips16 nop
2695         instruction.
2696
2697 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2698
2699         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2700         (build_endian_shift): Don't check proc64.
2701         (build_instruction): Always set memval to uword64.  Cast op2 to
2702         uword64 when shifting it left in memory instructions.  Always use
2703         the same code for stores--don't special case proc64.
2704
2705         * gencode.c (build_mips16_operands): Fix base PC value for PC
2706         relative operands.
2707         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2708         jal instruction.
2709         * interp.c (simJALDELAYSLOT): Define.
2710         (JALDELAYSLOT): Define.
2711         (INDELAYSLOT, INJALDELAYSLOT): Define.
2712         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2713
2714 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2715
2716         * interp.c (sim_open): add flush_cache as a PMON routine
2717         (sim_monitor): handle flush_cache by ignoring it
2718
2719 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2720
2721         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2722         BigEndianMem.
2723         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2724         (BigEndianMem): Rename to ByteSwapMem and change sense.
2725         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2726         BigEndianMem references to !ByteSwapMem.
2727         (set_endianness): New function, with prototype.
2728         (sim_open): Call set_endianness.
2729         (sim_info): Use simBE instead of BigEndianMem.
2730         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2731         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2732         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2733         ifdefs, keeping the prototype declaration.
2734         (swap_word): Rewrite correctly.
2735         (ColdReset): Delete references to CONFIG.  Delete endianness related
2736         code; moved to set_endianness.
2737
2738 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2739
2740         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2741         * interp.c (CHECKHILO): Define away.
2742         (simSIGINT): New macro.
2743         (membank_size): Increase from 1MB to 2MB.
2744         (control_c): New function.
2745         (sim_resume): Rename parameter signal to signal_number.  Add local
2746         variable prev.  Call signal before and after simulate.
2747         (sim_stop_reason): Add simSIGINT support.
2748         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2749         functions always.
2750         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2751         if logfh is NULL.
2752         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2753         a call to sim_warning.
2754
2755 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2756
2757         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2758         16 bit instructions.
2759
2760 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2761
2762         Add support for mips16 (16 bit MIPS implementation):
2763         * gencode.c (inst_type): Add mips16 instruction encoding types.
2764         (GETDATASIZEINSN): Define.
2765         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2766         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2767         mtlo.
2768         (MIPS16_DECODE): New table, for mips16 instructions.
2769         (bitmap_val): New static function.
2770         (struct mips16_op): Define.
2771         (mips16_op_table): New table, for mips16 operands.
2772         (build_mips16_operands): New static function.
2773         (process_instructions): If PC is odd, decode a mips16
2774         instruction.  Break out instruction handling into new
2775         build_instruction function.
2776         (build_instruction): New static function, broken out of
2777         process_instructions.  Check modifiers rather than flags for SHIFT
2778         bit count and m[ft]{hi,lo} direction.
2779         (usage): Pass program name to fprintf.
2780         (main): Remove unused variable this_option_optind.  Change
2781         ``*loptarg++'' to ``loptarg++''.
2782         (my_strtoul): Parenthesize && within ||.
2783         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2784         (simulate): If PC is odd, fetch a 16 bit instruction, and
2785         increment PC by 2 rather than 4.
2786         * configure.in: Add case for mips16*-*-*.
2787         * configure: Rebuild.
2788
2789 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2790
2791         * interp.c: Allow -t to enable tracing in standalone simulator.
2792         Fix garbage output in trace file and error messages.
2793
2794 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2795
2796         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2797         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2798         * configure.in: Simplify using macros in ../common/aclocal.m4.
2799         * configure: Regenerated.
2800         * tconfig.in: New file.
2801
2802 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2803
2804         * interp.c: Fix bugs in 64-bit port.
2805         Use ansi function declarations for msvc compiler.
2806         Initialize and test file pointer in trace code.
2807         Prevent duplicate definition of LAST_EMED_REGNUM.
2808
2809 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2810
2811         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2812
2813 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2814
2815         * interp.c (SignalException): Check for explicit terminating
2816         breakpoint value.
2817         * gencode.c: Pass instruction value through SignalException()
2818         calls for Trap, Breakpoint and Syscall.
2819
2820 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2821
2822         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2823         only used on those hosts that provide it.
2824         * configure.in: Add sqrt() to list of functions to be checked for.
2825         * config.in: Re-generated.
2826         * configure: Re-generated.
2827
2828 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2829
2830         * gencode.c (process_instructions): Call build_endian_shift when
2831         expanding STORE RIGHT, to fix swr.
2832         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2833         clear the high bits.
2834         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2835         Fix float to int conversions to produce signed values.
2836
2837 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2838
2839         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2840         (process_instructions): Correct handling of nor instruction.
2841         Correct shift count for 32 bit shift instructions. Correct sign
2842         extension for arithmetic shifts to not shift the number of bits in
2843         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2844         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2845         Fix madd.
2846         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2847         It's OK to have a mult follow a mult.  What's not OK is to have a
2848         mult follow an mfhi.
2849         (Convert): Comment out incorrect rounding code.
2850
2851 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2852
2853         * interp.c (sim_monitor): Improved monitor printf
2854         simulation. Tidied up simulator warnings, and added "--log" option
2855         for directing warning message output.
2856         * gencode.c: Use sim_warning() rather than WARNING macro.
2857
2858 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2859
2860         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2861         getopt1.o, rather than on gencode.c.  Link objects together.
2862         Don't link against -liberty.
2863         (gencode.o, getopt.o, getopt1.o): New targets.
2864         * gencode.c: Include <ctype.h> and "ansidecl.h".
2865         (AND): Undefine after including "ansidecl.h".
2866         (ULONG_MAX): Define if not defined.
2867         (OP_*): Don't define macros; now defined in opcode/mips.h.
2868         (main): Call my_strtoul rather than strtoul.
2869         (my_strtoul): New static function.
2870
2871 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2872
2873         * gencode.c (process_instructions):  Generate word64 and uword64
2874         instead of `long long' and `unsigned long long' data types.
2875         * interp.c:  #include sysdep.h to get signals, and define default
2876         for SIGBUS.
2877         * (Convert):  Work around for Visual-C++ compiler bug with type
2878         conversion.
2879         * support.h:  Make things compile under Visual-C++ by using
2880         __int64 instead of `long long'.  Change many refs to long long
2881         into word64/uword64 typedefs.
2882
2883 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2884
2885         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2886         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2887         (docdir): Removed.
2888         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2889         (AC_PROG_INSTALL): Added.
2890         (AC_PROG_CC): Moved to before configure.host call.
2891         * configure: Rebuilt.
2892
2893 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2894
2895         * configure.in: Define @SIMCONF@ depending on mips target.
2896         * configure: Rebuild.
2897         * Makefile.in (run): Add @SIMCONF@ to control simulator
2898         construction.
2899         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2900         * interp.c: Remove some debugging, provide more detailed error
2901         messages, update memory accesses to use LOADDRMASK.
2902
2903 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2904
2905         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2906         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2907         stamp-h.
2908         * configure: Rebuild.
2909         * config.in: New file, generated by autoheader.
2910         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2911         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2912         HAVE_ANINT and HAVE_AINT, as appropriate.
2913         * Makefile.in (run): Use @LIBS@ rather than -lm.
2914         (interp.o): Depend upon config.h.
2915         (Makefile): Just rebuild Makefile.
2916         (clean): Remove stamp-h.
2917         (mostlyclean): Make the same as clean, not as distclean.
2918         (config.h, stamp-h): New targets.
2919
2920 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2921
2922         * interp.c (ColdReset): Fix boolean test. Make all simulator
2923         globals static.
2924
2925 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2926
2927         * interp.c (xfer_direct_word, xfer_direct_long,
2928         swap_direct_word, swap_direct_long, xfer_big_word,
2929         xfer_big_long, xfer_little_word, xfer_little_long,
2930         swap_word,swap_long): Added.
2931         * interp.c (ColdReset): Provide function indirection to
2932         host<->simulated_target transfer routines.
2933         * interp.c (sim_store_register, sim_fetch_register): Updated to
2934         make use of indirected transfer routines.
2935
2936 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2937
2938         * gencode.c (process_instructions): Ensure FP ABS instruction
2939         recognised.
2940         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2941         system call support.
2942
2943 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2944
2945         * interp.c (sim_do_command): Complain if callback structure not
2946         initialised.
2947
2948 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2949
2950         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2951         support for Sun hosts.
2952         * Makefile.in (gencode): Ensure the host compiler and libraries
2953         used for cross-hosted build.
2954
2955 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2956
2957         * interp.c, gencode.c: Some more (TODO) tidying.
2958
2959 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2960
2961         * gencode.c, interp.c: Replaced explicit long long references with
2962         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2963         * support.h (SET64LO, SET64HI): Macros added.
2964
2965 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2966
2967         * configure: Regenerate with autoconf 2.7.
2968
2969 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2970
2971         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2972         * support.h: Remove superfluous "1" from #if.
2973         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2974
2975 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2976
2977         * interp.c (StoreFPR): Control UndefinedResult() call on
2978         WARN_RESULT manifest.
2979
2980 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2981
2982         * gencode.c: Tidied instruction decoding, and added FP instruction
2983         support.
2984
2985         * interp.c: Added dineroIII, and BSD profiling support. Also
2986         run-time FP handling.
2987
2988 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2989
2990         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2991         gencode.c, interp.c, support.h: created.