sim/mips/ChangeLog

   1 2004-09-24  Monika Chaddha  <monika@acmet.com>
   2
   3         Committed by Andrew Cagney.
   4         * m16.igen (CMP, CMPI): Fix assembler.
   5
   6 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
   7
   8         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
   9         * configure: Regenerate.
  10
  11 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
  12
  13         * configure.in (sim_m16_machine): Include mipsIII.
  14         * configure: Regenerate.
  15
  16 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
  17
  18         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
  19         from COP0_BADVADDR.
  20         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
  21
  22 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
  23
  24         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
  25
  26 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
  27
  28         * mips.igen (check_fmt): Remove.
  29         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
  30         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
  31         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
  32         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
  33         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
  34         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
  35         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
  36         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
  37         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
  38         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
  39
  40 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
  41
  42         * sb1.igen (check_sbx): New function.
  43         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
  44
  45 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
  46             Richard Sandiford  <rsandifo@redhat.com>
  47
  48         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
  49         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
  50         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
  51         separate implementations for mipsIV and mipsV.  Use new macros to
  52         determine whether the restrictions apply.
  53
  54 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
  55
  56         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
  57         (check_mult_hilo): Improve comments.
  58         (check_div_hilo): Likewise.  Also, fork off a new version
  59         to handle mips32/mips64 (since there are no hazards to check
  60         in MIPS32/MIPS64).
  61
  62 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
  63
  64         * mips.igen (do_dmultx): Fix check for negative operands.
  65
  66 2003-05-16  Ian Lance Taylor  <ian@airs.com>
  67
  68         * Makefile.in (SHELL): Make sure this is defined.
  69         (various): Use $(SHELL) whenever we invoke move-if-change.
  70
  71 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
  72
  73         * cp1.c: Tweak attribution slightly.
  74         * cp1.h: Likewise.
  75         * mdmx.c: Likewise.
  76         * mdmx.igen: Likewise.
  77         * mips3d.igen: Likewise.
  78         * sb1.igen: Likewise.
  79
  80 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
  81
  82         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
  83         unsigned operands.
  84
  85 2003-02-27  Andrew Cagney  <cagney@redhat.com>
  86
  87         * interp.c (sim_open): Rename _bfd to bfd.
  88         (sim_create_inferior): Ditto.
  89
  90 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
  91
  92         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
  93
  94 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
  95
  96         * mips.igen (EI, DI): Remove.
  97
  98 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
  99
 100         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 101
 102 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 103             Andrew Cagney  <ac131313@redhat.com>
 104             Gavin Romig-Koch  <gavin@redhat.com>
 105             Graydon Hoare  <graydon@redhat.com>
 106             Aldy Hernandez  <aldyh@redhat.com>
 107             Dave Brolley  <brolley@redhat.com>
 108             Chris Demetriou  <cgd@broadcom.com>
 109
 110         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 111         (sim_mach_default): New variable.
 112         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 113         Add a new simulator generator, MULTI.
 114         * configure: Regenerate.
 115         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 116         (multi-run.o): New dependency.
 117         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 118         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 119         (tmp-multi): Combine them.
 120         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 121         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 122         (distclean-extra): New rule.
 123         * sim-main.h: Include bfd.h.
 124         (MIPS_MACH): New macro.
 125         * mips.igen (vr4120, vr5400, vr5500): New models.
 126         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 127         * vr.igen: Replace with new version.
 128
 129 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 130
 131         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 132         * configure: Regenerate.
 133
 134 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 135
 136         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 137         * mips.igen: Remove all invocations of check_branch_bug and
 138         mark_branch_bug.
 139
 140 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 141
 142         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 143
 144 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 145
 146         * mips.igen (do_load_double, do_store_double): New functions.
 147         (LDC1, SDC1): Rename to...
 148         (LDC1b, SDC1b): respectively.
 149         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 150
 151 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 152
 153         * cp1.c (fp_recip2): Modify initialization expression so that
 154         GCC will recognize it as constant.
 155
 156 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 157
 158         * mdmx.c (SD_): Delete.
 159         (Unpredictable): Re-define, for now, to directly invoke
 160         unpredictable_action().
 161         (mdmx_acc_op): Fix error in .ob immediate handling.
 162
 163 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 164
 165         * interp.c (sim_firmware_command): Initialize `address'.
 166
 167 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 168
 169         * configure: Regenerated to track ../common/aclocal.m4 changes.
 170
 171 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 172             Ed Satterthwaite  <ehs@broadcom.com>
 173
 174         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 175         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 176         * mips.igen: Include mips3d.igen.
 177         (mips3d): New model name for MIPS-3D ASE instructions.
 178         (CVT.W.fmt): Don't use this instruction for word (source) format
 179         instructions.
 180         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 181         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 182         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 183         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 184         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 185         (RSquareRoot1, RSquareRoot2): New macros.
 186         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 187         (fp_rsqrt2): New functions.
 188         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 189         * configure: Regenerate.
 190
 191 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 192             Ed Satterthwaite  <ehs@broadcom.com>
 193
 194         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 195         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 196         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 197         (convert): Note that this function is not used for paired-single
 198         format conversions.
 199         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 200         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 201         (check_fmt_p): Enable paired-single support.
 202         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 203         (PUU.PS): New instructions.
 204         (CVT.S.fmt): Don't use this instruction for paired-single format
 205         destinations.
 206         * sim-main.h (FP_formats): New value 'fmt_ps.'
 207         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 208         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 209
 210 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 211
 212         * mips.igen: Fix formatting of function calls in
 213         many FP operations.
 214
 215 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 216
 217         * mips.igen (MOVN, MOVZ): Trace result.
 218         (TNEI): Print "tnei" as the opcode name in traces.
 219         (CEIL.W): Add disassembly string for traces.
 220         (RSQRT.fmt): Make location of disassembly string consistent
 221         with other instructions.
 222
 223 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 224
 225         * mips.igen (X): Delete unused function.
 226
 227 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 228
 229         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 230
 231 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 232             Ed Satterthwaite  <ehs@broadcom.com>
 233
 234         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 235         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 236         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 237         (fp_nmsub): New prototypes.
 238         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 239         (NegMultiplySub): New defines.
 240         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 241         (MADD.D, MADD.S): Replace with...
 242         (MADD.fmt): New instruction.
 243         (MSUB.D, MSUB.S): Replace with...
 244         (MSUB.fmt): New instruction.
 245         (NMADD.D, NMADD.S): Replace with...
 246         (NMADD.fmt): New instruction.
 247         (NMSUB.D, MSUB.S): Replace with...
 248         (NMSUB.fmt): New instruction.
 249
 250 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 251             Ed Satterthwaite  <ehs@broadcom.com>
 252
 253         * cp1.c: Fix more comment spelling and formatting.
 254         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 255         (denorm_mode): New function.
 256         (fpu_unary, fpu_binary): Round results after operation, collect
 257         status from rounding operations, and update the FCSR.
 258         (convert): Collect status from integer conversions and rounding
 259         operations, and update the FCSR.  Adjust NaN values that result
 260         from conversions.  Convert to use sim_io_eprintf rather than
 261         fprintf, and remove some debugging code.
 262         * cp1.h (fenr_FS): New define.
 263
 264 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 265
 266         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 267         rounding mode to sim FP rounding mode flag conversion code into...
 268         (rounding_mode): New function.
 269
 270 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 271
 272         * cp1.c: Clean up formatting of a few comments.
 273         (value_fpr): Reformat switch statement.
 274
 275 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 276             Ed Satterthwaite  <ehs@broadcom.com>
 277
 278         * cp1.h: New file.
 279         * sim-main.h: Include cp1.h.
 280         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 281         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 282         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 283         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 284         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 285         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 286         * cp1.c: Don't include sim-fpu.h; already included by
 287         sim-main.h.  Clean up formatting of some comments.
 288         (NaN, Equal, Less): Remove.
 289         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 290         (fp_cmp): New functions.
 291         * mips.igen (do_c_cond_fmt): Remove.
 292         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 293         Compare.  Add result tracing.
 294         (CxC1): Remove, replace with...
 295         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 296         (DMxC1): Remove, replace with...
 297         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 298         (MxC1): Remove, replace with...
 299         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 300
 301 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 302
 303         * sim-main.h (FGRIDX): Remove, replace all uses with...
 304         (FGR_BASE): New macro.
 305         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 306         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 307         (NR_FGR, FGR): Likewise.
 308         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 309         * mips.igen: Likewise.
 310
 311 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 312
 313         * cp1.c: Add an FSF Copyright notice to this file.
 314
 315 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 316             Ed Satterthwaite  <ehs@broadcom.com>
 317
 318         * cp1.c (Infinity): Remove.
 319         * sim-main.h (Infinity): Likewise.
 320
 321         * cp1.c (fp_unary, fp_binary): New functions.
 322         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 323         (fp_sqrt): New functions, implemented in terms of the above.
 324         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 325         (Recip, SquareRoot): Remove (replaced by functions above).
 326         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 327         (fp_recip, fp_sqrt): New prototypes.
 328         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 329         (Recip, SquareRoot): Replace prototypes with #defines which
 330         invoke the functions above.
 331
 332 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 333
 334         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 335         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 336         file, remove PARAMS from prototypes.
 337         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 338         simulator state arguments.
 339         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 340         pass simulator state arguments.
 341         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 342         (store_fpr, convert): Remove 'sd' argument.
 343         (value_fpr): Likewise.  Convert to use 'SD' instead.
 344
 345 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 346
 347         * cp1.c (Min, Max): Remove #if 0'd functions.
 348         * sim-main.h (Min, Max): Remove.
 349
 350 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 351
 352         * cp1.c: fix formatting of switch case and default labels.
 353         * interp.c: Likewise.
 354         * sim-main.c: Likewise.
 355
 356 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 357
 358         * cp1.c: Clean up comments which describe FP formats.
 359          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 360
 361 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 362             Ed Satterthwaite  <ehs@broadcom.com>
 363
 364         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 365         Broadcom SiByte SB-1 processor configurations.
 366         * configure: Regenerate.
 367         * sb1.igen: New file.
 368         * mips.igen: Include sb1.igen.
 369         (sb1): New model.
 370         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 371         * mdmx.igen: Add "sb1" model to all appropriate functions and
 372         instructions.
 373         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 374         (ob_func, ob_acc): Reference the above.
 375         (qh_acc): Adjust to keep the same size as ob_acc.
 376         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 377         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 378
 379 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 380
 381         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 382
 383 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 384             Ed Satterthwaite  <ehs@broadcom.com>
 385
 386         * mips.igen (mdmx): New (pseudo-)model.
 387         * mdmx.c, mdmx.igen: New files.
 388         * Makefile.in (SIM_OBJS): Add mdmx.o.
 389         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 390         New typedefs.
 391         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 392         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 393         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 394         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 395         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 396         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 397         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 398         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 399         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 400         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 401         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 402         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 403         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 404         (qh_fmtsel): New macros.
 405         (_sim_cpu): New member "acc".
 406         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 407         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 408
 409 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 410
 411         * interp.c: Use 'deprecated' rather than 'depreciated.'
 412         * sim-main.h: Likewise.
 413
 414 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 415
 416         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 417         which wouldn't compile anyway.
 418         * sim-main.h (unpredictable_action): New function prototype.
 419         (Unpredictable): Define to call igen function unpredictable().
 420         (NotWordValue): New macro to call igen function not_word_value().
 421         (UndefinedResult): Remove.
 422         * interp.c (undefined_result): Remove.
 423         (unpredictable_action): New function.
 424         * mips.igen (not_word_value, unpredictable): New functions.
 425         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 426         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 427         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 428         NotWordValue() to check for unpredictable inputs, then
 429         Unpredictable() to handle them.
 430
 431 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 432
 433         * mips.igen: Fix formatting of calls to Unpredictable().
 434
 435 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 436
 437         * interp.c (sim_open): Revert previous change.
 438
 439 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 440
 441         * interp.c (sim_open): Disable chunk of code that wrote code in
 442         vector table entries.
 443
 444 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 445
 446         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 447         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 448         unused definitions.
 449
 450 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 451
 452         * cp1.c: Fix many formatting issues.
 453
 454 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 455
 456         * cp1.c (fpu_format_name): New function to replace...
 457         (DOFMT): This.  Delete, and update all callers.
 458         (fpu_rounding_mode_name): New function to replace...
 459         (RMMODE): This.  Delete, and update all callers.
 460
 461 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 462
 463         * interp.c: Move FPU support routines from here to...
 464         * cp1.c: Here.  New file.
 465         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 466         (cp1.o): New target.
 467
 468 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 469
 470         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 471         * mips.igen (mips32, mips64): New models, add to all instructions
 472         and functions as appropriate.
 473         (loadstore_ea, check_u64): New variant for model mips64.
 474         (check_fmt_p): New variant for models mipsV and mips64, remove
 475         mipsV model marking fro other variant.
 476         (SLL) Rename to...
 477         (SLLa) this.
 478         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 479         for mips32 and mips64.
 480         (DCLO, DCLZ): New instructions for mips64.
 481
 482 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 483
 484         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 485         immediate or code as a hex value with the "%#lx" format.
 486         (ANDI): Likewise, and fix printed instruction name.
 487
 488 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 489
 490         * sim-main.h (UndefinedResult, Unpredictable): New macros
 491         which currently do nothing.
 492
 493 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 494
 495         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 496         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 497         (status_CU3): New definitions.
 498
 499         * sim-main.h (ExceptionCause): Add new values for MIPS32
 500         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 501         for DebugBreakPoint and NMIReset to note their status in
 502         MIPS32 and MIPS64.
 503         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 504         (SignalExceptionCacheErr): New exception macros.
 505
 506 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 507
 508         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 509         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 510         is always enabled.
 511         (SignalExceptionCoProcessorUnusable): Take as argument the
 512         unusable coprocessor number.
 513
 514 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 515
 516         * mips.igen: Fix formatting of all SignalException calls.
 517
 518 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 519
 520         * sim-main.h (SIGNEXTEND): Remove.
 521
 522 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 523
 524         * mips.igen: Remove gencode comment from top of file, fix
 525         spelling in another comment.
 526
 527 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 528
 529         * mips.igen (check_fmt, check_fmt_p): New functions to check
 530         whether specific floating point formats are usable.
 531         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 532         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 533         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 534         Use the new functions.
 535         (do_c_cond_fmt): Remove format checks...
 536         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 537
 538 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 539
 540         * mips.igen: Fix formatting of check_fpu calls.
 541
 542 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 543
 544         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 545
 546 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 547
 548         * mips.igen: Remove whitespace at end of lines.
 549
 550 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 551
 552         * mips.igen (loadstore_ea): New function to do effective
 553         address calculations.
 554         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 555         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 556         CACHE): Use loadstore_ea to do effective address computations.
 557
 558 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 559
 560         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 561         * mips.igen (LL, CxC1, MxC1): Likewise.
 562
 563 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 564
 565         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 566         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 567         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 568         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 569         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 570         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 571         Don't split opcode fields by hand, use the opcode field values
 572         provided by igen.
 573
 574 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 575
 576         * mips.igen (do_divu): Fix spacing.
 577
 578         * mips.igen (do_dsllv): Move to be right before DSLLV,
 579         to match the rest of the do_<shift> functions.
 580
 581 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 582
 583         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 584         DSRL32, do_dsrlv): Trace inputs and results.
 585
 586 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 587
 588         * mips.igen (CACHE): Provide instruction-printing string.
 589
 590         * interp.c (signal_exception): Comment tokens after #endif.
 591
 592 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 593
 594         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 595         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 596         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 597         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 598         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 599         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 600         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 601         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 602
 603 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 604
 605         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 606         instruction-printing string.
 607         (LWU): Use '64' as the filter flag.
 608
 609 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 610
 611         * mips.igen (SDXC1): Fix instruction-printing string.
 612
 613 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 614
 615         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 616         filter flags "32,f".
 617
 618 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 619
 620         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 621         as the filter flag.
 622
 623 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 624
 625         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 626         add a comma) so that it more closely match the MIPS ISA
 627         documentation opcode partitioning.
 628         (PREF): Put useful names on opcode fields, and include
 629         instruction-printing string.
 630
 631 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 632
 633         * mips.igen (check_u64): New function which in the future will
 634         check whether 64-bit instructions are usable and signal an
 635         exception if not.  Currently a no-op.
 636         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 637         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 638         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 639         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 640
 641         * mips.igen (check_fpu): New function which in the future will
 642         check whether FPU instructions are usable and signal an exception
 643         if not.  Currently a no-op.
 644         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 645         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 646         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 647         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 648         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 649         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 650         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 651         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 652
 653 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 654
 655         * mips.igen (do_load_left, do_load_right): Move to be immediately
 656         following do_load.
 657         (do_store_left, do_store_right): Move to be immediately following
 658         do_store.
 659
 660 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 661
 662         * mips.igen (mipsV): New model name.  Also, add it to
 663         all instructions and functions where it is appropriate.
 664
 665 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 666
 667         * mips.igen: For all functions and instructions, list model
 668         names that support that instruction one per line.
 669
 670 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 671
 672         * mips.igen: Add some additional comments about supported
 673         models, and about which instructions go where.
 674         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 675         order as is used in the rest of the file.
 676
 677 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 678
 679         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 680         indicating that ALU32_END or ALU64_END are there to check
 681         for overflow.
 682         (DADD): Likewise, but also remove previous comment about
 683         overflow checking.
 684
 685 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 686
 687         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 688         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 689         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 690         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 691         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 692         fields (i.e., add and move commas) so that they more closely
 693         match the MIPS ISA documentation opcode partitioning.
 694
 695 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 696
 697         * mips.igen (ADDI): Print immediate value.
 698         (BREAK): Print code.
 699         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 700         (SLL): Print "nop" specially, and don't run the code
 701         that does the shift for the "nop" case.
 702
 703 2001-11-17  Fred Fish  <fnf@redhat.com>
 704
 705         * sim-main.h (float_operation): Move enum declaration outside
 706         of _sim_cpu struct declaration.
 707
 708 2001-04-12  Jim Blandy  <jimb@redhat.com>
 709
 710         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 711         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 712         set of the FCSR.
 713         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 714         PENDING_FILL, and you can get the intended effect gracefully by
 715         calling PENDING_SCHED directly.
 716
 717 2001-02-23  Ben Elliston  <bje@redhat.com>
 718
 719         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 720         already defined elsewhere.
 721
 722 2001-02-19  Ben Elliston  <bje@redhat.com>
 723
 724         * sim-main.h (sim_monitor): Return an int.
 725         * interp.c (sim_monitor): Add return values.
 726         (signal_exception): Handle error conditions from sim_monitor.
 727
 728 2001-02-08  Ben Elliston  <bje@redhat.com>
 729
 730         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 731         (store_memory): Likewise, pass cia to sim_core_write*.
 732
 733 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 734
 735         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 736         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 737
 738 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 739
 740         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 741         * Makefile.in: Don't delete *.igen when cleaning directory.
 742
 743 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 744
 745         * m16.igen (break): Call SignalException not sim_engine_halt.
 746
 747 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 748
 749         From Jason Eckhardt:
 750         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 751
 752 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 753
 754         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 755
 756 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 757
 758         * mips.igen (do_dmultx): Fix typo.
 759
 760 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 761
 762         * configure: Regenerated to track ../common/aclocal.m4 changes.
 763
 764 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 765
 766         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 767
 768 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 769
 770         * sim-main.h (GPR_CLEAR): Define macro.
 771
 772 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 773
 774         * interp.c (decode_coproc): Output long using %lx and not %s.
 775
 776 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 777
 778         * interp.c (sim_open): Sort & extend dummy memory regions for
 779         --board=jmr3904 for eCos.
 780
 781 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 782
 783         * configure: Regenerated.
 784
 785 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 786
 787         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 788         calls, conditional on the simulator being in verbose mode.
 789
 790 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 791
 792         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 793         cache don't get ReservedInstruction traps.
 794
 795 1999-11-29  Mark Salter  <msalter@cygnus.com>
 796
 797         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 798         to clear status bits in sdisr register. This is how the hardware works.
 799
 800         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 801         being used by cygmon.
 802
 803 1999-11-11  Andrew Haley  <aph@cygnus.com>
 804
 805         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 806         instructions.
 807
 808 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 809
 810         * mips.igen (MULT): Correct previous mis-applied patch.
 811
 812 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 813
 814         * mips.igen (delayslot32): Handle sequence like
 815         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 816         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 817         (MULT): Actually pass the third register...
 818
 819 1999-09-03  Mark Salter  <msalter@cygnus.com>
 820
 821         * interp.c (sim_open): Added more memory aliases for additional
 822         hardware being touched by cygmon on jmr3904 board.
 823
 824 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 825
 826         * configure: Regenerated to track ../common/aclocal.m4 changes.
 827
 828 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 829
 830         * interp.c (sim_store_register): Handle case where client - GDB -
 831         specifies that a 4 byte register is 8 bytes in size.
 832         (sim_fetch_register): Ditto.
 833
 834 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 835
 836         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 837         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 838         (idt_monitor_base): Base address for IDT monitor traps.
 839         (pmon_monitor_base): Ditto for PMON.
 840         (lsipmon_monitor_base): Ditto for LSI PMON.
 841         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 842         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 843         (sim_firmware_command): New function.
 844         (mips_option_handler): Call it for OPTION_FIRMWARE.
 845         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 846         option was given, add no monitor by default.  Add BREAK hooks only if
 847         monitors are also there.
 848
 849 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 850
 851         * interp.c (sim_monitor): Flush output before reading input.
 852
 853 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 854
 855         * tconfig.in (SIM_HANDLES_LMA): Always define.
 856
 857 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 858
 859         From Mark Salter <msalter@cygnus.com>:
 860         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 861         (sim_open): Add setup for BSP board.
 862
 863 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 864
 865         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 866         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 867         them as unimplemented.
 868
 869 1999-05-08  Felix Lee  <flee@cygnus.com>
 870
 871         * configure: Regenerated to track ../common/aclocal.m4 changes.
 872
 873 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 874
 875         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 876
 877 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 878
 879         * configure.in: Any mips64vr5*-*-* target should have
 880         -DTARGET_ENABLE_FR=1.
 881         (default_endian): Any mips64vr*el-*-* target should default to
 882         LITTLE_ENDIAN.
 883         * configure: Re-generate.
 884
 885 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 886
 887         * mips.igen (ldl): Extend from _16_, not 32.
 888
 889 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 890
 891         * interp.c (sim_store_register): Force registers written to by GDB
 892         into an un-interpreted state.
 893
 894 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 895
 896         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 897         CPU, start periodic background I/O polls.
 898         (tx3904sio_poll): New function: periodic I/O poller.
 899
 900 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 901
 902         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 903
 904 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 905
 906         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 907         case statement.
 908
 909 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 910
 911         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 912         (load_word): Call SIM_CORE_SIGNAL hook on error.
 913         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 914         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 915         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 916         * sim-main.h (COP0_BADVADDR): Define.
 917         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 918         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 919         (_sim_cpu): Add exc_* fields to store register value snapshots.
 920         * mips.igen (*): Replace memory-related SignalException* calls
 921         with references to SIM_CORE_SIGNAL hook.
 922
 923         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 924         fix.
 925         * sim-main.c (*): Minor warning cleanups.
 926
 927 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 928
 929         * m16.igen (DADDIU5): Correct type-o.
 930
 931 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 932
 933         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 934         variables.
 935
 936 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 937
 938         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 939         to include path.
 940         (interp.o): Add dependency on itable.h
 941         (oengine.c, gencode): Delete remaining references.
 942         (BUILT_SRC_FROM_GEN): Clean up.
 943
 944 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 945
 946         * vr4run.c: New.
 947         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 948         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 949         tmp-run-hack) : New.
 950         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 951         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 952         Drop the "64" qualifier to get the HACK generator working.
 953         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 954         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 955         qualifier to get the hack generator working.
 956         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 957         (DSLL): Use do_dsll.
 958         (DSLLV): Use do_dsllv.
 959         (DSRA): Use do_dsra.
 960         (DSRL): Use do_dsrl.
 961         (DSRLV): Use do_dsrlv.
 962         (BC1): Move *vr4100 to get the HACK generator working.
 963         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 964         get the HACK generator working.
 965         (MACC) Rename to get the HACK generator working.
 966         (DMACC,MACCS,DMACCS): Add the 64.
 967
 968 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 969
 970         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 971         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 972
 973 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 974
 975     * mips/interp.c (DEBUG): Cleanups.
 976
 977 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 978
 979         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 980         (tx3904sio_tickle): fflush after a stdout character output.
 981
 982 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 983
 984         * interp.c (sim_close): Uninstall modules.
 985
 986 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 987
 988         * sim-main.h, interp.c (sim_monitor): Change to global
 989         function.
 990
 991 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 992
 993         * configure.in (vr4100): Only include vr4100 instructions in
 994         simulator.
 995         * configure: Re-generate.
 996         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 997
 998 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 999
1000         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1001         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1002         true alternative.
1003
1004         * configure.in (sim_default_gen, sim_use_gen): Replace with
1005         sim_gen.
1006         (--enable-sim-igen): Delete config option. Always using IGEN.
1007         * configure: Re-generate.
1008
1009         * Makefile.in (gencode): Kill, kill, kill.
1010         * gencode.c: Ditto.
1011
1012 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1013
1014         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1015         bit mips16 igen simulator.
1016         * configure: Re-generate.
1017
1018         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1019         as part of vr4100 ISA.
1020         * vr.igen: Mark all instructions as 64 bit only.
1021
1022 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1023
1024         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1025         Pacify GCC.
1026
1027 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1028
1029         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1030         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1031         * configure: Re-generate.
1032
1033         * m16.igen (BREAK): Define breakpoint instruction.
1034         (JALX32): Mark instruction as mips16 and not r3900.
1035         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1036
1037         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1038
1039 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1040
1041         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1042         insn as a debug breakpoint.
1043
1044         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1045         pending.slot_size.
1046         (PENDING_SCHED): Clean up trace statement.
1047         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1048         (PENDING_FILL): Delay write by only one cycle.
1049         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1050
1051         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1052         of pending writes.
1053         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1054         32 & 64.
1055         (pending_tick): Move incrementing of index to FOR statement.
1056         (pending_tick): Only update PENDING_OUT after a write has occured.
1057
1058         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1059         build simulator.
1060         * configure: Re-generate.
1061
1062         * interp.c (sim_engine_run OLD): Delete explicit call to
1063         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1064
1065 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1066
1067         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1068         interrupt level number to match changed SignalExceptionInterrupt
1069         macro.
1070
1071 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1072
1073         * interp.c: #include "itable.h" if WITH_IGEN.
1074         (get_insn_name): New function.
1075         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1076         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1077
1078 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1079
1080         * configure: Rebuilt to inhale new common/aclocal.m4.
1081
1082 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1083
1084         * dv-tx3904sio.c: Include sim-assert.h.
1085
1086 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1087
1088         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1089         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1090         Reorganize target-specific sim-hardware checks.
1091         * configure: rebuilt.
1092         * interp.c (sim_open): For tx39 target boards, set
1093         OPERATING_ENVIRONMENT, add tx3904sio devices.
1094         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1095         ROM executables.  Install dv-sockser into sim-modules list.
1096
1097         * dv-tx3904irc.c: Compiler warning clean-up.
1098         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1099         frequent hw-trace messages.
1100
1101 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1102
1103         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1104
1105 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1106
1107         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1108
1109         * vr.igen: New file.
1110         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1111         * mips.igen: Define vr4100 model. Include vr.igen.
1112 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1113
1114         * mips.igen (check_mf_hilo): Correct check.
1115
1116 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1117
1118         * sim-main.h (interrupt_event): Add prototype.
1119
1120         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1121         register_ptr, register_value.
1122         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1123
1124         * sim-main.h (tracefh): Make extern.
1125
1126 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1127
1128         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1129         Reduce unnecessarily high timer event frequency.
1130         * dv-tx3904cpu.c: Ditto for interrupt event.
1131
1132 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1133
1134         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1135         to allay warnings.
1136         (interrupt_event): Made non-static.
1137
1138         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1139         interchange of configuration values for external vs. internal
1140         clock dividers.
1141
1142 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1143
1144         * mips.igen (BREAK): Moved code to here for
1145         simulator-reserved break instructions.
1146         * gencode.c (build_instruction): Ditto.
1147         * interp.c (signal_exception): Code moved from here.  Non-
1148         reserved instructions now use exception vector, rather
1149         than halting sim.
1150         * sim-main.h: Moved magic constants to here.
1151
1152 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1153
1154         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1155         register upon non-zero interrupt event level, clear upon zero
1156         event value.
1157         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1158         by passing zero event value.
1159         (*_io_{read,write}_buffer): Endianness fixes.
1160         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1161         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1162
1163         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1164         serial I/O and timer module at base address 0xFFFF0000.
1165
1166 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1167
1168         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1169         and BigEndianCPU.
1170
1171 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1172
1173         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1174         parts.
1175         * configure: Update.
1176
1177 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1178
1179         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1180         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1181         * configure.in: Include tx3904tmr in hw_device list.
1182         * configure: Rebuilt.
1183         * interp.c (sim_open): Instantiate three timer instances.
1184         Fix address typo of tx3904irc instance.
1185
1186 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1187
1188         * interp.c (signal_exception): SystemCall exception now uses
1189         the exception vector.
1190
1191 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1192
1193         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1194         to allay warnings.
1195
1196 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1197
1198         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1199
1200 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1201
1202         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1203
1204         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1205         sim-main.h. Declare a struct hw_descriptor instead of struct
1206         hw_device_descriptor.
1207
1208 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1209
1210         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1211         right bits and then re-align left hand bytes to correct byte
1212         lanes.  Fix incorrect computation in do_store_left when loading
1213         bytes from second word.
1214
1215 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1216
1217         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1218         * interp.c (sim_open): Only create a device tree when HW is
1219         enabled.
1220
1221         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1222         * interp.c (signal_exception): Ditto.
1223
1224 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1225
1226         * gencode.c: Mark BEGEZALL as LIKELY.
1227
1228 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1229
1230         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1231         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1232
1233 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1234
1235         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1236         modules.  Recognize TX39 target with "mips*tx39" pattern.
1237         * configure: Rebuilt.
1238         * sim-main.h (*): Added many macros defining bits in
1239         TX39 control registers.
1240         (SignalInterrupt): Send actual PC instead of NULL.
1241         (SignalNMIReset): New exception type.
1242         * interp.c (board): New variable for future use to identify
1243         a particular board being simulated.
1244         (mips_option_handler,mips_options): Added "--board" option.
1245         (interrupt_event): Send actual PC.
1246         (sim_open): Make memory layout conditional on board setting.
1247         (signal_exception): Initial implementation of hardware interrupt
1248         handling.  Accept another break instruction variant for simulator
1249         exit.
1250         (decode_coproc): Implement RFE instruction for TX39.
1251         (mips.igen): Decode RFE instruction as such.
1252         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1253         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1254         bbegin to implement memory map.
1255         * dv-tx3904cpu.c: New file.
1256         * dv-tx3904irc.c: New file.
1257
1258 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1259
1260         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1261
1262 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1263
1264         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1265         with calls to check_div_hilo.
1266
1267 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1268
1269         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1270         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1271         Add special r3900 version of do_mult_hilo.
1272         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1273         with calls to check_mult_hilo.
1274         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1275         with calls to check_div_hilo.
1276
1277 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1278
1279         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1280         Document a replacement.
1281
1282 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1283
1284         * interp.c (sim_monitor): Make mon_printf work.
1285
1286 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1287
1288         * sim-main.h (INSN_NAME): New arg `cpu'.
1289
1290 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1291
1292         * configure: Regenerated to track ../common/aclocal.m4 changes.
1293
1294 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1295
1296         * configure: Regenerated to track ../common/aclocal.m4 changes.
1297         * config.in: Ditto.
1298
1299 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1300
1301         * acconfig.h: New file.
1302         * configure.in: Reverted change of Apr 24; use sinclude again.
1303
1304 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1305
1306         * configure: Regenerated to track ../common/aclocal.m4 changes.
1307         * config.in: Ditto.
1308
1309 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1310
1311         * configure.in: Don't call sinclude.
1312
1313 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1314
1315         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1316
1317 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1318
1319         * mips.igen (ERET): Implement.
1320
1321         * interp.c (decode_coproc): Return sign-extended EPC.
1322
1323         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1324
1325         * interp.c (signal_exception): Do not ignore Trap.
1326         (signal_exception): On TRAP, restart at exception address.
1327         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1328         (signal_exception): Update.
1329         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1330         so that TRAP instructions are caught.
1331
1332 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1333
1334         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1335         contains HI/LO access history.
1336         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1337         (HIACCESS, LOACCESS): Delete, replace with
1338         (HIHISTORY, LOHISTORY): New macros.
1339         (CHECKHILO): Delete all, moved to mips.igen
1340
1341         * gencode.c (build_instruction): Do not generate checks for
1342         correct HI/LO register usage.
1343
1344         * interp.c (old_engine_run): Delete checks for correct HI/LO
1345         register usage.
1346
1347         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1348         check_mf_cycles): New functions.
1349         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1350         do_divu, domultx, do_mult, do_multu): Use.
1351
1352         * tx.igen ("madd", "maddu"): Use.
1353
1354 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1355
1356         * mips.igen (DSRAV): Use function do_dsrav.
1357         (SRAV): Use new function do_srav.
1358
1359         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1360         (B): Sign extend 11 bit immediate.
1361         (EXT-B*): Shift 16 bit immediate left by 1.
1362         (ADDIU*): Don't sign extend immediate value.
1363
1364 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1365
1366         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1367
1368         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1369         functions.
1370
1371         * mips.igen (delayslot32, nullify_next_insn): New functions.
1372         (m16.igen): Always include.
1373         (do_*): Add more tracing.
1374
1375         * m16.igen (delayslot16): Add NIA argument, could be called by a
1376         32 bit MIPS16 instruction.
1377
1378         * interp.c (ifetch16): Move function from here.
1379         * sim-main.c (ifetch16): To here.
1380
1381         * sim-main.c (ifetch16, ifetch32): Update to match current
1382         implementations of LH, LW.
1383         (signal_exception): Don't print out incorrect hex value of illegal
1384         instruction.
1385
1386 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1387
1388         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1389         instruction.
1390
1391         * m16.igen: Implement MIPS16 instructions.
1392
1393         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1394         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1395         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1396         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1397         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1398         bodies of corresponding code from 32 bit insn to these.  Also used
1399         by MIPS16 versions of functions.
1400
1401         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1402         (IMEM16): Drop NR argument from macro.
1403
1404 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1405
1406         * Makefile.in (SIM_OBJS): Add sim-main.o.
1407
1408         * sim-main.h (address_translation, load_memory, store_memory,
1409         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1410         as INLINE_SIM_MAIN.
1411         (pr_addr, pr_uword64): Declare.
1412         (sim-main.c): Include when H_REVEALS_MODULE_P.
1413
1414         * interp.c (address_translation, load_memory, store_memory,
1415         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1416         from here.
1417         * sim-main.c: To here. Fix compilation problems.
1418
1419         * configure.in: Enable inlining.
1420         * configure: Re-config.
1421
1422 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1423
1424         * configure: Regenerated to track ../common/aclocal.m4 changes.
1425
1426 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1427
1428         * mips.igen: Include tx.igen.
1429         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1430         * tx.igen: New file, contains MADD and MADDU.
1431
1432         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1433         the hardwired constant `7'.
1434         (store_memory): Ditto.
1435         (LOADDRMASK): Move definition to sim-main.h.
1436
1437         mips.igen (MTC0): Enable for r3900.
1438         (ADDU): Add trace.
1439
1440         mips.igen (do_load_byte): Delete.
1441         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1442         do_store_right): New functions.
1443         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1444
1445         configure.in: Let the tx39 use igen again.
1446         configure: Update.
1447
1448 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1449
1450         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1451         not an address sized quantity.  Return zero for cache sizes.
1452
1453 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1454
1455         * mips.igen (r3900): r3900 does not support 64 bit integer
1456         operations.
1457
1458 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1459
1460         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1461         than igen one.
1462         * configure : Rebuild.
1463
1464 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1465
1466         * configure: Regenerated to track ../common/aclocal.m4 changes.
1467
1468 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1469
1470         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1471
1472 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1473
1474         * configure: Regenerated to track ../common/aclocal.m4 changes.
1475         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1476
1477 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1478
1479         * configure: Regenerated to track ../common/aclocal.m4 changes.
1480
1481 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1482
1483         * interp.c (Max, Min): Comment out functions. Not yet used.
1484
1485 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1486
1487         * configure: Regenerated to track ../common/aclocal.m4 changes.
1488
1489 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1490
1491         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1492         configurable settings for stand-alone simulator.
1493
1494         * configure.in: Added X11 search, just in case.
1495
1496         * configure: Regenerated.
1497
1498 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1499
1500         * interp.c (sim_write, sim_read, load_memory, store_memory):
1501         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1502
1503 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1504
1505         * sim-main.h (GETFCC): Return an unsigned value.
1506
1507 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1508
1509         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1510         (DADD): Result destination is RD not RT.
1511
1512 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1513
1514         * sim-main.h (HIACCESS, LOACCESS): Always define.
1515
1516         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1517
1518         * interp.c (sim_info): Delete.
1519
1520 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1521
1522         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1523         (mips_option_handler): New argument `cpu'.
1524         (sim_open): Update call to sim_add_option_table.
1525
1526 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1527
1528         * mips.igen (CxC1): Add tracing.
1529
1530 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1531
1532         * sim-main.h (Max, Min): Declare.
1533
1534         * interp.c (Max, Min): New functions.
1535
1536         * mips.igen (BC1): Add tracing.
1537
1538 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1539
1540         * interp.c Added memory map for stack in vr4100
1541
1542 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1543
1544         * interp.c (load_memory): Add missing "break"'s.
1545
1546 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1547
1548         * interp.c (sim_store_register, sim_fetch_register): Pass in
1549         length parameter.  Return -1.
1550
1551 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1552
1553         * interp.c: Added hardware init hook, fixed warnings.
1554
1555 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1556
1557         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1558
1559 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1560
1561         * interp.c (ifetch16): New function.
1562
1563         * sim-main.h (IMEM32): Rename IMEM.
1564         (IMEM16_IMMED): Define.
1565         (IMEM16): Define.
1566         (DELAY_SLOT): Update.
1567
1568         * m16run.c (sim_engine_run): New file.
1569
1570         * m16.igen: All instructions except LB.
1571         (LB): Call do_load_byte.
1572         * mips.igen (do_load_byte): New function.
1573         (LB): Call do_load_byte.
1574
1575         * mips.igen: Move spec for insn bit size and high bit from here.
1576         * Makefile.in (tmp-igen, tmp-m16): To here.
1577
1578         * m16.dc: New file, decode mips16 instructions.
1579
1580         * Makefile.in (SIM_NO_ALL): Define.
1581         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1582
1583 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1584
1585         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1586         point unit to 32 bit registers.
1587         * configure: Re-generate.
1588
1589 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1590
1591         * configure.in (sim_use_gen): Make IGEN the default simulator
1592         generator for generic 32 and 64 bit mips targets.
1593         * configure: Re-generate.
1594
1595 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1596
1597         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1598         bitsize.
1599
1600         * interp.c (sim_fetch_register, sim_store_register): Read/write
1601         FGR from correct location.
1602         (sim_open): Set size of FGR's according to
1603         WITH_TARGET_FLOATING_POINT_BITSIZE.
1604
1605         * sim-main.h (FGR): Store floating point registers in a separate
1606         array.
1607
1608 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1609
1610         * configure: Regenerated to track ../common/aclocal.m4 changes.
1611
1612 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1613
1614         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1615
1616         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1617
1618         * interp.c (pending_tick): New function.  Deliver pending writes.
1619
1620         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1621         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1622         it can handle mixed sized quantites and single bits.
1623
1624 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1625
1626         * interp.c (oengine.h): Do not include when building with IGEN.
1627         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1628         (sim_info): Ditto for PROCESSOR_64BIT.
1629         (sim_monitor): Replace ut_reg with unsigned_word.
1630         (*): Ditto for t_reg.
1631         (LOADDRMASK): Define.
1632         (sim_open): Remove defunct check that host FP is IEEE compliant,
1633         using software to emulate floating point.
1634         (value_fpr, ...): Always compile, was conditional on HASFPU.
1635
1636 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1637
1638         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1639         size.
1640
1641         * interp.c (SD, CPU): Define.
1642         (mips_option_handler): Set flags in each CPU.
1643         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1644         (sim_close): Do not clear STATE, deleted anyway.
1645         (sim_write, sim_read): Assume CPU zero's vm should be used for
1646         data transfers.
1647         (sim_create_inferior): Set the PC for all processors.
1648         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1649         argument.
1650         (mips16_entry): Pass correct nr of args to store_word, load_word.
1651         (ColdReset): Cold reset all cpu's.
1652         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1653         (sim_monitor, load_memory, store_memory, signal_exception): Use
1654         `CPU' instead of STATE_CPU.
1655
1656
1657         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1658         SD or CPU_.
1659
1660         * sim-main.h (signal_exception): Add sim_cpu arg.
1661         (SignalException*): Pass both SD and CPU to signal_exception.
1662         * interp.c (signal_exception): Update.
1663
1664         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1665         Ditto
1666         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1667         address_translation): Ditto
1668         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1669
1670 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1671
1672         * configure: Regenerated to track ../common/aclocal.m4 changes.
1673
1674 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1675
1676         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1677
1678         * mips.igen (model): Map processor names onto BFD name.
1679
1680         * sim-main.h (CPU_CIA): Delete.
1681         (SET_CIA, GET_CIA): Define
1682
1683 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1684
1685         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1686         regiser.
1687
1688         * configure.in (default_endian): Configure a big-endian simulator
1689         by default.
1690         * configure: Re-generate.
1691
1692 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1693
1694         * configure: Regenerated to track ../common/aclocal.m4 changes.
1695
1696 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1697
1698         * interp.c (sim_monitor): Handle Densan monitor outbyte
1699         and inbyte functions.
1700
1701 1997-12-29  Felix Lee  <flee@cygnus.com>
1702
1703         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1704
1705 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1706
1707         * Makefile.in (tmp-igen): Arrange for $zero to always be
1708         reset to zero after every instruction.
1709
1710 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1711
1712         * configure: Regenerated to track ../common/aclocal.m4 changes.
1713         * config.in: Ditto.
1714
1715 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1716
1717         * mips.igen (MSUB): Fix to work like MADD.
1718         * gencode.c (MSUB): Similarly.
1719
1720 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1721
1722         * configure: Regenerated to track ../common/aclocal.m4 changes.
1723
1724 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1725
1726         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1727
1728 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1729
1730         * sim-main.h (sim-fpu.h): Include.
1731
1732         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1733         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1734         using host independant sim_fpu module.
1735
1736 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1737
1738         * interp.c (signal_exception): Report internal errors with SIGABRT
1739         not SIGQUIT.
1740
1741         * sim-main.h (C0_CONFIG): New register.
1742         (signal.h): No longer include.
1743
1744         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1745
1746 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1747
1748         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1749
1750 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1751
1752         * mips.igen: Tag vr5000 instructions.
1753         (ANDI): Was missing mipsIV model, fix assembler syntax.
1754         (do_c_cond_fmt): New function.
1755         (C.cond.fmt): Handle mips I-III which do not support CC field
1756         separatly.
1757         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1758         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1759         in IV3.2 spec.
1760         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1761         vr5000 which saves LO in a GPR separatly.
1762
1763         * configure.in (enable-sim-igen): For vr5000, select vr5000
1764         specific instructions.
1765         * configure: Re-generate.
1766
1767 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1768
1769         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1770
1771         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1772         fmt_uninterpreted_64 bit cases to switch.  Convert to
1773         fmt_formatted,
1774
1775         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1776
1777         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1778         as specified in IV3.2 spec.
1779         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1780
1781 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1782
1783         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1784         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1785         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1786         PENDING_FILL versions of instructions.  Simplify.
1787         (X): New function.
1788         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1789         instructions.
1790         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1791         a signed value.
1792         (MTHI, MFHI): Disable code checking HI-LO.
1793
1794         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1795         global.
1796         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1797
1798 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1799
1800         * gencode.c (build_mips16_operands): Replace IPC with cia.
1801
1802         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1803         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1804         IPC to `cia'.
1805         (UndefinedResult): Replace function with macro/function
1806         combination.
1807         (sim_engine_run): Don't save PC in IPC.
1808
1809         * sim-main.h (IPC): Delete.
1810
1811
1812         * interp.c (signal_exception, store_word, load_word,
1813         address_translation, load_memory, store_memory, cache_op,
1814         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1815         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1816         current instruction address - cia - argument.
1817         (sim_read, sim_write): Call address_translation directly.
1818         (sim_engine_run): Rename variable vaddr to cia.
1819         (signal_exception): Pass cia to sim_monitor
1820
1821         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1822         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1823         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1824
1825         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1826         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1827         SIM_ASSERT.
1828
1829         * interp.c (signal_exception): Pass restart address to
1830         sim_engine_restart.
1831
1832         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1833         idecode.o): Add dependency.
1834
1835         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1836         Delete definitions
1837         (DELAY_SLOT): Update NIA not PC with branch address.
1838         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1839
1840         * mips.igen: Use CIA not PC in branch calculations.
1841         (illegal): Call SignalException.
1842         (BEQ, ADDIU): Fix assembler.
1843
1844 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1845
1846         * m16.igen (JALX): Was missing.
1847
1848         * configure.in (enable-sim-igen): New configuration option.
1849         * configure: Re-generate.
1850
1851         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1852
1853         * interp.c (load_memory, store_memory): Delete parameter RAW.
1854         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1855         bypassing {load,store}_memory.
1856
1857         * sim-main.h (ByteSwapMem): Delete definition.
1858
1859         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1860
1861         * interp.c (sim_do_command, sim_commands): Delete mips specific
1862         commands.  Handled by module sim-options.
1863
1864         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1865         (WITH_MODULO_MEMORY): Define.
1866
1867         * interp.c (sim_info): Delete code printing memory size.
1868
1869         * interp.c (mips_size): Nee sim_size, delete function.
1870         (power2): Delete.
1871         (monitor, monitor_base, monitor_size): Delete global variables.
1872         (sim_open, sim_close): Delete code creating monitor and other
1873         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1874         manage memory regions.
1875         (load_memory, store_memory): Use sim-core for memory model.
1876
1877         * interp.c (address_translation): Delete all memory map code
1878         except line forcing 32 bit addresses.
1879
1880 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1881
1882         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1883         trace options.
1884
1885         * interp.c (logfh, logfile): Delete globals.
1886         (sim_open, sim_close): Delete code opening & closing log file.
1887         (mips_option_handler): Delete -l and -n options.
1888         (OPTION mips_options): Ditto.
1889
1890         * interp.c (OPTION mips_options): Rename option trace to dinero.
1891         (mips_option_handler): Update.
1892
1893 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1894
1895         * interp.c (fetch_str): New function.
1896         (sim_monitor): Rewrite using sim_read & sim_write.
1897         (sim_open): Check magic number.
1898         (sim_open): Write monitor vectors into memory using sim_write.
1899         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1900         (sim_read, sim_write): Simplify - transfer data one byte at a
1901         time.
1902         (load_memory, store_memory): Clarify meaning of parameter RAW.
1903
1904         * sim-main.h (isHOST): Defete definition.
1905         (isTARGET): Mark as depreciated.
1906         (address_translation): Delete parameter HOST.
1907
1908         * interp.c (address_translation): Delete parameter HOST.
1909
1910 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1911
1912         * mips.igen:
1913
1914         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1915         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1916
1917 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1918
1919         * mips.igen: Add model filter field to records.
1920
1921 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1922
1923         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1924
1925         interp.c (sim_engine_run): Do not compile function sim_engine_run
1926         when WITH_IGEN == 1.
1927
1928         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1929         target architecture.
1930
1931         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1932         igen. Replace with configuration variables sim_igen_flags /
1933         sim_m16_flags.
1934
1935         * m16.igen: New file.  Copy mips16 insns here.
1936         * mips.igen: From here.
1937
1938 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1939
1940         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1941         to top.
1942         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1943
1944 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1945
1946         * gencode.c (build_instruction): Follow sim_write's lead in using
1947         BigEndianMem instead of !ByteSwapMem.
1948
1949 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1950
1951         * configure.in (sim_gen): Dependent on target, select type of
1952         generator.  Always select old style generator.
1953
1954         configure: Re-generate.
1955
1956         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1957         targets.
1958         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1959         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1960         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1961         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1962         SIM_@sim_gen@_*, set by autoconf.
1963
1964 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1965
1966         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1967
1968         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1969         CURRENT_FLOATING_POINT instead.
1970
1971         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1972         (address_translation): Raise exception InstructionFetch when
1973         translation fails and isINSTRUCTION.
1974
1975         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1976         sim_engine_run): Change type of of vaddr and paddr to
1977         address_word.
1978         (address_translation, prefetch, load_memory, store_memory,
1979         cache_op): Change type of vAddr and pAddr to address_word.
1980
1981         * gencode.c (build_instruction): Change type of vaddr and paddr to
1982         address_word.
1983
1984 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1985
1986         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1987         macro to obtain result of ALU op.
1988
1989 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1990
1991         * interp.c (sim_info): Call profile_print.
1992
1993 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1994
1995         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1996
1997         * sim-main.h (WITH_PROFILE): Do not define, defined in
1998         common/sim-config.h.  Use sim-profile module.
1999         (simPROFILE): Delete defintion.
2000
2001         * interp.c (PROFILE): Delete definition.
2002         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2003         (sim_close): Delete code writing profile histogram.
2004         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2005         Delete.
2006         (sim_engine_run): Delete code profiling the PC.
2007
2008 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2009
2010         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2011
2012         * interp.c (sim_monitor): Make register pointers of type
2013         unsigned_word*.
2014
2015         * sim-main.h: Make registers of type unsigned_word not
2016         signed_word.
2017
2018 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2019
2020         * interp.c (sync_operation): Rename from SyncOperation, make
2021         global, add SD argument.
2022         (prefetch): Rename from Prefetch, make global, add SD argument.
2023         (decode_coproc): Make global.
2024
2025         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2026
2027         * gencode.c (build_instruction): Generate DecodeCoproc not
2028         decode_coproc calls.
2029
2030         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2031         (SizeFGR): Move to sim-main.h
2032         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2033         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2034         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2035         sim-main.h.
2036         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2037         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2038         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2039         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2040         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2041         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2042
2043         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2044         exception.
2045         (sim-alu.h): Include.
2046         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2047         (sim_cia): Typedef to instruction_address.
2048
2049 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2050
2051         * Makefile.in (interp.o): Rename generated file engine.c to
2052         oengine.c.
2053
2054         * interp.c: Update.
2055
2056 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2057
2058         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2059
2060 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2061
2062         * gencode.c (build_instruction): For "FPSQRT", output correct
2063         number of arguments to Recip.
2064
2065 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2066
2067         * Makefile.in (interp.o): Depends on sim-main.h
2068
2069         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2070
2071         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2072         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2073         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2074         STATE, DSSTATE): Define
2075         (GPR, FGRIDX, ..): Define.
2076
2077         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2078         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2079         (GPR, FGRIDX, ...): Delete macros.
2080
2081         * interp.c: Update names to match defines from sim-main.h
2082
2083 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2084
2085         * interp.c (sim_monitor): Add SD argument.
2086         (sim_warning): Delete.  Replace calls with calls to
2087         sim_io_eprintf.
2088         (sim_error): Delete. Replace calls with sim_io_error.
2089         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2090         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2091         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2092         argument.
2093         (mips_size): Rename from sim_size. Add SD argument.
2094
2095         * interp.c (simulator): Delete global variable.
2096         (callback): Delete global variable.
2097         (mips_option_handler, sim_open, sim_write, sim_read,
2098         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2099         sim_size,sim_monitor): Use sim_io_* not callback->*.
2100         (sim_open): ZALLOC simulator struct.
2101         (PROFILE): Do not define.
2102
2103 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2104
2105         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2106         support.h with corresponding code.
2107
2108         * sim-main.h (word64, uword64), support.h: Move definition to
2109         sim-main.h.
2110         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2111
2112         * support.h: Delete
2113         * Makefile.in: Update dependencies
2114         * interp.c: Do not include.
2115
2116 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2117
2118         * interp.c (address_translation, load_memory, store_memory,
2119         cache_op): Rename to from AddressTranslation et.al., make global,
2120         add SD argument
2121
2122         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2123         CacheOp): Define.
2124
2125         * interp.c (SignalException): Rename to signal_exception, make
2126         global.
2127
2128         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2129
2130         * sim-main.h (SignalException, SignalExceptionInterrupt,
2131         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2132         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2133         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2134         Define.
2135
2136         * interp.c, support.h: Use.
2137
2138 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2139
2140         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2141         to value_fpr / store_fpr. Add SD argument.
2142         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2143         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2144
2145         * sim-main.h (ValueFPR, StoreFPR): Define.
2146
2147 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2148
2149         * interp.c (sim_engine_run): Check consistency between configure
2150         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2151         and HASFPU.
2152
2153         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2154         (mips_fpu): Configure WITH_FLOATING_POINT.
2155         (mips_endian): Configure WITH_TARGET_ENDIAN.
2156         * configure: Update.
2157
2158 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2159
2160         * configure: Regenerated to track ../common/aclocal.m4 changes.
2161
2162 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2163
2164         * configure: Regenerated.
2165
2166 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2167
2168         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2169
2170 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2171
2172         * gencode.c (print_igen_insn_models): Assume certain architectures
2173         include all mips* instructions.
2174         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2175         instruction.
2176
2177         * Makefile.in (tmp.igen): Add target. Generate igen input from
2178         gencode file.
2179
2180         * gencode.c (FEATURE_IGEN): Define.
2181         (main): Add --igen option.  Generate output in igen format.
2182         (process_instructions): Format output according to igen option.
2183         (print_igen_insn_format): New function.
2184         (print_igen_insn_models): New function.
2185         (process_instructions): Only issue warnings and ignore
2186         instructions when no FEATURE_IGEN.
2187
2188 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2189
2190         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2191         MIPS targets.
2192
2193 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2194
2195         * configure: Regenerated to track ../common/aclocal.m4 changes.
2196
2197 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2198
2199         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2200         SIM_RESERVED_BITS): Delete, moved to common.
2201         (SIM_EXTRA_CFLAGS): Update.
2202
2203 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2204
2205         * configure.in: Configure non-strict memory alignment.
2206         * configure: Regenerated to track ../common/aclocal.m4 changes.
2207
2208 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2209
2210         * configure: Regenerated to track ../common/aclocal.m4 changes.
2211
2212 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2213
2214         * gencode.c (SDBBP,DERET): Added (3900) insns.
2215         (RFE): Turn on for 3900.
2216         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2217         (dsstate): Made global.
2218         (SUBTARGET_R3900): Added.
2219         (CANCELDELAYSLOT): New.
2220         (SignalException): Ignore SystemCall rather than ignore and
2221         terminate.  Add DebugBreakPoint handling.
2222         (decode_coproc): New insns RFE, DERET; and new registers Debug
2223         and DEPC protected by SUBTARGET_R3900.
2224         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2225         bits explicitly.
2226         * Makefile.in,configure.in: Add mips subtarget option.
2227         * configure: Update.
2228
2229 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2230
2231         * gencode.c: Add r3900 (tx39).
2232
2233
2234 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2235
2236         * gencode.c (build_instruction): Don't need to subtract 4 for
2237         JALR, just 2.
2238
2239 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2240
2241         * interp.c: Correct some HASFPU problems.
2242
2243 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2244
2245         * configure: Regenerated to track ../common/aclocal.m4 changes.
2246
2247 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2248
2249         * interp.c (mips_options): Fix samples option short form, should
2250         be `x'.
2251
2252 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2253
2254         * interp.c (sim_info): Enable info code.  Was just returning.
2255
2256 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2257
2258         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2259         MFC0.
2260
2261 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2262
2263         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2264         constants.
2265         (build_instruction): Ditto for LL.
2266
2267 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2268
2269         * configure: Regenerated to track ../common/aclocal.m4 changes.
2270
2271 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2272
2273         * configure: Regenerated to track ../common/aclocal.m4 changes.
2274         * config.in: Ditto.
2275
2276 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2277
2278         * interp.c (sim_open): Add call to sim_analyze_program, update
2279         call to sim_config.
2280
2281 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2282
2283         * interp.c (sim_kill): Delete.
2284         (sim_create_inferior): Add ABFD argument. Set PC from same.
2285         (sim_load): Move code initializing trap handlers from here.
2286         (sim_open): To here.
2287         (sim_load): Delete, use sim-hload.c.
2288
2289         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2290
2291 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2292
2293         * configure: Regenerated to track ../common/aclocal.m4 changes.
2294         * config.in: Ditto.
2295
2296 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2297
2298         * interp.c (sim_open): Add ABFD argument.
2299         (sim_load): Move call to sim_config from here.
2300         (sim_open): To here.  Check return status.
2301
2302 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2303
2304         * gencode.c (build_instruction): Two arg MADD should
2305         not assign result to $0.
2306
2307 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2308
2309         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2310         * sim/mips/configure.in: Regenerate.
2311
2312 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2313
2314         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2315         signed8, unsigned8 et.al. types.
2316
2317         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2318         hosts when selecting subreg.
2319
2320 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2321
2322         * interp.c (sim_engine_run): Reset the ZERO register to zero
2323         regardless of FEATURE_WARN_ZERO.
2324         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2325
2326 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2327
2328         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2329         (SignalException): For BreakPoints ignore any mode bits and just
2330         save the PC.
2331         (SignalException): Always set the CAUSE register.
2332
2333 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2334
2335         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2336         exception has been taken.
2337
2338         * interp.c: Implement the ERET and mt/f sr instructions.
2339
2340 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2341
2342         * interp.c (SignalException): Don't bother restarting an
2343         interrupt.
2344
2345 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2346
2347         * interp.c (SignalException): Really take an interrupt.
2348         (interrupt_event): Only deliver interrupts when enabled.
2349
2350 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2351
2352         * interp.c (sim_info): Only print info when verbose.
2353         (sim_info) Use sim_io_printf for output.
2354
2355 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2356
2357         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2358         mips architectures.
2359
2360 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2361
2362         * interp.c (sim_do_command): Check for common commands if a
2363         simulator specific command fails.
2364
2365 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2366
2367         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2368         and simBE when DEBUG is defined.
2369
2370 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2371
2372         * interp.c (interrupt_event): New function.  Pass exception event
2373         onto exception handler.
2374
2375         * configure.in: Check for stdlib.h.
2376         * configure: Regenerate.
2377
2378         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2379         variable declaration.
2380         (build_instruction): Initialize memval1.
2381         (build_instruction): Add UNUSED attribute to byte, bigend,
2382         reverse.
2383         (build_operands): Ditto.
2384
2385         * interp.c: Fix GCC warnings.
2386         (sim_get_quit_code): Delete.
2387
2388         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2389         * Makefile.in: Ditto.
2390         * configure: Re-generate.
2391
2392         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2393
2394 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2395
2396         * interp.c (mips_option_handler): New function parse argumes using
2397         sim-options.
2398         (myname): Replace with STATE_MY_NAME.
2399         (sim_open): Delete check for host endianness - performed by
2400         sim_config.
2401         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2402         (sim_open): Move much of the initialization from here.
2403         (sim_load): To here.  After the image has been loaded and
2404         endianness set.
2405         (sim_open): Move ColdReset from here.
2406         (sim_create_inferior): To here.
2407         (sim_open): Make FP check less dependant on host endianness.
2408
2409         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2410         run.
2411         * interp.c (sim_set_callbacks): Delete.
2412
2413         * interp.c (membank, membank_base, membank_size): Replace with
2414         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2415         (sim_open): Remove call to callback->init. gdb/run do this.
2416
2417         * interp.c: Update
2418
2419         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2420
2421         * interp.c (big_endian_p): Delete, replaced by
2422         current_target_byte_order.
2423
2424 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2425
2426         * interp.c (host_read_long, host_read_word, host_swap_word,
2427         host_swap_long): Delete. Using common sim-endian.
2428         (sim_fetch_register, sim_store_register): Use H2T.
2429         (pipeline_ticks): Delete.  Handled by sim-events.
2430         (sim_info): Update.
2431         (sim_engine_run): Update.
2432
2433 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2434
2435         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2436         reason from here.
2437         (SignalException): To here. Signal using sim_engine_halt.
2438         (sim_stop_reason): Delete, moved to common.
2439
2440 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2441
2442         * interp.c (sim_open): Add callback argument.
2443         (sim_set_callbacks): Delete SIM_DESC argument.
2444         (sim_size): Ditto.
2445
2446 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2447
2448         * Makefile.in (SIM_OBJS): Add common modules.
2449
2450         * interp.c (sim_set_callbacks): Also set SD callback.
2451         (set_endianness, xfer_*, swap_*): Delete.
2452         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2453         Change to functions using sim-endian macros.
2454         (control_c, sim_stop): Delete, use common version.
2455         (simulate): Convert into.
2456         (sim_engine_run): This function.
2457         (sim_resume): Delete.
2458
2459         * interp.c (simulation): New variable - the simulator object.
2460         (sim_kind): Delete global - merged into simulation.
2461         (sim_load): Cleanup.  Move PC assignment from here.
2462         (sim_create_inferior): To here.
2463
2464         * sim-main.h: New file.
2465         * interp.c (sim-main.h): Include.
2466
2467 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2468
2469         * configure: Regenerated to track ../common/aclocal.m4 changes.
2470
2471 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2472
2473         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2474
2475 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2476
2477         * gencode.c (build_instruction): DIV instructions: check
2478         for division by zero and integer overflow before using
2479         host's division operation.
2480
2481 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2482
2483         * Makefile.in (SIM_OBJS): Add sim-load.o.
2484         * interp.c: #include bfd.h.
2485         (target_byte_order): Delete.
2486         (sim_kind, myname, big_endian_p): New static locals.
2487         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2488         after argument parsing.  Recognize -E arg, set endianness accordingly.
2489         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2490         load file into simulator.  Set PC from bfd.
2491         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2492         (set_endianness): Use big_endian_p instead of target_byte_order.
2493
2494 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2495
2496         * interp.c (sim_size): Delete prototype - conflicts with
2497         definition in remote-sim.h.  Correct definition.
2498
2499 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2500
2501         * configure: Regenerated to track ../common/aclocal.m4 changes.
2502         * config.in: Ditto.
2503
2504 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2505
2506         * interp.c (sim_open): New arg `kind'.
2507
2508         * configure: Regenerated to track ../common/aclocal.m4 changes.
2509
2510 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2511
2512         * configure: Regenerated to track ../common/aclocal.m4 changes.
2513
2514 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2515
2516         * interp.c (sim_open): Set optind to 0 before calling getopt.
2517
2518 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2519
2520         * configure: Regenerated to track ../common/aclocal.m4 changes.
2521
2522 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2523
2524         * interp.c : Replace uses of pr_addr with pr_uword64
2525         where the bit length is always 64 independent of SIM_ADDR.
2526         (pr_uword64) : added.
2527
2528 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2529
2530         * configure: Re-generate.
2531
2532 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2533
2534         * configure: Regenerate to track ../common/aclocal.m4 changes.
2535
2536 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2537
2538         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2539         in argv form.
2540         (other sim_*): New SIM_DESC argument.
2541
2542 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2543
2544         * interp.c: Fix printing of addresses for non-64-bit targets.
2545         (pr_addr): Add function to print address based on size.
2546
2547 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2548
2549         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2550
2551 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2552
2553         * gencode.c (build_mips16_operands): Correct computation of base
2554         address for extended PC relative instruction.
2555
2556 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2557
2558         * interp.c (mips16_entry): Add support for floating point cases.
2559         (SignalException): Pass floating point cases to mips16_entry.
2560         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2561         registers.
2562         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2563         or fmt_word.
2564         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2565         and then set the state to fmt_uninterpreted.
2566         (COP_SW): Temporarily set the state to fmt_word while calling
2567         ValueFPR.
2568
2569 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2570
2571         * gencode.c (build_instruction): The high order may be set in the
2572         comparison flags at any ISA level, not just ISA 4.
2573
2574 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2575
2576         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2577         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2578         * configure.in: sinclude ../common/aclocal.m4.
2579         * configure: Regenerated.
2580
2581 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2582
2583         * configure: Rebuild after change to aclocal.m4.
2584
2585 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2586
2587         * configure configure.in Makefile.in:  Update to new configure
2588         scheme which is more compatible with WinGDB builds.
2589         * configure.in:  Improve comment on how to run autoconf.
2590         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2591         * Makefile.in:  Use autoconf substitution to install common
2592         makefile fragment.
2593
2594 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2595
2596         * gencode.c (build_instruction): Use BigEndianCPU instead of
2597         ByteSwapMem.
2598
2599 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2600
2601         * interp.c (sim_monitor): Make output to stdout visible in
2602         wingdb's I/O log window.
2603
2604 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2605
2606         * support.h: Undo previous change to SIGTRAP
2607         and SIGQUIT values.
2608
2609 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2610
2611         * interp.c (store_word, load_word): New static functions.
2612         (mips16_entry): New static function.
2613         (SignalException): Look for mips16 entry and exit instructions.
2614         (simulate): Use the correct index when setting fpr_state after
2615         doing a pending move.
2616
2617 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2618
2619         * interp.c: Fix byte-swapping code throughout to work on
2620         both little- and big-endian hosts.
2621
2622 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2623
2624         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2625         with gdb/config/i386/xm-windows.h.
2626
2627 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2628
2629         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2630         that messes up arithmetic shifts.
2631
2632 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2633
2634         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2635         SIGTRAP and SIGQUIT for _WIN32.
2636
2637 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2638
2639         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2640         force a 64 bit multiplication.
2641         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2642         destination register is 0, since that is the default mips16 nop
2643         instruction.
2644
2645 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2646
2647         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2648         (build_endian_shift): Don't check proc64.
2649         (build_instruction): Always set memval to uword64.  Cast op2 to
2650         uword64 when shifting it left in memory instructions.  Always use
2651         the same code for stores--don't special case proc64.
2652
2653         * gencode.c (build_mips16_operands): Fix base PC value for PC
2654         relative operands.
2655         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2656         jal instruction.
2657         * interp.c (simJALDELAYSLOT): Define.
2658         (JALDELAYSLOT): Define.
2659         (INDELAYSLOT, INJALDELAYSLOT): Define.
2660         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2661
2662 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2663
2664         * interp.c (sim_open): add flush_cache as a PMON routine
2665         (sim_monitor): handle flush_cache by ignoring it
2666
2667 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2668
2669         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2670         BigEndianMem.
2671         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2672         (BigEndianMem): Rename to ByteSwapMem and change sense.
2673         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2674         BigEndianMem references to !ByteSwapMem.
2675         (set_endianness): New function, with prototype.
2676         (sim_open): Call set_endianness.
2677         (sim_info): Use simBE instead of BigEndianMem.
2678         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2679         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2680         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2681         ifdefs, keeping the prototype declaration.
2682         (swap_word): Rewrite correctly.
2683         (ColdReset): Delete references to CONFIG.  Delete endianness related
2684         code; moved to set_endianness.
2685
2686 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2687
2688         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2689         * interp.c (CHECKHILO): Define away.
2690         (simSIGINT): New macro.
2691         (membank_size): Increase from 1MB to 2MB.
2692         (control_c): New function.
2693         (sim_resume): Rename parameter signal to signal_number.  Add local
2694         variable prev.  Call signal before and after simulate.
2695         (sim_stop_reason): Add simSIGINT support.
2696         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2697         functions always.
2698         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2699         if logfh is NULL.
2700         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2701         a call to sim_warning.
2702
2703 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2704
2705         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2706         16 bit instructions.
2707
2708 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2709
2710         Add support for mips16 (16 bit MIPS implementation):
2711         * gencode.c (inst_type): Add mips16 instruction encoding types.
2712         (GETDATASIZEINSN): Define.
2713         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2714         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2715         mtlo.
2716         (MIPS16_DECODE): New table, for mips16 instructions.
2717         (bitmap_val): New static function.
2718         (struct mips16_op): Define.
2719         (mips16_op_table): New table, for mips16 operands.
2720         (build_mips16_operands): New static function.
2721         (process_instructions): If PC is odd, decode a mips16
2722         instruction.  Break out instruction handling into new
2723         build_instruction function.
2724         (build_instruction): New static function, broken out of
2725         process_instructions.  Check modifiers rather than flags for SHIFT
2726         bit count and m[ft]{hi,lo} direction.
2727         (usage): Pass program name to fprintf.
2728         (main): Remove unused variable this_option_optind.  Change
2729         ``*loptarg++'' to ``loptarg++''.
2730         (my_strtoul): Parenthesize && within ||.
2731         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2732         (simulate): If PC is odd, fetch a 16 bit instruction, and
2733         increment PC by 2 rather than 4.
2734         * configure.in: Add case for mips16*-*-*.
2735         * configure: Rebuild.
2736
2737 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2738
2739         * interp.c: Allow -t to enable tracing in standalone simulator.
2740         Fix garbage output in trace file and error messages.
2741
2742 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2743
2744         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2745         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2746         * configure.in: Simplify using macros in ../common/aclocal.m4.
2747         * configure: Regenerated.
2748         * tconfig.in: New file.
2749
2750 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2751
2752         * interp.c: Fix bugs in 64-bit port.
2753         Use ansi function declarations for msvc compiler.
2754         Initialize and test file pointer in trace code.
2755         Prevent duplicate definition of LAST_EMED_REGNUM.
2756
2757 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2758
2759         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2760
2761 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2762
2763         * interp.c (SignalException): Check for explicit terminating
2764         breakpoint value.
2765         * gencode.c: Pass instruction value through SignalException()
2766         calls for Trap, Breakpoint and Syscall.
2767
2768 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2769
2770         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2771         only used on those hosts that provide it.
2772         * configure.in: Add sqrt() to list of functions to be checked for.
2773         * config.in: Re-generated.
2774         * configure: Re-generated.
2775
2776 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2777
2778         * gencode.c (process_instructions): Call build_endian_shift when
2779         expanding STORE RIGHT, to fix swr.
2780         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2781         clear the high bits.
2782         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2783         Fix float to int conversions to produce signed values.
2784
2785 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2786
2787         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2788         (process_instructions): Correct handling of nor instruction.
2789         Correct shift count for 32 bit shift instructions. Correct sign
2790         extension for arithmetic shifts to not shift the number of bits in
2791         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2792         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2793         Fix madd.
2794         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2795         It's OK to have a mult follow a mult.  What's not OK is to have a
2796         mult follow an mfhi.
2797         (Convert): Comment out incorrect rounding code.
2798
2799 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2800
2801         * interp.c (sim_monitor): Improved monitor printf
2802         simulation. Tidied up simulator warnings, and added "--log" option
2803         for directing warning message output.
2804         * gencode.c: Use sim_warning() rather than WARNING macro.
2805
2806 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2807
2808         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2809         getopt1.o, rather than on gencode.c.  Link objects together.
2810         Don't link against -liberty.
2811         (gencode.o, getopt.o, getopt1.o): New targets.
2812         * gencode.c: Include <ctype.h> and "ansidecl.h".
2813         (AND): Undefine after including "ansidecl.h".
2814         (ULONG_MAX): Define if not defined.
2815         (OP_*): Don't define macros; now defined in opcode/mips.h.
2816         (main): Call my_strtoul rather than strtoul.
2817         (my_strtoul): New static function.
2818
2819 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2820
2821         * gencode.c (process_instructions):  Generate word64 and uword64
2822         instead of `long long' and `unsigned long long' data types.
2823         * interp.c:  #include sysdep.h to get signals, and define default
2824         for SIGBUS.
2825         * (Convert):  Work around for Visual-C++ compiler bug with type
2826         conversion.
2827         * support.h:  Make things compile under Visual-C++ by using
2828         __int64 instead of `long long'.  Change many refs to long long
2829         into word64/uword64 typedefs.
2830
2831 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2832
2833         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2834         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2835         (docdir): Removed.
2836         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2837         (AC_PROG_INSTALL): Added.
2838         (AC_PROG_CC): Moved to before configure.host call.
2839         * configure: Rebuilt.
2840
2841 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2842
2843         * configure.in: Define @SIMCONF@ depending on mips target.
2844         * configure: Rebuild.
2845         * Makefile.in (run): Add @SIMCONF@ to control simulator
2846         construction.
2847         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2848         * interp.c: Remove some debugging, provide more detailed error
2849         messages, update memory accesses to use LOADDRMASK.
2850
2851 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2852
2853         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2854         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2855         stamp-h.
2856         * configure: Rebuild.
2857         * config.in: New file, generated by autoheader.
2858         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2859         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2860         HAVE_ANINT and HAVE_AINT, as appropriate.
2861         * Makefile.in (run): Use @LIBS@ rather than -lm.
2862         (interp.o): Depend upon config.h.
2863         (Makefile): Just rebuild Makefile.
2864         (clean): Remove stamp-h.
2865         (mostlyclean): Make the same as clean, not as distclean.
2866         (config.h, stamp-h): New targets.
2867
2868 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2869
2870         * interp.c (ColdReset): Fix boolean test. Make all simulator
2871         globals static.
2872
2873 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2874
2875         * interp.c (xfer_direct_word, xfer_direct_long,
2876         swap_direct_word, swap_direct_long, xfer_big_word,
2877         xfer_big_long, xfer_little_word, xfer_little_long,
2878         swap_word,swap_long): Added.
2879         * interp.c (ColdReset): Provide function indirection to
2880         host<->simulated_target transfer routines.
2881         * interp.c (sim_store_register, sim_fetch_register): Updated to
2882         make use of indirected transfer routines.
2883
2884 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2885
2886         * gencode.c (process_instructions): Ensure FP ABS instruction
2887         recognised.
2888         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2889         system call support.
2890
2891 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2892
2893         * interp.c (sim_do_command): Complain if callback structure not
2894         initialised.
2895
2896 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2897
2898         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2899         support for Sun hosts.
2900         * Makefile.in (gencode): Ensure the host compiler and libraries
2901         used for cross-hosted build.
2902
2903 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2904
2905         * interp.c, gencode.c: Some more (TODO) tidying.
2906
2907 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2908
2909         * gencode.c, interp.c: Replaced explicit long long references with
2910         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2911         * support.h (SET64LO, SET64HI): Macros added.
2912
2913 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2914
2915         * configure: Regenerate with autoconf 2.7.
2916
2917 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2918
2919         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2920         * support.h: Remove superfluous "1" from #if.
2921         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2922
2923 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2924
2925         * interp.c (StoreFPR): Control UndefinedResult() call on
2926         WARN_RESULT manifest.
2927
2928 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2929
2930         * gencode.c: Tidied instruction decoding, and added FP instruction
2931         support.
2932
2933         * interp.c: Added dineroIII, and BSD profiling support. Also
2934         run-time FP handling.
2935
2936 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2937
2938         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2939         gencode.c, interp.c, support.h: created.