sim/mips/ChangeLog

   1 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * cp1.c: fix formatting of switch case and default labels.
   4         * interp.c: Likewise.
   5         * sim-main.c: Likewise.
   6
   7 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
   8
   9         * cp1.c: Clean up comments which describe FP formats.
  10          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
  11
  12 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
  13             Ed Satterthwaite  <ehs@broadcom.com>
  14
  15         * configure.in (mipsisa64sb1*-*-*): New target for supporting
  16         Broadcom SiByte SB-1 processor configurations.
  17         * configure: Regenerate.
  18         * sb1.igen: New file.
  19         * mips.igen: Include sb1.igen.
  20         (sb1): New model.
  21         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
  22         * mdmx.igen: Add "sb1" model to all appropriate functions and
  23         instructions.
  24         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
  25         (ob_func, ob_acc): Reference the above.
  26         (qh_acc): Adjust to keep the same size as ob_acc.
  27         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
  28         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
  29
  30 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
  31
  32         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
  33
  34 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
  35             Ed Satterthwaite  <ehs@broadcom.com>
  36
  37         * mips.igen (mdmx): New (pseudo-)model.
  38         * mdmx.c, mdmx.igen: New files.
  39         * Makefile.in (SIM_OBJS): Add mdmx.o.
  40         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
  41         New typedefs.
  42         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
  43         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
  44         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
  45         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
  46         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
  47         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
  48         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
  49         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
  50         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
  51         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
  52         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
  53         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
  54         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
  55         (qh_fmtsel): New macros.
  56         (_sim_cpu): New member "acc".
  57         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
  58         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
  59
  60 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
  61
  62         * interp.c: Use 'deprecated' rather than 'depreciated.'
  63         * sim-main.h: Likewise.
  64
  65 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
  66
  67         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
  68         which wouldn't compile anyway.
  69         * sim-main.h (unpredictable_action): New function prototype.
  70         (Unpredictable): Define to call igen function unpredictable().
  71         (NotWordValue): New macro to call igen function not_word_value().
  72         (UndefinedResult): Remove.
  73         * interp.c (undefined_result): Remove.
  74         (unpredictable_action): New function.
  75         * mips.igen (not_word_value, unpredictable): New functions.
  76         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
  77         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
  78         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
  79         NotWordValue() to check for unpredictable inputs, then
  80         Unpredictable() to handle them.
  81
  82 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
  83
  84         * mips.igen: Fix formatting of calls to Unpredictable().
  85
  86 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
  87
  88         * interp.c (sim_open): Revert previous change.
  89
  90 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
  91
  92         * interp.c (sim_open): Disable chunk of code that wrote code in
  93         vector table entries.
  94
  95 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
  96
  97         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
  98         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
  99         unused definitions.
 100
 101 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 102
 103         * cp1.c: Fix many formatting issues.
 104
 105 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 106
 107         * cp1.c (fpu_format_name): New function to replace...
 108         (DOFMT): This.  Delete, and update all callers.
 109         (fpu_rounding_mode_name): New function to replace...
 110         (RMMODE): This.  Delete, and update all callers.
 111
 112 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 113
 114         * interp.c: Move FPU support routines from here to...
 115         * cp1.c: Here.  New file.
 116         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 117         (cp1.o): New target.
 118
 119 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 120
 121         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 122         * mips.igen (mips32, mips64): New models, add to all instructions
 123         and functions as appropriate.
 124         (loadstore_ea, check_u64): New variant for model mips64.
 125         (check_fmt_p): New variant for models mipsV and mips64, remove
 126         mipsV model marking fro other variant.
 127         (SLL) Rename to...
 128         (SLLa) this.
 129         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 130         for mips32 and mips64.
 131         (DCLO, DCLZ): New instructions for mips64.
 132
 133 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 134
 135         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 136         immediate or code as a hex value with the "%#lx" format.
 137         (ANDI): Likewise, and fix printed instruction name.
 138
 139 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 140
 141         * sim-main.h (UndefinedResult, Unpredictable): New macros
 142         which currently do nothing.
 143
 144 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 145
 146         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 147         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 148         (status_CU3): New definitions.
 149
 150         * sim-main.h (ExceptionCause): Add new values for MIPS32
 151         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 152         for DebugBreakPoint and NMIReset to note their status in
 153         MIPS32 and MIPS64.
 154         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 155         (SignalExceptionCacheErr): New exception macros.
 156
 157 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 158
 159         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 160         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 161         is always enabled.
 162         (SignalExceptionCoProcessorUnusable): Take as argument the
 163         unusable coprocessor number.
 164
 165 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 166
 167         * mips.igen: Fix formatting of all SignalException calls.
 168
 169 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 170
 171         * sim-main.h (SIGNEXTEND): Remove.
 172
 173 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 174
 175         * mips.igen: Remove gencode comment from top of file, fix
 176         spelling in another comment.
 177
 178 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 179
 180         * mips.igen (check_fmt, check_fmt_p): New functions to check
 181         whether specific floating point formats are usable.
 182         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 183         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 184         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 185         Use the new functions.
 186         (do_c_cond_fmt): Remove format checks...
 187         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 188
 189 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 190
 191         * mips.igen: Fix formatting of check_fpu calls.
 192
 193 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 194
 195         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 196
 197 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 198
 199         * mips.igen: Remove whitespace at end of lines.
 200
 201 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 202
 203         * mips.igen (loadstore_ea): New function to do effective
 204         address calculations.
 205         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 206         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 207         CACHE): Use loadstore_ea to do effective address computations.
 208
 209 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 210
 211         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 212         * mips.igen (LL, CxC1, MxC1): Likewise.
 213
 214 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 215
 216         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 217         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 218         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 219         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 220         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 221         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 222         Don't split opcode fields by hand, use the opcode field values
 223         provided by igen.
 224
 225 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 226
 227         * mips.igen (do_divu): Fix spacing.
 228
 229         * mips.igen (do_dsllv): Move to be right before DSLLV,
 230         to match the rest of the do_<shift> functions.
 231
 232 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 233
 234         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 235         DSRL32, do_dsrlv): Trace inputs and results.
 236
 237 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 238
 239         * mips.igen (CACHE): Provide instruction-printing string.
 240
 241         * interp.c (signal_exception): Comment tokens after #endif.
 242
 243 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 244
 245         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 246         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 247         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 248         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 249         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 250         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 251         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 252         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 253
 254 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 255
 256         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 257         instruction-printing string.
 258         (LWU): Use '64' as the filter flag.
 259
 260 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 261
 262         * mips.igen (SDXC1): Fix instruction-printing string.
 263
 264 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 265
 266         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 267         filter flags "32,f".
 268
 269 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 270
 271         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 272         as the filter flag.
 273
 274 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 275
 276         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 277         add a comma) so that it more closely match the MIPS ISA
 278         documentation opcode partitioning.
 279         (PREF): Put useful names on opcode fields, and include
 280         instruction-printing string.
 281
 282 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 283
 284         * mips.igen (check_u64): New function which in the future will
 285         check whether 64-bit instructions are usable and signal an
 286         exception if not.  Currently a no-op.
 287         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 288         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 289         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 290         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 291
 292         * mips.igen (check_fpu): New function which in the future will
 293         check whether FPU instructions are usable and signal an exception
 294         if not.  Currently a no-op.
 295         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 296         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 297         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 298         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 299         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 300         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 301         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 302         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 303
 304 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 305
 306         * mips.igen (do_load_left, do_load_right): Move to be immediately
 307         following do_load.
 308         (do_store_left, do_store_right): Move to be immediately following
 309         do_store.
 310
 311 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 312
 313         * mips.igen (mipsV): New model name.  Also, add it to
 314         all instructions and functions where it is appropriate.
 315
 316 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 317
 318         * mips.igen: For all functions and instructions, list model
 319         names that support that instruction one per line.
 320
 321 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 322
 323         * mips.igen: Add some additional comments about supported
 324         models, and about which instructions go where.
 325         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 326         order as is used in the rest of the file.
 327
 328 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 329
 330         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 331         indicating that ALU32_END or ALU64_END are there to check
 332         for overflow.
 333         (DADD): Likewise, but also remove previous comment about
 334         overflow checking.
 335
 336 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 337
 338         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 339         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 340         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 341         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 342         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 343         fields (i.e., add and move commas) so that they more closely
 344         match the MIPS ISA documentation opcode partitioning.
 345
 346 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 347
 348         * mips.igen (ADDI): Print immediate value.
 349         (BREAK): Print code.
 350         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 351         (SLL): Print "nop" specially, and don't run the code
 352         that does the shift for the "nop" case.
 353
 354 2001-11-17  Fred Fish  <fnf@redhat.com>
 355
 356         * sim-main.h (float_operation): Move enum declaration outside
 357         of _sim_cpu struct declaration.
 358
 359 2001-04-12  Jim Blandy  <jimb@redhat.com>
 360
 361         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 362         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 363         set of the FCSR.
 364         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 365         PENDING_FILL, and you can get the intended effect gracefully by
 366         calling PENDING_SCHED directly.
 367
 368 2001-02-23  Ben Elliston  <bje@redhat.com>
 369
 370         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 371         already defined elsewhere.
 372
 373 2001-02-19  Ben Elliston  <bje@redhat.com>
 374
 375         * sim-main.h (sim_monitor): Return an int.
 376         * interp.c (sim_monitor): Add return values.
 377         (signal_exception): Handle error conditions from sim_monitor.
 378
 379 2001-02-08  Ben Elliston  <bje@redhat.com>
 380
 381         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 382         (store_memory): Likewise, pass cia to sim_core_write*.
 383
 384 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 385
 386         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 387         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 388
 389 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 390
 391         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 392         * Makefile.in: Don't delete *.igen when cleaning directory.
 393
 394 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 395
 396         * m16.igen (break): Call SignalException not sim_engine_halt.
 397
 398 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 399
 400         From Jason Eckhardt:
 401         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 402
 403 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 404
 405         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 406
 407 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 408
 409         * mips.igen (do_dmultx): Fix typo.
 410
 411 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 412
 413         * configure: Regenerated to track ../common/aclocal.m4 changes.
 414
 415 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 416
 417         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 418
 419 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 420
 421         * sim-main.h (GPR_CLEAR): Define macro.
 422
 423 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 424
 425         * interp.c (decode_coproc): Output long using %lx and not %s.
 426
 427 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 428
 429         * interp.c (sim_open): Sort & extend dummy memory regions for
 430         --board=jmr3904 for eCos.
 431
 432 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 433
 434         * configure: Regenerated.
 435
 436 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 437
 438         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 439         calls, conditional on the simulator being in verbose mode.
 440
 441 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 442
 443         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 444         cache don't get ReservedInstruction traps.
 445
 446 1999-11-29  Mark Salter  <msalter@cygnus.com>
 447
 448         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 449         to clear status bits in sdisr register. This is how the hardware works.
 450
 451         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 452         being used by cygmon.
 453
 454 1999-11-11  Andrew Haley  <aph@cygnus.com>
 455
 456         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 457         instructions.
 458
 459 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 460
 461         * mips.igen (MULT): Correct previous mis-applied patch.
 462
 463 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 464
 465         * mips.igen (delayslot32): Handle sequence like
 466         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 467         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 468         (MULT): Actually pass the third register...
 469
 470 1999-09-03  Mark Salter  <msalter@cygnus.com>
 471
 472         * interp.c (sim_open): Added more memory aliases for additional
 473         hardware being touched by cygmon on jmr3904 board.
 474
 475 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 476
 477         * configure: Regenerated to track ../common/aclocal.m4 changes.
 478
 479 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 480
 481         * interp.c (sim_store_register): Handle case where client - GDB -
 482         specifies that a 4 byte register is 8 bytes in size.
 483         (sim_fetch_register): Ditto.
 484
 485 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 486
 487         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 488         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 489         (idt_monitor_base): Base address for IDT monitor traps.
 490         (pmon_monitor_base): Ditto for PMON.
 491         (lsipmon_monitor_base): Ditto for LSI PMON.
 492         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 493         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 494         (sim_firmware_command): New function.
 495         (mips_option_handler): Call it for OPTION_FIRMWARE.
 496         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 497         option was given, add no monitor by default.  Add BREAK hooks only if
 498         monitors are also there.
 499
 500 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 501
 502         * interp.c (sim_monitor): Flush output before reading input.
 503
 504 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 505
 506         * tconfig.in (SIM_HANDLES_LMA): Always define.
 507
 508 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 509
 510         From Mark Salter <msalter@cygnus.com>:
 511         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 512         (sim_open): Add setup for BSP board.
 513
 514 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 515
 516         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 517         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 518         them as unimplemented.
 519
 520 1999-05-08  Felix Lee  <flee@cygnus.com>
 521
 522         * configure: Regenerated to track ../common/aclocal.m4 changes.
 523
 524 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 525
 526         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 527
 528 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 529
 530         * configure.in: Any mips64vr5*-*-* target should have
 531         -DTARGET_ENABLE_FR=1.
 532         (default_endian): Any mips64vr*el-*-* target should default to
 533         LITTLE_ENDIAN.
 534         * configure: Re-generate.
 535
 536 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 537
 538         * mips.igen (ldl): Extend from _16_, not 32.
 539
 540 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 541
 542         * interp.c (sim_store_register): Force registers written to by GDB
 543         into an un-interpreted state.
 544
 545 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 546
 547         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 548         CPU, start periodic background I/O polls.
 549         (tx3904sio_poll): New function: periodic I/O poller.
 550
 551 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 552
 553         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 554
 555 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 556
 557         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 558         case statement.
 559
 560 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 561
 562         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 563         (load_word): Call SIM_CORE_SIGNAL hook on error.
 564         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 565         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 566         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 567         * sim-main.h (COP0_BADVADDR): Define.
 568         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 569         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 570         (_sim_cpu): Add exc_* fields to store register value snapshots.
 571         * mips.igen (*): Replace memory-related SignalException* calls
 572         with references to SIM_CORE_SIGNAL hook.
 573
 574         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 575         fix.
 576         * sim-main.c (*): Minor warning cleanups.
 577
 578 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 579
 580         * m16.igen (DADDIU5): Correct type-o.
 581
 582 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 583
 584         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 585         variables.
 586
 587 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 588
 589         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 590         to include path.
 591         (interp.o): Add dependency on itable.h
 592         (oengine.c, gencode): Delete remaining references.
 593         (BUILT_SRC_FROM_GEN): Clean up.
 594
 595 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 596
 597         * vr4run.c: New.
 598         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 599         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 600         tmp-run-hack) : New.
 601         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 602         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 603         Drop the "64" qualifier to get the HACK generator working.
 604         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 605         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 606         qualifier to get the hack generator working.
 607         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 608         (DSLL): Use do_dsll.
 609         (DSLLV): Use do_dsllv.
 610         (DSRA): Use do_dsra.
 611         (DSRL): Use do_dsrl.
 612         (DSRLV): Use do_dsrlv.
 613         (BC1): Move *vr4100 to get the HACK generator working.
 614         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 615         get the HACK generator working.
 616         (MACC) Rename to get the HACK generator working.
 617         (DMACC,MACCS,DMACCS): Add the 64.
 618
 619 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 620
 621         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 622         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 623
 624 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 625
 626     * mips/interp.c (DEBUG): Cleanups.
 627
 628 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 629
 630         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 631         (tx3904sio_tickle): fflush after a stdout character output.
 632
 633 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 634
 635         * interp.c (sim_close): Uninstall modules.
 636
 637 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 638
 639         * sim-main.h, interp.c (sim_monitor): Change to global
 640         function.
 641
 642 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 643
 644         * configure.in (vr4100): Only include vr4100 instructions in
 645         simulator.
 646         * configure: Re-generate.
 647         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 648
 649 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 650
 651         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 652         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 653         true alternative.
 654
 655         * configure.in (sim_default_gen, sim_use_gen): Replace with
 656         sim_gen.
 657         (--enable-sim-igen): Delete config option. Always using IGEN.
 658         * configure: Re-generate.
 659
 660         * Makefile.in (gencode): Kill, kill, kill.
 661         * gencode.c: Ditto.
 662
 663 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 664
 665         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 666         bit mips16 igen simulator.
 667         * configure: Re-generate.
 668
 669         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 670         as part of vr4100 ISA.
 671         * vr.igen: Mark all instructions as 64 bit only.
 672
 673 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 674
 675         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 676         Pacify GCC.
 677
 678 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 679
 680         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 681         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 682         * configure: Re-generate.
 683
 684         * m16.igen (BREAK): Define breakpoint instruction.
 685         (JALX32): Mark instruction as mips16 and not r3900.
 686         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 687
 688         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 689
 690 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 691
 692         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 693         insn as a debug breakpoint.
 694
 695         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 696         pending.slot_size.
 697         (PENDING_SCHED): Clean up trace statement.
 698         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 699         (PENDING_FILL): Delay write by only one cycle.
 700         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 701
 702         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 703         of pending writes.
 704         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 705         32 & 64.
 706         (pending_tick): Move incrementing of index to FOR statement.
 707         (pending_tick): Only update PENDING_OUT after a write has occured.
 708
 709         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 710         build simulator.
 711         * configure: Re-generate.
 712
 713         * interp.c (sim_engine_run OLD): Delete explicit call to
 714         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 715
 716 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 717
 718         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 719         interrupt level number to match changed SignalExceptionInterrupt
 720         macro.
 721
 722 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 723
 724         * interp.c: #include "itable.h" if WITH_IGEN.
 725         (get_insn_name): New function.
 726         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 727         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 728
 729 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 730
 731         * configure: Rebuilt to inhale new common/aclocal.m4.
 732
 733 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 734
 735         * dv-tx3904sio.c: Include sim-assert.h.
 736
 737 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 738
 739         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 740         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 741         Reorganize target-specific sim-hardware checks.
 742         * configure: rebuilt.
 743         * interp.c (sim_open): For tx39 target boards, set
 744         OPERATING_ENVIRONMENT, add tx3904sio devices.
 745         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 746         ROM executables.  Install dv-sockser into sim-modules list.
 747
 748         * dv-tx3904irc.c: Compiler warning clean-up.
 749         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 750         frequent hw-trace messages.
 751
 752 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 753
 754         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 755
 756 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 757
 758         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 759
 760         * vr.igen: New file.
 761         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 762         * mips.igen: Define vr4100 model. Include vr.igen.
 763 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 764
 765         * mips.igen (check_mf_hilo): Correct check.
 766
 767 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 768
 769         * sim-main.h (interrupt_event): Add prototype.
 770
 771         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 772         register_ptr, register_value.
 773         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 774
 775         * sim-main.h (tracefh): Make extern.
 776
 777 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 778
 779         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 780         Reduce unnecessarily high timer event frequency.
 781         * dv-tx3904cpu.c: Ditto for interrupt event.
 782
 783 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 784
 785         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 786         to allay warnings.
 787         (interrupt_event): Made non-static.
 788
 789         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 790         interchange of configuration values for external vs. internal
 791         clock dividers.
 792
 793 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 794
 795         * mips.igen (BREAK): Moved code to here for
 796         simulator-reserved break instructions.
 797         * gencode.c (build_instruction): Ditto.
 798         * interp.c (signal_exception): Code moved from here.  Non-
 799         reserved instructions now use exception vector, rather
 800         than halting sim.
 801         * sim-main.h: Moved magic constants to here.
 802
 803 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 804
 805         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 806         register upon non-zero interrupt event level, clear upon zero
 807         event value.
 808         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 809         by passing zero event value.
 810         (*_io_{read,write}_buffer): Endianness fixes.
 811         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 812         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 813
 814         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 815         serial I/O and timer module at base address 0xFFFF0000.
 816
 817 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 818
 819         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 820         and BigEndianCPU.
 821
 822 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 823
 824         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 825         parts.
 826         * configure: Update.
 827
 828 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 829
 830         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 831         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 832         * configure.in: Include tx3904tmr in hw_device list.
 833         * configure: Rebuilt.
 834         * interp.c (sim_open): Instantiate three timer instances.
 835         Fix address typo of tx3904irc instance.
 836
 837 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 838
 839         * interp.c (signal_exception): SystemCall exception now uses
 840         the exception vector.
 841
 842 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 843
 844         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 845         to allay warnings.
 846
 847 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 848
 849         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 850
 851 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 852
 853         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 854
 855         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 856         sim-main.h. Declare a struct hw_descriptor instead of struct
 857         hw_device_descriptor.
 858
 859 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 860
 861         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 862         right bits and then re-align left hand bytes to correct byte
 863         lanes.  Fix incorrect computation in do_store_left when loading
 864         bytes from second word.
 865
 866 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 867
 868         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 869         * interp.c (sim_open): Only create a device tree when HW is
 870         enabled.
 871
 872         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 873         * interp.c (signal_exception): Ditto.
 874
 875 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 876
 877         * gencode.c: Mark BEGEZALL as LIKELY.
 878
 879 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 880
 881         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 882         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 883
 884 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 885
 886         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 887         modules.  Recognize TX39 target with "mips*tx39" pattern.
 888         * configure: Rebuilt.
 889         * sim-main.h (*): Added many macros defining bits in
 890         TX39 control registers.
 891         (SignalInterrupt): Send actual PC instead of NULL.
 892         (SignalNMIReset): New exception type.
 893         * interp.c (board): New variable for future use to identify
 894         a particular board being simulated.
 895         (mips_option_handler,mips_options): Added "--board" option.
 896         (interrupt_event): Send actual PC.
 897         (sim_open): Make memory layout conditional on board setting.
 898         (signal_exception): Initial implementation of hardware interrupt
 899         handling.  Accept another break instruction variant for simulator
 900         exit.
 901         (decode_coproc): Implement RFE instruction for TX39.
 902         (mips.igen): Decode RFE instruction as such.
 903         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 904         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 905         bbegin to implement memory map.
 906         * dv-tx3904cpu.c: New file.
 907         * dv-tx3904irc.c: New file.
 908
 909 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 910
 911         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 912
 913 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 914
 915         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 916         with calls to check_div_hilo.
 917
 918 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 919
 920         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 921         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 922         Add special r3900 version of do_mult_hilo.
 923         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 924         with calls to check_mult_hilo.
 925         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 926         with calls to check_div_hilo.
 927
 928 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 929
 930         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 931         Document a replacement.
 932
 933 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 934
 935         * interp.c (sim_monitor): Make mon_printf work.
 936
 937 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 938
 939         * sim-main.h (INSN_NAME): New arg `cpu'.
 940
 941 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 942
 943         * configure: Regenerated to track ../common/aclocal.m4 changes.
 944
 945 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 946
 947         * configure: Regenerated to track ../common/aclocal.m4 changes.
 948         * config.in: Ditto.
 949
 950 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 951
 952         * acconfig.h: New file.
 953         * configure.in: Reverted change of Apr 24; use sinclude again.
 954
 955 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 956
 957         * configure: Regenerated to track ../common/aclocal.m4 changes.
 958         * config.in: Ditto.
 959
 960 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 961
 962         * configure.in: Don't call sinclude.
 963
 964 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 965
 966         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 967
 968 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 969
 970         * mips.igen (ERET): Implement.
 971
 972         * interp.c (decode_coproc): Return sign-extended EPC.
 973
 974         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 975
 976         * interp.c (signal_exception): Do not ignore Trap.
 977         (signal_exception): On TRAP, restart at exception address.
 978         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 979         (signal_exception): Update.
 980         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 981         so that TRAP instructions are caught.
 982
 983 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 984
 985         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 986         contains HI/LO access history.
 987         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 988         (HIACCESS, LOACCESS): Delete, replace with
 989         (HIHISTORY, LOHISTORY): New macros.
 990         (CHECKHILO): Delete all, moved to mips.igen
 991
 992         * gencode.c (build_instruction): Do not generate checks for
 993         correct HI/LO register usage.
 994
 995         * interp.c (old_engine_run): Delete checks for correct HI/LO
 996         register usage.
 997
 998         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 999         check_mf_cycles): New functions.
1000         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1001         do_divu, domultx, do_mult, do_multu): Use.
1002
1003         * tx.igen ("madd", "maddu"): Use.
1004
1005 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1006
1007         * mips.igen (DSRAV): Use function do_dsrav.
1008         (SRAV): Use new function do_srav.
1009
1010         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1011         (B): Sign extend 11 bit immediate.
1012         (EXT-B*): Shift 16 bit immediate left by 1.
1013         (ADDIU*): Don't sign extend immediate value.
1014
1015 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1016
1017         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1018
1019         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1020         functions.
1021
1022         * mips.igen (delayslot32, nullify_next_insn): New functions.
1023         (m16.igen): Always include.
1024         (do_*): Add more tracing.
1025
1026         * m16.igen (delayslot16): Add NIA argument, could be called by a
1027         32 bit MIPS16 instruction.
1028
1029         * interp.c (ifetch16): Move function from here.
1030         * sim-main.c (ifetch16): To here.
1031
1032         * sim-main.c (ifetch16, ifetch32): Update to match current
1033         implementations of LH, LW.
1034         (signal_exception): Don't print out incorrect hex value of illegal
1035         instruction.
1036
1037 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1038
1039         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1040         instruction.
1041
1042         * m16.igen: Implement MIPS16 instructions.
1043
1044         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1045         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1046         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1047         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1048         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1049         bodies of corresponding code from 32 bit insn to these.  Also used
1050         by MIPS16 versions of functions.
1051
1052         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1053         (IMEM16): Drop NR argument from macro.
1054
1055 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1056
1057         * Makefile.in (SIM_OBJS): Add sim-main.o.
1058
1059         * sim-main.h (address_translation, load_memory, store_memory,
1060         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1061         as INLINE_SIM_MAIN.
1062         (pr_addr, pr_uword64): Declare.
1063         (sim-main.c): Include when H_REVEALS_MODULE_P.
1064
1065         * interp.c (address_translation, load_memory, store_memory,
1066         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1067         from here.
1068         * sim-main.c: To here. Fix compilation problems.
1069
1070         * configure.in: Enable inlining.
1071         * configure: Re-config.
1072
1073 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1074
1075         * configure: Regenerated to track ../common/aclocal.m4 changes.
1076
1077 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1078
1079         * mips.igen: Include tx.igen.
1080         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1081         * tx.igen: New file, contains MADD and MADDU.
1082
1083         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1084         the hardwired constant `7'.
1085         (store_memory): Ditto.
1086         (LOADDRMASK): Move definition to sim-main.h.
1087
1088         mips.igen (MTC0): Enable for r3900.
1089         (ADDU): Add trace.
1090
1091         mips.igen (do_load_byte): Delete.
1092         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1093         do_store_right): New functions.
1094         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1095
1096         configure.in: Let the tx39 use igen again.
1097         configure: Update.
1098
1099 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1100
1101         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1102         not an address sized quantity.  Return zero for cache sizes.
1103
1104 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1105
1106         * mips.igen (r3900): r3900 does not support 64 bit integer
1107         operations.
1108
1109 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1110
1111         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1112         than igen one.
1113         * configure : Rebuild.
1114
1115 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1116
1117         * configure: Regenerated to track ../common/aclocal.m4 changes.
1118
1119 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1120
1121         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1122
1123 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1124
1125         * configure: Regenerated to track ../common/aclocal.m4 changes.
1126         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1127
1128 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1129
1130         * configure: Regenerated to track ../common/aclocal.m4 changes.
1131
1132 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1133
1134         * interp.c (Max, Min): Comment out functions. Not yet used.
1135
1136 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1137
1138         * configure: Regenerated to track ../common/aclocal.m4 changes.
1139
1140 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1141
1142         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1143         configurable settings for stand-alone simulator.
1144
1145         * configure.in: Added X11 search, just in case.
1146
1147         * configure: Regenerated.
1148
1149 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1150
1151         * interp.c (sim_write, sim_read, load_memory, store_memory):
1152         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1153
1154 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1155
1156         * sim-main.h (GETFCC): Return an unsigned value.
1157
1158 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1159
1160         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1161         (DADD): Result destination is RD not RT.
1162
1163 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1164
1165         * sim-main.h (HIACCESS, LOACCESS): Always define.
1166
1167         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1168
1169         * interp.c (sim_info): Delete.
1170
1171 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1172
1173         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1174         (mips_option_handler): New argument `cpu'.
1175         (sim_open): Update call to sim_add_option_table.
1176
1177 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1178
1179         * mips.igen (CxC1): Add tracing.
1180
1181 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1182
1183         * sim-main.h (Max, Min): Declare.
1184
1185         * interp.c (Max, Min): New functions.
1186
1187         * mips.igen (BC1): Add tracing.
1188
1189 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1190
1191         * interp.c Added memory map for stack in vr4100
1192
1193 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1194
1195         * interp.c (load_memory): Add missing "break"'s.
1196
1197 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1198
1199         * interp.c (sim_store_register, sim_fetch_register): Pass in
1200         length parameter.  Return -1.
1201
1202 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1203
1204         * interp.c: Added hardware init hook, fixed warnings.
1205
1206 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1207
1208         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1209
1210 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1211
1212         * interp.c (ifetch16): New function.
1213
1214         * sim-main.h (IMEM32): Rename IMEM.
1215         (IMEM16_IMMED): Define.
1216         (IMEM16): Define.
1217         (DELAY_SLOT): Update.
1218
1219         * m16run.c (sim_engine_run): New file.
1220
1221         * m16.igen: All instructions except LB.
1222         (LB): Call do_load_byte.
1223         * mips.igen (do_load_byte): New function.
1224         (LB): Call do_load_byte.
1225
1226         * mips.igen: Move spec for insn bit size and high bit from here.
1227         * Makefile.in (tmp-igen, tmp-m16): To here.
1228
1229         * m16.dc: New file, decode mips16 instructions.
1230
1231         * Makefile.in (SIM_NO_ALL): Define.
1232         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1233
1234 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1235
1236         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1237         point unit to 32 bit registers.
1238         * configure: Re-generate.
1239
1240 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1241
1242         * configure.in (sim_use_gen): Make IGEN the default simulator
1243         generator for generic 32 and 64 bit mips targets.
1244         * configure: Re-generate.
1245
1246 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1247
1248         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1249         bitsize.
1250
1251         * interp.c (sim_fetch_register, sim_store_register): Read/write
1252         FGR from correct location.
1253         (sim_open): Set size of FGR's according to
1254         WITH_TARGET_FLOATING_POINT_BITSIZE.
1255
1256         * sim-main.h (FGR): Store floating point registers in a separate
1257         array.
1258
1259 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1260
1261         * configure: Regenerated to track ../common/aclocal.m4 changes.
1262
1263 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1264
1265         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1266
1267         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1268
1269         * interp.c (pending_tick): New function.  Deliver pending writes.
1270
1271         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1272         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1273         it can handle mixed sized quantites and single bits.
1274
1275 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1276
1277         * interp.c (oengine.h): Do not include when building with IGEN.
1278         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1279         (sim_info): Ditto for PROCESSOR_64BIT.
1280         (sim_monitor): Replace ut_reg with unsigned_word.
1281         (*): Ditto for t_reg.
1282         (LOADDRMASK): Define.
1283         (sim_open): Remove defunct check that host FP is IEEE compliant,
1284         using software to emulate floating point.
1285         (value_fpr, ...): Always compile, was conditional on HASFPU.
1286
1287 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1288
1289         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1290         size.
1291
1292         * interp.c (SD, CPU): Define.
1293         (mips_option_handler): Set flags in each CPU.
1294         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1295         (sim_close): Do not clear STATE, deleted anyway.
1296         (sim_write, sim_read): Assume CPU zero's vm should be used for
1297         data transfers.
1298         (sim_create_inferior): Set the PC for all processors.
1299         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1300         argument.
1301         (mips16_entry): Pass correct nr of args to store_word, load_word.
1302         (ColdReset): Cold reset all cpu's.
1303         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1304         (sim_monitor, load_memory, store_memory, signal_exception): Use
1305         `CPU' instead of STATE_CPU.
1306
1307
1308         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1309         SD or CPU_.
1310
1311         * sim-main.h (signal_exception): Add sim_cpu arg.
1312         (SignalException*): Pass both SD and CPU to signal_exception.
1313         * interp.c (signal_exception): Update.
1314
1315         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1316         Ditto
1317         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1318         address_translation): Ditto
1319         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1320
1321 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1322
1323         * configure: Regenerated to track ../common/aclocal.m4 changes.
1324
1325 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1328
1329         * mips.igen (model): Map processor names onto BFD name.
1330
1331         * sim-main.h (CPU_CIA): Delete.
1332         (SET_CIA, GET_CIA): Define
1333
1334 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1335
1336         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1337         regiser.
1338
1339         * configure.in (default_endian): Configure a big-endian simulator
1340         by default.
1341         * configure: Re-generate.
1342
1343 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1344
1345         * configure: Regenerated to track ../common/aclocal.m4 changes.
1346
1347 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1348
1349         * interp.c (sim_monitor): Handle Densan monitor outbyte
1350         and inbyte functions.
1351
1352 1997-12-29  Felix Lee  <flee@cygnus.com>
1353
1354         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1355
1356 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1357
1358         * Makefile.in (tmp-igen): Arrange for $zero to always be
1359         reset to zero after every instruction.
1360
1361 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1362
1363         * configure: Regenerated to track ../common/aclocal.m4 changes.
1364         * config.in: Ditto.
1365
1366 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1367
1368         * mips.igen (MSUB): Fix to work like MADD.
1369         * gencode.c (MSUB): Similarly.
1370
1371 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1372
1373         * configure: Regenerated to track ../common/aclocal.m4 changes.
1374
1375 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1376
1377         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1378
1379 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1380
1381         * sim-main.h (sim-fpu.h): Include.
1382
1383         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1384         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1385         using host independant sim_fpu module.
1386
1387 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1388
1389         * interp.c (signal_exception): Report internal errors with SIGABRT
1390         not SIGQUIT.
1391
1392         * sim-main.h (C0_CONFIG): New register.
1393         (signal.h): No longer include.
1394
1395         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1396
1397 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1398
1399         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1400
1401 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1402
1403         * mips.igen: Tag vr5000 instructions.
1404         (ANDI): Was missing mipsIV model, fix assembler syntax.
1405         (do_c_cond_fmt): New function.
1406         (C.cond.fmt): Handle mips I-III which do not support CC field
1407         separatly.
1408         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1409         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1410         in IV3.2 spec.
1411         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1412         vr5000 which saves LO in a GPR separatly.
1413
1414         * configure.in (enable-sim-igen): For vr5000, select vr5000
1415         specific instructions.
1416         * configure: Re-generate.
1417
1418 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1419
1420         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1421
1422         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1423         fmt_uninterpreted_64 bit cases to switch.  Convert to
1424         fmt_formatted,
1425
1426         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1427
1428         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1429         as specified in IV3.2 spec.
1430         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1431
1432 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1433
1434         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1435         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1436         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1437         PENDING_FILL versions of instructions.  Simplify.
1438         (X): New function.
1439         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1440         instructions.
1441         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1442         a signed value.
1443         (MTHI, MFHI): Disable code checking HI-LO.
1444
1445         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1446         global.
1447         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1448
1449 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1450
1451         * gencode.c (build_mips16_operands): Replace IPC with cia.
1452
1453         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1454         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1455         IPC to `cia'.
1456         (UndefinedResult): Replace function with macro/function
1457         combination.
1458         (sim_engine_run): Don't save PC in IPC.
1459
1460         * sim-main.h (IPC): Delete.
1461
1462
1463         * interp.c (signal_exception, store_word, load_word,
1464         address_translation, load_memory, store_memory, cache_op,
1465         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1466         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1467         current instruction address - cia - argument.
1468         (sim_read, sim_write): Call address_translation directly.
1469         (sim_engine_run): Rename variable vaddr to cia.
1470         (signal_exception): Pass cia to sim_monitor
1471
1472         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1473         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1474         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1475
1476         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1477         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1478         SIM_ASSERT.
1479
1480         * interp.c (signal_exception): Pass restart address to
1481         sim_engine_restart.
1482
1483         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1484         idecode.o): Add dependency.
1485
1486         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1487         Delete definitions
1488         (DELAY_SLOT): Update NIA not PC with branch address.
1489         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1490
1491         * mips.igen: Use CIA not PC in branch calculations.
1492         (illegal): Call SignalException.
1493         (BEQ, ADDIU): Fix assembler.
1494
1495 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1496
1497         * m16.igen (JALX): Was missing.
1498
1499         * configure.in (enable-sim-igen): New configuration option.
1500         * configure: Re-generate.
1501
1502         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1503
1504         * interp.c (load_memory, store_memory): Delete parameter RAW.
1505         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1506         bypassing {load,store}_memory.
1507
1508         * sim-main.h (ByteSwapMem): Delete definition.
1509
1510         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1511
1512         * interp.c (sim_do_command, sim_commands): Delete mips specific
1513         commands.  Handled by module sim-options.
1514
1515         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1516         (WITH_MODULO_MEMORY): Define.
1517
1518         * interp.c (sim_info): Delete code printing memory size.
1519
1520         * interp.c (mips_size): Nee sim_size, delete function.
1521         (power2): Delete.
1522         (monitor, monitor_base, monitor_size): Delete global variables.
1523         (sim_open, sim_close): Delete code creating monitor and other
1524         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1525         manage memory regions.
1526         (load_memory, store_memory): Use sim-core for memory model.
1527
1528         * interp.c (address_translation): Delete all memory map code
1529         except line forcing 32 bit addresses.
1530
1531 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1532
1533         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1534         trace options.
1535
1536         * interp.c (logfh, logfile): Delete globals.
1537         (sim_open, sim_close): Delete code opening & closing log file.
1538         (mips_option_handler): Delete -l and -n options.
1539         (OPTION mips_options): Ditto.
1540
1541         * interp.c (OPTION mips_options): Rename option trace to dinero.
1542         (mips_option_handler): Update.
1543
1544 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1545
1546         * interp.c (fetch_str): New function.
1547         (sim_monitor): Rewrite using sim_read & sim_write.
1548         (sim_open): Check magic number.
1549         (sim_open): Write monitor vectors into memory using sim_write.
1550         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1551         (sim_read, sim_write): Simplify - transfer data one byte at a
1552         time.
1553         (load_memory, store_memory): Clarify meaning of parameter RAW.
1554
1555         * sim-main.h (isHOST): Defete definition.
1556         (isTARGET): Mark as depreciated.
1557         (address_translation): Delete parameter HOST.
1558
1559         * interp.c (address_translation): Delete parameter HOST.
1560
1561 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1562
1563         * mips.igen:
1564
1565         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1566         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1567
1568 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1569
1570         * mips.igen: Add model filter field to records.
1571
1572 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1573
1574         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1575
1576         interp.c (sim_engine_run): Do not compile function sim_engine_run
1577         when WITH_IGEN == 1.
1578
1579         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1580         target architecture.
1581
1582         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1583         igen. Replace with configuration variables sim_igen_flags /
1584         sim_m16_flags.
1585
1586         * m16.igen: New file.  Copy mips16 insns here.
1587         * mips.igen: From here.
1588
1589 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1590
1591         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1592         to top.
1593         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1594
1595 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1596
1597         * gencode.c (build_instruction): Follow sim_write's lead in using
1598         BigEndianMem instead of !ByteSwapMem.
1599
1600 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1601
1602         * configure.in (sim_gen): Dependent on target, select type of
1603         generator.  Always select old style generator.
1604
1605         configure: Re-generate.
1606
1607         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1608         targets.
1609         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1610         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1611         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1612         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1613         SIM_@sim_gen@_*, set by autoconf.
1614
1615 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1616
1617         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1618
1619         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1620         CURRENT_FLOATING_POINT instead.
1621
1622         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1623         (address_translation): Raise exception InstructionFetch when
1624         translation fails and isINSTRUCTION.
1625
1626         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1627         sim_engine_run): Change type of of vaddr and paddr to
1628         address_word.
1629         (address_translation, prefetch, load_memory, store_memory,
1630         cache_op): Change type of vAddr and pAddr to address_word.
1631
1632         * gencode.c (build_instruction): Change type of vaddr and paddr to
1633         address_word.
1634
1635 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1636
1637         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1638         macro to obtain result of ALU op.
1639
1640 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1641
1642         * interp.c (sim_info): Call profile_print.
1643
1644 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1645
1646         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1647
1648         * sim-main.h (WITH_PROFILE): Do not define, defined in
1649         common/sim-config.h.  Use sim-profile module.
1650         (simPROFILE): Delete defintion.
1651
1652         * interp.c (PROFILE): Delete definition.
1653         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1654         (sim_close): Delete code writing profile histogram.
1655         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1656         Delete.
1657         (sim_engine_run): Delete code profiling the PC.
1658
1659 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1660
1661         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1662
1663         * interp.c (sim_monitor): Make register pointers of type
1664         unsigned_word*.
1665
1666         * sim-main.h: Make registers of type unsigned_word not
1667         signed_word.
1668
1669 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1670
1671         * interp.c (sync_operation): Rename from SyncOperation, make
1672         global, add SD argument.
1673         (prefetch): Rename from Prefetch, make global, add SD argument.
1674         (decode_coproc): Make global.
1675
1676         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1677
1678         * gencode.c (build_instruction): Generate DecodeCoproc not
1679         decode_coproc calls.
1680
1681         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1682         (SizeFGR): Move to sim-main.h
1683         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1684         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1685         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1686         sim-main.h.
1687         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1688         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1689         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1690         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1691         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1692         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1693
1694         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1695         exception.
1696         (sim-alu.h): Include.
1697         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1698         (sim_cia): Typedef to instruction_address.
1699
1700 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1701
1702         * Makefile.in (interp.o): Rename generated file engine.c to
1703         oengine.c.
1704
1705         * interp.c: Update.
1706
1707 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1708
1709         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1710
1711 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1712
1713         * gencode.c (build_instruction): For "FPSQRT", output correct
1714         number of arguments to Recip.
1715
1716 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1717
1718         * Makefile.in (interp.o): Depends on sim-main.h
1719
1720         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1721
1722         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1723         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1724         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1725         STATE, DSSTATE): Define
1726         (GPR, FGRIDX, ..): Define.
1727
1728         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1729         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1730         (GPR, FGRIDX, ...): Delete macros.
1731
1732         * interp.c: Update names to match defines from sim-main.h
1733
1734 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * interp.c (sim_monitor): Add SD argument.
1737         (sim_warning): Delete.  Replace calls with calls to
1738         sim_io_eprintf.
1739         (sim_error): Delete. Replace calls with sim_io_error.
1740         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1741         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1742         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1743         argument.
1744         (mips_size): Rename from sim_size. Add SD argument.
1745
1746         * interp.c (simulator): Delete global variable.
1747         (callback): Delete global variable.
1748         (mips_option_handler, sim_open, sim_write, sim_read,
1749         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1750         sim_size,sim_monitor): Use sim_io_* not callback->*.
1751         (sim_open): ZALLOC simulator struct.
1752         (PROFILE): Do not define.
1753
1754 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1755
1756         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1757         support.h with corresponding code.
1758
1759         * sim-main.h (word64, uword64), support.h: Move definition to
1760         sim-main.h.
1761         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1762
1763         * support.h: Delete
1764         * Makefile.in: Update dependencies
1765         * interp.c: Do not include.
1766
1767 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1768
1769         * interp.c (address_translation, load_memory, store_memory,
1770         cache_op): Rename to from AddressTranslation et.al., make global,
1771         add SD argument
1772
1773         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1774         CacheOp): Define.
1775
1776         * interp.c (SignalException): Rename to signal_exception, make
1777         global.
1778
1779         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1780
1781         * sim-main.h (SignalException, SignalExceptionInterrupt,
1782         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1783         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1784         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1785         Define.
1786
1787         * interp.c, support.h: Use.
1788
1789 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1790
1791         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1792         to value_fpr / store_fpr. Add SD argument.
1793         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1794         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1795
1796         * sim-main.h (ValueFPR, StoreFPR): Define.
1797
1798 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1799
1800         * interp.c (sim_engine_run): Check consistency between configure
1801         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1802         and HASFPU.
1803
1804         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1805         (mips_fpu): Configure WITH_FLOATING_POINT.
1806         (mips_endian): Configure WITH_TARGET_ENDIAN.
1807         * configure: Update.
1808
1809 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1810
1811         * configure: Regenerated to track ../common/aclocal.m4 changes.
1812
1813 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1814
1815         * configure: Regenerated.
1816
1817 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1818
1819         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1820
1821 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1822
1823         * gencode.c (print_igen_insn_models): Assume certain architectures
1824         include all mips* instructions.
1825         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1826         instruction.
1827
1828         * Makefile.in (tmp.igen): Add target. Generate igen input from
1829         gencode file.
1830
1831         * gencode.c (FEATURE_IGEN): Define.
1832         (main): Add --igen option.  Generate output in igen format.
1833         (process_instructions): Format output according to igen option.
1834         (print_igen_insn_format): New function.
1835         (print_igen_insn_models): New function.
1836         (process_instructions): Only issue warnings and ignore
1837         instructions when no FEATURE_IGEN.
1838
1839 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1840
1841         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1842         MIPS targets.
1843
1844 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1845
1846         * configure: Regenerated to track ../common/aclocal.m4 changes.
1847
1848 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1849
1850         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1851         SIM_RESERVED_BITS): Delete, moved to common.
1852         (SIM_EXTRA_CFLAGS): Update.
1853
1854 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1855
1856         * configure.in: Configure non-strict memory alignment.
1857         * configure: Regenerated to track ../common/aclocal.m4 changes.
1858
1859 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1860
1861         * configure: Regenerated to track ../common/aclocal.m4 changes.
1862
1863 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1864
1865         * gencode.c (SDBBP,DERET): Added (3900) insns.
1866         (RFE): Turn on for 3900.
1867         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1868         (dsstate): Made global.
1869         (SUBTARGET_R3900): Added.
1870         (CANCELDELAYSLOT): New.
1871         (SignalException): Ignore SystemCall rather than ignore and
1872         terminate.  Add DebugBreakPoint handling.
1873         (decode_coproc): New insns RFE, DERET; and new registers Debug
1874         and DEPC protected by SUBTARGET_R3900.
1875         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1876         bits explicitly.
1877         * Makefile.in,configure.in: Add mips subtarget option.
1878         * configure: Update.
1879
1880 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1881
1882         * gencode.c: Add r3900 (tx39).
1883
1884
1885 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1886
1887         * gencode.c (build_instruction): Don't need to subtract 4 for
1888         JALR, just 2.
1889
1890 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1891
1892         * interp.c: Correct some HASFPU problems.
1893
1894 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1895
1896         * configure: Regenerated to track ../common/aclocal.m4 changes.
1897
1898 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1899
1900         * interp.c (mips_options): Fix samples option short form, should
1901         be `x'.
1902
1903 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1904
1905         * interp.c (sim_info): Enable info code.  Was just returning.
1906
1907 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1908
1909         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1910         MFC0.
1911
1912 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1913
1914         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1915         constants.
1916         (build_instruction): Ditto for LL.
1917
1918 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1919
1920         * configure: Regenerated to track ../common/aclocal.m4 changes.
1921
1922 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1923
1924         * configure: Regenerated to track ../common/aclocal.m4 changes.
1925         * config.in: Ditto.
1926
1927 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1928
1929         * interp.c (sim_open): Add call to sim_analyze_program, update
1930         call to sim_config.
1931
1932 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * interp.c (sim_kill): Delete.
1935         (sim_create_inferior): Add ABFD argument. Set PC from same.
1936         (sim_load): Move code initializing trap handlers from here.
1937         (sim_open): To here.
1938         (sim_load): Delete, use sim-hload.c.
1939
1940         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1941
1942 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1943
1944         * configure: Regenerated to track ../common/aclocal.m4 changes.
1945         * config.in: Ditto.
1946
1947 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1948
1949         * interp.c (sim_open): Add ABFD argument.
1950         (sim_load): Move call to sim_config from here.
1951         (sim_open): To here.  Check return status.
1952
1953 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1954
1955         * gencode.c (build_instruction): Two arg MADD should
1956         not assign result to $0.
1957
1958 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1959
1960         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1961         * sim/mips/configure.in: Regenerate.
1962
1963 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1964
1965         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1966         signed8, unsigned8 et.al. types.
1967
1968         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1969         hosts when selecting subreg.
1970
1971 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1972
1973         * interp.c (sim_engine_run): Reset the ZERO register to zero
1974         regardless of FEATURE_WARN_ZERO.
1975         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1976
1977 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1978
1979         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1980         (SignalException): For BreakPoints ignore any mode bits and just
1981         save the PC.
1982         (SignalException): Always set the CAUSE register.
1983
1984 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1985
1986         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1987         exception has been taken.
1988
1989         * interp.c: Implement the ERET and mt/f sr instructions.
1990
1991 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1992
1993         * interp.c (SignalException): Don't bother restarting an
1994         interrupt.
1995
1996 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1997
1998         * interp.c (SignalException): Really take an interrupt.
1999         (interrupt_event): Only deliver interrupts when enabled.
2000
2001 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2002
2003         * interp.c (sim_info): Only print info when verbose.
2004         (sim_info) Use sim_io_printf for output.
2005
2006 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2007
2008         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2009         mips architectures.
2010
2011 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2012
2013         * interp.c (sim_do_command): Check for common commands if a
2014         simulator specific command fails.
2015
2016 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2017
2018         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2019         and simBE when DEBUG is defined.
2020
2021 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2022
2023         * interp.c (interrupt_event): New function.  Pass exception event
2024         onto exception handler.
2025
2026         * configure.in: Check for stdlib.h.
2027         * configure: Regenerate.
2028
2029         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2030         variable declaration.
2031         (build_instruction): Initialize memval1.
2032         (build_instruction): Add UNUSED attribute to byte, bigend,
2033         reverse.
2034         (build_operands): Ditto.
2035
2036         * interp.c: Fix GCC warnings.
2037         (sim_get_quit_code): Delete.
2038
2039         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2040         * Makefile.in: Ditto.
2041         * configure: Re-generate.
2042
2043         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2044
2045 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2046
2047         * interp.c (mips_option_handler): New function parse argumes using
2048         sim-options.
2049         (myname): Replace with STATE_MY_NAME.
2050         (sim_open): Delete check for host endianness - performed by
2051         sim_config.
2052         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2053         (sim_open): Move much of the initialization from here.
2054         (sim_load): To here.  After the image has been loaded and
2055         endianness set.
2056         (sim_open): Move ColdReset from here.
2057         (sim_create_inferior): To here.
2058         (sim_open): Make FP check less dependant on host endianness.
2059
2060         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2061         run.
2062         * interp.c (sim_set_callbacks): Delete.
2063
2064         * interp.c (membank, membank_base, membank_size): Replace with
2065         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2066         (sim_open): Remove call to callback->init. gdb/run do this.
2067
2068         * interp.c: Update
2069
2070         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2071
2072         * interp.c (big_endian_p): Delete, replaced by
2073         current_target_byte_order.
2074
2075 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2076
2077         * interp.c (host_read_long, host_read_word, host_swap_word,
2078         host_swap_long): Delete. Using common sim-endian.
2079         (sim_fetch_register, sim_store_register): Use H2T.
2080         (pipeline_ticks): Delete.  Handled by sim-events.
2081         (sim_info): Update.
2082         (sim_engine_run): Update.
2083
2084 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2085
2086         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2087         reason from here.
2088         (SignalException): To here. Signal using sim_engine_halt.
2089         (sim_stop_reason): Delete, moved to common.
2090
2091 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2092
2093         * interp.c (sim_open): Add callback argument.
2094         (sim_set_callbacks): Delete SIM_DESC argument.
2095         (sim_size): Ditto.
2096
2097 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2098
2099         * Makefile.in (SIM_OBJS): Add common modules.
2100
2101         * interp.c (sim_set_callbacks): Also set SD callback.
2102         (set_endianness, xfer_*, swap_*): Delete.
2103         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2104         Change to functions using sim-endian macros.
2105         (control_c, sim_stop): Delete, use common version.
2106         (simulate): Convert into.
2107         (sim_engine_run): This function.
2108         (sim_resume): Delete.
2109
2110         * interp.c (simulation): New variable - the simulator object.
2111         (sim_kind): Delete global - merged into simulation.
2112         (sim_load): Cleanup.  Move PC assignment from here.
2113         (sim_create_inferior): To here.
2114
2115         * sim-main.h: New file.
2116         * interp.c (sim-main.h): Include.
2117
2118 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2119
2120         * configure: Regenerated to track ../common/aclocal.m4 changes.
2121
2122 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2123
2124         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2125
2126 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2127
2128         * gencode.c (build_instruction): DIV instructions: check
2129         for division by zero and integer overflow before using
2130         host's division operation.
2131
2132 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2133
2134         * Makefile.in (SIM_OBJS): Add sim-load.o.
2135         * interp.c: #include bfd.h.
2136         (target_byte_order): Delete.
2137         (sim_kind, myname, big_endian_p): New static locals.
2138         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2139         after argument parsing.  Recognize -E arg, set endianness accordingly.
2140         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2141         load file into simulator.  Set PC from bfd.
2142         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2143         (set_endianness): Use big_endian_p instead of target_byte_order.
2144
2145 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2146
2147         * interp.c (sim_size): Delete prototype - conflicts with
2148         definition in remote-sim.h.  Correct definition.
2149
2150 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2151
2152         * configure: Regenerated to track ../common/aclocal.m4 changes.
2153         * config.in: Ditto.
2154
2155 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2156
2157         * interp.c (sim_open): New arg `kind'.
2158
2159         * configure: Regenerated to track ../common/aclocal.m4 changes.
2160
2161 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2162
2163         * configure: Regenerated to track ../common/aclocal.m4 changes.
2164
2165 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2166
2167         * interp.c (sim_open): Set optind to 0 before calling getopt.
2168
2169 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2170
2171         * configure: Regenerated to track ../common/aclocal.m4 changes.
2172
2173 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2174
2175         * interp.c : Replace uses of pr_addr with pr_uword64
2176         where the bit length is always 64 independent of SIM_ADDR.
2177         (pr_uword64) : added.
2178
2179 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2180
2181         * configure: Re-generate.
2182
2183 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2184
2185         * configure: Regenerate to track ../common/aclocal.m4 changes.
2186
2187 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2188
2189         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2190         in argv form.
2191         (other sim_*): New SIM_DESC argument.
2192
2193 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2194
2195         * interp.c: Fix printing of addresses for non-64-bit targets.
2196         (pr_addr): Add function to print address based on size.
2197
2198 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2199
2200         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2201
2202 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2203
2204         * gencode.c (build_mips16_operands): Correct computation of base
2205         address for extended PC relative instruction.
2206
2207 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2208
2209         * interp.c (mips16_entry): Add support for floating point cases.
2210         (SignalException): Pass floating point cases to mips16_entry.
2211         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2212         registers.
2213         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2214         or fmt_word.
2215         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2216         and then set the state to fmt_uninterpreted.
2217         (COP_SW): Temporarily set the state to fmt_word while calling
2218         ValueFPR.
2219
2220 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2221
2222         * gencode.c (build_instruction): The high order may be set in the
2223         comparison flags at any ISA level, not just ISA 4.
2224
2225 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2226
2227         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2228         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2229         * configure.in: sinclude ../common/aclocal.m4.
2230         * configure: Regenerated.
2231
2232 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2233
2234         * configure: Rebuild after change to aclocal.m4.
2235
2236 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2237
2238         * configure configure.in Makefile.in:  Update to new configure
2239         scheme which is more compatible with WinGDB builds.
2240         * configure.in:  Improve comment on how to run autoconf.
2241         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2242         * Makefile.in:  Use autoconf substitution to install common
2243         makefile fragment.
2244
2245 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2246
2247         * gencode.c (build_instruction): Use BigEndianCPU instead of
2248         ByteSwapMem.
2249
2250 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2251
2252         * interp.c (sim_monitor): Make output to stdout visible in
2253         wingdb's I/O log window.
2254
2255 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2256
2257         * support.h: Undo previous change to SIGTRAP
2258         and SIGQUIT values.
2259
2260 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2261
2262         * interp.c (store_word, load_word): New static functions.
2263         (mips16_entry): New static function.
2264         (SignalException): Look for mips16 entry and exit instructions.
2265         (simulate): Use the correct index when setting fpr_state after
2266         doing a pending move.
2267
2268 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2269
2270         * interp.c: Fix byte-swapping code throughout to work on
2271         both little- and big-endian hosts.
2272
2273 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2274
2275         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2276         with gdb/config/i386/xm-windows.h.
2277
2278 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2279
2280         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2281         that messes up arithmetic shifts.
2282
2283 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2284
2285         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2286         SIGTRAP and SIGQUIT for _WIN32.
2287
2288 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2289
2290         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2291         force a 64 bit multiplication.
2292         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2293         destination register is 0, since that is the default mips16 nop
2294         instruction.
2295
2296 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2297
2298         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2299         (build_endian_shift): Don't check proc64.
2300         (build_instruction): Always set memval to uword64.  Cast op2 to
2301         uword64 when shifting it left in memory instructions.  Always use
2302         the same code for stores--don't special case proc64.
2303
2304         * gencode.c (build_mips16_operands): Fix base PC value for PC
2305         relative operands.
2306         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2307         jal instruction.
2308         * interp.c (simJALDELAYSLOT): Define.
2309         (JALDELAYSLOT): Define.
2310         (INDELAYSLOT, INJALDELAYSLOT): Define.
2311         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2312
2313 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2314
2315         * interp.c (sim_open): add flush_cache as a PMON routine
2316         (sim_monitor): handle flush_cache by ignoring it
2317
2318 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2319
2320         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2321         BigEndianMem.
2322         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2323         (BigEndianMem): Rename to ByteSwapMem and change sense.
2324         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2325         BigEndianMem references to !ByteSwapMem.
2326         (set_endianness): New function, with prototype.
2327         (sim_open): Call set_endianness.
2328         (sim_info): Use simBE instead of BigEndianMem.
2329         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2330         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2331         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2332         ifdefs, keeping the prototype declaration.
2333         (swap_word): Rewrite correctly.
2334         (ColdReset): Delete references to CONFIG.  Delete endianness related
2335         code; moved to set_endianness.
2336
2337 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2338
2339         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2340         * interp.c (CHECKHILO): Define away.
2341         (simSIGINT): New macro.
2342         (membank_size): Increase from 1MB to 2MB.
2343         (control_c): New function.
2344         (sim_resume): Rename parameter signal to signal_number.  Add local
2345         variable prev.  Call signal before and after simulate.
2346         (sim_stop_reason): Add simSIGINT support.
2347         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2348         functions always.
2349         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2350         if logfh is NULL.
2351         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2352         a call to sim_warning.
2353
2354 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2355
2356         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2357         16 bit instructions.
2358
2359 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2360
2361         Add support for mips16 (16 bit MIPS implementation):
2362         * gencode.c (inst_type): Add mips16 instruction encoding types.
2363         (GETDATASIZEINSN): Define.
2364         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2365         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2366         mtlo.
2367         (MIPS16_DECODE): New table, for mips16 instructions.
2368         (bitmap_val): New static function.
2369         (struct mips16_op): Define.
2370         (mips16_op_table): New table, for mips16 operands.
2371         (build_mips16_operands): New static function.
2372         (process_instructions): If PC is odd, decode a mips16
2373         instruction.  Break out instruction handling into new
2374         build_instruction function.
2375         (build_instruction): New static function, broken out of
2376         process_instructions.  Check modifiers rather than flags for SHIFT
2377         bit count and m[ft]{hi,lo} direction.
2378         (usage): Pass program name to fprintf.
2379         (main): Remove unused variable this_option_optind.  Change
2380         ``*loptarg++'' to ``loptarg++''.
2381         (my_strtoul): Parenthesize && within ||.
2382         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2383         (simulate): If PC is odd, fetch a 16 bit instruction, and
2384         increment PC by 2 rather than 4.
2385         * configure.in: Add case for mips16*-*-*.
2386         * configure: Rebuild.
2387
2388 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2389
2390         * interp.c: Allow -t to enable tracing in standalone simulator.
2391         Fix garbage output in trace file and error messages.
2392
2393 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2394
2395         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2396         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2397         * configure.in: Simplify using macros in ../common/aclocal.m4.
2398         * configure: Regenerated.
2399         * tconfig.in: New file.
2400
2401 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2402
2403         * interp.c: Fix bugs in 64-bit port.
2404         Use ansi function declarations for msvc compiler.
2405         Initialize and test file pointer in trace code.
2406         Prevent duplicate definition of LAST_EMED_REGNUM.
2407
2408 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2409
2410         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2411
2412 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2413
2414         * interp.c (SignalException): Check for explicit terminating
2415         breakpoint value.
2416         * gencode.c: Pass instruction value through SignalException()
2417         calls for Trap, Breakpoint and Syscall.
2418
2419 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2420
2421         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2422         only used on those hosts that provide it.
2423         * configure.in: Add sqrt() to list of functions to be checked for.
2424         * config.in: Re-generated.
2425         * configure: Re-generated.
2426
2427 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2428
2429         * gencode.c (process_instructions): Call build_endian_shift when
2430         expanding STORE RIGHT, to fix swr.
2431         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2432         clear the high bits.
2433         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2434         Fix float to int conversions to produce signed values.
2435
2436 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2437
2438         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2439         (process_instructions): Correct handling of nor instruction.
2440         Correct shift count for 32 bit shift instructions. Correct sign
2441         extension for arithmetic shifts to not shift the number of bits in
2442         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2443         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2444         Fix madd.
2445         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2446         It's OK to have a mult follow a mult.  What's not OK is to have a
2447         mult follow an mfhi.
2448         (Convert): Comment out incorrect rounding code.
2449
2450 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2451
2452         * interp.c (sim_monitor): Improved monitor printf
2453         simulation. Tidied up simulator warnings, and added "--log" option
2454         for directing warning message output.
2455         * gencode.c: Use sim_warning() rather than WARNING macro.
2456
2457 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2458
2459         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2460         getopt1.o, rather than on gencode.c.  Link objects together.
2461         Don't link against -liberty.
2462         (gencode.o, getopt.o, getopt1.o): New targets.
2463         * gencode.c: Include <ctype.h> and "ansidecl.h".
2464         (AND): Undefine after including "ansidecl.h".
2465         (ULONG_MAX): Define if not defined.
2466         (OP_*): Don't define macros; now defined in opcode/mips.h.
2467         (main): Call my_strtoul rather than strtoul.
2468         (my_strtoul): New static function.
2469
2470 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2471
2472         * gencode.c (process_instructions):  Generate word64 and uword64
2473         instead of `long long' and `unsigned long long' data types.
2474         * interp.c:  #include sysdep.h to get signals, and define default
2475         for SIGBUS.
2476         * (Convert):  Work around for Visual-C++ compiler bug with type
2477         conversion.
2478         * support.h:  Make things compile under Visual-C++ by using
2479         __int64 instead of `long long'.  Change many refs to long long
2480         into word64/uword64 typedefs.
2481
2482 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2483
2484         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2485         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2486         (docdir): Removed.
2487         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2488         (AC_PROG_INSTALL): Added.
2489         (AC_PROG_CC): Moved to before configure.host call.
2490         * configure: Rebuilt.
2491
2492 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2493
2494         * configure.in: Define @SIMCONF@ depending on mips target.
2495         * configure: Rebuild.
2496         * Makefile.in (run): Add @SIMCONF@ to control simulator
2497         construction.
2498         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2499         * interp.c: Remove some debugging, provide more detailed error
2500         messages, update memory accesses to use LOADDRMASK.
2501
2502 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2503
2504         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2505         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2506         stamp-h.
2507         * configure: Rebuild.
2508         * config.in: New file, generated by autoheader.
2509         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2510         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2511         HAVE_ANINT and HAVE_AINT, as appropriate.
2512         * Makefile.in (run): Use @LIBS@ rather than -lm.
2513         (interp.o): Depend upon config.h.
2514         (Makefile): Just rebuild Makefile.
2515         (clean): Remove stamp-h.
2516         (mostlyclean): Make the same as clean, not as distclean.
2517         (config.h, stamp-h): New targets.
2518
2519 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2520
2521         * interp.c (ColdReset): Fix boolean test. Make all simulator
2522         globals static.
2523
2524 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2525
2526         * interp.c (xfer_direct_word, xfer_direct_long,
2527         swap_direct_word, swap_direct_long, xfer_big_word,
2528         xfer_big_long, xfer_little_word, xfer_little_long,
2529         swap_word,swap_long): Added.
2530         * interp.c (ColdReset): Provide function indirection to
2531         host<->simulated_target transfer routines.
2532         * interp.c (sim_store_register, sim_fetch_register): Updated to
2533         make use of indirected transfer routines.
2534
2535 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2536
2537         * gencode.c (process_instructions): Ensure FP ABS instruction
2538         recognised.
2539         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2540         system call support.
2541
2542 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2543
2544         * interp.c (sim_do_command): Complain if callback structure not
2545         initialised.
2546
2547 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2548
2549         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2550         support for Sun hosts.
2551         * Makefile.in (gencode): Ensure the host compiler and libraries
2552         used for cross-hosted build.
2553
2554 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2555
2556         * interp.c, gencode.c: Some more (TODO) tidying.
2557
2558 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2559
2560         * gencode.c, interp.c: Replaced explicit long long references with
2561         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2562         * support.h (SET64LO, SET64HI): Macros added.
2563
2564 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2565
2566         * configure: Regenerate with autoconf 2.7.
2567
2568 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2569
2570         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2571         * support.h: Remove superfluous "1" from #if.
2572         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2573
2574 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2575
2576         * interp.c (StoreFPR): Control UndefinedResult() call on
2577         WARN_RESULT manifest.
2578
2579 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2580
2581         * gencode.c: Tidied instruction decoding, and added FP instruction
2582         support.
2583
2584         * interp.c: Added dineroIII, and BSD profiling support. Also
2585         run-time FP handling.
2586
2587 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2588
2589         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2590         gencode.c, interp.c, support.h: created.