1 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
3 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
4 that unconditionally allows fmt_ps.
5 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
6 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
7 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
8 filter from 64,f to 32,f.
9 (PREFX): Change filter from 64 to 32.
10 (LDXC1, LUXC1): Provide separate mips32r2 implementations
11 that use do_load_double instead of do_load. Make both LUXC1
12 versions unpredictable if SizeFGR () != 64.
13 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
14 instead of do_store. Remove unused variable. Make both SUXC1
15 versions unpredictable if SizeFGR () != 64.
17 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
19 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
20 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
23 2007-09-04 Nick Clifton <nickc@redhat.com>
25 * interp.c (options enum): Add OPTION_INFO_MEMORY.
26 (display_mem_info): New static variable.
27 (mips_option_handler): Handle OPTION_INFO_MEMORY.
28 (mips_options): Add info-memory and memory-info.
29 (sim_open): After processing the command line and board
30 specification, check display_mem_info. If it is set then
31 call the real handler for the --memory-info command line
34 2007-08-24 Joel Brobecker <brobecker@adacore.com>
36 * configure.ac: Change license of multi-run.c to GPL version 3.
37 * configure: Regenerate.
39 2007-06-28 Richard Sandiford <richard@codesourcery.com>
41 * configure.ac, configure: Revert last patch.
43 2007-06-26 Richard Sandiford <richard@codesourcery.com>
45 * configure.ac (sim_mipsisa3264_configs): New variable.
46 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
47 every configuration support all four targets, using the triplet to
48 determine the default.
49 * configure: Regenerate.
51 2007-06-25 Richard Sandiford <richard@codesourcery.com>
53 * Makefile.in (m16run.o): New rule.
55 2007-05-15 Thiemo Seufer <ths@mips.com>
57 * mips3264r2.igen (DSHD): Fix compile warning.
59 2007-05-14 Thiemo Seufer <ths@mips.com>
61 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
62 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
63 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
64 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
67 2007-03-01 Thiemo Seufer <ths@mips.com>
69 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
72 2007-02-20 Thiemo Seufer <ths@mips.com>
74 * dsp.igen: Update copyright notice.
75 * dsp2.igen: Fix copyright notice.
77 2007-02-20 Thiemo Seufer <ths@mips.com>
78 Chao-Ying Fu <fu@mips.com>
80 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
81 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
82 Add dsp2 to sim_igen_machine.
83 * configure: Regenerate.
84 * dsp.igen (do_ph_op): Add MUL support when op = 2.
85 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
86 (mulq_rs.ph): Use do_ph_mulq.
87 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
88 * mips.igen: Add dsp2 model and include dsp2.igen.
89 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
90 for *mips32r2, *mips64r2, *dsp.
91 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
92 for *mips32r2, *mips64r2, *dsp2.
93 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
95 2007-02-19 Thiemo Seufer <ths@mips.com>
96 Nigel Stephens <nigel@mips.com>
98 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
99 jumps with hazard barrier.
101 2007-02-19 Thiemo Seufer <ths@mips.com>
102 Nigel Stephens <nigel@mips.com>
104 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
105 after each call to sim_io_write.
107 2007-02-19 Thiemo Seufer <ths@mips.com>
108 Nigel Stephens <nigel@mips.com>
110 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
111 supported by this simulator.
112 (decode_coproc): Recognise additional CP0 Config registers
115 2007-02-19 Thiemo Seufer <ths@mips.com>
116 Nigel Stephens <nigel@mips.com>
117 David Ung <davidu@mips.com>
119 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
120 uninterpreted formats. If fmt is one of the uninterpreted types
121 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
122 fmt_word, and fmt_uninterpreted_64 like fmt_long.
123 (store_fpr): When writing an invalid odd register, set the
124 matching even register to fmt_unknown, not the following register.
125 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
126 the the memory window at offset 0 set by --memory-size command
128 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
130 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
132 (sim_monitor): When returning the memory size to the MIPS
133 application, use the value in STATE_MEM_SIZE, not an arbitrary
135 (cop_lw): Don' mess around with FPR_STATE, just pass
136 fmt_uninterpreted_32 to StoreFPR.
138 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
140 * mips.igen (not_word_value): Single version for mips32, mips64
143 2007-02-19 Thiemo Seufer <ths@mips.com>
144 Nigel Stephens <nigel@mips.com>
146 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
149 2007-02-17 Thiemo Seufer <ths@mips.com>
151 * configure.ac (mips*-sde-elf*): Move in front of generic machine
153 * configure: Regenerate.
155 2007-02-17 Thiemo Seufer <ths@mips.com>
157 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
158 Add mdmx to sim_igen_machine.
159 (mipsisa64*-*-*): Likewise. Remove dsp.
160 (mipsisa32*-*-*): Remove dsp.
161 * configure: Regenerate.
163 2007-02-13 Thiemo Seufer <ths@mips.com>
165 * configure.ac: Add mips*-sde-elf* target.
166 * configure: Regenerate.
168 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
170 * acconfig.h: Remove.
171 * config.in, configure: Regenerate.
173 2006-11-07 Thiemo Seufer <ths@mips.com>
175 * dsp.igen (do_w_op): Fix compiler warning.
177 2006-08-29 Thiemo Seufer <ths@mips.com>
178 David Ung <davidu@mips.com>
180 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
182 * configure: Regenerate.
183 * mips.igen (model): Add smartmips.
184 (MADDU): Increment ACX if carry.
185 (do_mult): Clear ACX.
186 (ROR,RORV): Add smartmips.
187 (include): Include smartmips.igen.
188 * sim-main.h (ACX): Set to REGISTERS[89].
189 * smartmips.igen: New file.
191 2006-08-29 Thiemo Seufer <ths@mips.com>
192 David Ung <davidu@mips.com>
194 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
195 mips3264r2.igen. Add missing dependency rules.
196 * m16e.igen: Support for mips16e save/restore instructions.
198 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
200 * configure: Regenerated.
202 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
204 * configure: Regenerated.
206 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
208 * configure: Regenerated.
210 2006-05-15 Chao-ying Fu <fu@mips.com>
212 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
214 2006-04-18 Nick Clifton <nickc@redhat.com>
216 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
219 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
221 * configure: Regenerate.
223 2005-12-14 Chao-ying Fu <fu@mips.com>
225 * Makefile.in (SIM_OBJS): Add dsp.o.
226 (dsp.o): New dependency.
227 (IGEN_INCLUDE): Add dsp.igen.
228 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
229 mipsisa64*-*-*): Add dsp to sim_igen_machine.
230 * configure: Regenerate.
231 * mips.igen: Add dsp model and include dsp.igen.
232 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
233 because these instructions are extended in DSP ASE.
234 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
235 adding 6 DSP accumulator registers and 1 DSP control register.
236 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
237 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
238 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
239 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
240 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
241 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
242 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
243 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
244 DSPCR_CCOND_SMASK): New define.
245 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
246 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
248 2005-07-08 Ian Lance Taylor <ian@airs.com>
250 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
252 2005-06-16 David Ung <davidu@mips.com>
253 Nigel Stephens <nigel@mips.com>
255 * mips.igen: New mips16e model and include m16e.igen.
256 (check_u64): Add mips16e tag.
257 * m16e.igen: New file for MIPS16e instructions.
258 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
259 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
261 * configure: Regenerate.
263 2005-05-26 David Ung <davidu@mips.com>
265 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
266 tags to all instructions which are applicable to the new ISAs.
267 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
269 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
271 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
273 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
274 * configure: Regenerate.
276 2005-03-23 Mark Kettenis <kettenis@gnu.org>
278 * configure: Regenerate.
280 2005-01-14 Andrew Cagney <cagney@gnu.org>
282 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
283 explicit call to AC_CONFIG_HEADER.
284 * configure: Regenerate.
286 2005-01-12 Andrew Cagney <cagney@gnu.org>
288 * configure.ac: Update to use ../common/common.m4.
289 * configure: Re-generate.
291 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
293 * configure: Regenerated to track ../common/aclocal.m4 changes.
295 2005-01-07 Andrew Cagney <cagney@gnu.org>
297 * configure.ac: Rename configure.in, require autoconf 2.59.
298 * configure: Re-generate.
300 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
302 * configure: Regenerate for ../common/aclocal.m4 update.
304 2004-09-24 Monika Chaddha <monika@acmet.com>
306 Committed by Andrew Cagney.
307 * m16.igen (CMP, CMPI): Fix assembler.
309 2004-08-18 Chris Demetriou <cgd@broadcom.com>
311 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
312 * configure: Regenerate.
314 2004-06-25 Chris Demetriou <cgd@broadcom.com>
316 * configure.in (sim_m16_machine): Include mipsIII.
317 * configure: Regenerate.
319 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
321 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
323 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
325 2004-04-10 Chris Demetriou <cgd@broadcom.com>
327 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
329 2004-04-09 Chris Demetriou <cgd@broadcom.com>
331 * mips.igen (check_fmt): Remove.
332 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
333 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
334 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
335 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
336 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
337 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
338 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
339 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
340 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
341 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
343 2004-04-09 Chris Demetriou <cgd@broadcom.com>
345 * sb1.igen (check_sbx): New function.
346 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
348 2004-03-29 Chris Demetriou <cgd@broadcom.com>
349 Richard Sandiford <rsandifo@redhat.com>
351 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
352 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
353 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
354 separate implementations for mipsIV and mipsV. Use new macros to
355 determine whether the restrictions apply.
357 2004-01-19 Chris Demetriou <cgd@broadcom.com>
359 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
360 (check_mult_hilo): Improve comments.
361 (check_div_hilo): Likewise. Also, fork off a new version
362 to handle mips32/mips64 (since there are no hazards to check
365 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
367 * mips.igen (do_dmultx): Fix check for negative operands.
369 2003-05-16 Ian Lance Taylor <ian@airs.com>
371 * Makefile.in (SHELL): Make sure this is defined.
372 (various): Use $(SHELL) whenever we invoke move-if-change.
374 2003-05-03 Chris Demetriou <cgd@broadcom.com>
376 * cp1.c: Tweak attribution slightly.
379 * mdmx.igen: Likewise.
380 * mips3d.igen: Likewise.
381 * sb1.igen: Likewise.
383 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
385 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
388 2003-02-27 Andrew Cagney <cagney@redhat.com>
390 * interp.c (sim_open): Rename _bfd to bfd.
391 (sim_create_inferior): Ditto.
393 2003-01-14 Chris Demetriou <cgd@broadcom.com>
395 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
397 2003-01-14 Chris Demetriou <cgd@broadcom.com>
399 * mips.igen (EI, DI): Remove.
401 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
403 * Makefile.in (tmp-run-multi): Fix mips16 filter.
405 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
406 Andrew Cagney <ac131313@redhat.com>
407 Gavin Romig-Koch <gavin@redhat.com>
408 Graydon Hoare <graydon@redhat.com>
409 Aldy Hernandez <aldyh@redhat.com>
410 Dave Brolley <brolley@redhat.com>
411 Chris Demetriou <cgd@broadcom.com>
413 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
414 (sim_mach_default): New variable.
415 (mips64vr-*-*, mips64vrel-*-*): New configurations.
416 Add a new simulator generator, MULTI.
417 * configure: Regenerate.
418 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
419 (multi-run.o): New dependency.
420 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
421 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
422 (tmp-multi): Combine them.
423 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
424 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
425 (distclean-extra): New rule.
426 * sim-main.h: Include bfd.h.
427 (MIPS_MACH): New macro.
428 * mips.igen (vr4120, vr5400, vr5500): New models.
429 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
430 * vr.igen: Replace with new version.
432 2003-01-04 Chris Demetriou <cgd@broadcom.com>
434 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
435 * configure: Regenerate.
437 2002-12-31 Chris Demetriou <cgd@broadcom.com>
439 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
440 * mips.igen: Remove all invocations of check_branch_bug and
443 2002-12-16 Chris Demetriou <cgd@broadcom.com>
445 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
447 2002-07-30 Chris Demetriou <cgd@broadcom.com>
449 * mips.igen (do_load_double, do_store_double): New functions.
450 (LDC1, SDC1): Rename to...
451 (LDC1b, SDC1b): respectively.
452 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
454 2002-07-29 Michael Snyder <msnyder@redhat.com>
456 * cp1.c (fp_recip2): Modify initialization expression so that
457 GCC will recognize it as constant.
459 2002-06-18 Chris Demetriou <cgd@broadcom.com>
461 * mdmx.c (SD_): Delete.
462 (Unpredictable): Re-define, for now, to directly invoke
463 unpredictable_action().
464 (mdmx_acc_op): Fix error in .ob immediate handling.
466 2002-06-18 Andrew Cagney <cagney@redhat.com>
468 * interp.c (sim_firmware_command): Initialize `address'.
470 2002-06-16 Andrew Cagney <ac131313@redhat.com>
472 * configure: Regenerated to track ../common/aclocal.m4 changes.
474 2002-06-14 Chris Demetriou <cgd@broadcom.com>
475 Ed Satterthwaite <ehs@broadcom.com>
477 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
478 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
479 * mips.igen: Include mips3d.igen.
480 (mips3d): New model name for MIPS-3D ASE instructions.
481 (CVT.W.fmt): Don't use this instruction for word (source) format
483 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
484 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
485 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
486 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
487 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
488 (RSquareRoot1, RSquareRoot2): New macros.
489 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
490 (fp_rsqrt2): New functions.
491 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
492 * configure: Regenerate.
494 2002-06-13 Chris Demetriou <cgd@broadcom.com>
495 Ed Satterthwaite <ehs@broadcom.com>
497 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
498 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
499 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
500 (convert): Note that this function is not used for paired-single
502 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
503 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
504 (check_fmt_p): Enable paired-single support.
505 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
506 (PUU.PS): New instructions.
507 (CVT.S.fmt): Don't use this instruction for paired-single format
509 * sim-main.h (FP_formats): New value 'fmt_ps.'
510 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
511 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
513 2002-06-12 Chris Demetriou <cgd@broadcom.com>
515 * mips.igen: Fix formatting of function calls in
518 2002-06-12 Chris Demetriou <cgd@broadcom.com>
520 * mips.igen (MOVN, MOVZ): Trace result.
521 (TNEI): Print "tnei" as the opcode name in traces.
522 (CEIL.W): Add disassembly string for traces.
523 (RSQRT.fmt): Make location of disassembly string consistent
524 with other instructions.
526 2002-06-12 Chris Demetriou <cgd@broadcom.com>
528 * mips.igen (X): Delete unused function.
530 2002-06-08 Andrew Cagney <cagney@redhat.com>
532 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
534 2002-06-07 Chris Demetriou <cgd@broadcom.com>
535 Ed Satterthwaite <ehs@broadcom.com>
537 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
538 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
539 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
540 (fp_nmsub): New prototypes.
541 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
542 (NegMultiplySub): New defines.
543 * mips.igen (RSQRT.fmt): Use RSquareRoot().
544 (MADD.D, MADD.S): Replace with...
545 (MADD.fmt): New instruction.
546 (MSUB.D, MSUB.S): Replace with...
547 (MSUB.fmt): New instruction.
548 (NMADD.D, NMADD.S): Replace with...
549 (NMADD.fmt): New instruction.
550 (NMSUB.D, MSUB.S): Replace with...
551 (NMSUB.fmt): New instruction.
553 2002-06-07 Chris Demetriou <cgd@broadcom.com>
554 Ed Satterthwaite <ehs@broadcom.com>
556 * cp1.c: Fix more comment spelling and formatting.
557 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
558 (denorm_mode): New function.
559 (fpu_unary, fpu_binary): Round results after operation, collect
560 status from rounding operations, and update the FCSR.
561 (convert): Collect status from integer conversions and rounding
562 operations, and update the FCSR. Adjust NaN values that result
563 from conversions. Convert to use sim_io_eprintf rather than
564 fprintf, and remove some debugging code.
565 * cp1.h (fenr_FS): New define.
567 2002-06-07 Chris Demetriou <cgd@broadcom.com>
569 * cp1.c (convert): Remove unusable debugging code, and move MIPS
570 rounding mode to sim FP rounding mode flag conversion code into...
571 (rounding_mode): New function.
573 2002-06-07 Chris Demetriou <cgd@broadcom.com>
575 * cp1.c: Clean up formatting of a few comments.
576 (value_fpr): Reformat switch statement.
578 2002-06-06 Chris Demetriou <cgd@broadcom.com>
579 Ed Satterthwaite <ehs@broadcom.com>
582 * sim-main.h: Include cp1.h.
583 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
584 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
585 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
586 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
587 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
588 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
589 * cp1.c: Don't include sim-fpu.h; already included by
590 sim-main.h. Clean up formatting of some comments.
591 (NaN, Equal, Less): Remove.
592 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
593 (fp_cmp): New functions.
594 * mips.igen (do_c_cond_fmt): Remove.
595 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
596 Compare. Add result tracing.
597 (CxC1): Remove, replace with...
598 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
599 (DMxC1): Remove, replace with...
600 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
601 (MxC1): Remove, replace with...
602 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
604 2002-06-04 Chris Demetriou <cgd@broadcom.com>
606 * sim-main.h (FGRIDX): Remove, replace all uses with...
607 (FGR_BASE): New macro.
608 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
609 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
610 (NR_FGR, FGR): Likewise.
611 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
612 * mips.igen: Likewise.
614 2002-06-04 Chris Demetriou <cgd@broadcom.com>
616 * cp1.c: Add an FSF Copyright notice to this file.
618 2002-06-04 Chris Demetriou <cgd@broadcom.com>
619 Ed Satterthwaite <ehs@broadcom.com>
621 * cp1.c (Infinity): Remove.
622 * sim-main.h (Infinity): Likewise.
624 * cp1.c (fp_unary, fp_binary): New functions.
625 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
626 (fp_sqrt): New functions, implemented in terms of the above.
627 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
628 (Recip, SquareRoot): Remove (replaced by functions above).
629 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
630 (fp_recip, fp_sqrt): New prototypes.
631 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
632 (Recip, SquareRoot): Replace prototypes with #defines which
633 invoke the functions above.
635 2002-06-03 Chris Demetriou <cgd@broadcom.com>
637 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
638 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
639 file, remove PARAMS from prototypes.
640 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
641 simulator state arguments.
642 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
643 pass simulator state arguments.
644 * cp1.c (SD): Redefine as CPU_STATE(cpu).
645 (store_fpr, convert): Remove 'sd' argument.
646 (value_fpr): Likewise. Convert to use 'SD' instead.
648 2002-06-03 Chris Demetriou <cgd@broadcom.com>
650 * cp1.c (Min, Max): Remove #if 0'd functions.
651 * sim-main.h (Min, Max): Remove.
653 2002-06-03 Chris Demetriou <cgd@broadcom.com>
655 * cp1.c: fix formatting of switch case and default labels.
656 * interp.c: Likewise.
657 * sim-main.c: Likewise.
659 2002-06-03 Chris Demetriou <cgd@broadcom.com>
661 * cp1.c: Clean up comments which describe FP formats.
662 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
664 2002-06-03 Chris Demetriou <cgd@broadcom.com>
665 Ed Satterthwaite <ehs@broadcom.com>
667 * configure.in (mipsisa64sb1*-*-*): New target for supporting
668 Broadcom SiByte SB-1 processor configurations.
669 * configure: Regenerate.
670 * sb1.igen: New file.
671 * mips.igen: Include sb1.igen.
673 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
674 * mdmx.igen: Add "sb1" model to all appropriate functions and
676 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
677 (ob_func, ob_acc): Reference the above.
678 (qh_acc): Adjust to keep the same size as ob_acc.
679 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
680 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
682 2002-06-03 Chris Demetriou <cgd@broadcom.com>
684 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
686 2002-06-02 Chris Demetriou <cgd@broadcom.com>
687 Ed Satterthwaite <ehs@broadcom.com>
689 * mips.igen (mdmx): New (pseudo-)model.
690 * mdmx.c, mdmx.igen: New files.
691 * Makefile.in (SIM_OBJS): Add mdmx.o.
692 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
694 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
695 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
696 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
697 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
698 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
699 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
700 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
701 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
702 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
703 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
704 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
705 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
706 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
707 (qh_fmtsel): New macros.
708 (_sim_cpu): New member "acc".
709 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
710 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
712 2002-05-01 Chris Demetriou <cgd@broadcom.com>
714 * interp.c: Use 'deprecated' rather than 'depreciated.'
715 * sim-main.h: Likewise.
717 2002-05-01 Chris Demetriou <cgd@broadcom.com>
719 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
720 which wouldn't compile anyway.
721 * sim-main.h (unpredictable_action): New function prototype.
722 (Unpredictable): Define to call igen function unpredictable().
723 (NotWordValue): New macro to call igen function not_word_value().
724 (UndefinedResult): Remove.
725 * interp.c (undefined_result): Remove.
726 (unpredictable_action): New function.
727 * mips.igen (not_word_value, unpredictable): New functions.
728 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
729 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
730 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
731 NotWordValue() to check for unpredictable inputs, then
732 Unpredictable() to handle them.
734 2002-02-24 Chris Demetriou <cgd@broadcom.com>
736 * mips.igen: Fix formatting of calls to Unpredictable().
738 2002-04-20 Andrew Cagney <ac131313@redhat.com>
740 * interp.c (sim_open): Revert previous change.
742 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
744 * interp.c (sim_open): Disable chunk of code that wrote code in
745 vector table entries.
747 2002-03-19 Chris Demetriou <cgd@broadcom.com>
749 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
750 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
753 2002-03-19 Chris Demetriou <cgd@broadcom.com>
755 * cp1.c: Fix many formatting issues.
757 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
759 * cp1.c (fpu_format_name): New function to replace...
760 (DOFMT): This. Delete, and update all callers.
761 (fpu_rounding_mode_name): New function to replace...
762 (RMMODE): This. Delete, and update all callers.
764 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
766 * interp.c: Move FPU support routines from here to...
767 * cp1.c: Here. New file.
768 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
771 2002-03-12 Chris Demetriou <cgd@broadcom.com>
773 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
774 * mips.igen (mips32, mips64): New models, add to all instructions
775 and functions as appropriate.
776 (loadstore_ea, check_u64): New variant for model mips64.
777 (check_fmt_p): New variant for models mipsV and mips64, remove
778 mipsV model marking fro other variant.
781 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
782 for mips32 and mips64.
783 (DCLO, DCLZ): New instructions for mips64.
785 2002-03-07 Chris Demetriou <cgd@broadcom.com>
787 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
788 immediate or code as a hex value with the "%#lx" format.
789 (ANDI): Likewise, and fix printed instruction name.
791 2002-03-05 Chris Demetriou <cgd@broadcom.com>
793 * sim-main.h (UndefinedResult, Unpredictable): New macros
794 which currently do nothing.
796 2002-03-05 Chris Demetriou <cgd@broadcom.com>
798 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
799 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
800 (status_CU3): New definitions.
802 * sim-main.h (ExceptionCause): Add new values for MIPS32
803 and MIPS64: MDMX, MCheck, CacheErr. Update comments
804 for DebugBreakPoint and NMIReset to note their status in
806 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
807 (SignalExceptionCacheErr): New exception macros.
809 2002-03-05 Chris Demetriou <cgd@broadcom.com>
811 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
812 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
814 (SignalExceptionCoProcessorUnusable): Take as argument the
815 unusable coprocessor number.
817 2002-03-05 Chris Demetriou <cgd@broadcom.com>
819 * mips.igen: Fix formatting of all SignalException calls.
821 2002-03-05 Chris Demetriou <cgd@broadcom.com>
823 * sim-main.h (SIGNEXTEND): Remove.
825 2002-03-04 Chris Demetriou <cgd@broadcom.com>
827 * mips.igen: Remove gencode comment from top of file, fix
828 spelling in another comment.
830 2002-03-04 Chris Demetriou <cgd@broadcom.com>
832 * mips.igen (check_fmt, check_fmt_p): New functions to check
833 whether specific floating point formats are usable.
834 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
835 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
836 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
837 Use the new functions.
838 (do_c_cond_fmt): Remove format checks...
839 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
841 2002-03-03 Chris Demetriou <cgd@broadcom.com>
843 * mips.igen: Fix formatting of check_fpu calls.
845 2002-03-03 Chris Demetriou <cgd@broadcom.com>
847 * mips.igen (FLOOR.L.fmt): Store correct destination register.
849 2002-03-03 Chris Demetriou <cgd@broadcom.com>
851 * mips.igen: Remove whitespace at end of lines.
853 2002-03-02 Chris Demetriou <cgd@broadcom.com>
855 * mips.igen (loadstore_ea): New function to do effective
856 address calculations.
857 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
858 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
859 CACHE): Use loadstore_ea to do effective address computations.
861 2002-03-02 Chris Demetriou <cgd@broadcom.com>
863 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
864 * mips.igen (LL, CxC1, MxC1): Likewise.
866 2002-03-02 Chris Demetriou <cgd@broadcom.com>
868 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
869 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
870 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
871 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
872 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
873 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
874 Don't split opcode fields by hand, use the opcode field values
877 2002-03-01 Chris Demetriou <cgd@broadcom.com>
879 * mips.igen (do_divu): Fix spacing.
881 * mips.igen (do_dsllv): Move to be right before DSLLV,
882 to match the rest of the do_<shift> functions.
884 2002-03-01 Chris Demetriou <cgd@broadcom.com>
886 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
887 DSRL32, do_dsrlv): Trace inputs and results.
889 2002-03-01 Chris Demetriou <cgd@broadcom.com>
891 * mips.igen (CACHE): Provide instruction-printing string.
893 * interp.c (signal_exception): Comment tokens after #endif.
895 2002-02-28 Chris Demetriou <cgd@broadcom.com>
897 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
898 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
899 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
900 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
901 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
902 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
903 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
904 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
906 2002-02-28 Chris Demetriou <cgd@broadcom.com>
908 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
909 instruction-printing string.
910 (LWU): Use '64' as the filter flag.
912 2002-02-28 Chris Demetriou <cgd@broadcom.com>
914 * mips.igen (SDXC1): Fix instruction-printing string.
916 2002-02-28 Chris Demetriou <cgd@broadcom.com>
918 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
921 2002-02-27 Chris Demetriou <cgd@broadcom.com>
923 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
926 2002-02-27 Chris Demetriou <cgd@broadcom.com>
928 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
929 add a comma) so that it more closely match the MIPS ISA
930 documentation opcode partitioning.
931 (PREF): Put useful names on opcode fields, and include
932 instruction-printing string.
934 2002-02-27 Chris Demetriou <cgd@broadcom.com>
936 * mips.igen (check_u64): New function which in the future will
937 check whether 64-bit instructions are usable and signal an
938 exception if not. Currently a no-op.
939 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
940 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
941 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
942 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
944 * mips.igen (check_fpu): New function which in the future will
945 check whether FPU instructions are usable and signal an exception
946 if not. Currently a no-op.
947 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
948 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
949 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
950 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
951 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
952 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
953 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
954 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
956 2002-02-27 Chris Demetriou <cgd@broadcom.com>
958 * mips.igen (do_load_left, do_load_right): Move to be immediately
960 (do_store_left, do_store_right): Move to be immediately following
963 2002-02-27 Chris Demetriou <cgd@broadcom.com>
965 * mips.igen (mipsV): New model name. Also, add it to
966 all instructions and functions where it is appropriate.
968 2002-02-18 Chris Demetriou <cgd@broadcom.com>
970 * mips.igen: For all functions and instructions, list model
971 names that support that instruction one per line.
973 2002-02-11 Chris Demetriou <cgd@broadcom.com>
975 * mips.igen: Add some additional comments about supported
976 models, and about which instructions go where.
977 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
978 order as is used in the rest of the file.
980 2002-02-11 Chris Demetriou <cgd@broadcom.com>
982 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
983 indicating that ALU32_END or ALU64_END are there to check
985 (DADD): Likewise, but also remove previous comment about
988 2002-02-10 Chris Demetriou <cgd@broadcom.com>
990 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
991 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
992 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
993 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
994 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
995 fields (i.e., add and move commas) so that they more closely
996 match the MIPS ISA documentation opcode partitioning.
998 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1000 * mips.igen (ADDI): Print immediate value.
1001 (BREAK): Print code.
1002 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1003 (SLL): Print "nop" specially, and don't run the code
1004 that does the shift for the "nop" case.
1006 2001-11-17 Fred Fish <fnf@redhat.com>
1008 * sim-main.h (float_operation): Move enum declaration outside
1009 of _sim_cpu struct declaration.
1011 2001-04-12 Jim Blandy <jimb@redhat.com>
1013 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1014 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1016 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1017 PENDING_FILL, and you can get the intended effect gracefully by
1018 calling PENDING_SCHED directly.
1020 2001-02-23 Ben Elliston <bje@redhat.com>
1022 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1023 already defined elsewhere.
1025 2001-02-19 Ben Elliston <bje@redhat.com>
1027 * sim-main.h (sim_monitor): Return an int.
1028 * interp.c (sim_monitor): Add return values.
1029 (signal_exception): Handle error conditions from sim_monitor.
1031 2001-02-08 Ben Elliston <bje@redhat.com>
1033 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1034 (store_memory): Likewise, pass cia to sim_core_write*.
1036 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1038 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1039 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1041 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1043 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1044 * Makefile.in: Don't delete *.igen when cleaning directory.
1046 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1048 * m16.igen (break): Call SignalException not sim_engine_halt.
1050 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1052 From Jason Eckhardt:
1053 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1055 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1057 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1059 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1061 * mips.igen (do_dmultx): Fix typo.
1063 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1065 * configure: Regenerated to track ../common/aclocal.m4 changes.
1067 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1069 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1071 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1073 * sim-main.h (GPR_CLEAR): Define macro.
1075 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1077 * interp.c (decode_coproc): Output long using %lx and not %s.
1079 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1081 * interp.c (sim_open): Sort & extend dummy memory regions for
1082 --board=jmr3904 for eCos.
1084 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1086 * configure: Regenerated.
1088 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1090 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1091 calls, conditional on the simulator being in verbose mode.
1093 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1095 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1096 cache don't get ReservedInstruction traps.
1098 1999-11-29 Mark Salter <msalter@cygnus.com>
1100 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1101 to clear status bits in sdisr register. This is how the hardware works.
1103 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1104 being used by cygmon.
1106 1999-11-11 Andrew Haley <aph@cygnus.com>
1108 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1111 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1113 * mips.igen (MULT): Correct previous mis-applied patch.
1115 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1117 * mips.igen (delayslot32): Handle sequence like
1118 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1119 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1120 (MULT): Actually pass the third register...
1122 1999-09-03 Mark Salter <msalter@cygnus.com>
1124 * interp.c (sim_open): Added more memory aliases for additional
1125 hardware being touched by cygmon on jmr3904 board.
1127 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1129 * configure: Regenerated to track ../common/aclocal.m4 changes.
1131 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1133 * interp.c (sim_store_register): Handle case where client - GDB -
1134 specifies that a 4 byte register is 8 bytes in size.
1135 (sim_fetch_register): Ditto.
1137 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1139 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1140 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1141 (idt_monitor_base): Base address for IDT monitor traps.
1142 (pmon_monitor_base): Ditto for PMON.
1143 (lsipmon_monitor_base): Ditto for LSI PMON.
1144 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1145 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1146 (sim_firmware_command): New function.
1147 (mips_option_handler): Call it for OPTION_FIRMWARE.
1148 (sim_open): Allocate memory for idt_monitor region. If "--board"
1149 option was given, add no monitor by default. Add BREAK hooks only if
1150 monitors are also there.
1152 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1154 * interp.c (sim_monitor): Flush output before reading input.
1156 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1158 * tconfig.in (SIM_HANDLES_LMA): Always define.
1160 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1162 From Mark Salter <msalter@cygnus.com>:
1163 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1164 (sim_open): Add setup for BSP board.
1166 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1168 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1169 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1170 them as unimplemented.
1172 1999-05-08 Felix Lee <flee@cygnus.com>
1174 * configure: Regenerated to track ../common/aclocal.m4 changes.
1176 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1178 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1180 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1182 * configure.in: Any mips64vr5*-*-* target should have
1183 -DTARGET_ENABLE_FR=1.
1184 (default_endian): Any mips64vr*el-*-* target should default to
1186 * configure: Re-generate.
1188 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1190 * mips.igen (ldl): Extend from _16_, not 32.
1192 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1194 * interp.c (sim_store_register): Force registers written to by GDB
1195 into an un-interpreted state.
1197 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1199 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1200 CPU, start periodic background I/O polls.
1201 (tx3904sio_poll): New function: periodic I/O poller.
1203 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1205 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1207 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1209 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1212 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1214 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1215 (load_word): Call SIM_CORE_SIGNAL hook on error.
1216 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1217 starting. For exception dispatching, pass PC instead of NULL_CIA.
1218 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1219 * sim-main.h (COP0_BADVADDR): Define.
1220 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1221 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1222 (_sim_cpu): Add exc_* fields to store register value snapshots.
1223 * mips.igen (*): Replace memory-related SignalException* calls
1224 with references to SIM_CORE_SIGNAL hook.
1226 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1228 * sim-main.c (*): Minor warning cleanups.
1230 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1232 * m16.igen (DADDIU5): Correct type-o.
1234 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1236 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1239 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1241 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1243 (interp.o): Add dependency on itable.h
1244 (oengine.c, gencode): Delete remaining references.
1245 (BUILT_SRC_FROM_GEN): Clean up.
1247 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1250 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1251 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1252 tmp-run-hack) : New.
1253 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1254 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1255 Drop the "64" qualifier to get the HACK generator working.
1256 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1257 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1258 qualifier to get the hack generator working.
1259 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1260 (DSLL): Use do_dsll.
1261 (DSLLV): Use do_dsllv.
1262 (DSRA): Use do_dsra.
1263 (DSRL): Use do_dsrl.
1264 (DSRLV): Use do_dsrlv.
1265 (BC1): Move *vr4100 to get the HACK generator working.
1266 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1267 get the HACK generator working.
1268 (MACC) Rename to get the HACK generator working.
1269 (DMACC,MACCS,DMACCS): Add the 64.
1271 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1273 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1274 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1276 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1278 * mips/interp.c (DEBUG): Cleanups.
1280 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1282 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1283 (tx3904sio_tickle): fflush after a stdout character output.
1285 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1287 * interp.c (sim_close): Uninstall modules.
1289 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1291 * sim-main.h, interp.c (sim_monitor): Change to global
1294 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1296 * configure.in (vr4100): Only include vr4100 instructions in
1298 * configure: Re-generate.
1299 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1301 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1303 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1304 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1307 * configure.in (sim_default_gen, sim_use_gen): Replace with
1309 (--enable-sim-igen): Delete config option. Always using IGEN.
1310 * configure: Re-generate.
1312 * Makefile.in (gencode): Kill, kill, kill.
1315 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1317 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1318 bit mips16 igen simulator.
1319 * configure: Re-generate.
1321 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1322 as part of vr4100 ISA.
1323 * vr.igen: Mark all instructions as 64 bit only.
1325 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1330 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1332 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1333 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1334 * configure: Re-generate.
1336 * m16.igen (BREAK): Define breakpoint instruction.
1337 (JALX32): Mark instruction as mips16 and not r3900.
1338 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1340 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1342 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1344 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1345 insn as a debug breakpoint.
1347 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1349 (PENDING_SCHED): Clean up trace statement.
1350 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1351 (PENDING_FILL): Delay write by only one cycle.
1352 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1354 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1356 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1358 (pending_tick): Move incrementing of index to FOR statement.
1359 (pending_tick): Only update PENDING_OUT after a write has occured.
1361 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1363 * configure: Re-generate.
1365 * interp.c (sim_engine_run OLD): Delete explicit call to
1366 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1368 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1370 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1371 interrupt level number to match changed SignalExceptionInterrupt
1374 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1376 * interp.c: #include "itable.h" if WITH_IGEN.
1377 (get_insn_name): New function.
1378 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1379 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1381 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1383 * configure: Rebuilt to inhale new common/aclocal.m4.
1385 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1387 * dv-tx3904sio.c: Include sim-assert.h.
1389 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1391 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1392 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1393 Reorganize target-specific sim-hardware checks.
1394 * configure: rebuilt.
1395 * interp.c (sim_open): For tx39 target boards, set
1396 OPERATING_ENVIRONMENT, add tx3904sio devices.
1397 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1398 ROM executables. Install dv-sockser into sim-modules list.
1400 * dv-tx3904irc.c: Compiler warning clean-up.
1401 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1402 frequent hw-trace messages.
1404 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1408 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1410 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1412 * vr.igen: New file.
1413 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1414 * mips.igen: Define vr4100 model. Include vr.igen.
1415 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1417 * mips.igen (check_mf_hilo): Correct check.
1419 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1421 * sim-main.h (interrupt_event): Add prototype.
1423 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1424 register_ptr, register_value.
1425 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1427 * sim-main.h (tracefh): Make extern.
1429 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1431 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1432 Reduce unnecessarily high timer event frequency.
1433 * dv-tx3904cpu.c: Ditto for interrupt event.
1435 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1437 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1439 (interrupt_event): Made non-static.
1441 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1442 interchange of configuration values for external vs. internal
1445 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1447 * mips.igen (BREAK): Moved code to here for
1448 simulator-reserved break instructions.
1449 * gencode.c (build_instruction): Ditto.
1450 * interp.c (signal_exception): Code moved from here. Non-
1451 reserved instructions now use exception vector, rather
1453 * sim-main.h: Moved magic constants to here.
1455 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1457 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1458 register upon non-zero interrupt event level, clear upon zero
1460 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1461 by passing zero event value.
1462 (*_io_{read,write}_buffer): Endianness fixes.
1463 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1464 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1466 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1467 serial I/O and timer module at base address 0xFFFF0000.
1469 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1471 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1474 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1476 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1478 * configure: Update.
1480 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1482 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1483 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1484 * configure.in: Include tx3904tmr in hw_device list.
1485 * configure: Rebuilt.
1486 * interp.c (sim_open): Instantiate three timer instances.
1487 Fix address typo of tx3904irc instance.
1489 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1491 * interp.c (signal_exception): SystemCall exception now uses
1492 the exception vector.
1494 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1496 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1499 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1501 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1503 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1505 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1507 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1508 sim-main.h. Declare a struct hw_descriptor instead of struct
1509 hw_device_descriptor.
1511 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1513 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1514 right bits and then re-align left hand bytes to correct byte
1515 lanes. Fix incorrect computation in do_store_left when loading
1516 bytes from second word.
1518 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1520 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1521 * interp.c (sim_open): Only create a device tree when HW is
1524 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1525 * interp.c (signal_exception): Ditto.
1527 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1529 * gencode.c: Mark BEGEZALL as LIKELY.
1531 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1533 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1534 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1536 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1538 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1539 modules. Recognize TX39 target with "mips*tx39" pattern.
1540 * configure: Rebuilt.
1541 * sim-main.h (*): Added many macros defining bits in
1542 TX39 control registers.
1543 (SignalInterrupt): Send actual PC instead of NULL.
1544 (SignalNMIReset): New exception type.
1545 * interp.c (board): New variable for future use to identify
1546 a particular board being simulated.
1547 (mips_option_handler,mips_options): Added "--board" option.
1548 (interrupt_event): Send actual PC.
1549 (sim_open): Make memory layout conditional on board setting.
1550 (signal_exception): Initial implementation of hardware interrupt
1551 handling. Accept another break instruction variant for simulator
1553 (decode_coproc): Implement RFE instruction for TX39.
1554 (mips.igen): Decode RFE instruction as such.
1555 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1556 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1557 bbegin to implement memory map.
1558 * dv-tx3904cpu.c: New file.
1559 * dv-tx3904irc.c: New file.
1561 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1563 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1565 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1567 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1568 with calls to check_div_hilo.
1570 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1572 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1573 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1574 Add special r3900 version of do_mult_hilo.
1575 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1576 with calls to check_mult_hilo.
1577 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1578 with calls to check_div_hilo.
1580 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1582 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1583 Document a replacement.
1585 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1587 * interp.c (sim_monitor): Make mon_printf work.
1589 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1591 * sim-main.h (INSN_NAME): New arg `cpu'.
1593 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1595 * configure: Regenerated to track ../common/aclocal.m4 changes.
1597 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1599 * configure: Regenerated to track ../common/aclocal.m4 changes.
1602 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1604 * acconfig.h: New file.
1605 * configure.in: Reverted change of Apr 24; use sinclude again.
1607 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1609 * configure: Regenerated to track ../common/aclocal.m4 changes.
1612 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1614 * configure.in: Don't call sinclude.
1616 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1618 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1620 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1622 * mips.igen (ERET): Implement.
1624 * interp.c (decode_coproc): Return sign-extended EPC.
1626 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1628 * interp.c (signal_exception): Do not ignore Trap.
1629 (signal_exception): On TRAP, restart at exception address.
1630 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1631 (signal_exception): Update.
1632 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1633 so that TRAP instructions are caught.
1635 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1637 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1638 contains HI/LO access history.
1639 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1640 (HIACCESS, LOACCESS): Delete, replace with
1641 (HIHISTORY, LOHISTORY): New macros.
1642 (CHECKHILO): Delete all, moved to mips.igen
1644 * gencode.c (build_instruction): Do not generate checks for
1645 correct HI/LO register usage.
1647 * interp.c (old_engine_run): Delete checks for correct HI/LO
1650 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1651 check_mf_cycles): New functions.
1652 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1653 do_divu, domultx, do_mult, do_multu): Use.
1655 * tx.igen ("madd", "maddu"): Use.
1657 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1659 * mips.igen (DSRAV): Use function do_dsrav.
1660 (SRAV): Use new function do_srav.
1662 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1663 (B): Sign extend 11 bit immediate.
1664 (EXT-B*): Shift 16 bit immediate left by 1.
1665 (ADDIU*): Don't sign extend immediate value.
1667 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1669 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1671 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1674 * mips.igen (delayslot32, nullify_next_insn): New functions.
1675 (m16.igen): Always include.
1676 (do_*): Add more tracing.
1678 * m16.igen (delayslot16): Add NIA argument, could be called by a
1679 32 bit MIPS16 instruction.
1681 * interp.c (ifetch16): Move function from here.
1682 * sim-main.c (ifetch16): To here.
1684 * sim-main.c (ifetch16, ifetch32): Update to match current
1685 implementations of LH, LW.
1686 (signal_exception): Don't print out incorrect hex value of illegal
1689 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1691 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1694 * m16.igen: Implement MIPS16 instructions.
1696 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1697 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1698 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1699 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1700 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1701 bodies of corresponding code from 32 bit insn to these. Also used
1702 by MIPS16 versions of functions.
1704 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1705 (IMEM16): Drop NR argument from macro.
1707 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1709 * Makefile.in (SIM_OBJS): Add sim-main.o.
1711 * sim-main.h (address_translation, load_memory, store_memory,
1712 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1714 (pr_addr, pr_uword64): Declare.
1715 (sim-main.c): Include when H_REVEALS_MODULE_P.
1717 * interp.c (address_translation, load_memory, store_memory,
1718 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1720 * sim-main.c: To here. Fix compilation problems.
1722 * configure.in: Enable inlining.
1723 * configure: Re-config.
1725 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1727 * configure: Regenerated to track ../common/aclocal.m4 changes.
1729 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1731 * mips.igen: Include tx.igen.
1732 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1733 * tx.igen: New file, contains MADD and MADDU.
1735 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1736 the hardwired constant `7'.
1737 (store_memory): Ditto.
1738 (LOADDRMASK): Move definition to sim-main.h.
1740 mips.igen (MTC0): Enable for r3900.
1743 mips.igen (do_load_byte): Delete.
1744 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1745 do_store_right): New functions.
1746 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1748 configure.in: Let the tx39 use igen again.
1751 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1753 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1754 not an address sized quantity. Return zero for cache sizes.
1756 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1758 * mips.igen (r3900): r3900 does not support 64 bit integer
1761 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1763 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1765 * configure : Rebuild.
1767 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1769 * configure: Regenerated to track ../common/aclocal.m4 changes.
1771 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1773 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1775 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1777 * configure: Regenerated to track ../common/aclocal.m4 changes.
1778 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1780 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1782 * configure: Regenerated to track ../common/aclocal.m4 changes.
1784 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786 * interp.c (Max, Min): Comment out functions. Not yet used.
1788 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1790 * configure: Regenerated to track ../common/aclocal.m4 changes.
1792 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1794 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1795 configurable settings for stand-alone simulator.
1797 * configure.in: Added X11 search, just in case.
1799 * configure: Regenerated.
1801 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1803 * interp.c (sim_write, sim_read, load_memory, store_memory):
1804 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1806 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1808 * sim-main.h (GETFCC): Return an unsigned value.
1810 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1812 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1813 (DADD): Result destination is RD not RT.
1815 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1817 * sim-main.h (HIACCESS, LOACCESS): Always define.
1819 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1821 * interp.c (sim_info): Delete.
1823 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1825 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1826 (mips_option_handler): New argument `cpu'.
1827 (sim_open): Update call to sim_add_option_table.
1829 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1831 * mips.igen (CxC1): Add tracing.
1833 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1835 * sim-main.h (Max, Min): Declare.
1837 * interp.c (Max, Min): New functions.
1839 * mips.igen (BC1): Add tracing.
1841 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1843 * interp.c Added memory map for stack in vr4100
1845 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1847 * interp.c (load_memory): Add missing "break"'s.
1849 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1851 * interp.c (sim_store_register, sim_fetch_register): Pass in
1852 length parameter. Return -1.
1854 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1856 * interp.c: Added hardware init hook, fixed warnings.
1858 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1860 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1862 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1864 * interp.c (ifetch16): New function.
1866 * sim-main.h (IMEM32): Rename IMEM.
1867 (IMEM16_IMMED): Define.
1869 (DELAY_SLOT): Update.
1871 * m16run.c (sim_engine_run): New file.
1873 * m16.igen: All instructions except LB.
1874 (LB): Call do_load_byte.
1875 * mips.igen (do_load_byte): New function.
1876 (LB): Call do_load_byte.
1878 * mips.igen: Move spec for insn bit size and high bit from here.
1879 * Makefile.in (tmp-igen, tmp-m16): To here.
1881 * m16.dc: New file, decode mips16 instructions.
1883 * Makefile.in (SIM_NO_ALL): Define.
1884 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1886 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1888 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1889 point unit to 32 bit registers.
1890 * configure: Re-generate.
1892 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1894 * configure.in (sim_use_gen): Make IGEN the default simulator
1895 generator for generic 32 and 64 bit mips targets.
1896 * configure: Re-generate.
1898 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1900 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1903 * interp.c (sim_fetch_register, sim_store_register): Read/write
1904 FGR from correct location.
1905 (sim_open): Set size of FGR's according to
1906 WITH_TARGET_FLOATING_POINT_BITSIZE.
1908 * sim-main.h (FGR): Store floating point registers in a separate
1911 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1913 * configure: Regenerated to track ../common/aclocal.m4 changes.
1915 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1917 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1919 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1921 * interp.c (pending_tick): New function. Deliver pending writes.
1923 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1924 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1925 it can handle mixed sized quantites and single bits.
1927 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1929 * interp.c (oengine.h): Do not include when building with IGEN.
1930 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1931 (sim_info): Ditto for PROCESSOR_64BIT.
1932 (sim_monitor): Replace ut_reg with unsigned_word.
1933 (*): Ditto for t_reg.
1934 (LOADDRMASK): Define.
1935 (sim_open): Remove defunct check that host FP is IEEE compliant,
1936 using software to emulate floating point.
1937 (value_fpr, ...): Always compile, was conditional on HASFPU.
1939 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1941 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1944 * interp.c (SD, CPU): Define.
1945 (mips_option_handler): Set flags in each CPU.
1946 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1947 (sim_close): Do not clear STATE, deleted anyway.
1948 (sim_write, sim_read): Assume CPU zero's vm should be used for
1950 (sim_create_inferior): Set the PC for all processors.
1951 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1953 (mips16_entry): Pass correct nr of args to store_word, load_word.
1954 (ColdReset): Cold reset all cpu's.
1955 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1956 (sim_monitor, load_memory, store_memory, signal_exception): Use
1957 `CPU' instead of STATE_CPU.
1960 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1963 * sim-main.h (signal_exception): Add sim_cpu arg.
1964 (SignalException*): Pass both SD and CPU to signal_exception.
1965 * interp.c (signal_exception): Update.
1967 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1969 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1970 address_translation): Ditto
1971 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1973 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1975 * configure: Regenerated to track ../common/aclocal.m4 changes.
1977 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1979 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1981 * mips.igen (model): Map processor names onto BFD name.
1983 * sim-main.h (CPU_CIA): Delete.
1984 (SET_CIA, GET_CIA): Define
1986 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1988 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1991 * configure.in (default_endian): Configure a big-endian simulator
1993 * configure: Re-generate.
1995 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1997 * configure: Regenerated to track ../common/aclocal.m4 changes.
1999 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2001 * interp.c (sim_monitor): Handle Densan monitor outbyte
2002 and inbyte functions.
2004 1997-12-29 Felix Lee <flee@cygnus.com>
2006 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2008 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2010 * Makefile.in (tmp-igen): Arrange for $zero to always be
2011 reset to zero after every instruction.
2013 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2015 * configure: Regenerated to track ../common/aclocal.m4 changes.
2018 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2020 * mips.igen (MSUB): Fix to work like MADD.
2021 * gencode.c (MSUB): Similarly.
2023 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2025 * configure: Regenerated to track ../common/aclocal.m4 changes.
2027 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2031 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2033 * sim-main.h (sim-fpu.h): Include.
2035 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2036 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2037 using host independant sim_fpu module.
2039 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041 * interp.c (signal_exception): Report internal errors with SIGABRT
2044 * sim-main.h (C0_CONFIG): New register.
2045 (signal.h): No longer include.
2047 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2049 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2051 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2053 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2055 * mips.igen: Tag vr5000 instructions.
2056 (ANDI): Was missing mipsIV model, fix assembler syntax.
2057 (do_c_cond_fmt): New function.
2058 (C.cond.fmt): Handle mips I-III which do not support CC field
2060 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2061 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2063 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2064 vr5000 which saves LO in a GPR separatly.
2066 * configure.in (enable-sim-igen): For vr5000, select vr5000
2067 specific instructions.
2068 * configure: Re-generate.
2070 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2072 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2074 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2075 fmt_uninterpreted_64 bit cases to switch. Convert to
2078 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2080 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2081 as specified in IV3.2 spec.
2082 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2084 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2086 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2087 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2088 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2089 PENDING_FILL versions of instructions. Simplify.
2091 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2093 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2095 (MTHI, MFHI): Disable code checking HI-LO.
2097 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2099 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2101 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103 * gencode.c (build_mips16_operands): Replace IPC with cia.
2105 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2106 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2108 (UndefinedResult): Replace function with macro/function
2110 (sim_engine_run): Don't save PC in IPC.
2112 * sim-main.h (IPC): Delete.
2115 * interp.c (signal_exception, store_word, load_word,
2116 address_translation, load_memory, store_memory, cache_op,
2117 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2118 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2119 current instruction address - cia - argument.
2120 (sim_read, sim_write): Call address_translation directly.
2121 (sim_engine_run): Rename variable vaddr to cia.
2122 (signal_exception): Pass cia to sim_monitor
2124 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2125 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2126 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2128 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2129 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2132 * interp.c (signal_exception): Pass restart address to
2135 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2136 idecode.o): Add dependency.
2138 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2140 (DELAY_SLOT): Update NIA not PC with branch address.
2141 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2143 * mips.igen: Use CIA not PC in branch calculations.
2144 (illegal): Call SignalException.
2145 (BEQ, ADDIU): Fix assembler.
2147 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2149 * m16.igen (JALX): Was missing.
2151 * configure.in (enable-sim-igen): New configuration option.
2152 * configure: Re-generate.
2154 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2156 * interp.c (load_memory, store_memory): Delete parameter RAW.
2157 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2158 bypassing {load,store}_memory.
2160 * sim-main.h (ByteSwapMem): Delete definition.
2162 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2164 * interp.c (sim_do_command, sim_commands): Delete mips specific
2165 commands. Handled by module sim-options.
2167 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2168 (WITH_MODULO_MEMORY): Define.
2170 * interp.c (sim_info): Delete code printing memory size.
2172 * interp.c (mips_size): Nee sim_size, delete function.
2174 (monitor, monitor_base, monitor_size): Delete global variables.
2175 (sim_open, sim_close): Delete code creating monitor and other
2176 memory regions. Use sim-memopts module, via sim_do_commandf, to
2177 manage memory regions.
2178 (load_memory, store_memory): Use sim-core for memory model.
2180 * interp.c (address_translation): Delete all memory map code
2181 except line forcing 32 bit addresses.
2183 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2188 * interp.c (logfh, logfile): Delete globals.
2189 (sim_open, sim_close): Delete code opening & closing log file.
2190 (mips_option_handler): Delete -l and -n options.
2191 (OPTION mips_options): Ditto.
2193 * interp.c (OPTION mips_options): Rename option trace to dinero.
2194 (mips_option_handler): Update.
2196 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2198 * interp.c (fetch_str): New function.
2199 (sim_monitor): Rewrite using sim_read & sim_write.
2200 (sim_open): Check magic number.
2201 (sim_open): Write monitor vectors into memory using sim_write.
2202 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2203 (sim_read, sim_write): Simplify - transfer data one byte at a
2205 (load_memory, store_memory): Clarify meaning of parameter RAW.
2207 * sim-main.h (isHOST): Defete definition.
2208 (isTARGET): Mark as depreciated.
2209 (address_translation): Delete parameter HOST.
2211 * interp.c (address_translation): Delete parameter HOST.
2213 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2217 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2218 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2220 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2222 * mips.igen: Add model filter field to records.
2224 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2226 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2228 interp.c (sim_engine_run): Do not compile function sim_engine_run
2229 when WITH_IGEN == 1.
2231 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2232 target architecture.
2234 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2235 igen. Replace with configuration variables sim_igen_flags /
2238 * m16.igen: New file. Copy mips16 insns here.
2239 * mips.igen: From here.
2241 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2243 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2245 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2247 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2249 * gencode.c (build_instruction): Follow sim_write's lead in using
2250 BigEndianMem instead of !ByteSwapMem.
2252 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2254 * configure.in (sim_gen): Dependent on target, select type of
2255 generator. Always select old style generator.
2257 configure: Re-generate.
2259 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2261 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2262 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2263 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2264 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2265 SIM_@sim_gen@_*, set by autoconf.
2267 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2269 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2271 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2272 CURRENT_FLOATING_POINT instead.
2274 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2275 (address_translation): Raise exception InstructionFetch when
2276 translation fails and isINSTRUCTION.
2278 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2279 sim_engine_run): Change type of of vaddr and paddr to
2281 (address_translation, prefetch, load_memory, store_memory,
2282 cache_op): Change type of vAddr and pAddr to address_word.
2284 * gencode.c (build_instruction): Change type of vaddr and paddr to
2287 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2289 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2290 macro to obtain result of ALU op.
2292 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2294 * interp.c (sim_info): Call profile_print.
2296 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2298 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2300 * sim-main.h (WITH_PROFILE): Do not define, defined in
2301 common/sim-config.h. Use sim-profile module.
2302 (simPROFILE): Delete defintion.
2304 * interp.c (PROFILE): Delete definition.
2305 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2306 (sim_close): Delete code writing profile histogram.
2307 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2309 (sim_engine_run): Delete code profiling the PC.
2311 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2313 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2315 * interp.c (sim_monitor): Make register pointers of type
2318 * sim-main.h: Make registers of type unsigned_word not
2321 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2323 * interp.c (sync_operation): Rename from SyncOperation, make
2324 global, add SD argument.
2325 (prefetch): Rename from Prefetch, make global, add SD argument.
2326 (decode_coproc): Make global.
2328 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2330 * gencode.c (build_instruction): Generate DecodeCoproc not
2331 decode_coproc calls.
2333 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2334 (SizeFGR): Move to sim-main.h
2335 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2336 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2337 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2339 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2340 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2341 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2342 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2343 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2344 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2346 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2348 (sim-alu.h): Include.
2349 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2350 (sim_cia): Typedef to instruction_address.
2352 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354 * Makefile.in (interp.o): Rename generated file engine.c to
2359 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2361 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2363 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2365 * gencode.c (build_instruction): For "FPSQRT", output correct
2366 number of arguments to Recip.
2368 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2370 * Makefile.in (interp.o): Depends on sim-main.h
2372 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2374 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2375 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2376 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2377 STATE, DSSTATE): Define
2378 (GPR, FGRIDX, ..): Define.
2380 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2381 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2382 (GPR, FGRIDX, ...): Delete macros.
2384 * interp.c: Update names to match defines from sim-main.h
2386 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2388 * interp.c (sim_monitor): Add SD argument.
2389 (sim_warning): Delete. Replace calls with calls to
2391 (sim_error): Delete. Replace calls with sim_io_error.
2392 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2393 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2394 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2396 (mips_size): Rename from sim_size. Add SD argument.
2398 * interp.c (simulator): Delete global variable.
2399 (callback): Delete global variable.
2400 (mips_option_handler, sim_open, sim_write, sim_read,
2401 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2402 sim_size,sim_monitor): Use sim_io_* not callback->*.
2403 (sim_open): ZALLOC simulator struct.
2404 (PROFILE): Do not define.
2406 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2408 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2409 support.h with corresponding code.
2411 * sim-main.h (word64, uword64), support.h: Move definition to
2413 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2416 * Makefile.in: Update dependencies
2417 * interp.c: Do not include.
2419 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2421 * interp.c (address_translation, load_memory, store_memory,
2422 cache_op): Rename to from AddressTranslation et.al., make global,
2425 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2428 * interp.c (SignalException): Rename to signal_exception, make
2431 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2433 * sim-main.h (SignalException, SignalExceptionInterrupt,
2434 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2435 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2436 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2439 * interp.c, support.h: Use.
2441 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2443 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2444 to value_fpr / store_fpr. Add SD argument.
2445 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2446 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2448 * sim-main.h (ValueFPR, StoreFPR): Define.
2450 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2452 * interp.c (sim_engine_run): Check consistency between configure
2453 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2456 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2457 (mips_fpu): Configure WITH_FLOATING_POINT.
2458 (mips_endian): Configure WITH_TARGET_ENDIAN.
2459 * configure: Update.
2461 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2463 * configure: Regenerated to track ../common/aclocal.m4 changes.
2465 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2467 * configure: Regenerated.
2469 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2471 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2473 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2475 * gencode.c (print_igen_insn_models): Assume certain architectures
2476 include all mips* instructions.
2477 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2480 * Makefile.in (tmp.igen): Add target. Generate igen input from
2483 * gencode.c (FEATURE_IGEN): Define.
2484 (main): Add --igen option. Generate output in igen format.
2485 (process_instructions): Format output according to igen option.
2486 (print_igen_insn_format): New function.
2487 (print_igen_insn_models): New function.
2488 (process_instructions): Only issue warnings and ignore
2489 instructions when no FEATURE_IGEN.
2491 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2493 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2496 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498 * configure: Regenerated to track ../common/aclocal.m4 changes.
2500 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2503 SIM_RESERVED_BITS): Delete, moved to common.
2504 (SIM_EXTRA_CFLAGS): Update.
2506 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2508 * configure.in: Configure non-strict memory alignment.
2509 * configure: Regenerated to track ../common/aclocal.m4 changes.
2511 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2513 * configure: Regenerated to track ../common/aclocal.m4 changes.
2515 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2517 * gencode.c (SDBBP,DERET): Added (3900) insns.
2518 (RFE): Turn on for 3900.
2519 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2520 (dsstate): Made global.
2521 (SUBTARGET_R3900): Added.
2522 (CANCELDELAYSLOT): New.
2523 (SignalException): Ignore SystemCall rather than ignore and
2524 terminate. Add DebugBreakPoint handling.
2525 (decode_coproc): New insns RFE, DERET; and new registers Debug
2526 and DEPC protected by SUBTARGET_R3900.
2527 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2529 * Makefile.in,configure.in: Add mips subtarget option.
2530 * configure: Update.
2532 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2534 * gencode.c: Add r3900 (tx39).
2537 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2539 * gencode.c (build_instruction): Don't need to subtract 4 for
2542 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2544 * interp.c: Correct some HASFPU problems.
2546 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2548 * configure: Regenerated to track ../common/aclocal.m4 changes.
2550 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2552 * interp.c (mips_options): Fix samples option short form, should
2555 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2557 * interp.c (sim_info): Enable info code. Was just returning.
2559 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2561 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2564 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2566 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2568 (build_instruction): Ditto for LL.
2570 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2572 * configure: Regenerated to track ../common/aclocal.m4 changes.
2574 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576 * configure: Regenerated to track ../common/aclocal.m4 changes.
2579 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2581 * interp.c (sim_open): Add call to sim_analyze_program, update
2584 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2586 * interp.c (sim_kill): Delete.
2587 (sim_create_inferior): Add ABFD argument. Set PC from same.
2588 (sim_load): Move code initializing trap handlers from here.
2589 (sim_open): To here.
2590 (sim_load): Delete, use sim-hload.c.
2592 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2594 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596 * configure: Regenerated to track ../common/aclocal.m4 changes.
2599 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2601 * interp.c (sim_open): Add ABFD argument.
2602 (sim_load): Move call to sim_config from here.
2603 (sim_open): To here. Check return status.
2605 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2607 * gencode.c (build_instruction): Two arg MADD should
2608 not assign result to $0.
2610 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2612 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2613 * sim/mips/configure.in: Regenerate.
2615 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2617 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2618 signed8, unsigned8 et.al. types.
2620 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2621 hosts when selecting subreg.
2623 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2625 * interp.c (sim_engine_run): Reset the ZERO register to zero
2626 regardless of FEATURE_WARN_ZERO.
2627 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2629 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2631 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2632 (SignalException): For BreakPoints ignore any mode bits and just
2634 (SignalException): Always set the CAUSE register.
2636 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2638 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2639 exception has been taken.
2641 * interp.c: Implement the ERET and mt/f sr instructions.
2643 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645 * interp.c (SignalException): Don't bother restarting an
2648 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2650 * interp.c (SignalException): Really take an interrupt.
2651 (interrupt_event): Only deliver interrupts when enabled.
2653 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2655 * interp.c (sim_info): Only print info when verbose.
2656 (sim_info) Use sim_io_printf for output.
2658 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2660 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2663 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2665 * interp.c (sim_do_command): Check for common commands if a
2666 simulator specific command fails.
2668 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2670 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2671 and simBE when DEBUG is defined.
2673 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2675 * interp.c (interrupt_event): New function. Pass exception event
2676 onto exception handler.
2678 * configure.in: Check for stdlib.h.
2679 * configure: Regenerate.
2681 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2682 variable declaration.
2683 (build_instruction): Initialize memval1.
2684 (build_instruction): Add UNUSED attribute to byte, bigend,
2686 (build_operands): Ditto.
2688 * interp.c: Fix GCC warnings.
2689 (sim_get_quit_code): Delete.
2691 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2692 * Makefile.in: Ditto.
2693 * configure: Re-generate.
2695 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2697 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2699 * interp.c (mips_option_handler): New function parse argumes using
2701 (myname): Replace with STATE_MY_NAME.
2702 (sim_open): Delete check for host endianness - performed by
2704 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2705 (sim_open): Move much of the initialization from here.
2706 (sim_load): To here. After the image has been loaded and
2708 (sim_open): Move ColdReset from here.
2709 (sim_create_inferior): To here.
2710 (sim_open): Make FP check less dependant on host endianness.
2712 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2714 * interp.c (sim_set_callbacks): Delete.
2716 * interp.c (membank, membank_base, membank_size): Replace with
2717 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2718 (sim_open): Remove call to callback->init. gdb/run do this.
2722 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2724 * interp.c (big_endian_p): Delete, replaced by
2725 current_target_byte_order.
2727 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729 * interp.c (host_read_long, host_read_word, host_swap_word,
2730 host_swap_long): Delete. Using common sim-endian.
2731 (sim_fetch_register, sim_store_register): Use H2T.
2732 (pipeline_ticks): Delete. Handled by sim-events.
2734 (sim_engine_run): Update.
2736 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2738 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2740 (SignalException): To here. Signal using sim_engine_halt.
2741 (sim_stop_reason): Delete, moved to common.
2743 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2745 * interp.c (sim_open): Add callback argument.
2746 (sim_set_callbacks): Delete SIM_DESC argument.
2749 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2751 * Makefile.in (SIM_OBJS): Add common modules.
2753 * interp.c (sim_set_callbacks): Also set SD callback.
2754 (set_endianness, xfer_*, swap_*): Delete.
2755 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2756 Change to functions using sim-endian macros.
2757 (control_c, sim_stop): Delete, use common version.
2758 (simulate): Convert into.
2759 (sim_engine_run): This function.
2760 (sim_resume): Delete.
2762 * interp.c (simulation): New variable - the simulator object.
2763 (sim_kind): Delete global - merged into simulation.
2764 (sim_load): Cleanup. Move PC assignment from here.
2765 (sim_create_inferior): To here.
2767 * sim-main.h: New file.
2768 * interp.c (sim-main.h): Include.
2770 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2772 * configure: Regenerated to track ../common/aclocal.m4 changes.
2774 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2776 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2778 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2780 * gencode.c (build_instruction): DIV instructions: check
2781 for division by zero and integer overflow before using
2782 host's division operation.
2784 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2786 * Makefile.in (SIM_OBJS): Add sim-load.o.
2787 * interp.c: #include bfd.h.
2788 (target_byte_order): Delete.
2789 (sim_kind, myname, big_endian_p): New static locals.
2790 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2791 after argument parsing. Recognize -E arg, set endianness accordingly.
2792 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2793 load file into simulator. Set PC from bfd.
2794 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2795 (set_endianness): Use big_endian_p instead of target_byte_order.
2797 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2799 * interp.c (sim_size): Delete prototype - conflicts with
2800 definition in remote-sim.h. Correct definition.
2802 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2804 * configure: Regenerated to track ../common/aclocal.m4 changes.
2807 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2809 * interp.c (sim_open): New arg `kind'.
2811 * configure: Regenerated to track ../common/aclocal.m4 changes.
2813 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2815 * configure: Regenerated to track ../common/aclocal.m4 changes.
2817 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2819 * interp.c (sim_open): Set optind to 0 before calling getopt.
2821 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2823 * configure: Regenerated to track ../common/aclocal.m4 changes.
2825 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2827 * interp.c : Replace uses of pr_addr with pr_uword64
2828 where the bit length is always 64 independent of SIM_ADDR.
2829 (pr_uword64) : added.
2831 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2833 * configure: Re-generate.
2835 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2837 * configure: Regenerate to track ../common/aclocal.m4 changes.
2839 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2841 * interp.c (sim_open): New SIM_DESC result. Argument is now
2843 (other sim_*): New SIM_DESC argument.
2845 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2847 * interp.c: Fix printing of addresses for non-64-bit targets.
2848 (pr_addr): Add function to print address based on size.
2850 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2852 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2854 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2856 * gencode.c (build_mips16_operands): Correct computation of base
2857 address for extended PC relative instruction.
2859 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2861 * interp.c (mips16_entry): Add support for floating point cases.
2862 (SignalException): Pass floating point cases to mips16_entry.
2863 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2865 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2867 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2868 and then set the state to fmt_uninterpreted.
2869 (COP_SW): Temporarily set the state to fmt_word while calling
2872 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2874 * gencode.c (build_instruction): The high order may be set in the
2875 comparison flags at any ISA level, not just ISA 4.
2877 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2879 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2880 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2881 * configure.in: sinclude ../common/aclocal.m4.
2882 * configure: Regenerated.
2884 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2886 * configure: Rebuild after change to aclocal.m4.
2888 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2890 * configure configure.in Makefile.in: Update to new configure
2891 scheme which is more compatible with WinGDB builds.
2892 * configure.in: Improve comment on how to run autoconf.
2893 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2894 * Makefile.in: Use autoconf substitution to install common
2897 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2899 * gencode.c (build_instruction): Use BigEndianCPU instead of
2902 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2904 * interp.c (sim_monitor): Make output to stdout visible in
2905 wingdb's I/O log window.
2907 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2909 * support.h: Undo previous change to SIGTRAP
2912 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2914 * interp.c (store_word, load_word): New static functions.
2915 (mips16_entry): New static function.
2916 (SignalException): Look for mips16 entry and exit instructions.
2917 (simulate): Use the correct index when setting fpr_state after
2918 doing a pending move.
2920 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2922 * interp.c: Fix byte-swapping code throughout to work on
2923 both little- and big-endian hosts.
2925 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2927 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2928 with gdb/config/i386/xm-windows.h.
2930 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2932 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2933 that messes up arithmetic shifts.
2935 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2937 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2938 SIGTRAP and SIGQUIT for _WIN32.
2940 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2942 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2943 force a 64 bit multiplication.
2944 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2945 destination register is 0, since that is the default mips16 nop
2948 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2950 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2951 (build_endian_shift): Don't check proc64.
2952 (build_instruction): Always set memval to uword64. Cast op2 to
2953 uword64 when shifting it left in memory instructions. Always use
2954 the same code for stores--don't special case proc64.
2956 * gencode.c (build_mips16_operands): Fix base PC value for PC
2958 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2960 * interp.c (simJALDELAYSLOT): Define.
2961 (JALDELAYSLOT): Define.
2962 (INDELAYSLOT, INJALDELAYSLOT): Define.
2963 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2965 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2967 * interp.c (sim_open): add flush_cache as a PMON routine
2968 (sim_monitor): handle flush_cache by ignoring it
2970 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2972 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2974 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2975 (BigEndianMem): Rename to ByteSwapMem and change sense.
2976 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2977 BigEndianMem references to !ByteSwapMem.
2978 (set_endianness): New function, with prototype.
2979 (sim_open): Call set_endianness.
2980 (sim_info): Use simBE instead of BigEndianMem.
2981 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2982 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2983 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2984 ifdefs, keeping the prototype declaration.
2985 (swap_word): Rewrite correctly.
2986 (ColdReset): Delete references to CONFIG. Delete endianness related
2987 code; moved to set_endianness.
2989 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2991 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2992 * interp.c (CHECKHILO): Define away.
2993 (simSIGINT): New macro.
2994 (membank_size): Increase from 1MB to 2MB.
2995 (control_c): New function.
2996 (sim_resume): Rename parameter signal to signal_number. Add local
2997 variable prev. Call signal before and after simulate.
2998 (sim_stop_reason): Add simSIGINT support.
2999 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3001 (sim_warning): Delete call to SignalException. Do call printf_filtered
3003 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3004 a call to sim_warning.
3006 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3008 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3009 16 bit instructions.
3011 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3013 Add support for mips16 (16 bit MIPS implementation):
3014 * gencode.c (inst_type): Add mips16 instruction encoding types.
3015 (GETDATASIZEINSN): Define.
3016 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3017 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3019 (MIPS16_DECODE): New table, for mips16 instructions.
3020 (bitmap_val): New static function.
3021 (struct mips16_op): Define.
3022 (mips16_op_table): New table, for mips16 operands.
3023 (build_mips16_operands): New static function.
3024 (process_instructions): If PC is odd, decode a mips16
3025 instruction. Break out instruction handling into new
3026 build_instruction function.
3027 (build_instruction): New static function, broken out of
3028 process_instructions. Check modifiers rather than flags for SHIFT
3029 bit count and m[ft]{hi,lo} direction.
3030 (usage): Pass program name to fprintf.
3031 (main): Remove unused variable this_option_optind. Change
3032 ``*loptarg++'' to ``loptarg++''.
3033 (my_strtoul): Parenthesize && within ||.
3034 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3035 (simulate): If PC is odd, fetch a 16 bit instruction, and
3036 increment PC by 2 rather than 4.
3037 * configure.in: Add case for mips16*-*-*.
3038 * configure: Rebuild.
3040 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3042 * interp.c: Allow -t to enable tracing in standalone simulator.
3043 Fix garbage output in trace file and error messages.
3045 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3047 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3048 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3049 * configure.in: Simplify using macros in ../common/aclocal.m4.
3050 * configure: Regenerated.
3051 * tconfig.in: New file.
3053 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3055 * interp.c: Fix bugs in 64-bit port.
3056 Use ansi function declarations for msvc compiler.
3057 Initialize and test file pointer in trace code.
3058 Prevent duplicate definition of LAST_EMED_REGNUM.
3060 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3062 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3064 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3066 * interp.c (SignalException): Check for explicit terminating
3068 * gencode.c: Pass instruction value through SignalException()
3069 calls for Trap, Breakpoint and Syscall.
3071 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3073 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3074 only used on those hosts that provide it.
3075 * configure.in: Add sqrt() to list of functions to be checked for.
3076 * config.in: Re-generated.
3077 * configure: Re-generated.
3079 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3081 * gencode.c (process_instructions): Call build_endian_shift when
3082 expanding STORE RIGHT, to fix swr.
3083 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3084 clear the high bits.
3085 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3086 Fix float to int conversions to produce signed values.
3088 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3090 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3091 (process_instructions): Correct handling of nor instruction.
3092 Correct shift count for 32 bit shift instructions. Correct sign
3093 extension for arithmetic shifts to not shift the number of bits in
3094 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3095 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3097 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3098 It's OK to have a mult follow a mult. What's not OK is to have a
3099 mult follow an mfhi.
3100 (Convert): Comment out incorrect rounding code.
3102 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3104 * interp.c (sim_monitor): Improved monitor printf
3105 simulation. Tidied up simulator warnings, and added "--log" option
3106 for directing warning message output.
3107 * gencode.c: Use sim_warning() rather than WARNING macro.
3109 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3111 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3112 getopt1.o, rather than on gencode.c. Link objects together.
3113 Don't link against -liberty.
3114 (gencode.o, getopt.o, getopt1.o): New targets.
3115 * gencode.c: Include <ctype.h> and "ansidecl.h".
3116 (AND): Undefine after including "ansidecl.h".
3117 (ULONG_MAX): Define if not defined.
3118 (OP_*): Don't define macros; now defined in opcode/mips.h.
3119 (main): Call my_strtoul rather than strtoul.
3120 (my_strtoul): New static function.
3122 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3124 * gencode.c (process_instructions): Generate word64 and uword64
3125 instead of `long long' and `unsigned long long' data types.
3126 * interp.c: #include sysdep.h to get signals, and define default
3128 * (Convert): Work around for Visual-C++ compiler bug with type
3130 * support.h: Make things compile under Visual-C++ by using
3131 __int64 instead of `long long'. Change many refs to long long
3132 into word64/uword64 typedefs.
3134 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3136 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3137 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3139 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3140 (AC_PROG_INSTALL): Added.
3141 (AC_PROG_CC): Moved to before configure.host call.
3142 * configure: Rebuilt.
3144 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3146 * configure.in: Define @SIMCONF@ depending on mips target.
3147 * configure: Rebuild.
3148 * Makefile.in (run): Add @SIMCONF@ to control simulator
3150 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3151 * interp.c: Remove some debugging, provide more detailed error
3152 messages, update memory accesses to use LOADDRMASK.
3154 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3156 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3157 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3159 * configure: Rebuild.
3160 * config.in: New file, generated by autoheader.
3161 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3162 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3163 HAVE_ANINT and HAVE_AINT, as appropriate.
3164 * Makefile.in (run): Use @LIBS@ rather than -lm.
3165 (interp.o): Depend upon config.h.
3166 (Makefile): Just rebuild Makefile.
3167 (clean): Remove stamp-h.
3168 (mostlyclean): Make the same as clean, not as distclean.
3169 (config.h, stamp-h): New targets.
3171 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3173 * interp.c (ColdReset): Fix boolean test. Make all simulator
3176 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3178 * interp.c (xfer_direct_word, xfer_direct_long,
3179 swap_direct_word, swap_direct_long, xfer_big_word,
3180 xfer_big_long, xfer_little_word, xfer_little_long,
3181 swap_word,swap_long): Added.
3182 * interp.c (ColdReset): Provide function indirection to
3183 host<->simulated_target transfer routines.
3184 * interp.c (sim_store_register, sim_fetch_register): Updated to
3185 make use of indirected transfer routines.
3187 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3189 * gencode.c (process_instructions): Ensure FP ABS instruction
3191 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3192 system call support.
3194 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3196 * interp.c (sim_do_command): Complain if callback structure not
3199 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3201 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3202 support for Sun hosts.
3203 * Makefile.in (gencode): Ensure the host compiler and libraries
3204 used for cross-hosted build.
3206 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3208 * interp.c, gencode.c: Some more (TODO) tidying.
3210 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3212 * gencode.c, interp.c: Replaced explicit long long references with
3213 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3214 * support.h (SET64LO, SET64HI): Macros added.
3216 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3218 * configure: Regenerate with autoconf 2.7.
3220 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3222 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3223 * support.h: Remove superfluous "1" from #if.
3224 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3226 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3228 * interp.c (StoreFPR): Control UndefinedResult() call on
3229 WARN_RESULT manifest.
3231 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3233 * gencode.c: Tidied instruction decoding, and added FP instruction
3236 * interp.c: Added dineroIII, and BSD profiling support. Also
3237 run-time FP handling.
3239 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3241 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3242 gencode.c, interp.c, support.h: created.