1 2002-06-07 Chris Demetriou <cgd@broadcom.com>
2 Ed Satterthwaite <ehs@broadcom.com>
4 * cp1.c: Fix more comment spelling and formatting.
5 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
6 (denorm_mode): New function.
7 (fpu_unary, fpu_binary): Round results after operation, collect
8 status from rounding operations, and update the FCSR.
9 (convert): Collect status from integer conversions and rounding
10 operations, and update the FCSR. Adjust NaN values that result
11 from conversions. Convert to use sim_io_eprintf rather than
12 fprintf, and remove some debugging code.
13 * cp1.h (fenr_FS): New define.
15 2002-06-07 Chris Demetriou <cgd@broadcom.com>
17 * cp1.c (convert): Remove unusable debugging code, and move MIPS
18 rounding mode to sim FP rounding mode flag conversion code into...
19 (rounding_mode): New function.
21 2002-06-07 Chris Demetriou <cgd@broadcom.com>
23 * cp1.c: Clean up formatting of a few comments.
24 (value_fpr): Reformat switch statement.
26 2002-06-06 Chris Demetriou <cgd@broadcom.com>
27 Ed Satterthwaite <ehs@broadcom.com>
30 * sim-main.h: Include cp1.h.
31 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
32 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
33 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
34 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
35 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
36 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
37 * cp1.c: Don't include sim-fpu.h; already included by
38 sim-main.h. Clean up formatting of some comments.
39 (NaN, Equal, Less): Remove.
40 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
41 (fp_cmp): New functions.
42 * mips.igen (do_c_cond_fmt): Remove.
43 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
44 Compare. Add result tracing.
45 (CxC1): Remove, replace with...
46 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
47 (DMxC1): Remove, replace with...
48 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
49 (MxC1): Remove, replace with...
50 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
52 2002-06-04 Chris Demetriou <cgd@broadcom.com>
54 * sim-main.h (FGRIDX): Remove, replace all uses with...
55 (FGR_BASE): New macro.
56 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
57 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
58 (NR_FGR, FGR): Likewise.
59 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
60 * mips.igen: Likewise.
62 2002-06-04 Chris Demetriou <cgd@broadcom.com>
64 * cp1.c: Add an FSF Copyright notice to this file.
66 2002-06-04 Chris Demetriou <cgd@broadcom.com>
67 Ed Satterthwaite <ehs@broadcom.com>
69 * cp1.c (Infinity): Remove.
70 * sim-main.h (Infinity): Likewise.
72 * cp1.c (fp_unary, fp_binary): New functions.
73 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
74 (fp_sqrt): New functions, implemented in terms of the above.
75 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
76 (Recip, SquareRoot): Remove (replaced by functions above).
77 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
78 (fp_recip, fp_sqrt): New prototypes.
79 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
80 (Recip, SquareRoot): Replace prototypes with #defines which
81 invoke the functions above.
83 2002-06-03 Chris Demetriou <cgd@broadcom.com>
85 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
86 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
87 file, remove PARAMS from prototypes.
88 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
89 simulator state arguments.
90 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
91 pass simulator state arguments.
92 * cp1.c (SD): Redefine as CPU_STATE(cpu).
93 (store_fpr, convert): Remove 'sd' argument.
94 (value_fpr): Likewise. Convert to use 'SD' instead.
96 2002-06-03 Chris Demetriou <cgd@broadcom.com>
98 * cp1.c (Min, Max): Remove #if 0'd functions.
99 * sim-main.h (Min, Max): Remove.
101 2002-06-03 Chris Demetriou <cgd@broadcom.com>
103 * cp1.c: fix formatting of switch case and default labels.
104 * interp.c: Likewise.
105 * sim-main.c: Likewise.
107 2002-06-03 Chris Demetriou <cgd@broadcom.com>
109 * cp1.c: Clean up comments which describe FP formats.
110 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
112 2002-06-03 Chris Demetriou <cgd@broadcom.com>
113 Ed Satterthwaite <ehs@broadcom.com>
115 * configure.in (mipsisa64sb1*-*-*): New target for supporting
116 Broadcom SiByte SB-1 processor configurations.
117 * configure: Regenerate.
118 * sb1.igen: New file.
119 * mips.igen: Include sb1.igen.
121 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
122 * mdmx.igen: Add "sb1" model to all appropriate functions and
124 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
125 (ob_func, ob_acc): Reference the above.
126 (qh_acc): Adjust to keep the same size as ob_acc.
127 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
128 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
130 2002-06-03 Chris Demetriou <cgd@broadcom.com>
132 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
134 2002-06-02 Chris Demetriou <cgd@broadcom.com>
135 Ed Satterthwaite <ehs@broadcom.com>
137 * mips.igen (mdmx): New (pseudo-)model.
138 * mdmx.c, mdmx.igen: New files.
139 * Makefile.in (SIM_OBJS): Add mdmx.o.
140 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
142 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
143 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
144 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
145 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
146 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
147 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
148 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
149 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
150 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
151 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
152 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
153 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
154 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
155 (qh_fmtsel): New macros.
156 (_sim_cpu): New member "acc".
157 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
158 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
160 2002-05-01 Chris Demetriou <cgd@broadcom.com>
162 * interp.c: Use 'deprecated' rather than 'depreciated.'
163 * sim-main.h: Likewise.
165 2002-05-01 Chris Demetriou <cgd@broadcom.com>
167 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
168 which wouldn't compile anyway.
169 * sim-main.h (unpredictable_action): New function prototype.
170 (Unpredictable): Define to call igen function unpredictable().
171 (NotWordValue): New macro to call igen function not_word_value().
172 (UndefinedResult): Remove.
173 * interp.c (undefined_result): Remove.
174 (unpredictable_action): New function.
175 * mips.igen (not_word_value, unpredictable): New functions.
176 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
177 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
178 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
179 NotWordValue() to check for unpredictable inputs, then
180 Unpredictable() to handle them.
182 2002-02-24 Chris Demetriou <cgd@broadcom.com>
184 * mips.igen: Fix formatting of calls to Unpredictable().
186 2002-04-20 Andrew Cagney <ac131313@redhat.com>
188 * interp.c (sim_open): Revert previous change.
190 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
192 * interp.c (sim_open): Disable chunk of code that wrote code in
193 vector table entries.
195 2002-03-19 Chris Demetriou <cgd@broadcom.com>
197 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
198 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
201 2002-03-19 Chris Demetriou <cgd@broadcom.com>
203 * cp1.c: Fix many formatting issues.
205 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
207 * cp1.c (fpu_format_name): New function to replace...
208 (DOFMT): This. Delete, and update all callers.
209 (fpu_rounding_mode_name): New function to replace...
210 (RMMODE): This. Delete, and update all callers.
212 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
214 * interp.c: Move FPU support routines from here to...
215 * cp1.c: Here. New file.
216 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
219 2002-03-12 Chris Demetriou <cgd@broadcom.com>
221 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
222 * mips.igen (mips32, mips64): New models, add to all instructions
223 and functions as appropriate.
224 (loadstore_ea, check_u64): New variant for model mips64.
225 (check_fmt_p): New variant for models mipsV and mips64, remove
226 mipsV model marking fro other variant.
229 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
230 for mips32 and mips64.
231 (DCLO, DCLZ): New instructions for mips64.
233 2002-03-07 Chris Demetriou <cgd@broadcom.com>
235 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
236 immediate or code as a hex value with the "%#lx" format.
237 (ANDI): Likewise, and fix printed instruction name.
239 2002-03-05 Chris Demetriou <cgd@broadcom.com>
241 * sim-main.h (UndefinedResult, Unpredictable): New macros
242 which currently do nothing.
244 2002-03-05 Chris Demetriou <cgd@broadcom.com>
246 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
247 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
248 (status_CU3): New definitions.
250 * sim-main.h (ExceptionCause): Add new values for MIPS32
251 and MIPS64: MDMX, MCheck, CacheErr. Update comments
252 for DebugBreakPoint and NMIReset to note their status in
254 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
255 (SignalExceptionCacheErr): New exception macros.
257 2002-03-05 Chris Demetriou <cgd@broadcom.com>
259 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
260 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
262 (SignalExceptionCoProcessorUnusable): Take as argument the
263 unusable coprocessor number.
265 2002-03-05 Chris Demetriou <cgd@broadcom.com>
267 * mips.igen: Fix formatting of all SignalException calls.
269 2002-03-05 Chris Demetriou <cgd@broadcom.com>
271 * sim-main.h (SIGNEXTEND): Remove.
273 2002-03-04 Chris Demetriou <cgd@broadcom.com>
275 * mips.igen: Remove gencode comment from top of file, fix
276 spelling in another comment.
278 2002-03-04 Chris Demetriou <cgd@broadcom.com>
280 * mips.igen (check_fmt, check_fmt_p): New functions to check
281 whether specific floating point formats are usable.
282 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
283 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
284 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
285 Use the new functions.
286 (do_c_cond_fmt): Remove format checks...
287 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
289 2002-03-03 Chris Demetriou <cgd@broadcom.com>
291 * mips.igen: Fix formatting of check_fpu calls.
293 2002-03-03 Chris Demetriou <cgd@broadcom.com>
295 * mips.igen (FLOOR.L.fmt): Store correct destination register.
297 2002-03-03 Chris Demetriou <cgd@broadcom.com>
299 * mips.igen: Remove whitespace at end of lines.
301 2002-03-02 Chris Demetriou <cgd@broadcom.com>
303 * mips.igen (loadstore_ea): New function to do effective
304 address calculations.
305 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
306 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
307 CACHE): Use loadstore_ea to do effective address computations.
309 2002-03-02 Chris Demetriou <cgd@broadcom.com>
311 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
312 * mips.igen (LL, CxC1, MxC1): Likewise.
314 2002-03-02 Chris Demetriou <cgd@broadcom.com>
316 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
317 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
318 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
319 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
320 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
321 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
322 Don't split opcode fields by hand, use the opcode field values
325 2002-03-01 Chris Demetriou <cgd@broadcom.com>
327 * mips.igen (do_divu): Fix spacing.
329 * mips.igen (do_dsllv): Move to be right before DSLLV,
330 to match the rest of the do_<shift> functions.
332 2002-03-01 Chris Demetriou <cgd@broadcom.com>
334 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
335 DSRL32, do_dsrlv): Trace inputs and results.
337 2002-03-01 Chris Demetriou <cgd@broadcom.com>
339 * mips.igen (CACHE): Provide instruction-printing string.
341 * interp.c (signal_exception): Comment tokens after #endif.
343 2002-02-28 Chris Demetriou <cgd@broadcom.com>
345 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
346 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
347 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
348 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
349 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
350 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
351 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
352 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
354 2002-02-28 Chris Demetriou <cgd@broadcom.com>
356 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
357 instruction-printing string.
358 (LWU): Use '64' as the filter flag.
360 2002-02-28 Chris Demetriou <cgd@broadcom.com>
362 * mips.igen (SDXC1): Fix instruction-printing string.
364 2002-02-28 Chris Demetriou <cgd@broadcom.com>
366 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
369 2002-02-27 Chris Demetriou <cgd@broadcom.com>
371 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
374 2002-02-27 Chris Demetriou <cgd@broadcom.com>
376 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
377 add a comma) so that it more closely match the MIPS ISA
378 documentation opcode partitioning.
379 (PREF): Put useful names on opcode fields, and include
380 instruction-printing string.
382 2002-02-27 Chris Demetriou <cgd@broadcom.com>
384 * mips.igen (check_u64): New function which in the future will
385 check whether 64-bit instructions are usable and signal an
386 exception if not. Currently a no-op.
387 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
388 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
389 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
390 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
392 * mips.igen (check_fpu): New function which in the future will
393 check whether FPU instructions are usable and signal an exception
394 if not. Currently a no-op.
395 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
396 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
397 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
398 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
399 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
400 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
401 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
402 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
404 2002-02-27 Chris Demetriou <cgd@broadcom.com>
406 * mips.igen (do_load_left, do_load_right): Move to be immediately
408 (do_store_left, do_store_right): Move to be immediately following
411 2002-02-27 Chris Demetriou <cgd@broadcom.com>
413 * mips.igen (mipsV): New model name. Also, add it to
414 all instructions and functions where it is appropriate.
416 2002-02-18 Chris Demetriou <cgd@broadcom.com>
418 * mips.igen: For all functions and instructions, list model
419 names that support that instruction one per line.
421 2002-02-11 Chris Demetriou <cgd@broadcom.com>
423 * mips.igen: Add some additional comments about supported
424 models, and about which instructions go where.
425 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
426 order as is used in the rest of the file.
428 2002-02-11 Chris Demetriou <cgd@broadcom.com>
430 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
431 indicating that ALU32_END or ALU64_END are there to check
433 (DADD): Likewise, but also remove previous comment about
436 2002-02-10 Chris Demetriou <cgd@broadcom.com>
438 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
439 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
440 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
441 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
442 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
443 fields (i.e., add and move commas) so that they more closely
444 match the MIPS ISA documentation opcode partitioning.
446 2002-02-10 Chris Demetriou <cgd@broadcom.com>
448 * mips.igen (ADDI): Print immediate value.
450 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
451 (SLL): Print "nop" specially, and don't run the code
452 that does the shift for the "nop" case.
454 2001-11-17 Fred Fish <fnf@redhat.com>
456 * sim-main.h (float_operation): Move enum declaration outside
457 of _sim_cpu struct declaration.
459 2001-04-12 Jim Blandy <jimb@redhat.com>
461 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
462 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
464 * sim-main.h (COCIDX): Remove definition; this isn't supported by
465 PENDING_FILL, and you can get the intended effect gracefully by
466 calling PENDING_SCHED directly.
468 2001-02-23 Ben Elliston <bje@redhat.com>
470 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
471 already defined elsewhere.
473 2001-02-19 Ben Elliston <bje@redhat.com>
475 * sim-main.h (sim_monitor): Return an int.
476 * interp.c (sim_monitor): Add return values.
477 (signal_exception): Handle error conditions from sim_monitor.
479 2001-02-08 Ben Elliston <bje@redhat.com>
481 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
482 (store_memory): Likewise, pass cia to sim_core_write*.
484 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
486 On advice from Chris G. Demetriou <cgd@sibyte.com>:
487 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
489 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
491 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
492 * Makefile.in: Don't delete *.igen when cleaning directory.
494 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
496 * m16.igen (break): Call SignalException not sim_engine_halt.
498 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
501 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
503 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
505 * mips.igen (MxC1, DMxC1): Fix printf formatting.
507 2000-05-24 Michael Hayes <mhayes@cygnus.com>
509 * mips.igen (do_dmultx): Fix typo.
511 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
513 * configure: Regenerated to track ../common/aclocal.m4 changes.
515 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
517 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
519 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
521 * sim-main.h (GPR_CLEAR): Define macro.
523 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
525 * interp.c (decode_coproc): Output long using %lx and not %s.
527 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
529 * interp.c (sim_open): Sort & extend dummy memory regions for
530 --board=jmr3904 for eCos.
532 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
534 * configure: Regenerated.
536 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
538 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
539 calls, conditional on the simulator being in verbose mode.
541 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
543 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
544 cache don't get ReservedInstruction traps.
546 1999-11-29 Mark Salter <msalter@cygnus.com>
548 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
549 to clear status bits in sdisr register. This is how the hardware works.
551 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
552 being used by cygmon.
554 1999-11-11 Andrew Haley <aph@cygnus.com>
556 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
559 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
561 * mips.igen (MULT): Correct previous mis-applied patch.
563 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
565 * mips.igen (delayslot32): Handle sequence like
566 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
567 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
568 (MULT): Actually pass the third register...
570 1999-09-03 Mark Salter <msalter@cygnus.com>
572 * interp.c (sim_open): Added more memory aliases for additional
573 hardware being touched by cygmon on jmr3904 board.
575 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
577 * configure: Regenerated to track ../common/aclocal.m4 changes.
579 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
581 * interp.c (sim_store_register): Handle case where client - GDB -
582 specifies that a 4 byte register is 8 bytes in size.
583 (sim_fetch_register): Ditto.
585 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
587 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
588 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
589 (idt_monitor_base): Base address for IDT monitor traps.
590 (pmon_monitor_base): Ditto for PMON.
591 (lsipmon_monitor_base): Ditto for LSI PMON.
592 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
593 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
594 (sim_firmware_command): New function.
595 (mips_option_handler): Call it for OPTION_FIRMWARE.
596 (sim_open): Allocate memory for idt_monitor region. If "--board"
597 option was given, add no monitor by default. Add BREAK hooks only if
598 monitors are also there.
600 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
602 * interp.c (sim_monitor): Flush output before reading input.
604 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
606 * tconfig.in (SIM_HANDLES_LMA): Always define.
608 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
610 From Mark Salter <msalter@cygnus.com>:
611 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
612 (sim_open): Add setup for BSP board.
614 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
616 * mips.igen (MULT, MULTU): Add syntax for two operand version.
617 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
618 them as unimplemented.
620 1999-05-08 Felix Lee <flee@cygnus.com>
622 * configure: Regenerated to track ../common/aclocal.m4 changes.
624 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
626 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
628 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
630 * configure.in: Any mips64vr5*-*-* target should have
631 -DTARGET_ENABLE_FR=1.
632 (default_endian): Any mips64vr*el-*-* target should default to
634 * configure: Re-generate.
636 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
638 * mips.igen (ldl): Extend from _16_, not 32.
640 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
642 * interp.c (sim_store_register): Force registers written to by GDB
643 into an un-interpreted state.
645 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
647 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
648 CPU, start periodic background I/O polls.
649 (tx3904sio_poll): New function: periodic I/O poller.
651 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
653 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
655 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
657 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
660 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
662 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
663 (load_word): Call SIM_CORE_SIGNAL hook on error.
664 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
665 starting. For exception dispatching, pass PC instead of NULL_CIA.
666 (decode_coproc): Use COP0_BADVADDR to store faulting address.
667 * sim-main.h (COP0_BADVADDR): Define.
668 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
669 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
670 (_sim_cpu): Add exc_* fields to store register value snapshots.
671 * mips.igen (*): Replace memory-related SignalException* calls
672 with references to SIM_CORE_SIGNAL hook.
674 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
676 * sim-main.c (*): Minor warning cleanups.
678 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
680 * m16.igen (DADDIU5): Correct type-o.
682 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
684 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
687 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
689 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
691 (interp.o): Add dependency on itable.h
692 (oengine.c, gencode): Delete remaining references.
693 (BUILT_SRC_FROM_GEN): Clean up.
695 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
698 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
699 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
701 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
702 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
703 Drop the "64" qualifier to get the HACK generator working.
704 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
705 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
706 qualifier to get the hack generator working.
707 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
709 (DSLLV): Use do_dsllv.
712 (DSRLV): Use do_dsrlv.
713 (BC1): Move *vr4100 to get the HACK generator working.
714 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
715 get the HACK generator working.
716 (MACC) Rename to get the HACK generator working.
717 (DMACC,MACCS,DMACCS): Add the 64.
719 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
721 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
722 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
724 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
726 * mips/interp.c (DEBUG): Cleanups.
728 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
730 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
731 (tx3904sio_tickle): fflush after a stdout character output.
733 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
735 * interp.c (sim_close): Uninstall modules.
737 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
739 * sim-main.h, interp.c (sim_monitor): Change to global
742 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
744 * configure.in (vr4100): Only include vr4100 instructions in
746 * configure: Re-generate.
747 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
749 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
751 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
752 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
755 * configure.in (sim_default_gen, sim_use_gen): Replace with
757 (--enable-sim-igen): Delete config option. Always using IGEN.
758 * configure: Re-generate.
760 * Makefile.in (gencode): Kill, kill, kill.
763 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
765 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
766 bit mips16 igen simulator.
767 * configure: Re-generate.
769 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
770 as part of vr4100 ISA.
771 * vr.igen: Mark all instructions as 64 bit only.
773 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
775 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
778 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
780 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
781 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
782 * configure: Re-generate.
784 * m16.igen (BREAK): Define breakpoint instruction.
785 (JALX32): Mark instruction as mips16 and not r3900.
786 * mips.igen (C.cond.fmt): Fix typo in instruction format.
788 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
790 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
792 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
793 insn as a debug breakpoint.
795 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
797 (PENDING_SCHED): Clean up trace statement.
798 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
799 (PENDING_FILL): Delay write by only one cycle.
800 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
802 * sim-main.c (pending_tick): Clean up trace statements. Add trace
804 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
806 (pending_tick): Move incrementing of index to FOR statement.
807 (pending_tick): Only update PENDING_OUT after a write has occured.
809 * configure.in: Add explicit mips-lsi-* target. Use gencode to
811 * configure: Re-generate.
813 * interp.c (sim_engine_run OLD): Delete explicit call to
814 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
816 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
818 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
819 interrupt level number to match changed SignalExceptionInterrupt
822 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
824 * interp.c: #include "itable.h" if WITH_IGEN.
825 (get_insn_name): New function.
826 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
827 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
829 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
831 * configure: Rebuilt to inhale new common/aclocal.m4.
833 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
835 * dv-tx3904sio.c: Include sim-assert.h.
837 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
839 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
840 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
841 Reorganize target-specific sim-hardware checks.
842 * configure: rebuilt.
843 * interp.c (sim_open): For tx39 target boards, set
844 OPERATING_ENVIRONMENT, add tx3904sio devices.
845 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
846 ROM executables. Install dv-sockser into sim-modules list.
848 * dv-tx3904irc.c: Compiler warning clean-up.
849 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
850 frequent hw-trace messages.
852 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
854 * vr.igen (MulAcc): Identify as a vr4100 specific function.
856 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
858 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
861 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
862 * mips.igen: Define vr4100 model. Include vr.igen.
863 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
865 * mips.igen (check_mf_hilo): Correct check.
867 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
869 * sim-main.h (interrupt_event): Add prototype.
871 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
872 register_ptr, register_value.
873 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
875 * sim-main.h (tracefh): Make extern.
877 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
879 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
880 Reduce unnecessarily high timer event frequency.
881 * dv-tx3904cpu.c: Ditto for interrupt event.
883 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
885 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
887 (interrupt_event): Made non-static.
889 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
890 interchange of configuration values for external vs. internal
893 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
895 * mips.igen (BREAK): Moved code to here for
896 simulator-reserved break instructions.
897 * gencode.c (build_instruction): Ditto.
898 * interp.c (signal_exception): Code moved from here. Non-
899 reserved instructions now use exception vector, rather
901 * sim-main.h: Moved magic constants to here.
903 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
905 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
906 register upon non-zero interrupt event level, clear upon zero
908 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
909 by passing zero event value.
910 (*_io_{read,write}_buffer): Endianness fixes.
911 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
912 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
914 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
915 serial I/O and timer module at base address 0xFFFF0000.
917 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
919 * mips.igen (SWC1) : Correct the handling of ReverseEndian
922 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
924 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
928 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
930 * dv-tx3904tmr.c: New file - implements tx3904 timer.
931 * dv-tx3904{irc,cpu}.c: Mild reformatting.
932 * configure.in: Include tx3904tmr in hw_device list.
933 * configure: Rebuilt.
934 * interp.c (sim_open): Instantiate three timer instances.
935 Fix address typo of tx3904irc instance.
937 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
939 * interp.c (signal_exception): SystemCall exception now uses
940 the exception vector.
942 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
944 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
947 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
949 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
951 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
953 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
955 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
956 sim-main.h. Declare a struct hw_descriptor instead of struct
957 hw_device_descriptor.
959 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
961 * mips.igen (do_store_left, do_load_left): Compute nr of left and
962 right bits and then re-align left hand bytes to correct byte
963 lanes. Fix incorrect computation in do_store_left when loading
964 bytes from second word.
966 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
968 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
969 * interp.c (sim_open): Only create a device tree when HW is
972 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
973 * interp.c (signal_exception): Ditto.
975 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
977 * gencode.c: Mark BEGEZALL as LIKELY.
979 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
981 * sim-main.h (ALU32_END): Sign extend 32 bit results.
982 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
984 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
986 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
987 modules. Recognize TX39 target with "mips*tx39" pattern.
988 * configure: Rebuilt.
989 * sim-main.h (*): Added many macros defining bits in
990 TX39 control registers.
991 (SignalInterrupt): Send actual PC instead of NULL.
992 (SignalNMIReset): New exception type.
993 * interp.c (board): New variable for future use to identify
994 a particular board being simulated.
995 (mips_option_handler,mips_options): Added "--board" option.
996 (interrupt_event): Send actual PC.
997 (sim_open): Make memory layout conditional on board setting.
998 (signal_exception): Initial implementation of hardware interrupt
999 handling. Accept another break instruction variant for simulator
1001 (decode_coproc): Implement RFE instruction for TX39.
1002 (mips.igen): Decode RFE instruction as such.
1003 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1004 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1005 bbegin to implement memory map.
1006 * dv-tx3904cpu.c: New file.
1007 * dv-tx3904irc.c: New file.
1009 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1011 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1013 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1015 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1016 with calls to check_div_hilo.
1018 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1020 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1021 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1022 Add special r3900 version of do_mult_hilo.
1023 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1024 with calls to check_mult_hilo.
1025 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1026 with calls to check_div_hilo.
1028 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1030 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1031 Document a replacement.
1033 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1035 * interp.c (sim_monitor): Make mon_printf work.
1037 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1039 * sim-main.h (INSN_NAME): New arg `cpu'.
1041 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1043 * configure: Regenerated to track ../common/aclocal.m4 changes.
1045 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1047 * configure: Regenerated to track ../common/aclocal.m4 changes.
1050 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1052 * acconfig.h: New file.
1053 * configure.in: Reverted change of Apr 24; use sinclude again.
1055 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1057 * configure: Regenerated to track ../common/aclocal.m4 changes.
1060 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1062 * configure.in: Don't call sinclude.
1064 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1066 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1068 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070 * mips.igen (ERET): Implement.
1072 * interp.c (decode_coproc): Return sign-extended EPC.
1074 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1076 * interp.c (signal_exception): Do not ignore Trap.
1077 (signal_exception): On TRAP, restart at exception address.
1078 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1079 (signal_exception): Update.
1080 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1081 so that TRAP instructions are caught.
1083 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1085 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1086 contains HI/LO access history.
1087 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1088 (HIACCESS, LOACCESS): Delete, replace with
1089 (HIHISTORY, LOHISTORY): New macros.
1090 (CHECKHILO): Delete all, moved to mips.igen
1092 * gencode.c (build_instruction): Do not generate checks for
1093 correct HI/LO register usage.
1095 * interp.c (old_engine_run): Delete checks for correct HI/LO
1098 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1099 check_mf_cycles): New functions.
1100 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1101 do_divu, domultx, do_mult, do_multu): Use.
1103 * tx.igen ("madd", "maddu"): Use.
1105 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1107 * mips.igen (DSRAV): Use function do_dsrav.
1108 (SRAV): Use new function do_srav.
1110 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1111 (B): Sign extend 11 bit immediate.
1112 (EXT-B*): Shift 16 bit immediate left by 1.
1113 (ADDIU*): Don't sign extend immediate value.
1115 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1117 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1119 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1122 * mips.igen (delayslot32, nullify_next_insn): New functions.
1123 (m16.igen): Always include.
1124 (do_*): Add more tracing.
1126 * m16.igen (delayslot16): Add NIA argument, could be called by a
1127 32 bit MIPS16 instruction.
1129 * interp.c (ifetch16): Move function from here.
1130 * sim-main.c (ifetch16): To here.
1132 * sim-main.c (ifetch16, ifetch32): Update to match current
1133 implementations of LH, LW.
1134 (signal_exception): Don't print out incorrect hex value of illegal
1137 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1139 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1142 * m16.igen: Implement MIPS16 instructions.
1144 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1145 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1146 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1147 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1148 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1149 bodies of corresponding code from 32 bit insn to these. Also used
1150 by MIPS16 versions of functions.
1152 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1153 (IMEM16): Drop NR argument from macro.
1155 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1157 * Makefile.in (SIM_OBJS): Add sim-main.o.
1159 * sim-main.h (address_translation, load_memory, store_memory,
1160 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1162 (pr_addr, pr_uword64): Declare.
1163 (sim-main.c): Include when H_REVEALS_MODULE_P.
1165 * interp.c (address_translation, load_memory, store_memory,
1166 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1168 * sim-main.c: To here. Fix compilation problems.
1170 * configure.in: Enable inlining.
1171 * configure: Re-config.
1173 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1175 * configure: Regenerated to track ../common/aclocal.m4 changes.
1177 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1179 * mips.igen: Include tx.igen.
1180 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1181 * tx.igen: New file, contains MADD and MADDU.
1183 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1184 the hardwired constant `7'.
1185 (store_memory): Ditto.
1186 (LOADDRMASK): Move definition to sim-main.h.
1188 mips.igen (MTC0): Enable for r3900.
1191 mips.igen (do_load_byte): Delete.
1192 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1193 do_store_right): New functions.
1194 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1196 configure.in: Let the tx39 use igen again.
1199 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1201 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1202 not an address sized quantity. Return zero for cache sizes.
1204 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1206 * mips.igen (r3900): r3900 does not support 64 bit integer
1209 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1211 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1213 * configure : Rebuild.
1215 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1217 * configure: Regenerated to track ../common/aclocal.m4 changes.
1219 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1221 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1223 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1225 * configure: Regenerated to track ../common/aclocal.m4 changes.
1226 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1228 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1230 * configure: Regenerated to track ../common/aclocal.m4 changes.
1232 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1234 * interp.c (Max, Min): Comment out functions. Not yet used.
1236 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1238 * configure: Regenerated to track ../common/aclocal.m4 changes.
1240 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1242 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1243 configurable settings for stand-alone simulator.
1245 * configure.in: Added X11 search, just in case.
1247 * configure: Regenerated.
1249 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1251 * interp.c (sim_write, sim_read, load_memory, store_memory):
1252 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1254 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1256 * sim-main.h (GETFCC): Return an unsigned value.
1258 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1260 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1261 (DADD): Result destination is RD not RT.
1263 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1265 * sim-main.h (HIACCESS, LOACCESS): Always define.
1267 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1269 * interp.c (sim_info): Delete.
1271 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1273 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1274 (mips_option_handler): New argument `cpu'.
1275 (sim_open): Update call to sim_add_option_table.
1277 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1279 * mips.igen (CxC1): Add tracing.
1281 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1283 * sim-main.h (Max, Min): Declare.
1285 * interp.c (Max, Min): New functions.
1287 * mips.igen (BC1): Add tracing.
1289 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1291 * interp.c Added memory map for stack in vr4100
1293 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1295 * interp.c (load_memory): Add missing "break"'s.
1297 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1299 * interp.c (sim_store_register, sim_fetch_register): Pass in
1300 length parameter. Return -1.
1302 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1304 * interp.c: Added hardware init hook, fixed warnings.
1306 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1308 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1310 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1312 * interp.c (ifetch16): New function.
1314 * sim-main.h (IMEM32): Rename IMEM.
1315 (IMEM16_IMMED): Define.
1317 (DELAY_SLOT): Update.
1319 * m16run.c (sim_engine_run): New file.
1321 * m16.igen: All instructions except LB.
1322 (LB): Call do_load_byte.
1323 * mips.igen (do_load_byte): New function.
1324 (LB): Call do_load_byte.
1326 * mips.igen: Move spec for insn bit size and high bit from here.
1327 * Makefile.in (tmp-igen, tmp-m16): To here.
1329 * m16.dc: New file, decode mips16 instructions.
1331 * Makefile.in (SIM_NO_ALL): Define.
1332 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1334 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1336 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1337 point unit to 32 bit registers.
1338 * configure: Re-generate.
1340 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1342 * configure.in (sim_use_gen): Make IGEN the default simulator
1343 generator for generic 32 and 64 bit mips targets.
1344 * configure: Re-generate.
1346 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1348 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1351 * interp.c (sim_fetch_register, sim_store_register): Read/write
1352 FGR from correct location.
1353 (sim_open): Set size of FGR's according to
1354 WITH_TARGET_FLOATING_POINT_BITSIZE.
1356 * sim-main.h (FGR): Store floating point registers in a separate
1359 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361 * configure: Regenerated to track ../common/aclocal.m4 changes.
1363 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1365 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1367 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1369 * interp.c (pending_tick): New function. Deliver pending writes.
1371 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1372 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1373 it can handle mixed sized quantites and single bits.
1375 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1377 * interp.c (oengine.h): Do not include when building with IGEN.
1378 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1379 (sim_info): Ditto for PROCESSOR_64BIT.
1380 (sim_monitor): Replace ut_reg with unsigned_word.
1381 (*): Ditto for t_reg.
1382 (LOADDRMASK): Define.
1383 (sim_open): Remove defunct check that host FP is IEEE compliant,
1384 using software to emulate floating point.
1385 (value_fpr, ...): Always compile, was conditional on HASFPU.
1387 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1389 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1392 * interp.c (SD, CPU): Define.
1393 (mips_option_handler): Set flags in each CPU.
1394 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1395 (sim_close): Do not clear STATE, deleted anyway.
1396 (sim_write, sim_read): Assume CPU zero's vm should be used for
1398 (sim_create_inferior): Set the PC for all processors.
1399 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1401 (mips16_entry): Pass correct nr of args to store_word, load_word.
1402 (ColdReset): Cold reset all cpu's.
1403 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1404 (sim_monitor, load_memory, store_memory, signal_exception): Use
1405 `CPU' instead of STATE_CPU.
1408 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1411 * sim-main.h (signal_exception): Add sim_cpu arg.
1412 (SignalException*): Pass both SD and CPU to signal_exception.
1413 * interp.c (signal_exception): Update.
1415 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1417 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1418 address_translation): Ditto
1419 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1421 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1423 * configure: Regenerated to track ../common/aclocal.m4 changes.
1425 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1427 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1429 * mips.igen (model): Map processor names onto BFD name.
1431 * sim-main.h (CPU_CIA): Delete.
1432 (SET_CIA, GET_CIA): Define
1434 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1436 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1439 * configure.in (default_endian): Configure a big-endian simulator
1441 * configure: Re-generate.
1443 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1445 * configure: Regenerated to track ../common/aclocal.m4 changes.
1447 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1449 * interp.c (sim_monitor): Handle Densan monitor outbyte
1450 and inbyte functions.
1452 1997-12-29 Felix Lee <flee@cygnus.com>
1454 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1456 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1458 * Makefile.in (tmp-igen): Arrange for $zero to always be
1459 reset to zero after every instruction.
1461 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463 * configure: Regenerated to track ../common/aclocal.m4 changes.
1466 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1468 * mips.igen (MSUB): Fix to work like MADD.
1469 * gencode.c (MSUB): Similarly.
1471 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1473 * configure: Regenerated to track ../common/aclocal.m4 changes.
1475 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1479 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1481 * sim-main.h (sim-fpu.h): Include.
1483 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1484 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1485 using host independant sim_fpu module.
1487 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489 * interp.c (signal_exception): Report internal errors with SIGABRT
1492 * sim-main.h (C0_CONFIG): New register.
1493 (signal.h): No longer include.
1495 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1497 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1499 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1501 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1503 * mips.igen: Tag vr5000 instructions.
1504 (ANDI): Was missing mipsIV model, fix assembler syntax.
1505 (do_c_cond_fmt): New function.
1506 (C.cond.fmt): Handle mips I-III which do not support CC field
1508 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1509 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1511 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1512 vr5000 which saves LO in a GPR separatly.
1514 * configure.in (enable-sim-igen): For vr5000, select vr5000
1515 specific instructions.
1516 * configure: Re-generate.
1518 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1520 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1522 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1523 fmt_uninterpreted_64 bit cases to switch. Convert to
1526 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1528 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1529 as specified in IV3.2 spec.
1530 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1532 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1534 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1535 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1536 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1537 PENDING_FILL versions of instructions. Simplify.
1539 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1541 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1543 (MTHI, MFHI): Disable code checking HI-LO.
1545 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1547 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1549 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1551 * gencode.c (build_mips16_operands): Replace IPC with cia.
1553 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1554 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1556 (UndefinedResult): Replace function with macro/function
1558 (sim_engine_run): Don't save PC in IPC.
1560 * sim-main.h (IPC): Delete.
1563 * interp.c (signal_exception, store_word, load_word,
1564 address_translation, load_memory, store_memory, cache_op,
1565 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1566 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1567 current instruction address - cia - argument.
1568 (sim_read, sim_write): Call address_translation directly.
1569 (sim_engine_run): Rename variable vaddr to cia.
1570 (signal_exception): Pass cia to sim_monitor
1572 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1573 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1574 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1576 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1577 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1580 * interp.c (signal_exception): Pass restart address to
1583 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1584 idecode.o): Add dependency.
1586 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1588 (DELAY_SLOT): Update NIA not PC with branch address.
1589 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1591 * mips.igen: Use CIA not PC in branch calculations.
1592 (illegal): Call SignalException.
1593 (BEQ, ADDIU): Fix assembler.
1595 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597 * m16.igen (JALX): Was missing.
1599 * configure.in (enable-sim-igen): New configuration option.
1600 * configure: Re-generate.
1602 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1604 * interp.c (load_memory, store_memory): Delete parameter RAW.
1605 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1606 bypassing {load,store}_memory.
1608 * sim-main.h (ByteSwapMem): Delete definition.
1610 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1612 * interp.c (sim_do_command, sim_commands): Delete mips specific
1613 commands. Handled by module sim-options.
1615 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1616 (WITH_MODULO_MEMORY): Define.
1618 * interp.c (sim_info): Delete code printing memory size.
1620 * interp.c (mips_size): Nee sim_size, delete function.
1622 (monitor, monitor_base, monitor_size): Delete global variables.
1623 (sim_open, sim_close): Delete code creating monitor and other
1624 memory regions. Use sim-memopts module, via sim_do_commandf, to
1625 manage memory regions.
1626 (load_memory, store_memory): Use sim-core for memory model.
1628 * interp.c (address_translation): Delete all memory map code
1629 except line forcing 32 bit addresses.
1631 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1636 * interp.c (logfh, logfile): Delete globals.
1637 (sim_open, sim_close): Delete code opening & closing log file.
1638 (mips_option_handler): Delete -l and -n options.
1639 (OPTION mips_options): Ditto.
1641 * interp.c (OPTION mips_options): Rename option trace to dinero.
1642 (mips_option_handler): Update.
1644 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1646 * interp.c (fetch_str): New function.
1647 (sim_monitor): Rewrite using sim_read & sim_write.
1648 (sim_open): Check magic number.
1649 (sim_open): Write monitor vectors into memory using sim_write.
1650 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1651 (sim_read, sim_write): Simplify - transfer data one byte at a
1653 (load_memory, store_memory): Clarify meaning of parameter RAW.
1655 * sim-main.h (isHOST): Defete definition.
1656 (isTARGET): Mark as depreciated.
1657 (address_translation): Delete parameter HOST.
1659 * interp.c (address_translation): Delete parameter HOST.
1661 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1665 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1666 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1668 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670 * mips.igen: Add model filter field to records.
1672 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1674 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1676 interp.c (sim_engine_run): Do not compile function sim_engine_run
1677 when WITH_IGEN == 1.
1679 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1680 target architecture.
1682 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1683 igen. Replace with configuration variables sim_igen_flags /
1686 * m16.igen: New file. Copy mips16 insns here.
1687 * mips.igen: From here.
1689 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1691 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1693 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1695 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1697 * gencode.c (build_instruction): Follow sim_write's lead in using
1698 BigEndianMem instead of !ByteSwapMem.
1700 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702 * configure.in (sim_gen): Dependent on target, select type of
1703 generator. Always select old style generator.
1705 configure: Re-generate.
1707 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1709 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1710 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1711 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1712 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1713 SIM_@sim_gen@_*, set by autoconf.
1715 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1719 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1720 CURRENT_FLOATING_POINT instead.
1722 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1723 (address_translation): Raise exception InstructionFetch when
1724 translation fails and isINSTRUCTION.
1726 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1727 sim_engine_run): Change type of of vaddr and paddr to
1729 (address_translation, prefetch, load_memory, store_memory,
1730 cache_op): Change type of vAddr and pAddr to address_word.
1732 * gencode.c (build_instruction): Change type of vaddr and paddr to
1735 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1738 macro to obtain result of ALU op.
1740 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1742 * interp.c (sim_info): Call profile_print.
1744 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1746 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1748 * sim-main.h (WITH_PROFILE): Do not define, defined in
1749 common/sim-config.h. Use sim-profile module.
1750 (simPROFILE): Delete defintion.
1752 * interp.c (PROFILE): Delete definition.
1753 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1754 (sim_close): Delete code writing profile histogram.
1755 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1757 (sim_engine_run): Delete code profiling the PC.
1759 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1763 * interp.c (sim_monitor): Make register pointers of type
1766 * sim-main.h: Make registers of type unsigned_word not
1769 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771 * interp.c (sync_operation): Rename from SyncOperation, make
1772 global, add SD argument.
1773 (prefetch): Rename from Prefetch, make global, add SD argument.
1774 (decode_coproc): Make global.
1776 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1778 * gencode.c (build_instruction): Generate DecodeCoproc not
1779 decode_coproc calls.
1781 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1782 (SizeFGR): Move to sim-main.h
1783 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1784 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1785 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1787 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1788 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1789 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1790 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1791 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1792 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1794 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1796 (sim-alu.h): Include.
1797 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1798 (sim_cia): Typedef to instruction_address.
1800 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1802 * Makefile.in (interp.o): Rename generated file engine.c to
1807 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1809 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1811 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1813 * gencode.c (build_instruction): For "FPSQRT", output correct
1814 number of arguments to Recip.
1816 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818 * Makefile.in (interp.o): Depends on sim-main.h
1820 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1822 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1823 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1824 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1825 STATE, DSSTATE): Define
1826 (GPR, FGRIDX, ..): Define.
1828 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1829 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1830 (GPR, FGRIDX, ...): Delete macros.
1832 * interp.c: Update names to match defines from sim-main.h
1834 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * interp.c (sim_monitor): Add SD argument.
1837 (sim_warning): Delete. Replace calls with calls to
1839 (sim_error): Delete. Replace calls with sim_io_error.
1840 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1841 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1842 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1844 (mips_size): Rename from sim_size. Add SD argument.
1846 * interp.c (simulator): Delete global variable.
1847 (callback): Delete global variable.
1848 (mips_option_handler, sim_open, sim_write, sim_read,
1849 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1850 sim_size,sim_monitor): Use sim_io_* not callback->*.
1851 (sim_open): ZALLOC simulator struct.
1852 (PROFILE): Do not define.
1854 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1856 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1857 support.h with corresponding code.
1859 * sim-main.h (word64, uword64), support.h: Move definition to
1861 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1864 * Makefile.in: Update dependencies
1865 * interp.c: Do not include.
1867 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1869 * interp.c (address_translation, load_memory, store_memory,
1870 cache_op): Rename to from AddressTranslation et.al., make global,
1873 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1876 * interp.c (SignalException): Rename to signal_exception, make
1879 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1881 * sim-main.h (SignalException, SignalExceptionInterrupt,
1882 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1883 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1884 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1887 * interp.c, support.h: Use.
1889 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1891 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1892 to value_fpr / store_fpr. Add SD argument.
1893 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1894 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1896 * sim-main.h (ValueFPR, StoreFPR): Define.
1898 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900 * interp.c (sim_engine_run): Check consistency between configure
1901 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1904 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1905 (mips_fpu): Configure WITH_FLOATING_POINT.
1906 (mips_endian): Configure WITH_TARGET_ENDIAN.
1907 * configure: Update.
1909 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1911 * configure: Regenerated to track ../common/aclocal.m4 changes.
1913 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1915 * configure: Regenerated.
1917 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1919 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1921 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1923 * gencode.c (print_igen_insn_models): Assume certain architectures
1924 include all mips* instructions.
1925 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1928 * Makefile.in (tmp.igen): Add target. Generate igen input from
1931 * gencode.c (FEATURE_IGEN): Define.
1932 (main): Add --igen option. Generate output in igen format.
1933 (process_instructions): Format output according to igen option.
1934 (print_igen_insn_format): New function.
1935 (print_igen_insn_models): New function.
1936 (process_instructions): Only issue warnings and ignore
1937 instructions when no FEATURE_IGEN.
1939 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1941 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1944 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1946 * configure: Regenerated to track ../common/aclocal.m4 changes.
1948 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1950 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1951 SIM_RESERVED_BITS): Delete, moved to common.
1952 (SIM_EXTRA_CFLAGS): Update.
1954 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1956 * configure.in: Configure non-strict memory alignment.
1957 * configure: Regenerated to track ../common/aclocal.m4 changes.
1959 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1961 * configure: Regenerated to track ../common/aclocal.m4 changes.
1963 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1965 * gencode.c (SDBBP,DERET): Added (3900) insns.
1966 (RFE): Turn on for 3900.
1967 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1968 (dsstate): Made global.
1969 (SUBTARGET_R3900): Added.
1970 (CANCELDELAYSLOT): New.
1971 (SignalException): Ignore SystemCall rather than ignore and
1972 terminate. Add DebugBreakPoint handling.
1973 (decode_coproc): New insns RFE, DERET; and new registers Debug
1974 and DEPC protected by SUBTARGET_R3900.
1975 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1977 * Makefile.in,configure.in: Add mips subtarget option.
1978 * configure: Update.
1980 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1982 * gencode.c: Add r3900 (tx39).
1985 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1987 * gencode.c (build_instruction): Don't need to subtract 4 for
1990 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1992 * interp.c: Correct some HASFPU problems.
1994 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1996 * configure: Regenerated to track ../common/aclocal.m4 changes.
1998 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2000 * interp.c (mips_options): Fix samples option short form, should
2003 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2005 * interp.c (sim_info): Enable info code. Was just returning.
2007 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2009 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2012 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2016 (build_instruction): Ditto for LL.
2018 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2020 * configure: Regenerated to track ../common/aclocal.m4 changes.
2022 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2024 * configure: Regenerated to track ../common/aclocal.m4 changes.
2027 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029 * interp.c (sim_open): Add call to sim_analyze_program, update
2032 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2034 * interp.c (sim_kill): Delete.
2035 (sim_create_inferior): Add ABFD argument. Set PC from same.
2036 (sim_load): Move code initializing trap handlers from here.
2037 (sim_open): To here.
2038 (sim_load): Delete, use sim-hload.c.
2040 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2042 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2044 * configure: Regenerated to track ../common/aclocal.m4 changes.
2047 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2049 * interp.c (sim_open): Add ABFD argument.
2050 (sim_load): Move call to sim_config from here.
2051 (sim_open): To here. Check return status.
2053 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2055 * gencode.c (build_instruction): Two arg MADD should
2056 not assign result to $0.
2058 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2060 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2061 * sim/mips/configure.in: Regenerate.
2063 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2065 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2066 signed8, unsigned8 et.al. types.
2068 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2069 hosts when selecting subreg.
2071 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2073 * interp.c (sim_engine_run): Reset the ZERO register to zero
2074 regardless of FEATURE_WARN_ZERO.
2075 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2077 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2079 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2080 (SignalException): For BreakPoints ignore any mode bits and just
2082 (SignalException): Always set the CAUSE register.
2084 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2086 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2087 exception has been taken.
2089 * interp.c: Implement the ERET and mt/f sr instructions.
2091 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093 * interp.c (SignalException): Don't bother restarting an
2096 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098 * interp.c (SignalException): Really take an interrupt.
2099 (interrupt_event): Only deliver interrupts when enabled.
2101 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103 * interp.c (sim_info): Only print info when verbose.
2104 (sim_info) Use sim_io_printf for output.
2106 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2108 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2111 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2113 * interp.c (sim_do_command): Check for common commands if a
2114 simulator specific command fails.
2116 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2118 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2119 and simBE when DEBUG is defined.
2121 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2123 * interp.c (interrupt_event): New function. Pass exception event
2124 onto exception handler.
2126 * configure.in: Check for stdlib.h.
2127 * configure: Regenerate.
2129 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2130 variable declaration.
2131 (build_instruction): Initialize memval1.
2132 (build_instruction): Add UNUSED attribute to byte, bigend,
2134 (build_operands): Ditto.
2136 * interp.c: Fix GCC warnings.
2137 (sim_get_quit_code): Delete.
2139 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2140 * Makefile.in: Ditto.
2141 * configure: Re-generate.
2143 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2145 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147 * interp.c (mips_option_handler): New function parse argumes using
2149 (myname): Replace with STATE_MY_NAME.
2150 (sim_open): Delete check for host endianness - performed by
2152 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2153 (sim_open): Move much of the initialization from here.
2154 (sim_load): To here. After the image has been loaded and
2156 (sim_open): Move ColdReset from here.
2157 (sim_create_inferior): To here.
2158 (sim_open): Make FP check less dependant on host endianness.
2160 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2162 * interp.c (sim_set_callbacks): Delete.
2164 * interp.c (membank, membank_base, membank_size): Replace with
2165 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2166 (sim_open): Remove call to callback->init. gdb/run do this.
2170 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2172 * interp.c (big_endian_p): Delete, replaced by
2173 current_target_byte_order.
2175 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2177 * interp.c (host_read_long, host_read_word, host_swap_word,
2178 host_swap_long): Delete. Using common sim-endian.
2179 (sim_fetch_register, sim_store_register): Use H2T.
2180 (pipeline_ticks): Delete. Handled by sim-events.
2182 (sim_engine_run): Update.
2184 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2186 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2188 (SignalException): To here. Signal using sim_engine_halt.
2189 (sim_stop_reason): Delete, moved to common.
2191 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2193 * interp.c (sim_open): Add callback argument.
2194 (sim_set_callbacks): Delete SIM_DESC argument.
2197 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2199 * Makefile.in (SIM_OBJS): Add common modules.
2201 * interp.c (sim_set_callbacks): Also set SD callback.
2202 (set_endianness, xfer_*, swap_*): Delete.
2203 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2204 Change to functions using sim-endian macros.
2205 (control_c, sim_stop): Delete, use common version.
2206 (simulate): Convert into.
2207 (sim_engine_run): This function.
2208 (sim_resume): Delete.
2210 * interp.c (simulation): New variable - the simulator object.
2211 (sim_kind): Delete global - merged into simulation.
2212 (sim_load): Cleanup. Move PC assignment from here.
2213 (sim_create_inferior): To here.
2215 * sim-main.h: New file.
2216 * interp.c (sim-main.h): Include.
2218 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2220 * configure: Regenerated to track ../common/aclocal.m4 changes.
2222 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2224 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2226 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2228 * gencode.c (build_instruction): DIV instructions: check
2229 for division by zero and integer overflow before using
2230 host's division operation.
2232 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2234 * Makefile.in (SIM_OBJS): Add sim-load.o.
2235 * interp.c: #include bfd.h.
2236 (target_byte_order): Delete.
2237 (sim_kind, myname, big_endian_p): New static locals.
2238 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2239 after argument parsing. Recognize -E arg, set endianness accordingly.
2240 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2241 load file into simulator. Set PC from bfd.
2242 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2243 (set_endianness): Use big_endian_p instead of target_byte_order.
2245 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2247 * interp.c (sim_size): Delete prototype - conflicts with
2248 definition in remote-sim.h. Correct definition.
2250 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2252 * configure: Regenerated to track ../common/aclocal.m4 changes.
2255 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2257 * interp.c (sim_open): New arg `kind'.
2259 * configure: Regenerated to track ../common/aclocal.m4 changes.
2261 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2263 * configure: Regenerated to track ../common/aclocal.m4 changes.
2265 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2267 * interp.c (sim_open): Set optind to 0 before calling getopt.
2269 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2271 * configure: Regenerated to track ../common/aclocal.m4 changes.
2273 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2275 * interp.c : Replace uses of pr_addr with pr_uword64
2276 where the bit length is always 64 independent of SIM_ADDR.
2277 (pr_uword64) : added.
2279 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2281 * configure: Re-generate.
2283 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2285 * configure: Regenerate to track ../common/aclocal.m4 changes.
2287 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2289 * interp.c (sim_open): New SIM_DESC result. Argument is now
2291 (other sim_*): New SIM_DESC argument.
2293 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2295 * interp.c: Fix printing of addresses for non-64-bit targets.
2296 (pr_addr): Add function to print address based on size.
2298 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2300 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2302 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2304 * gencode.c (build_mips16_operands): Correct computation of base
2305 address for extended PC relative instruction.
2307 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2309 * interp.c (mips16_entry): Add support for floating point cases.
2310 (SignalException): Pass floating point cases to mips16_entry.
2311 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2313 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2315 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2316 and then set the state to fmt_uninterpreted.
2317 (COP_SW): Temporarily set the state to fmt_word while calling
2320 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2322 * gencode.c (build_instruction): The high order may be set in the
2323 comparison flags at any ISA level, not just ISA 4.
2325 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2327 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2328 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2329 * configure.in: sinclude ../common/aclocal.m4.
2330 * configure: Regenerated.
2332 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2334 * configure: Rebuild after change to aclocal.m4.
2336 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2338 * configure configure.in Makefile.in: Update to new configure
2339 scheme which is more compatible with WinGDB builds.
2340 * configure.in: Improve comment on how to run autoconf.
2341 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2342 * Makefile.in: Use autoconf substitution to install common
2345 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2347 * gencode.c (build_instruction): Use BigEndianCPU instead of
2350 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2352 * interp.c (sim_monitor): Make output to stdout visible in
2353 wingdb's I/O log window.
2355 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2357 * support.h: Undo previous change to SIGTRAP
2360 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2362 * interp.c (store_word, load_word): New static functions.
2363 (mips16_entry): New static function.
2364 (SignalException): Look for mips16 entry and exit instructions.
2365 (simulate): Use the correct index when setting fpr_state after
2366 doing a pending move.
2368 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2370 * interp.c: Fix byte-swapping code throughout to work on
2371 both little- and big-endian hosts.
2373 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2375 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2376 with gdb/config/i386/xm-windows.h.
2378 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2380 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2381 that messes up arithmetic shifts.
2383 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2385 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2386 SIGTRAP and SIGQUIT for _WIN32.
2388 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2390 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2391 force a 64 bit multiplication.
2392 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2393 destination register is 0, since that is the default mips16 nop
2396 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2398 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2399 (build_endian_shift): Don't check proc64.
2400 (build_instruction): Always set memval to uword64. Cast op2 to
2401 uword64 when shifting it left in memory instructions. Always use
2402 the same code for stores--don't special case proc64.
2404 * gencode.c (build_mips16_operands): Fix base PC value for PC
2406 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2408 * interp.c (simJALDELAYSLOT): Define.
2409 (JALDELAYSLOT): Define.
2410 (INDELAYSLOT, INJALDELAYSLOT): Define.
2411 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2413 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2415 * interp.c (sim_open): add flush_cache as a PMON routine
2416 (sim_monitor): handle flush_cache by ignoring it
2418 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2420 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2422 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2423 (BigEndianMem): Rename to ByteSwapMem and change sense.
2424 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2425 BigEndianMem references to !ByteSwapMem.
2426 (set_endianness): New function, with prototype.
2427 (sim_open): Call set_endianness.
2428 (sim_info): Use simBE instead of BigEndianMem.
2429 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2430 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2431 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2432 ifdefs, keeping the prototype declaration.
2433 (swap_word): Rewrite correctly.
2434 (ColdReset): Delete references to CONFIG. Delete endianness related
2435 code; moved to set_endianness.
2437 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2439 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2440 * interp.c (CHECKHILO): Define away.
2441 (simSIGINT): New macro.
2442 (membank_size): Increase from 1MB to 2MB.
2443 (control_c): New function.
2444 (sim_resume): Rename parameter signal to signal_number. Add local
2445 variable prev. Call signal before and after simulate.
2446 (sim_stop_reason): Add simSIGINT support.
2447 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2449 (sim_warning): Delete call to SignalException. Do call printf_filtered
2451 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2452 a call to sim_warning.
2454 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2456 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2457 16 bit instructions.
2459 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2461 Add support for mips16 (16 bit MIPS implementation):
2462 * gencode.c (inst_type): Add mips16 instruction encoding types.
2463 (GETDATASIZEINSN): Define.
2464 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2465 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2467 (MIPS16_DECODE): New table, for mips16 instructions.
2468 (bitmap_val): New static function.
2469 (struct mips16_op): Define.
2470 (mips16_op_table): New table, for mips16 operands.
2471 (build_mips16_operands): New static function.
2472 (process_instructions): If PC is odd, decode a mips16
2473 instruction. Break out instruction handling into new
2474 build_instruction function.
2475 (build_instruction): New static function, broken out of
2476 process_instructions. Check modifiers rather than flags for SHIFT
2477 bit count and m[ft]{hi,lo} direction.
2478 (usage): Pass program name to fprintf.
2479 (main): Remove unused variable this_option_optind. Change
2480 ``*loptarg++'' to ``loptarg++''.
2481 (my_strtoul): Parenthesize && within ||.
2482 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2483 (simulate): If PC is odd, fetch a 16 bit instruction, and
2484 increment PC by 2 rather than 4.
2485 * configure.in: Add case for mips16*-*-*.
2486 * configure: Rebuild.
2488 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2490 * interp.c: Allow -t to enable tracing in standalone simulator.
2491 Fix garbage output in trace file and error messages.
2493 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2495 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2496 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2497 * configure.in: Simplify using macros in ../common/aclocal.m4.
2498 * configure: Regenerated.
2499 * tconfig.in: New file.
2501 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2503 * interp.c: Fix bugs in 64-bit port.
2504 Use ansi function declarations for msvc compiler.
2505 Initialize and test file pointer in trace code.
2506 Prevent duplicate definition of LAST_EMED_REGNUM.
2508 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2510 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2512 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2514 * interp.c (SignalException): Check for explicit terminating
2516 * gencode.c: Pass instruction value through SignalException()
2517 calls for Trap, Breakpoint and Syscall.
2519 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2521 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2522 only used on those hosts that provide it.
2523 * configure.in: Add sqrt() to list of functions to be checked for.
2524 * config.in: Re-generated.
2525 * configure: Re-generated.
2527 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2529 * gencode.c (process_instructions): Call build_endian_shift when
2530 expanding STORE RIGHT, to fix swr.
2531 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2532 clear the high bits.
2533 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2534 Fix float to int conversions to produce signed values.
2536 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2538 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2539 (process_instructions): Correct handling of nor instruction.
2540 Correct shift count for 32 bit shift instructions. Correct sign
2541 extension for arithmetic shifts to not shift the number of bits in
2542 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2543 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2545 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2546 It's OK to have a mult follow a mult. What's not OK is to have a
2547 mult follow an mfhi.
2548 (Convert): Comment out incorrect rounding code.
2550 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2552 * interp.c (sim_monitor): Improved monitor printf
2553 simulation. Tidied up simulator warnings, and added "--log" option
2554 for directing warning message output.
2555 * gencode.c: Use sim_warning() rather than WARNING macro.
2557 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2559 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2560 getopt1.o, rather than on gencode.c. Link objects together.
2561 Don't link against -liberty.
2562 (gencode.o, getopt.o, getopt1.o): New targets.
2563 * gencode.c: Include <ctype.h> and "ansidecl.h".
2564 (AND): Undefine after including "ansidecl.h".
2565 (ULONG_MAX): Define if not defined.
2566 (OP_*): Don't define macros; now defined in opcode/mips.h.
2567 (main): Call my_strtoul rather than strtoul.
2568 (my_strtoul): New static function.
2570 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2572 * gencode.c (process_instructions): Generate word64 and uword64
2573 instead of `long long' and `unsigned long long' data types.
2574 * interp.c: #include sysdep.h to get signals, and define default
2576 * (Convert): Work around for Visual-C++ compiler bug with type
2578 * support.h: Make things compile under Visual-C++ by using
2579 __int64 instead of `long long'. Change many refs to long long
2580 into word64/uword64 typedefs.
2582 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2584 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2585 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2587 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2588 (AC_PROG_INSTALL): Added.
2589 (AC_PROG_CC): Moved to before configure.host call.
2590 * configure: Rebuilt.
2592 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2594 * configure.in: Define @SIMCONF@ depending on mips target.
2595 * configure: Rebuild.
2596 * Makefile.in (run): Add @SIMCONF@ to control simulator
2598 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2599 * interp.c: Remove some debugging, provide more detailed error
2600 messages, update memory accesses to use LOADDRMASK.
2602 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2604 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2605 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2607 * configure: Rebuild.
2608 * config.in: New file, generated by autoheader.
2609 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2610 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2611 HAVE_ANINT and HAVE_AINT, as appropriate.
2612 * Makefile.in (run): Use @LIBS@ rather than -lm.
2613 (interp.o): Depend upon config.h.
2614 (Makefile): Just rebuild Makefile.
2615 (clean): Remove stamp-h.
2616 (mostlyclean): Make the same as clean, not as distclean.
2617 (config.h, stamp-h): New targets.
2619 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2621 * interp.c (ColdReset): Fix boolean test. Make all simulator
2624 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2626 * interp.c (xfer_direct_word, xfer_direct_long,
2627 swap_direct_word, swap_direct_long, xfer_big_word,
2628 xfer_big_long, xfer_little_word, xfer_little_long,
2629 swap_word,swap_long): Added.
2630 * interp.c (ColdReset): Provide function indirection to
2631 host<->simulated_target transfer routines.
2632 * interp.c (sim_store_register, sim_fetch_register): Updated to
2633 make use of indirected transfer routines.
2635 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2637 * gencode.c (process_instructions): Ensure FP ABS instruction
2639 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2640 system call support.
2642 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2644 * interp.c (sim_do_command): Complain if callback structure not
2647 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2649 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2650 support for Sun hosts.
2651 * Makefile.in (gencode): Ensure the host compiler and libraries
2652 used for cross-hosted build.
2654 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2656 * interp.c, gencode.c: Some more (TODO) tidying.
2658 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2660 * gencode.c, interp.c: Replaced explicit long long references with
2661 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2662 * support.h (SET64LO, SET64HI): Macros added.
2664 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2666 * configure: Regenerate with autoconf 2.7.
2668 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2670 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2671 * support.h: Remove superfluous "1" from #if.
2672 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2674 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2676 * interp.c (StoreFPR): Control UndefinedResult() call on
2677 WARN_RESULT manifest.
2679 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2681 * gencode.c: Tidied instruction decoding, and added FP instruction
2684 * interp.c: Added dineroIII, and BSD profiling support. Also
2685 run-time FP handling.
2687 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2689 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2690 gencode.c, interp.c, support.h: created.