1 2002-06-04 Chris Demetriou <cgd@broadcom.com>
2 Ed Satterthwaite <ehs@broadcom.com>
4 * cp1.c (Infinity): Remove.
5 * sim-main.h (Infinity): Likewise.
7 * cp1.c (fp_unary, fp_binary): New functions.
8 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
9 (fp_sqrt): New functions, implemented in terms of the above.
10 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
11 (Recip, SquareRoot): Remove (replaced by functions above).
12 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
13 (fp_recip, fp_sqrt): New prototypes.
14 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
15 (Recip, SquareRoot): Replace prototypes with #defines which
16 invoke the functions above.
18 2002-06-03 Chris Demetriou <cgd@broadcom.com>
20 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
21 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
22 file, remove PARAMS from prototypes.
23 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
24 simulator state arguments.
25 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
26 pass simulator state arguments.
27 * cp1.c (SD): Redefine as CPU_STATE(cpu).
28 (store_fpr, convert): Remove 'sd' argument.
29 (value_fpr): Likewise. Convert to use 'SD' instead.
31 2002-06-03 Chris Demetriou <cgd@broadcom.com>
33 * cp1.c (Min, Max): Remove #if 0'd functions.
34 * sim-main.h (Min, Max): Remove.
36 2002-06-03 Chris Demetriou <cgd@broadcom.com>
38 * cp1.c: fix formatting of switch case and default labels.
40 * sim-main.c: Likewise.
42 2002-06-03 Chris Demetriou <cgd@broadcom.com>
44 * cp1.c: Clean up comments which describe FP formats.
45 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
47 2002-06-03 Chris Demetriou <cgd@broadcom.com>
48 Ed Satterthwaite <ehs@broadcom.com>
50 * configure.in (mipsisa64sb1*-*-*): New target for supporting
51 Broadcom SiByte SB-1 processor configurations.
52 * configure: Regenerate.
54 * mips.igen: Include sb1.igen.
56 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
57 * mdmx.igen: Add "sb1" model to all appropriate functions and
59 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
60 (ob_func, ob_acc): Reference the above.
61 (qh_acc): Adjust to keep the same size as ob_acc.
62 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
63 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
65 2002-06-03 Chris Demetriou <cgd@broadcom.com>
67 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
69 2002-06-02 Chris Demetriou <cgd@broadcom.com>
70 Ed Satterthwaite <ehs@broadcom.com>
72 * mips.igen (mdmx): New (pseudo-)model.
73 * mdmx.c, mdmx.igen: New files.
74 * Makefile.in (SIM_OBJS): Add mdmx.o.
75 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
77 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
78 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
79 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
80 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
81 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
82 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
83 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
84 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
85 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
86 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
87 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
88 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
89 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
90 (qh_fmtsel): New macros.
91 (_sim_cpu): New member "acc".
92 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
93 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
95 2002-05-01 Chris Demetriou <cgd@broadcom.com>
97 * interp.c: Use 'deprecated' rather than 'depreciated.'
98 * sim-main.h: Likewise.
100 2002-05-01 Chris Demetriou <cgd@broadcom.com>
102 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
103 which wouldn't compile anyway.
104 * sim-main.h (unpredictable_action): New function prototype.
105 (Unpredictable): Define to call igen function unpredictable().
106 (NotWordValue): New macro to call igen function not_word_value().
107 (UndefinedResult): Remove.
108 * interp.c (undefined_result): Remove.
109 (unpredictable_action): New function.
110 * mips.igen (not_word_value, unpredictable): New functions.
111 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
112 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
113 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
114 NotWordValue() to check for unpredictable inputs, then
115 Unpredictable() to handle them.
117 2002-02-24 Chris Demetriou <cgd@broadcom.com>
119 * mips.igen: Fix formatting of calls to Unpredictable().
121 2002-04-20 Andrew Cagney <ac131313@redhat.com>
123 * interp.c (sim_open): Revert previous change.
125 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
127 * interp.c (sim_open): Disable chunk of code that wrote code in
128 vector table entries.
130 2002-03-19 Chris Demetriou <cgd@broadcom.com>
132 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
133 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
136 2002-03-19 Chris Demetriou <cgd@broadcom.com>
138 * cp1.c: Fix many formatting issues.
140 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
142 * cp1.c (fpu_format_name): New function to replace...
143 (DOFMT): This. Delete, and update all callers.
144 (fpu_rounding_mode_name): New function to replace...
145 (RMMODE): This. Delete, and update all callers.
147 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
149 * interp.c: Move FPU support routines from here to...
150 * cp1.c: Here. New file.
151 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
154 2002-03-12 Chris Demetriou <cgd@broadcom.com>
156 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
157 * mips.igen (mips32, mips64): New models, add to all instructions
158 and functions as appropriate.
159 (loadstore_ea, check_u64): New variant for model mips64.
160 (check_fmt_p): New variant for models mipsV and mips64, remove
161 mipsV model marking fro other variant.
164 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
165 for mips32 and mips64.
166 (DCLO, DCLZ): New instructions for mips64.
168 2002-03-07 Chris Demetriou <cgd@broadcom.com>
170 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
171 immediate or code as a hex value with the "%#lx" format.
172 (ANDI): Likewise, and fix printed instruction name.
174 2002-03-05 Chris Demetriou <cgd@broadcom.com>
176 * sim-main.h (UndefinedResult, Unpredictable): New macros
177 which currently do nothing.
179 2002-03-05 Chris Demetriou <cgd@broadcom.com>
181 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
182 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
183 (status_CU3): New definitions.
185 * sim-main.h (ExceptionCause): Add new values for MIPS32
186 and MIPS64: MDMX, MCheck, CacheErr. Update comments
187 for DebugBreakPoint and NMIReset to note their status in
189 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
190 (SignalExceptionCacheErr): New exception macros.
192 2002-03-05 Chris Demetriou <cgd@broadcom.com>
194 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
195 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
197 (SignalExceptionCoProcessorUnusable): Take as argument the
198 unusable coprocessor number.
200 2002-03-05 Chris Demetriou <cgd@broadcom.com>
202 * mips.igen: Fix formatting of all SignalException calls.
204 2002-03-05 Chris Demetriou <cgd@broadcom.com>
206 * sim-main.h (SIGNEXTEND): Remove.
208 2002-03-04 Chris Demetriou <cgd@broadcom.com>
210 * mips.igen: Remove gencode comment from top of file, fix
211 spelling in another comment.
213 2002-03-04 Chris Demetriou <cgd@broadcom.com>
215 * mips.igen (check_fmt, check_fmt_p): New functions to check
216 whether specific floating point formats are usable.
217 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
218 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
219 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
220 Use the new functions.
221 (do_c_cond_fmt): Remove format checks...
222 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
224 2002-03-03 Chris Demetriou <cgd@broadcom.com>
226 * mips.igen: Fix formatting of check_fpu calls.
228 2002-03-03 Chris Demetriou <cgd@broadcom.com>
230 * mips.igen (FLOOR.L.fmt): Store correct destination register.
232 2002-03-03 Chris Demetriou <cgd@broadcom.com>
234 * mips.igen: Remove whitespace at end of lines.
236 2002-03-02 Chris Demetriou <cgd@broadcom.com>
238 * mips.igen (loadstore_ea): New function to do effective
239 address calculations.
240 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
241 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
242 CACHE): Use loadstore_ea to do effective address computations.
244 2002-03-02 Chris Demetriou <cgd@broadcom.com>
246 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
247 * mips.igen (LL, CxC1, MxC1): Likewise.
249 2002-03-02 Chris Demetriou <cgd@broadcom.com>
251 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
252 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
253 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
254 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
255 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
256 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
257 Don't split opcode fields by hand, use the opcode field values
260 2002-03-01 Chris Demetriou <cgd@broadcom.com>
262 * mips.igen (do_divu): Fix spacing.
264 * mips.igen (do_dsllv): Move to be right before DSLLV,
265 to match the rest of the do_<shift> functions.
267 2002-03-01 Chris Demetriou <cgd@broadcom.com>
269 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
270 DSRL32, do_dsrlv): Trace inputs and results.
272 2002-03-01 Chris Demetriou <cgd@broadcom.com>
274 * mips.igen (CACHE): Provide instruction-printing string.
276 * interp.c (signal_exception): Comment tokens after #endif.
278 2002-02-28 Chris Demetriou <cgd@broadcom.com>
280 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
281 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
282 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
283 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
284 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
285 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
286 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
287 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
289 2002-02-28 Chris Demetriou <cgd@broadcom.com>
291 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
292 instruction-printing string.
293 (LWU): Use '64' as the filter flag.
295 2002-02-28 Chris Demetriou <cgd@broadcom.com>
297 * mips.igen (SDXC1): Fix instruction-printing string.
299 2002-02-28 Chris Demetriou <cgd@broadcom.com>
301 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
304 2002-02-27 Chris Demetriou <cgd@broadcom.com>
306 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
309 2002-02-27 Chris Demetriou <cgd@broadcom.com>
311 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
312 add a comma) so that it more closely match the MIPS ISA
313 documentation opcode partitioning.
314 (PREF): Put useful names on opcode fields, and include
315 instruction-printing string.
317 2002-02-27 Chris Demetriou <cgd@broadcom.com>
319 * mips.igen (check_u64): New function which in the future will
320 check whether 64-bit instructions are usable and signal an
321 exception if not. Currently a no-op.
322 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
323 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
324 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
325 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
327 * mips.igen (check_fpu): New function which in the future will
328 check whether FPU instructions are usable and signal an exception
329 if not. Currently a no-op.
330 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
331 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
332 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
333 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
334 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
335 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
336 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
337 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
339 2002-02-27 Chris Demetriou <cgd@broadcom.com>
341 * mips.igen (do_load_left, do_load_right): Move to be immediately
343 (do_store_left, do_store_right): Move to be immediately following
346 2002-02-27 Chris Demetriou <cgd@broadcom.com>
348 * mips.igen (mipsV): New model name. Also, add it to
349 all instructions and functions where it is appropriate.
351 2002-02-18 Chris Demetriou <cgd@broadcom.com>
353 * mips.igen: For all functions and instructions, list model
354 names that support that instruction one per line.
356 2002-02-11 Chris Demetriou <cgd@broadcom.com>
358 * mips.igen: Add some additional comments about supported
359 models, and about which instructions go where.
360 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
361 order as is used in the rest of the file.
363 2002-02-11 Chris Demetriou <cgd@broadcom.com>
365 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
366 indicating that ALU32_END or ALU64_END are there to check
368 (DADD): Likewise, but also remove previous comment about
371 2002-02-10 Chris Demetriou <cgd@broadcom.com>
373 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
374 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
375 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
376 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
377 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
378 fields (i.e., add and move commas) so that they more closely
379 match the MIPS ISA documentation opcode partitioning.
381 2002-02-10 Chris Demetriou <cgd@broadcom.com>
383 * mips.igen (ADDI): Print immediate value.
385 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
386 (SLL): Print "nop" specially, and don't run the code
387 that does the shift for the "nop" case.
389 2001-11-17 Fred Fish <fnf@redhat.com>
391 * sim-main.h (float_operation): Move enum declaration outside
392 of _sim_cpu struct declaration.
394 2001-04-12 Jim Blandy <jimb@redhat.com>
396 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
397 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
399 * sim-main.h (COCIDX): Remove definition; this isn't supported by
400 PENDING_FILL, and you can get the intended effect gracefully by
401 calling PENDING_SCHED directly.
403 2001-02-23 Ben Elliston <bje@redhat.com>
405 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
406 already defined elsewhere.
408 2001-02-19 Ben Elliston <bje@redhat.com>
410 * sim-main.h (sim_monitor): Return an int.
411 * interp.c (sim_monitor): Add return values.
412 (signal_exception): Handle error conditions from sim_monitor.
414 2001-02-08 Ben Elliston <bje@redhat.com>
416 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
417 (store_memory): Likewise, pass cia to sim_core_write*.
419 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
421 On advice from Chris G. Demetriou <cgd@sibyte.com>:
422 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
424 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
426 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
427 * Makefile.in: Don't delete *.igen when cleaning directory.
429 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
431 * m16.igen (break): Call SignalException not sim_engine_halt.
433 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
436 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
438 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
440 * mips.igen (MxC1, DMxC1): Fix printf formatting.
442 2000-05-24 Michael Hayes <mhayes@cygnus.com>
444 * mips.igen (do_dmultx): Fix typo.
446 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
448 * configure: Regenerated to track ../common/aclocal.m4 changes.
450 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
452 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
454 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
456 * sim-main.h (GPR_CLEAR): Define macro.
458 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
460 * interp.c (decode_coproc): Output long using %lx and not %s.
462 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
464 * interp.c (sim_open): Sort & extend dummy memory regions for
465 --board=jmr3904 for eCos.
467 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
469 * configure: Regenerated.
471 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
473 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
474 calls, conditional on the simulator being in verbose mode.
476 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
478 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
479 cache don't get ReservedInstruction traps.
481 1999-11-29 Mark Salter <msalter@cygnus.com>
483 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
484 to clear status bits in sdisr register. This is how the hardware works.
486 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
487 being used by cygmon.
489 1999-11-11 Andrew Haley <aph@cygnus.com>
491 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
494 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
496 * mips.igen (MULT): Correct previous mis-applied patch.
498 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
500 * mips.igen (delayslot32): Handle sequence like
501 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
502 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
503 (MULT): Actually pass the third register...
505 1999-09-03 Mark Salter <msalter@cygnus.com>
507 * interp.c (sim_open): Added more memory aliases for additional
508 hardware being touched by cygmon on jmr3904 board.
510 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
512 * configure: Regenerated to track ../common/aclocal.m4 changes.
514 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
516 * interp.c (sim_store_register): Handle case where client - GDB -
517 specifies that a 4 byte register is 8 bytes in size.
518 (sim_fetch_register): Ditto.
520 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
522 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
523 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
524 (idt_monitor_base): Base address for IDT monitor traps.
525 (pmon_monitor_base): Ditto for PMON.
526 (lsipmon_monitor_base): Ditto for LSI PMON.
527 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
528 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
529 (sim_firmware_command): New function.
530 (mips_option_handler): Call it for OPTION_FIRMWARE.
531 (sim_open): Allocate memory for idt_monitor region. If "--board"
532 option was given, add no monitor by default. Add BREAK hooks only if
533 monitors are also there.
535 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
537 * interp.c (sim_monitor): Flush output before reading input.
539 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
541 * tconfig.in (SIM_HANDLES_LMA): Always define.
543 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
545 From Mark Salter <msalter@cygnus.com>:
546 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
547 (sim_open): Add setup for BSP board.
549 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
551 * mips.igen (MULT, MULTU): Add syntax for two operand version.
552 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
553 them as unimplemented.
555 1999-05-08 Felix Lee <flee@cygnus.com>
557 * configure: Regenerated to track ../common/aclocal.m4 changes.
559 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
561 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
563 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
565 * configure.in: Any mips64vr5*-*-* target should have
566 -DTARGET_ENABLE_FR=1.
567 (default_endian): Any mips64vr*el-*-* target should default to
569 * configure: Re-generate.
571 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
573 * mips.igen (ldl): Extend from _16_, not 32.
575 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
577 * interp.c (sim_store_register): Force registers written to by GDB
578 into an un-interpreted state.
580 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
582 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
583 CPU, start periodic background I/O polls.
584 (tx3904sio_poll): New function: periodic I/O poller.
586 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
588 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
590 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
592 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
595 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
597 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
598 (load_word): Call SIM_CORE_SIGNAL hook on error.
599 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
600 starting. For exception dispatching, pass PC instead of NULL_CIA.
601 (decode_coproc): Use COP0_BADVADDR to store faulting address.
602 * sim-main.h (COP0_BADVADDR): Define.
603 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
604 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
605 (_sim_cpu): Add exc_* fields to store register value snapshots.
606 * mips.igen (*): Replace memory-related SignalException* calls
607 with references to SIM_CORE_SIGNAL hook.
609 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
611 * sim-main.c (*): Minor warning cleanups.
613 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
615 * m16.igen (DADDIU5): Correct type-o.
617 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
619 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
622 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
624 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
626 (interp.o): Add dependency on itable.h
627 (oengine.c, gencode): Delete remaining references.
628 (BUILT_SRC_FROM_GEN): Clean up.
630 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
633 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
634 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
636 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
637 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
638 Drop the "64" qualifier to get the HACK generator working.
639 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
640 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
641 qualifier to get the hack generator working.
642 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
644 (DSLLV): Use do_dsllv.
647 (DSRLV): Use do_dsrlv.
648 (BC1): Move *vr4100 to get the HACK generator working.
649 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
650 get the HACK generator working.
651 (MACC) Rename to get the HACK generator working.
652 (DMACC,MACCS,DMACCS): Add the 64.
654 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
656 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
657 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
659 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
661 * mips/interp.c (DEBUG): Cleanups.
663 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
665 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
666 (tx3904sio_tickle): fflush after a stdout character output.
668 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
670 * interp.c (sim_close): Uninstall modules.
672 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
674 * sim-main.h, interp.c (sim_monitor): Change to global
677 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
679 * configure.in (vr4100): Only include vr4100 instructions in
681 * configure: Re-generate.
682 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
684 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
686 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
687 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
690 * configure.in (sim_default_gen, sim_use_gen): Replace with
692 (--enable-sim-igen): Delete config option. Always using IGEN.
693 * configure: Re-generate.
695 * Makefile.in (gencode): Kill, kill, kill.
698 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
700 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
701 bit mips16 igen simulator.
702 * configure: Re-generate.
704 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
705 as part of vr4100 ISA.
706 * vr.igen: Mark all instructions as 64 bit only.
708 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
710 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
713 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
715 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
716 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
717 * configure: Re-generate.
719 * m16.igen (BREAK): Define breakpoint instruction.
720 (JALX32): Mark instruction as mips16 and not r3900.
721 * mips.igen (C.cond.fmt): Fix typo in instruction format.
723 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
725 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
727 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
728 insn as a debug breakpoint.
730 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
732 (PENDING_SCHED): Clean up trace statement.
733 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
734 (PENDING_FILL): Delay write by only one cycle.
735 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
737 * sim-main.c (pending_tick): Clean up trace statements. Add trace
739 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
741 (pending_tick): Move incrementing of index to FOR statement.
742 (pending_tick): Only update PENDING_OUT after a write has occured.
744 * configure.in: Add explicit mips-lsi-* target. Use gencode to
746 * configure: Re-generate.
748 * interp.c (sim_engine_run OLD): Delete explicit call to
749 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
751 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
753 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
754 interrupt level number to match changed SignalExceptionInterrupt
757 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
759 * interp.c: #include "itable.h" if WITH_IGEN.
760 (get_insn_name): New function.
761 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
762 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
764 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
766 * configure: Rebuilt to inhale new common/aclocal.m4.
768 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
770 * dv-tx3904sio.c: Include sim-assert.h.
772 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
774 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
775 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
776 Reorganize target-specific sim-hardware checks.
777 * configure: rebuilt.
778 * interp.c (sim_open): For tx39 target boards, set
779 OPERATING_ENVIRONMENT, add tx3904sio devices.
780 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
781 ROM executables. Install dv-sockser into sim-modules list.
783 * dv-tx3904irc.c: Compiler warning clean-up.
784 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
785 frequent hw-trace messages.
787 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
789 * vr.igen (MulAcc): Identify as a vr4100 specific function.
791 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
793 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
796 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
797 * mips.igen: Define vr4100 model. Include vr.igen.
798 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
800 * mips.igen (check_mf_hilo): Correct check.
802 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
804 * sim-main.h (interrupt_event): Add prototype.
806 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
807 register_ptr, register_value.
808 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
810 * sim-main.h (tracefh): Make extern.
812 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
814 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
815 Reduce unnecessarily high timer event frequency.
816 * dv-tx3904cpu.c: Ditto for interrupt event.
818 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
820 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
822 (interrupt_event): Made non-static.
824 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
825 interchange of configuration values for external vs. internal
828 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
830 * mips.igen (BREAK): Moved code to here for
831 simulator-reserved break instructions.
832 * gencode.c (build_instruction): Ditto.
833 * interp.c (signal_exception): Code moved from here. Non-
834 reserved instructions now use exception vector, rather
836 * sim-main.h: Moved magic constants to here.
838 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
840 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
841 register upon non-zero interrupt event level, clear upon zero
843 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
844 by passing zero event value.
845 (*_io_{read,write}_buffer): Endianness fixes.
846 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
847 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
849 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
850 serial I/O and timer module at base address 0xFFFF0000.
852 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
854 * mips.igen (SWC1) : Correct the handling of ReverseEndian
857 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
859 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
863 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
865 * dv-tx3904tmr.c: New file - implements tx3904 timer.
866 * dv-tx3904{irc,cpu}.c: Mild reformatting.
867 * configure.in: Include tx3904tmr in hw_device list.
868 * configure: Rebuilt.
869 * interp.c (sim_open): Instantiate three timer instances.
870 Fix address typo of tx3904irc instance.
872 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
874 * interp.c (signal_exception): SystemCall exception now uses
875 the exception vector.
877 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
879 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
882 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
884 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
886 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
888 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
890 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
891 sim-main.h. Declare a struct hw_descriptor instead of struct
892 hw_device_descriptor.
894 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
896 * mips.igen (do_store_left, do_load_left): Compute nr of left and
897 right bits and then re-align left hand bytes to correct byte
898 lanes. Fix incorrect computation in do_store_left when loading
899 bytes from second word.
901 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
903 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
904 * interp.c (sim_open): Only create a device tree when HW is
907 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
908 * interp.c (signal_exception): Ditto.
910 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
912 * gencode.c: Mark BEGEZALL as LIKELY.
914 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
916 * sim-main.h (ALU32_END): Sign extend 32 bit results.
917 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
919 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
921 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
922 modules. Recognize TX39 target with "mips*tx39" pattern.
923 * configure: Rebuilt.
924 * sim-main.h (*): Added many macros defining bits in
925 TX39 control registers.
926 (SignalInterrupt): Send actual PC instead of NULL.
927 (SignalNMIReset): New exception type.
928 * interp.c (board): New variable for future use to identify
929 a particular board being simulated.
930 (mips_option_handler,mips_options): Added "--board" option.
931 (interrupt_event): Send actual PC.
932 (sim_open): Make memory layout conditional on board setting.
933 (signal_exception): Initial implementation of hardware interrupt
934 handling. Accept another break instruction variant for simulator
936 (decode_coproc): Implement RFE instruction for TX39.
937 (mips.igen): Decode RFE instruction as such.
938 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
939 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
940 bbegin to implement memory map.
941 * dv-tx3904cpu.c: New file.
942 * dv-tx3904irc.c: New file.
944 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
946 * mips.igen (check_mt_hilo): Create a separate r3900 version.
948 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
950 * tx.igen (madd,maddu): Replace calls to check_op_hilo
951 with calls to check_div_hilo.
953 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
955 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
956 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
957 Add special r3900 version of do_mult_hilo.
958 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
959 with calls to check_mult_hilo.
960 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
961 with calls to check_div_hilo.
963 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
965 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
966 Document a replacement.
968 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
970 * interp.c (sim_monitor): Make mon_printf work.
972 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
974 * sim-main.h (INSN_NAME): New arg `cpu'.
976 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
978 * configure: Regenerated to track ../common/aclocal.m4 changes.
980 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
982 * configure: Regenerated to track ../common/aclocal.m4 changes.
985 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
987 * acconfig.h: New file.
988 * configure.in: Reverted change of Apr 24; use sinclude again.
990 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
992 * configure: Regenerated to track ../common/aclocal.m4 changes.
995 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
997 * configure.in: Don't call sinclude.
999 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1001 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1003 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1005 * mips.igen (ERET): Implement.
1007 * interp.c (decode_coproc): Return sign-extended EPC.
1009 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1011 * interp.c (signal_exception): Do not ignore Trap.
1012 (signal_exception): On TRAP, restart at exception address.
1013 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1014 (signal_exception): Update.
1015 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1016 so that TRAP instructions are caught.
1018 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1020 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1021 contains HI/LO access history.
1022 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1023 (HIACCESS, LOACCESS): Delete, replace with
1024 (HIHISTORY, LOHISTORY): New macros.
1025 (CHECKHILO): Delete all, moved to mips.igen
1027 * gencode.c (build_instruction): Do not generate checks for
1028 correct HI/LO register usage.
1030 * interp.c (old_engine_run): Delete checks for correct HI/LO
1033 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1034 check_mf_cycles): New functions.
1035 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1036 do_divu, domultx, do_mult, do_multu): Use.
1038 * tx.igen ("madd", "maddu"): Use.
1040 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1042 * mips.igen (DSRAV): Use function do_dsrav.
1043 (SRAV): Use new function do_srav.
1045 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1046 (B): Sign extend 11 bit immediate.
1047 (EXT-B*): Shift 16 bit immediate left by 1.
1048 (ADDIU*): Don't sign extend immediate value.
1050 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1052 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1054 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1057 * mips.igen (delayslot32, nullify_next_insn): New functions.
1058 (m16.igen): Always include.
1059 (do_*): Add more tracing.
1061 * m16.igen (delayslot16): Add NIA argument, could be called by a
1062 32 bit MIPS16 instruction.
1064 * interp.c (ifetch16): Move function from here.
1065 * sim-main.c (ifetch16): To here.
1067 * sim-main.c (ifetch16, ifetch32): Update to match current
1068 implementations of LH, LW.
1069 (signal_exception): Don't print out incorrect hex value of illegal
1072 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1077 * m16.igen: Implement MIPS16 instructions.
1079 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1080 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1081 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1082 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1083 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1084 bodies of corresponding code from 32 bit insn to these. Also used
1085 by MIPS16 versions of functions.
1087 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1088 (IMEM16): Drop NR argument from macro.
1090 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1092 * Makefile.in (SIM_OBJS): Add sim-main.o.
1094 * sim-main.h (address_translation, load_memory, store_memory,
1095 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1097 (pr_addr, pr_uword64): Declare.
1098 (sim-main.c): Include when H_REVEALS_MODULE_P.
1100 * interp.c (address_translation, load_memory, store_memory,
1101 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1103 * sim-main.c: To here. Fix compilation problems.
1105 * configure.in: Enable inlining.
1106 * configure: Re-config.
1108 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1110 * configure: Regenerated to track ../common/aclocal.m4 changes.
1112 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1114 * mips.igen: Include tx.igen.
1115 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1116 * tx.igen: New file, contains MADD and MADDU.
1118 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1119 the hardwired constant `7'.
1120 (store_memory): Ditto.
1121 (LOADDRMASK): Move definition to sim-main.h.
1123 mips.igen (MTC0): Enable for r3900.
1126 mips.igen (do_load_byte): Delete.
1127 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1128 do_store_right): New functions.
1129 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1131 configure.in: Let the tx39 use igen again.
1134 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1136 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1137 not an address sized quantity. Return zero for cache sizes.
1139 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1141 * mips.igen (r3900): r3900 does not support 64 bit integer
1144 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1146 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1148 * configure : Rebuild.
1150 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1152 * configure: Regenerated to track ../common/aclocal.m4 changes.
1154 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1156 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1158 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1160 * configure: Regenerated to track ../common/aclocal.m4 changes.
1161 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1163 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1165 * configure: Regenerated to track ../common/aclocal.m4 changes.
1167 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1169 * interp.c (Max, Min): Comment out functions. Not yet used.
1171 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1173 * configure: Regenerated to track ../common/aclocal.m4 changes.
1175 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1177 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1178 configurable settings for stand-alone simulator.
1180 * configure.in: Added X11 search, just in case.
1182 * configure: Regenerated.
1184 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1186 * interp.c (sim_write, sim_read, load_memory, store_memory):
1187 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1189 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1191 * sim-main.h (GETFCC): Return an unsigned value.
1193 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1195 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1196 (DADD): Result destination is RD not RT.
1198 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1200 * sim-main.h (HIACCESS, LOACCESS): Always define.
1202 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1204 * interp.c (sim_info): Delete.
1206 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1208 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1209 (mips_option_handler): New argument `cpu'.
1210 (sim_open): Update call to sim_add_option_table.
1212 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1214 * mips.igen (CxC1): Add tracing.
1216 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1218 * sim-main.h (Max, Min): Declare.
1220 * interp.c (Max, Min): New functions.
1222 * mips.igen (BC1): Add tracing.
1224 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1226 * interp.c Added memory map for stack in vr4100
1228 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1230 * interp.c (load_memory): Add missing "break"'s.
1232 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1234 * interp.c (sim_store_register, sim_fetch_register): Pass in
1235 length parameter. Return -1.
1237 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1239 * interp.c: Added hardware init hook, fixed warnings.
1241 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1243 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1245 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1247 * interp.c (ifetch16): New function.
1249 * sim-main.h (IMEM32): Rename IMEM.
1250 (IMEM16_IMMED): Define.
1252 (DELAY_SLOT): Update.
1254 * m16run.c (sim_engine_run): New file.
1256 * m16.igen: All instructions except LB.
1257 (LB): Call do_load_byte.
1258 * mips.igen (do_load_byte): New function.
1259 (LB): Call do_load_byte.
1261 * mips.igen: Move spec for insn bit size and high bit from here.
1262 * Makefile.in (tmp-igen, tmp-m16): To here.
1264 * m16.dc: New file, decode mips16 instructions.
1266 * Makefile.in (SIM_NO_ALL): Define.
1267 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1269 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1271 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1272 point unit to 32 bit registers.
1273 * configure: Re-generate.
1275 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1277 * configure.in (sim_use_gen): Make IGEN the default simulator
1278 generator for generic 32 and 64 bit mips targets.
1279 * configure: Re-generate.
1281 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1283 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1286 * interp.c (sim_fetch_register, sim_store_register): Read/write
1287 FGR from correct location.
1288 (sim_open): Set size of FGR's according to
1289 WITH_TARGET_FLOATING_POINT_BITSIZE.
1291 * sim-main.h (FGR): Store floating point registers in a separate
1294 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1296 * configure: Regenerated to track ../common/aclocal.m4 changes.
1298 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1300 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1302 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1304 * interp.c (pending_tick): New function. Deliver pending writes.
1306 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1307 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1308 it can handle mixed sized quantites and single bits.
1310 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1312 * interp.c (oengine.h): Do not include when building with IGEN.
1313 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1314 (sim_info): Ditto for PROCESSOR_64BIT.
1315 (sim_monitor): Replace ut_reg with unsigned_word.
1316 (*): Ditto for t_reg.
1317 (LOADDRMASK): Define.
1318 (sim_open): Remove defunct check that host FP is IEEE compliant,
1319 using software to emulate floating point.
1320 (value_fpr, ...): Always compile, was conditional on HASFPU.
1322 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1324 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1327 * interp.c (SD, CPU): Define.
1328 (mips_option_handler): Set flags in each CPU.
1329 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1330 (sim_close): Do not clear STATE, deleted anyway.
1331 (sim_write, sim_read): Assume CPU zero's vm should be used for
1333 (sim_create_inferior): Set the PC for all processors.
1334 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1336 (mips16_entry): Pass correct nr of args to store_word, load_word.
1337 (ColdReset): Cold reset all cpu's.
1338 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1339 (sim_monitor, load_memory, store_memory, signal_exception): Use
1340 `CPU' instead of STATE_CPU.
1343 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1346 * sim-main.h (signal_exception): Add sim_cpu arg.
1347 (SignalException*): Pass both SD and CPU to signal_exception.
1348 * interp.c (signal_exception): Update.
1350 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1352 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1353 address_translation): Ditto
1354 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1356 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1358 * configure: Regenerated to track ../common/aclocal.m4 changes.
1360 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1362 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1364 * mips.igen (model): Map processor names onto BFD name.
1366 * sim-main.h (CPU_CIA): Delete.
1367 (SET_CIA, GET_CIA): Define
1369 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1371 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1374 * configure.in (default_endian): Configure a big-endian simulator
1376 * configure: Re-generate.
1378 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1380 * configure: Regenerated to track ../common/aclocal.m4 changes.
1382 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1384 * interp.c (sim_monitor): Handle Densan monitor outbyte
1385 and inbyte functions.
1387 1997-12-29 Felix Lee <flee@cygnus.com>
1389 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1391 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1393 * Makefile.in (tmp-igen): Arrange for $zero to always be
1394 reset to zero after every instruction.
1396 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1398 * configure: Regenerated to track ../common/aclocal.m4 changes.
1401 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1403 * mips.igen (MSUB): Fix to work like MADD.
1404 * gencode.c (MSUB): Similarly.
1406 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1408 * configure: Regenerated to track ../common/aclocal.m4 changes.
1410 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1412 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1414 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1416 * sim-main.h (sim-fpu.h): Include.
1418 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1419 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1420 using host independant sim_fpu module.
1422 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1424 * interp.c (signal_exception): Report internal errors with SIGABRT
1427 * sim-main.h (C0_CONFIG): New register.
1428 (signal.h): No longer include.
1430 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1432 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1434 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1436 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1438 * mips.igen: Tag vr5000 instructions.
1439 (ANDI): Was missing mipsIV model, fix assembler syntax.
1440 (do_c_cond_fmt): New function.
1441 (C.cond.fmt): Handle mips I-III which do not support CC field
1443 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1444 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1446 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1447 vr5000 which saves LO in a GPR separatly.
1449 * configure.in (enable-sim-igen): For vr5000, select vr5000
1450 specific instructions.
1451 * configure: Re-generate.
1453 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1457 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1458 fmt_uninterpreted_64 bit cases to switch. Convert to
1461 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1463 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1464 as specified in IV3.2 spec.
1465 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1467 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1469 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1470 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1471 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1472 PENDING_FILL versions of instructions. Simplify.
1474 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1476 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1478 (MTHI, MFHI): Disable code checking HI-LO.
1480 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1482 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1484 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1486 * gencode.c (build_mips16_operands): Replace IPC with cia.
1488 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1489 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1491 (UndefinedResult): Replace function with macro/function
1493 (sim_engine_run): Don't save PC in IPC.
1495 * sim-main.h (IPC): Delete.
1498 * interp.c (signal_exception, store_word, load_word,
1499 address_translation, load_memory, store_memory, cache_op,
1500 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1501 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1502 current instruction address - cia - argument.
1503 (sim_read, sim_write): Call address_translation directly.
1504 (sim_engine_run): Rename variable vaddr to cia.
1505 (signal_exception): Pass cia to sim_monitor
1507 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1508 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1509 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1511 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1512 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1515 * interp.c (signal_exception): Pass restart address to
1518 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1519 idecode.o): Add dependency.
1521 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1523 (DELAY_SLOT): Update NIA not PC with branch address.
1524 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1526 * mips.igen: Use CIA not PC in branch calculations.
1527 (illegal): Call SignalException.
1528 (BEQ, ADDIU): Fix assembler.
1530 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1532 * m16.igen (JALX): Was missing.
1534 * configure.in (enable-sim-igen): New configuration option.
1535 * configure: Re-generate.
1537 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1539 * interp.c (load_memory, store_memory): Delete parameter RAW.
1540 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1541 bypassing {load,store}_memory.
1543 * sim-main.h (ByteSwapMem): Delete definition.
1545 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1547 * interp.c (sim_do_command, sim_commands): Delete mips specific
1548 commands. Handled by module sim-options.
1550 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1551 (WITH_MODULO_MEMORY): Define.
1553 * interp.c (sim_info): Delete code printing memory size.
1555 * interp.c (mips_size): Nee sim_size, delete function.
1557 (monitor, monitor_base, monitor_size): Delete global variables.
1558 (sim_open, sim_close): Delete code creating monitor and other
1559 memory regions. Use sim-memopts module, via sim_do_commandf, to
1560 manage memory regions.
1561 (load_memory, store_memory): Use sim-core for memory model.
1563 * interp.c (address_translation): Delete all memory map code
1564 except line forcing 32 bit addresses.
1566 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1571 * interp.c (logfh, logfile): Delete globals.
1572 (sim_open, sim_close): Delete code opening & closing log file.
1573 (mips_option_handler): Delete -l and -n options.
1574 (OPTION mips_options): Ditto.
1576 * interp.c (OPTION mips_options): Rename option trace to dinero.
1577 (mips_option_handler): Update.
1579 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581 * interp.c (fetch_str): New function.
1582 (sim_monitor): Rewrite using sim_read & sim_write.
1583 (sim_open): Check magic number.
1584 (sim_open): Write monitor vectors into memory using sim_write.
1585 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1586 (sim_read, sim_write): Simplify - transfer data one byte at a
1588 (load_memory, store_memory): Clarify meaning of parameter RAW.
1590 * sim-main.h (isHOST): Defete definition.
1591 (isTARGET): Mark as depreciated.
1592 (address_translation): Delete parameter HOST.
1594 * interp.c (address_translation): Delete parameter HOST.
1596 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1600 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1601 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1603 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605 * mips.igen: Add model filter field to records.
1607 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1609 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1611 interp.c (sim_engine_run): Do not compile function sim_engine_run
1612 when WITH_IGEN == 1.
1614 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1615 target architecture.
1617 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1618 igen. Replace with configuration variables sim_igen_flags /
1621 * m16.igen: New file. Copy mips16 insns here.
1622 * mips.igen: From here.
1624 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1626 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1628 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1630 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1632 * gencode.c (build_instruction): Follow sim_write's lead in using
1633 BigEndianMem instead of !ByteSwapMem.
1635 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637 * configure.in (sim_gen): Dependent on target, select type of
1638 generator. Always select old style generator.
1640 configure: Re-generate.
1642 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1644 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1645 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1646 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1647 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1648 SIM_@sim_gen@_*, set by autoconf.
1650 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1652 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1654 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1655 CURRENT_FLOATING_POINT instead.
1657 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1658 (address_translation): Raise exception InstructionFetch when
1659 translation fails and isINSTRUCTION.
1661 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1662 sim_engine_run): Change type of of vaddr and paddr to
1664 (address_translation, prefetch, load_memory, store_memory,
1665 cache_op): Change type of vAddr and pAddr to address_word.
1667 * gencode.c (build_instruction): Change type of vaddr and paddr to
1670 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1673 macro to obtain result of ALU op.
1675 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1677 * interp.c (sim_info): Call profile_print.
1679 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1681 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1683 * sim-main.h (WITH_PROFILE): Do not define, defined in
1684 common/sim-config.h. Use sim-profile module.
1685 (simPROFILE): Delete defintion.
1687 * interp.c (PROFILE): Delete definition.
1688 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1689 (sim_close): Delete code writing profile histogram.
1690 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1692 (sim_engine_run): Delete code profiling the PC.
1694 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1698 * interp.c (sim_monitor): Make register pointers of type
1701 * sim-main.h: Make registers of type unsigned_word not
1704 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706 * interp.c (sync_operation): Rename from SyncOperation, make
1707 global, add SD argument.
1708 (prefetch): Rename from Prefetch, make global, add SD argument.
1709 (decode_coproc): Make global.
1711 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1713 * gencode.c (build_instruction): Generate DecodeCoproc not
1714 decode_coproc calls.
1716 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1717 (SizeFGR): Move to sim-main.h
1718 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1719 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1720 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1722 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1723 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1724 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1725 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1726 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1727 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1729 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1731 (sim-alu.h): Include.
1732 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1733 (sim_cia): Typedef to instruction_address.
1735 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737 * Makefile.in (interp.o): Rename generated file engine.c to
1742 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1746 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1748 * gencode.c (build_instruction): For "FPSQRT", output correct
1749 number of arguments to Recip.
1751 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1753 * Makefile.in (interp.o): Depends on sim-main.h
1755 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1757 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1758 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1759 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1760 STATE, DSSTATE): Define
1761 (GPR, FGRIDX, ..): Define.
1763 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1764 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1765 (GPR, FGRIDX, ...): Delete macros.
1767 * interp.c: Update names to match defines from sim-main.h
1769 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771 * interp.c (sim_monitor): Add SD argument.
1772 (sim_warning): Delete. Replace calls with calls to
1774 (sim_error): Delete. Replace calls with sim_io_error.
1775 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1776 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1777 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1779 (mips_size): Rename from sim_size. Add SD argument.
1781 * interp.c (simulator): Delete global variable.
1782 (callback): Delete global variable.
1783 (mips_option_handler, sim_open, sim_write, sim_read,
1784 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1785 sim_size,sim_monitor): Use sim_io_* not callback->*.
1786 (sim_open): ZALLOC simulator struct.
1787 (PROFILE): Do not define.
1789 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1791 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1792 support.h with corresponding code.
1794 * sim-main.h (word64, uword64), support.h: Move definition to
1796 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1799 * Makefile.in: Update dependencies
1800 * interp.c: Do not include.
1802 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1804 * interp.c (address_translation, load_memory, store_memory,
1805 cache_op): Rename to from AddressTranslation et.al., make global,
1808 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1811 * interp.c (SignalException): Rename to signal_exception, make
1814 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1816 * sim-main.h (SignalException, SignalExceptionInterrupt,
1817 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1818 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1819 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1822 * interp.c, support.h: Use.
1824 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1826 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1827 to value_fpr / store_fpr. Add SD argument.
1828 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1829 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1831 * sim-main.h (ValueFPR, StoreFPR): Define.
1833 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1835 * interp.c (sim_engine_run): Check consistency between configure
1836 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1839 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1840 (mips_fpu): Configure WITH_FLOATING_POINT.
1841 (mips_endian): Configure WITH_TARGET_ENDIAN.
1842 * configure: Update.
1844 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1846 * configure: Regenerated to track ../common/aclocal.m4 changes.
1848 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1850 * configure: Regenerated.
1852 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1854 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1856 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1858 * gencode.c (print_igen_insn_models): Assume certain architectures
1859 include all mips* instructions.
1860 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1863 * Makefile.in (tmp.igen): Add target. Generate igen input from
1866 * gencode.c (FEATURE_IGEN): Define.
1867 (main): Add --igen option. Generate output in igen format.
1868 (process_instructions): Format output according to igen option.
1869 (print_igen_insn_format): New function.
1870 (print_igen_insn_models): New function.
1871 (process_instructions): Only issue warnings and ignore
1872 instructions when no FEATURE_IGEN.
1874 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1876 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1879 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1881 * configure: Regenerated to track ../common/aclocal.m4 changes.
1883 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1886 SIM_RESERVED_BITS): Delete, moved to common.
1887 (SIM_EXTRA_CFLAGS): Update.
1889 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1891 * configure.in: Configure non-strict memory alignment.
1892 * configure: Regenerated to track ../common/aclocal.m4 changes.
1894 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896 * configure: Regenerated to track ../common/aclocal.m4 changes.
1898 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1900 * gencode.c (SDBBP,DERET): Added (3900) insns.
1901 (RFE): Turn on for 3900.
1902 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1903 (dsstate): Made global.
1904 (SUBTARGET_R3900): Added.
1905 (CANCELDELAYSLOT): New.
1906 (SignalException): Ignore SystemCall rather than ignore and
1907 terminate. Add DebugBreakPoint handling.
1908 (decode_coproc): New insns RFE, DERET; and new registers Debug
1909 and DEPC protected by SUBTARGET_R3900.
1910 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1912 * Makefile.in,configure.in: Add mips subtarget option.
1913 * configure: Update.
1915 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1917 * gencode.c: Add r3900 (tx39).
1920 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1922 * gencode.c (build_instruction): Don't need to subtract 4 for
1925 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1927 * interp.c: Correct some HASFPU problems.
1929 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1931 * configure: Regenerated to track ../common/aclocal.m4 changes.
1933 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935 * interp.c (mips_options): Fix samples option short form, should
1938 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1940 * interp.c (sim_info): Enable info code. Was just returning.
1942 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1944 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1947 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1949 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1951 (build_instruction): Ditto for LL.
1953 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1955 * configure: Regenerated to track ../common/aclocal.m4 changes.
1957 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1959 * configure: Regenerated to track ../common/aclocal.m4 changes.
1962 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1964 * interp.c (sim_open): Add call to sim_analyze_program, update
1967 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1969 * interp.c (sim_kill): Delete.
1970 (sim_create_inferior): Add ABFD argument. Set PC from same.
1971 (sim_load): Move code initializing trap handlers from here.
1972 (sim_open): To here.
1973 (sim_load): Delete, use sim-hload.c.
1975 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1977 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979 * configure: Regenerated to track ../common/aclocal.m4 changes.
1982 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984 * interp.c (sim_open): Add ABFD argument.
1985 (sim_load): Move call to sim_config from here.
1986 (sim_open): To here. Check return status.
1988 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1990 * gencode.c (build_instruction): Two arg MADD should
1991 not assign result to $0.
1993 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1995 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1996 * sim/mips/configure.in: Regenerate.
1998 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2000 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2001 signed8, unsigned8 et.al. types.
2003 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2004 hosts when selecting subreg.
2006 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2008 * interp.c (sim_engine_run): Reset the ZERO register to zero
2009 regardless of FEATURE_WARN_ZERO.
2010 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2012 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2015 (SignalException): For BreakPoints ignore any mode bits and just
2017 (SignalException): Always set the CAUSE register.
2019 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2021 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2022 exception has been taken.
2024 * interp.c: Implement the ERET and mt/f sr instructions.
2026 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2028 * interp.c (SignalException): Don't bother restarting an
2031 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2033 * interp.c (SignalException): Really take an interrupt.
2034 (interrupt_event): Only deliver interrupts when enabled.
2036 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2038 * interp.c (sim_info): Only print info when verbose.
2039 (sim_info) Use sim_io_printf for output.
2041 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2046 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2048 * interp.c (sim_do_command): Check for common commands if a
2049 simulator specific command fails.
2051 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2053 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2054 and simBE when DEBUG is defined.
2056 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2058 * interp.c (interrupt_event): New function. Pass exception event
2059 onto exception handler.
2061 * configure.in: Check for stdlib.h.
2062 * configure: Regenerate.
2064 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2065 variable declaration.
2066 (build_instruction): Initialize memval1.
2067 (build_instruction): Add UNUSED attribute to byte, bigend,
2069 (build_operands): Ditto.
2071 * interp.c: Fix GCC warnings.
2072 (sim_get_quit_code): Delete.
2074 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2075 * Makefile.in: Ditto.
2076 * configure: Re-generate.
2078 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2080 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2082 * interp.c (mips_option_handler): New function parse argumes using
2084 (myname): Replace with STATE_MY_NAME.
2085 (sim_open): Delete check for host endianness - performed by
2087 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2088 (sim_open): Move much of the initialization from here.
2089 (sim_load): To here. After the image has been loaded and
2091 (sim_open): Move ColdReset from here.
2092 (sim_create_inferior): To here.
2093 (sim_open): Make FP check less dependant on host endianness.
2095 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2097 * interp.c (sim_set_callbacks): Delete.
2099 * interp.c (membank, membank_base, membank_size): Replace with
2100 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2101 (sim_open): Remove call to callback->init. gdb/run do this.
2105 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2107 * interp.c (big_endian_p): Delete, replaced by
2108 current_target_byte_order.
2110 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112 * interp.c (host_read_long, host_read_word, host_swap_word,
2113 host_swap_long): Delete. Using common sim-endian.
2114 (sim_fetch_register, sim_store_register): Use H2T.
2115 (pipeline_ticks): Delete. Handled by sim-events.
2117 (sim_engine_run): Update.
2119 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2121 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2123 (SignalException): To here. Signal using sim_engine_halt.
2124 (sim_stop_reason): Delete, moved to common.
2126 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2128 * interp.c (sim_open): Add callback argument.
2129 (sim_set_callbacks): Delete SIM_DESC argument.
2132 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2134 * Makefile.in (SIM_OBJS): Add common modules.
2136 * interp.c (sim_set_callbacks): Also set SD callback.
2137 (set_endianness, xfer_*, swap_*): Delete.
2138 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2139 Change to functions using sim-endian macros.
2140 (control_c, sim_stop): Delete, use common version.
2141 (simulate): Convert into.
2142 (sim_engine_run): This function.
2143 (sim_resume): Delete.
2145 * interp.c (simulation): New variable - the simulator object.
2146 (sim_kind): Delete global - merged into simulation.
2147 (sim_load): Cleanup. Move PC assignment from here.
2148 (sim_create_inferior): To here.
2150 * sim-main.h: New file.
2151 * interp.c (sim-main.h): Include.
2153 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2155 * configure: Regenerated to track ../common/aclocal.m4 changes.
2157 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2159 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2161 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2163 * gencode.c (build_instruction): DIV instructions: check
2164 for division by zero and integer overflow before using
2165 host's division operation.
2167 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2169 * Makefile.in (SIM_OBJS): Add sim-load.o.
2170 * interp.c: #include bfd.h.
2171 (target_byte_order): Delete.
2172 (sim_kind, myname, big_endian_p): New static locals.
2173 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2174 after argument parsing. Recognize -E arg, set endianness accordingly.
2175 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2176 load file into simulator. Set PC from bfd.
2177 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2178 (set_endianness): Use big_endian_p instead of target_byte_order.
2180 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2182 * interp.c (sim_size): Delete prototype - conflicts with
2183 definition in remote-sim.h. Correct definition.
2185 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2187 * configure: Regenerated to track ../common/aclocal.m4 changes.
2190 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2192 * interp.c (sim_open): New arg `kind'.
2194 * configure: Regenerated to track ../common/aclocal.m4 changes.
2196 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2198 * configure: Regenerated to track ../common/aclocal.m4 changes.
2200 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2202 * interp.c (sim_open): Set optind to 0 before calling getopt.
2204 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2206 * configure: Regenerated to track ../common/aclocal.m4 changes.
2208 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2210 * interp.c : Replace uses of pr_addr with pr_uword64
2211 where the bit length is always 64 independent of SIM_ADDR.
2212 (pr_uword64) : added.
2214 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2216 * configure: Re-generate.
2218 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2220 * configure: Regenerate to track ../common/aclocal.m4 changes.
2222 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2224 * interp.c (sim_open): New SIM_DESC result. Argument is now
2226 (other sim_*): New SIM_DESC argument.
2228 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2230 * interp.c: Fix printing of addresses for non-64-bit targets.
2231 (pr_addr): Add function to print address based on size.
2233 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2235 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2237 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2239 * gencode.c (build_mips16_operands): Correct computation of base
2240 address for extended PC relative instruction.
2242 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2244 * interp.c (mips16_entry): Add support for floating point cases.
2245 (SignalException): Pass floating point cases to mips16_entry.
2246 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2248 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2250 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2251 and then set the state to fmt_uninterpreted.
2252 (COP_SW): Temporarily set the state to fmt_word while calling
2255 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2257 * gencode.c (build_instruction): The high order may be set in the
2258 comparison flags at any ISA level, not just ISA 4.
2260 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2262 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2263 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2264 * configure.in: sinclude ../common/aclocal.m4.
2265 * configure: Regenerated.
2267 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2269 * configure: Rebuild after change to aclocal.m4.
2271 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2273 * configure configure.in Makefile.in: Update to new configure
2274 scheme which is more compatible with WinGDB builds.
2275 * configure.in: Improve comment on how to run autoconf.
2276 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2277 * Makefile.in: Use autoconf substitution to install common
2280 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2282 * gencode.c (build_instruction): Use BigEndianCPU instead of
2285 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2287 * interp.c (sim_monitor): Make output to stdout visible in
2288 wingdb's I/O log window.
2290 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2292 * support.h: Undo previous change to SIGTRAP
2295 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2297 * interp.c (store_word, load_word): New static functions.
2298 (mips16_entry): New static function.
2299 (SignalException): Look for mips16 entry and exit instructions.
2300 (simulate): Use the correct index when setting fpr_state after
2301 doing a pending move.
2303 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2305 * interp.c: Fix byte-swapping code throughout to work on
2306 both little- and big-endian hosts.
2308 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2310 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2311 with gdb/config/i386/xm-windows.h.
2313 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2315 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2316 that messes up arithmetic shifts.
2318 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2320 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2321 SIGTRAP and SIGQUIT for _WIN32.
2323 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2325 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2326 force a 64 bit multiplication.
2327 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2328 destination register is 0, since that is the default mips16 nop
2331 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2333 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2334 (build_endian_shift): Don't check proc64.
2335 (build_instruction): Always set memval to uword64. Cast op2 to
2336 uword64 when shifting it left in memory instructions. Always use
2337 the same code for stores--don't special case proc64.
2339 * gencode.c (build_mips16_operands): Fix base PC value for PC
2341 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2343 * interp.c (simJALDELAYSLOT): Define.
2344 (JALDELAYSLOT): Define.
2345 (INDELAYSLOT, INJALDELAYSLOT): Define.
2346 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2348 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2350 * interp.c (sim_open): add flush_cache as a PMON routine
2351 (sim_monitor): handle flush_cache by ignoring it
2353 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2355 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2357 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2358 (BigEndianMem): Rename to ByteSwapMem and change sense.
2359 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2360 BigEndianMem references to !ByteSwapMem.
2361 (set_endianness): New function, with prototype.
2362 (sim_open): Call set_endianness.
2363 (sim_info): Use simBE instead of BigEndianMem.
2364 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2365 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2366 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2367 ifdefs, keeping the prototype declaration.
2368 (swap_word): Rewrite correctly.
2369 (ColdReset): Delete references to CONFIG. Delete endianness related
2370 code; moved to set_endianness.
2372 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2374 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2375 * interp.c (CHECKHILO): Define away.
2376 (simSIGINT): New macro.
2377 (membank_size): Increase from 1MB to 2MB.
2378 (control_c): New function.
2379 (sim_resume): Rename parameter signal to signal_number. Add local
2380 variable prev. Call signal before and after simulate.
2381 (sim_stop_reason): Add simSIGINT support.
2382 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2384 (sim_warning): Delete call to SignalException. Do call printf_filtered
2386 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2387 a call to sim_warning.
2389 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2391 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2392 16 bit instructions.
2394 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2396 Add support for mips16 (16 bit MIPS implementation):
2397 * gencode.c (inst_type): Add mips16 instruction encoding types.
2398 (GETDATASIZEINSN): Define.
2399 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2400 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2402 (MIPS16_DECODE): New table, for mips16 instructions.
2403 (bitmap_val): New static function.
2404 (struct mips16_op): Define.
2405 (mips16_op_table): New table, for mips16 operands.
2406 (build_mips16_operands): New static function.
2407 (process_instructions): If PC is odd, decode a mips16
2408 instruction. Break out instruction handling into new
2409 build_instruction function.
2410 (build_instruction): New static function, broken out of
2411 process_instructions. Check modifiers rather than flags for SHIFT
2412 bit count and m[ft]{hi,lo} direction.
2413 (usage): Pass program name to fprintf.
2414 (main): Remove unused variable this_option_optind. Change
2415 ``*loptarg++'' to ``loptarg++''.
2416 (my_strtoul): Parenthesize && within ||.
2417 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2418 (simulate): If PC is odd, fetch a 16 bit instruction, and
2419 increment PC by 2 rather than 4.
2420 * configure.in: Add case for mips16*-*-*.
2421 * configure: Rebuild.
2423 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2425 * interp.c: Allow -t to enable tracing in standalone simulator.
2426 Fix garbage output in trace file and error messages.
2428 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2430 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2431 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2432 * configure.in: Simplify using macros in ../common/aclocal.m4.
2433 * configure: Regenerated.
2434 * tconfig.in: New file.
2436 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2438 * interp.c: Fix bugs in 64-bit port.
2439 Use ansi function declarations for msvc compiler.
2440 Initialize and test file pointer in trace code.
2441 Prevent duplicate definition of LAST_EMED_REGNUM.
2443 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2445 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2447 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2449 * interp.c (SignalException): Check for explicit terminating
2451 * gencode.c: Pass instruction value through SignalException()
2452 calls for Trap, Breakpoint and Syscall.
2454 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2456 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2457 only used on those hosts that provide it.
2458 * configure.in: Add sqrt() to list of functions to be checked for.
2459 * config.in: Re-generated.
2460 * configure: Re-generated.
2462 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2464 * gencode.c (process_instructions): Call build_endian_shift when
2465 expanding STORE RIGHT, to fix swr.
2466 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2467 clear the high bits.
2468 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2469 Fix float to int conversions to produce signed values.
2471 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2473 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2474 (process_instructions): Correct handling of nor instruction.
2475 Correct shift count for 32 bit shift instructions. Correct sign
2476 extension for arithmetic shifts to not shift the number of bits in
2477 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2478 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2480 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2481 It's OK to have a mult follow a mult. What's not OK is to have a
2482 mult follow an mfhi.
2483 (Convert): Comment out incorrect rounding code.
2485 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2487 * interp.c (sim_monitor): Improved monitor printf
2488 simulation. Tidied up simulator warnings, and added "--log" option
2489 for directing warning message output.
2490 * gencode.c: Use sim_warning() rather than WARNING macro.
2492 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2494 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2495 getopt1.o, rather than on gencode.c. Link objects together.
2496 Don't link against -liberty.
2497 (gencode.o, getopt.o, getopt1.o): New targets.
2498 * gencode.c: Include <ctype.h> and "ansidecl.h".
2499 (AND): Undefine after including "ansidecl.h".
2500 (ULONG_MAX): Define if not defined.
2501 (OP_*): Don't define macros; now defined in opcode/mips.h.
2502 (main): Call my_strtoul rather than strtoul.
2503 (my_strtoul): New static function.
2505 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2507 * gencode.c (process_instructions): Generate word64 and uword64
2508 instead of `long long' and `unsigned long long' data types.
2509 * interp.c: #include sysdep.h to get signals, and define default
2511 * (Convert): Work around for Visual-C++ compiler bug with type
2513 * support.h: Make things compile under Visual-C++ by using
2514 __int64 instead of `long long'. Change many refs to long long
2515 into word64/uword64 typedefs.
2517 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2519 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2520 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2522 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2523 (AC_PROG_INSTALL): Added.
2524 (AC_PROG_CC): Moved to before configure.host call.
2525 * configure: Rebuilt.
2527 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2529 * configure.in: Define @SIMCONF@ depending on mips target.
2530 * configure: Rebuild.
2531 * Makefile.in (run): Add @SIMCONF@ to control simulator
2533 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2534 * interp.c: Remove some debugging, provide more detailed error
2535 messages, update memory accesses to use LOADDRMASK.
2537 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2539 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2540 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2542 * configure: Rebuild.
2543 * config.in: New file, generated by autoheader.
2544 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2545 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2546 HAVE_ANINT and HAVE_AINT, as appropriate.
2547 * Makefile.in (run): Use @LIBS@ rather than -lm.
2548 (interp.o): Depend upon config.h.
2549 (Makefile): Just rebuild Makefile.
2550 (clean): Remove stamp-h.
2551 (mostlyclean): Make the same as clean, not as distclean.
2552 (config.h, stamp-h): New targets.
2554 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2556 * interp.c (ColdReset): Fix boolean test. Make all simulator
2559 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2561 * interp.c (xfer_direct_word, xfer_direct_long,
2562 swap_direct_word, swap_direct_long, xfer_big_word,
2563 xfer_big_long, xfer_little_word, xfer_little_long,
2564 swap_word,swap_long): Added.
2565 * interp.c (ColdReset): Provide function indirection to
2566 host<->simulated_target transfer routines.
2567 * interp.c (sim_store_register, sim_fetch_register): Updated to
2568 make use of indirected transfer routines.
2570 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2572 * gencode.c (process_instructions): Ensure FP ABS instruction
2574 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2575 system call support.
2577 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2579 * interp.c (sim_do_command): Complain if callback structure not
2582 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2584 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2585 support for Sun hosts.
2586 * Makefile.in (gencode): Ensure the host compiler and libraries
2587 used for cross-hosted build.
2589 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2591 * interp.c, gencode.c: Some more (TODO) tidying.
2593 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2595 * gencode.c, interp.c: Replaced explicit long long references with
2596 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2597 * support.h (SET64LO, SET64HI): Macros added.
2599 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2601 * configure: Regenerate with autoconf 2.7.
2603 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2605 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2606 * support.h: Remove superfluous "1" from #if.
2607 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2609 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2611 * interp.c (StoreFPR): Control UndefinedResult() call on
2612 WARN_RESULT manifest.
2614 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2616 * gencode.c: Tidied instruction decoding, and added FP instruction
2619 * interp.c: Added dineroIII, and BSD profiling support. Also
2620 run-time FP handling.
2622 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2624 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2625 gencode.c, interp.c, support.h: created.