1 2001-02-19 Ben Elliston <bje@redhat.com>
3 * sim-main.h (sim_monitor): Return an int.
4 * interp.c (sim_monitor): Add return values.
5 (signal_exception): Handle error conditions from sim_monitor.
7 2001-02-08 Ben Elliston <bje@redhat.com>
9 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
10 (store_memory): Likewise, pass cia to sim_core_write*.
12 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
14 On advice from Chris G. Demetriou <cgd@sibyte.com>:
15 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
17 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
19 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
20 * Makefile.in: Don't delete *.igen when cleaning directory.
22 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
24 * m16.igen (break): Call SignalException not sim_engine_halt.
26 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
29 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
31 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
33 * mips.igen (MxC1, DMxC1): Fix printf formatting.
35 2000-05-24 Michael Hayes <mhayes@cygnus.com>
37 * mips.igen (do_dmultx): Fix typo.
39 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
41 * configure: Regenerated to track ../common/aclocal.m4 changes.
43 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
45 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
47 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
49 * sim-main.h (GPR_CLEAR): Define macro.
51 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
53 * interp.c (decode_coproc): Output long using %lx and not %s.
55 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
57 * interp.c (sim_open): Sort & extend dummy memory regions for
58 --board=jmr3904 for eCos.
60 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
62 * configure: Regenerated.
64 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
66 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
67 calls, conditional on the simulator being in verbose mode.
69 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
71 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
72 cache don't get ReservedInstruction traps.
74 1999-11-29 Mark Salter <msalter@cygnus.com>
76 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
77 to clear status bits in sdisr register. This is how the hardware works.
79 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
82 1999-11-11 Andrew Haley <aph@cygnus.com>
84 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
87 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
89 * mips.igen (MULT): Correct previous mis-applied patch.
91 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
93 * mips.igen (delayslot32): Handle sequence like
94 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
95 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
96 (MULT): Actually pass the third register...
98 1999-09-03 Mark Salter <msalter@cygnus.com>
100 * interp.c (sim_open): Added more memory aliases for additional
101 hardware being touched by cygmon on jmr3904 board.
103 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
105 * configure: Regenerated to track ../common/aclocal.m4 changes.
107 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
109 * interp.c (sim_store_register): Handle case where client - GDB -
110 specifies that a 4 byte register is 8 bytes in size.
111 (sim_fetch_register): Ditto.
113 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
115 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
116 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
117 (idt_monitor_base): Base address for IDT monitor traps.
118 (pmon_monitor_base): Ditto for PMON.
119 (lsipmon_monitor_base): Ditto for LSI PMON.
120 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
121 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
122 (sim_firmware_command): New function.
123 (mips_option_handler): Call it for OPTION_FIRMWARE.
124 (sim_open): Allocate memory for idt_monitor region. If "--board"
125 option was given, add no monitor by default. Add BREAK hooks only if
126 monitors are also there.
128 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
130 * interp.c (sim_monitor): Flush output before reading input.
132 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
134 * tconfig.in (SIM_HANDLES_LMA): Always define.
136 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
138 From Mark Salter <msalter@cygnus.com>:
139 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
140 (sim_open): Add setup for BSP board.
142 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
144 * mips.igen (MULT, MULTU): Add syntax for two operand version.
145 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
146 them as unimplemented.
148 1999-05-08 Felix Lee <flee@cygnus.com>
150 * configure: Regenerated to track ../common/aclocal.m4 changes.
152 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
154 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
156 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
158 * configure.in: Any mips64vr5*-*-* target should have
159 -DTARGET_ENABLE_FR=1.
160 (default_endian): Any mips64vr*el-*-* target should default to
162 * configure: Re-generate.
164 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
166 * mips.igen (ldl): Extend from _16_, not 32.
168 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
170 * interp.c (sim_store_register): Force registers written to by GDB
171 into an un-interpreted state.
173 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
175 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
176 CPU, start periodic background I/O polls.
177 (tx3904sio_poll): New function: periodic I/O poller.
179 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
181 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
183 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
185 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
188 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
190 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
191 (load_word): Call SIM_CORE_SIGNAL hook on error.
192 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
193 starting. For exception dispatching, pass PC instead of NULL_CIA.
194 (decode_coproc): Use COP0_BADVADDR to store faulting address.
195 * sim-main.h (COP0_BADVADDR): Define.
196 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
197 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
198 (_sim_cpu): Add exc_* fields to store register value snapshots.
199 * mips.igen (*): Replace memory-related SignalException* calls
200 with references to SIM_CORE_SIGNAL hook.
202 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
204 * sim-main.c (*): Minor warning cleanups.
206 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
208 * m16.igen (DADDIU5): Correct type-o.
210 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
212 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
215 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
217 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
219 (interp.o): Add dependency on itable.h
220 (oengine.c, gencode): Delete remaining references.
221 (BUILT_SRC_FROM_GEN): Clean up.
223 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
226 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
227 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
229 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
230 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
231 Drop the "64" qualifier to get the HACK generator working.
232 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
233 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
234 qualifier to get the hack generator working.
235 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
237 (DSLLV): Use do_dsllv.
240 (DSRLV): Use do_dsrlv.
241 (BC1): Move *vr4100 to get the HACK generator working.
242 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
243 get the HACK generator working.
244 (MACC) Rename to get the HACK generator working.
245 (DMACC,MACCS,DMACCS): Add the 64.
247 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
249 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
250 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
252 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
254 * mips/interp.c (DEBUG): Cleanups.
256 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
258 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
259 (tx3904sio_tickle): fflush after a stdout character output.
261 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
263 * interp.c (sim_close): Uninstall modules.
265 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
267 * sim-main.h, interp.c (sim_monitor): Change to global
270 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
272 * configure.in (vr4100): Only include vr4100 instructions in
274 * configure: Re-generate.
275 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
277 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
279 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
280 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
283 * configure.in (sim_default_gen, sim_use_gen): Replace with
285 (--enable-sim-igen): Delete config option. Always using IGEN.
286 * configure: Re-generate.
288 * Makefile.in (gencode): Kill, kill, kill.
291 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
293 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
294 bit mips16 igen simulator.
295 * configure: Re-generate.
297 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
298 as part of vr4100 ISA.
299 * vr.igen: Mark all instructions as 64 bit only.
301 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
303 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
306 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
308 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
309 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
310 * configure: Re-generate.
312 * m16.igen (BREAK): Define breakpoint instruction.
313 (JALX32): Mark instruction as mips16 and not r3900.
314 * mips.igen (C.cond.fmt): Fix typo in instruction format.
316 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
318 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
320 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
321 insn as a debug breakpoint.
323 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
325 (PENDING_SCHED): Clean up trace statement.
326 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
327 (PENDING_FILL): Delay write by only one cycle.
328 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
330 * sim-main.c (pending_tick): Clean up trace statements. Add trace
332 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
334 (pending_tick): Move incrementing of index to FOR statement.
335 (pending_tick): Only update PENDING_OUT after a write has occured.
337 * configure.in: Add explicit mips-lsi-* target. Use gencode to
339 * configure: Re-generate.
341 * interp.c (sim_engine_run OLD): Delete explicit call to
342 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
344 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
346 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
347 interrupt level number to match changed SignalExceptionInterrupt
350 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
352 * interp.c: #include "itable.h" if WITH_IGEN.
353 (get_insn_name): New function.
354 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
355 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
357 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
359 * configure: Rebuilt to inhale new common/aclocal.m4.
361 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
363 * dv-tx3904sio.c: Include sim-assert.h.
365 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
367 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
368 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
369 Reorganize target-specific sim-hardware checks.
370 * configure: rebuilt.
371 * interp.c (sim_open): For tx39 target boards, set
372 OPERATING_ENVIRONMENT, add tx3904sio devices.
373 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
374 ROM executables. Install dv-sockser into sim-modules list.
376 * dv-tx3904irc.c: Compiler warning clean-up.
377 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
378 frequent hw-trace messages.
380 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
382 * vr.igen (MulAcc): Identify as a vr4100 specific function.
384 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
386 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
389 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
390 * mips.igen: Define vr4100 model. Include vr.igen.
391 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
393 * mips.igen (check_mf_hilo): Correct check.
395 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
397 * sim-main.h (interrupt_event): Add prototype.
399 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
400 register_ptr, register_value.
401 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
403 * sim-main.h (tracefh): Make extern.
405 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
407 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
408 Reduce unnecessarily high timer event frequency.
409 * dv-tx3904cpu.c: Ditto for interrupt event.
411 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
413 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
415 (interrupt_event): Made non-static.
417 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
418 interchange of configuration values for external vs. internal
421 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
423 * mips.igen (BREAK): Moved code to here for
424 simulator-reserved break instructions.
425 * gencode.c (build_instruction): Ditto.
426 * interp.c (signal_exception): Code moved from here. Non-
427 reserved instructions now use exception vector, rather
429 * sim-main.h: Moved magic constants to here.
431 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
433 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
434 register upon non-zero interrupt event level, clear upon zero
436 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
437 by passing zero event value.
438 (*_io_{read,write}_buffer): Endianness fixes.
439 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
440 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
442 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
443 serial I/O and timer module at base address 0xFFFF0000.
445 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
447 * mips.igen (SWC1) : Correct the handling of ReverseEndian
450 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
452 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
456 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
458 * dv-tx3904tmr.c: New file - implements tx3904 timer.
459 * dv-tx3904{irc,cpu}.c: Mild reformatting.
460 * configure.in: Include tx3904tmr in hw_device list.
461 * configure: Rebuilt.
462 * interp.c (sim_open): Instantiate three timer instances.
463 Fix address typo of tx3904irc instance.
465 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
467 * interp.c (signal_exception): SystemCall exception now uses
468 the exception vector.
470 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
472 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
475 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
477 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
479 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
481 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
483 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
484 sim-main.h. Declare a struct hw_descriptor instead of struct
485 hw_device_descriptor.
487 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
489 * mips.igen (do_store_left, do_load_left): Compute nr of left and
490 right bits and then re-align left hand bytes to correct byte
491 lanes. Fix incorrect computation in do_store_left when loading
492 bytes from second word.
494 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
496 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
497 * interp.c (sim_open): Only create a device tree when HW is
500 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
501 * interp.c (signal_exception): Ditto.
503 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
505 * gencode.c: Mark BEGEZALL as LIKELY.
507 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
509 * sim-main.h (ALU32_END): Sign extend 32 bit results.
510 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
512 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
514 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
515 modules. Recognize TX39 target with "mips*tx39" pattern.
516 * configure: Rebuilt.
517 * sim-main.h (*): Added many macros defining bits in
518 TX39 control registers.
519 (SignalInterrupt): Send actual PC instead of NULL.
520 (SignalNMIReset): New exception type.
521 * interp.c (board): New variable for future use to identify
522 a particular board being simulated.
523 (mips_option_handler,mips_options): Added "--board" option.
524 (interrupt_event): Send actual PC.
525 (sim_open): Make memory layout conditional on board setting.
526 (signal_exception): Initial implementation of hardware interrupt
527 handling. Accept another break instruction variant for simulator
529 (decode_coproc): Implement RFE instruction for TX39.
530 (mips.igen): Decode RFE instruction as such.
531 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
532 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
533 bbegin to implement memory map.
534 * dv-tx3904cpu.c: New file.
535 * dv-tx3904irc.c: New file.
537 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
539 * mips.igen (check_mt_hilo): Create a separate r3900 version.
541 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
543 * tx.igen (madd,maddu): Replace calls to check_op_hilo
544 with calls to check_div_hilo.
546 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
548 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
549 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
550 Add special r3900 version of do_mult_hilo.
551 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
552 with calls to check_mult_hilo.
553 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
554 with calls to check_div_hilo.
556 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
558 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
559 Document a replacement.
561 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
563 * interp.c (sim_monitor): Make mon_printf work.
565 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
567 * sim-main.h (INSN_NAME): New arg `cpu'.
569 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
571 * configure: Regenerated to track ../common/aclocal.m4 changes.
573 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
575 * configure: Regenerated to track ../common/aclocal.m4 changes.
578 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
580 * acconfig.h: New file.
581 * configure.in: Reverted change of Apr 24; use sinclude again.
583 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
585 * configure: Regenerated to track ../common/aclocal.m4 changes.
588 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
590 * configure.in: Don't call sinclude.
592 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
594 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
596 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
598 * mips.igen (ERET): Implement.
600 * interp.c (decode_coproc): Return sign-extended EPC.
602 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
604 * interp.c (signal_exception): Do not ignore Trap.
605 (signal_exception): On TRAP, restart at exception address.
606 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
607 (signal_exception): Update.
608 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
609 so that TRAP instructions are caught.
611 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
613 * sim-main.h (struct hilo_access, struct hilo_history): Define,
614 contains HI/LO access history.
615 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
616 (HIACCESS, LOACCESS): Delete, replace with
617 (HIHISTORY, LOHISTORY): New macros.
618 (CHECKHILO): Delete all, moved to mips.igen
620 * gencode.c (build_instruction): Do not generate checks for
621 correct HI/LO register usage.
623 * interp.c (old_engine_run): Delete checks for correct HI/LO
626 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
627 check_mf_cycles): New functions.
628 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
629 do_divu, domultx, do_mult, do_multu): Use.
631 * tx.igen ("madd", "maddu"): Use.
633 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
635 * mips.igen (DSRAV): Use function do_dsrav.
636 (SRAV): Use new function do_srav.
638 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
639 (B): Sign extend 11 bit immediate.
640 (EXT-B*): Shift 16 bit immediate left by 1.
641 (ADDIU*): Don't sign extend immediate value.
643 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
645 * m16run.c (sim_engine_run): Restore CIA after handling an event.
647 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
650 * mips.igen (delayslot32, nullify_next_insn): New functions.
651 (m16.igen): Always include.
652 (do_*): Add more tracing.
654 * m16.igen (delayslot16): Add NIA argument, could be called by a
655 32 bit MIPS16 instruction.
657 * interp.c (ifetch16): Move function from here.
658 * sim-main.c (ifetch16): To here.
660 * sim-main.c (ifetch16, ifetch32): Update to match current
661 implementations of LH, LW.
662 (signal_exception): Don't print out incorrect hex value of illegal
665 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
667 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
670 * m16.igen: Implement MIPS16 instructions.
672 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
673 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
674 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
675 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
676 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
677 bodies of corresponding code from 32 bit insn to these. Also used
678 by MIPS16 versions of functions.
680 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
681 (IMEM16): Drop NR argument from macro.
683 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
685 * Makefile.in (SIM_OBJS): Add sim-main.o.
687 * sim-main.h (address_translation, load_memory, store_memory,
688 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
690 (pr_addr, pr_uword64): Declare.
691 (sim-main.c): Include when H_REVEALS_MODULE_P.
693 * interp.c (address_translation, load_memory, store_memory,
694 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
696 * sim-main.c: To here. Fix compilation problems.
698 * configure.in: Enable inlining.
699 * configure: Re-config.
701 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
703 * configure: Regenerated to track ../common/aclocal.m4 changes.
705 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
707 * mips.igen: Include tx.igen.
708 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
709 * tx.igen: New file, contains MADD and MADDU.
711 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
712 the hardwired constant `7'.
713 (store_memory): Ditto.
714 (LOADDRMASK): Move definition to sim-main.h.
716 mips.igen (MTC0): Enable for r3900.
719 mips.igen (do_load_byte): Delete.
720 (do_load, do_store, do_load_left, do_load_write, do_store_left,
721 do_store_right): New functions.
722 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
724 configure.in: Let the tx39 use igen again.
727 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
729 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
730 not an address sized quantity. Return zero for cache sizes.
732 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
734 * mips.igen (r3900): r3900 does not support 64 bit integer
737 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
739 * configure.in (mipstx39*-*-*): Use gencode simulator rather
741 * configure : Rebuild.
743 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
745 * configure: Regenerated to track ../common/aclocal.m4 changes.
747 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
749 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
751 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
753 * configure: Regenerated to track ../common/aclocal.m4 changes.
754 * config.in: Regenerated to track ../common/aclocal.m4 changes.
756 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
758 * configure: Regenerated to track ../common/aclocal.m4 changes.
760 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
762 * interp.c (Max, Min): Comment out functions. Not yet used.
764 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
766 * configure: Regenerated to track ../common/aclocal.m4 changes.
768 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
770 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
771 configurable settings for stand-alone simulator.
773 * configure.in: Added X11 search, just in case.
775 * configure: Regenerated.
777 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
779 * interp.c (sim_write, sim_read, load_memory, store_memory):
780 Replace sim_core_*_map with read_map, write_map, exec_map resp.
782 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
784 * sim-main.h (GETFCC): Return an unsigned value.
786 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
788 * mips.igen (DIV): Fix check for -1 / MIN_INT.
789 (DADD): Result destination is RD not RT.
791 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
793 * sim-main.h (HIACCESS, LOACCESS): Always define.
795 * mdmx.igen (Maxi, Mini): Rename Max, Min.
797 * interp.c (sim_info): Delete.
799 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
801 * interp.c (DECLARE_OPTION_HANDLER): Use it.
802 (mips_option_handler): New argument `cpu'.
803 (sim_open): Update call to sim_add_option_table.
805 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
807 * mips.igen (CxC1): Add tracing.
809 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
811 * sim-main.h (Max, Min): Declare.
813 * interp.c (Max, Min): New functions.
815 * mips.igen (BC1): Add tracing.
817 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
819 * interp.c Added memory map for stack in vr4100
821 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
823 * interp.c (load_memory): Add missing "break"'s.
825 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
827 * interp.c (sim_store_register, sim_fetch_register): Pass in
828 length parameter. Return -1.
830 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
832 * interp.c: Added hardware init hook, fixed warnings.
834 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
836 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
838 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
840 * interp.c (ifetch16): New function.
842 * sim-main.h (IMEM32): Rename IMEM.
843 (IMEM16_IMMED): Define.
845 (DELAY_SLOT): Update.
847 * m16run.c (sim_engine_run): New file.
849 * m16.igen: All instructions except LB.
850 (LB): Call do_load_byte.
851 * mips.igen (do_load_byte): New function.
852 (LB): Call do_load_byte.
854 * mips.igen: Move spec for insn bit size and high bit from here.
855 * Makefile.in (tmp-igen, tmp-m16): To here.
857 * m16.dc: New file, decode mips16 instructions.
859 * Makefile.in (SIM_NO_ALL): Define.
860 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
862 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
864 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
865 point unit to 32 bit registers.
866 * configure: Re-generate.
868 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
870 * configure.in (sim_use_gen): Make IGEN the default simulator
871 generator for generic 32 and 64 bit mips targets.
872 * configure: Re-generate.
874 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
876 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
879 * interp.c (sim_fetch_register, sim_store_register): Read/write
880 FGR from correct location.
881 (sim_open): Set size of FGR's according to
882 WITH_TARGET_FLOATING_POINT_BITSIZE.
884 * sim-main.h (FGR): Store floating point registers in a separate
887 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
889 * configure: Regenerated to track ../common/aclocal.m4 changes.
891 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
893 * interp.c (ColdReset): Call PENDING_INVALIDATE.
895 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
897 * interp.c (pending_tick): New function. Deliver pending writes.
899 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
900 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
901 it can handle mixed sized quantites and single bits.
903 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
905 * interp.c (oengine.h): Do not include when building with IGEN.
906 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
907 (sim_info): Ditto for PROCESSOR_64BIT.
908 (sim_monitor): Replace ut_reg with unsigned_word.
909 (*): Ditto for t_reg.
910 (LOADDRMASK): Define.
911 (sim_open): Remove defunct check that host FP is IEEE compliant,
912 using software to emulate floating point.
913 (value_fpr, ...): Always compile, was conditional on HASFPU.
915 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
917 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
920 * interp.c (SD, CPU): Define.
921 (mips_option_handler): Set flags in each CPU.
922 (interrupt_event): Assume CPU 0 is the one being iterrupted.
923 (sim_close): Do not clear STATE, deleted anyway.
924 (sim_write, sim_read): Assume CPU zero's vm should be used for
926 (sim_create_inferior): Set the PC for all processors.
927 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
929 (mips16_entry): Pass correct nr of args to store_word, load_word.
930 (ColdReset): Cold reset all cpu's.
931 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
932 (sim_monitor, load_memory, store_memory, signal_exception): Use
933 `CPU' instead of STATE_CPU.
936 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
939 * sim-main.h (signal_exception): Add sim_cpu arg.
940 (SignalException*): Pass both SD and CPU to signal_exception.
941 * interp.c (signal_exception): Update.
943 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
945 (sync_operation, prefetch, cache_op, store_memory, load_memory,
946 address_translation): Ditto
947 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
949 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
951 * configure: Regenerated to track ../common/aclocal.m4 changes.
953 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
955 * interp.c (sim_engine_run): Add `nr_cpus' argument.
957 * mips.igen (model): Map processor names onto BFD name.
959 * sim-main.h (CPU_CIA): Delete.
960 (SET_CIA, GET_CIA): Define
962 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
964 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
967 * configure.in (default_endian): Configure a big-endian simulator
969 * configure: Re-generate.
971 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
973 * configure: Regenerated to track ../common/aclocal.m4 changes.
975 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
977 * interp.c (sim_monitor): Handle Densan monitor outbyte
978 and inbyte functions.
980 1997-12-29 Felix Lee <flee@cygnus.com>
982 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
984 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
986 * Makefile.in (tmp-igen): Arrange for $zero to always be
987 reset to zero after every instruction.
989 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
991 * configure: Regenerated to track ../common/aclocal.m4 changes.
994 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
996 * mips.igen (MSUB): Fix to work like MADD.
997 * gencode.c (MSUB): Similarly.
999 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1001 * configure: Regenerated to track ../common/aclocal.m4 changes.
1003 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1005 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1007 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1009 * sim-main.h (sim-fpu.h): Include.
1011 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1012 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1013 using host independant sim_fpu module.
1015 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1017 * interp.c (signal_exception): Report internal errors with SIGABRT
1020 * sim-main.h (C0_CONFIG): New register.
1021 (signal.h): No longer include.
1023 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1025 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1027 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1029 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1031 * mips.igen: Tag vr5000 instructions.
1032 (ANDI): Was missing mipsIV model, fix assembler syntax.
1033 (do_c_cond_fmt): New function.
1034 (C.cond.fmt): Handle mips I-III which do not support CC field
1036 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1037 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1039 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1040 vr5000 which saves LO in a GPR separatly.
1042 * configure.in (enable-sim-igen): For vr5000, select vr5000
1043 specific instructions.
1044 * configure: Re-generate.
1046 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1048 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1050 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1051 fmt_uninterpreted_64 bit cases to switch. Convert to
1054 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1056 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1057 as specified in IV3.2 spec.
1058 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1060 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1062 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1063 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1064 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1065 PENDING_FILL versions of instructions. Simplify.
1067 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1069 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1071 (MTHI, MFHI): Disable code checking HI-LO.
1073 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1075 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1077 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1079 * gencode.c (build_mips16_operands): Replace IPC with cia.
1081 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1082 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1084 (UndefinedResult): Replace function with macro/function
1086 (sim_engine_run): Don't save PC in IPC.
1088 * sim-main.h (IPC): Delete.
1091 * interp.c (signal_exception, store_word, load_word,
1092 address_translation, load_memory, store_memory, cache_op,
1093 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1094 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1095 current instruction address - cia - argument.
1096 (sim_read, sim_write): Call address_translation directly.
1097 (sim_engine_run): Rename variable vaddr to cia.
1098 (signal_exception): Pass cia to sim_monitor
1100 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1101 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1102 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1104 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1105 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1108 * interp.c (signal_exception): Pass restart address to
1111 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1112 idecode.o): Add dependency.
1114 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1116 (DELAY_SLOT): Update NIA not PC with branch address.
1117 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1119 * mips.igen: Use CIA not PC in branch calculations.
1120 (illegal): Call SignalException.
1121 (BEQ, ADDIU): Fix assembler.
1123 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1125 * m16.igen (JALX): Was missing.
1127 * configure.in (enable-sim-igen): New configuration option.
1128 * configure: Re-generate.
1130 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1132 * interp.c (load_memory, store_memory): Delete parameter RAW.
1133 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1134 bypassing {load,store}_memory.
1136 * sim-main.h (ByteSwapMem): Delete definition.
1138 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1140 * interp.c (sim_do_command, sim_commands): Delete mips specific
1141 commands. Handled by module sim-options.
1143 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1144 (WITH_MODULO_MEMORY): Define.
1146 * interp.c (sim_info): Delete code printing memory size.
1148 * interp.c (mips_size): Nee sim_size, delete function.
1150 (monitor, monitor_base, monitor_size): Delete global variables.
1151 (sim_open, sim_close): Delete code creating monitor and other
1152 memory regions. Use sim-memopts module, via sim_do_commandf, to
1153 manage memory regions.
1154 (load_memory, store_memory): Use sim-core for memory model.
1156 * interp.c (address_translation): Delete all memory map code
1157 except line forcing 32 bit addresses.
1159 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1161 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1164 * interp.c (logfh, logfile): Delete globals.
1165 (sim_open, sim_close): Delete code opening & closing log file.
1166 (mips_option_handler): Delete -l and -n options.
1167 (OPTION mips_options): Ditto.
1169 * interp.c (OPTION mips_options): Rename option trace to dinero.
1170 (mips_option_handler): Update.
1172 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1174 * interp.c (fetch_str): New function.
1175 (sim_monitor): Rewrite using sim_read & sim_write.
1176 (sim_open): Check magic number.
1177 (sim_open): Write monitor vectors into memory using sim_write.
1178 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1179 (sim_read, sim_write): Simplify - transfer data one byte at a
1181 (load_memory, store_memory): Clarify meaning of parameter RAW.
1183 * sim-main.h (isHOST): Defete definition.
1184 (isTARGET): Mark as depreciated.
1185 (address_translation): Delete parameter HOST.
1187 * interp.c (address_translation): Delete parameter HOST.
1189 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1193 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1194 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1196 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1198 * mips.igen: Add model filter field to records.
1200 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1202 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1204 interp.c (sim_engine_run): Do not compile function sim_engine_run
1205 when WITH_IGEN == 1.
1207 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1208 target architecture.
1210 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1211 igen. Replace with configuration variables sim_igen_flags /
1214 * m16.igen: New file. Copy mips16 insns here.
1215 * mips.igen: From here.
1217 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1221 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1223 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1225 * gencode.c (build_instruction): Follow sim_write's lead in using
1226 BigEndianMem instead of !ByteSwapMem.
1228 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1230 * configure.in (sim_gen): Dependent on target, select type of
1231 generator. Always select old style generator.
1233 configure: Re-generate.
1235 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1237 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1238 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1239 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1240 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1241 SIM_@sim_gen@_*, set by autoconf.
1243 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1245 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1247 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1248 CURRENT_FLOATING_POINT instead.
1250 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1251 (address_translation): Raise exception InstructionFetch when
1252 translation fails and isINSTRUCTION.
1254 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1255 sim_engine_run): Change type of of vaddr and paddr to
1257 (address_translation, prefetch, load_memory, store_memory,
1258 cache_op): Change type of vAddr and pAddr to address_word.
1260 * gencode.c (build_instruction): Change type of vaddr and paddr to
1263 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1265 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1266 macro to obtain result of ALU op.
1268 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1270 * interp.c (sim_info): Call profile_print.
1272 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1274 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1276 * sim-main.h (WITH_PROFILE): Do not define, defined in
1277 common/sim-config.h. Use sim-profile module.
1278 (simPROFILE): Delete defintion.
1280 * interp.c (PROFILE): Delete definition.
1281 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1282 (sim_close): Delete code writing profile histogram.
1283 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1285 (sim_engine_run): Delete code profiling the PC.
1287 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1289 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1291 * interp.c (sim_monitor): Make register pointers of type
1294 * sim-main.h: Make registers of type unsigned_word not
1297 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1299 * interp.c (sync_operation): Rename from SyncOperation, make
1300 global, add SD argument.
1301 (prefetch): Rename from Prefetch, make global, add SD argument.
1302 (decode_coproc): Make global.
1304 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1306 * gencode.c (build_instruction): Generate DecodeCoproc not
1307 decode_coproc calls.
1309 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1310 (SizeFGR): Move to sim-main.h
1311 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1312 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1313 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1315 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1316 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1317 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1318 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1319 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1320 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1322 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1324 (sim-alu.h): Include.
1325 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1326 (sim_cia): Typedef to instruction_address.
1328 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1330 * Makefile.in (interp.o): Rename generated file engine.c to
1335 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1337 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1339 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1341 * gencode.c (build_instruction): For "FPSQRT", output correct
1342 number of arguments to Recip.
1344 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1346 * Makefile.in (interp.o): Depends on sim-main.h
1348 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1350 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1351 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1352 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1353 STATE, DSSTATE): Define
1354 (GPR, FGRIDX, ..): Define.
1356 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1357 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1358 (GPR, FGRIDX, ...): Delete macros.
1360 * interp.c: Update names to match defines from sim-main.h
1362 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1364 * interp.c (sim_monitor): Add SD argument.
1365 (sim_warning): Delete. Replace calls with calls to
1367 (sim_error): Delete. Replace calls with sim_io_error.
1368 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1369 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1370 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1372 (mips_size): Rename from sim_size. Add SD argument.
1374 * interp.c (simulator): Delete global variable.
1375 (callback): Delete global variable.
1376 (mips_option_handler, sim_open, sim_write, sim_read,
1377 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1378 sim_size,sim_monitor): Use sim_io_* not callback->*.
1379 (sim_open): ZALLOC simulator struct.
1380 (PROFILE): Do not define.
1382 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1384 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1385 support.h with corresponding code.
1387 * sim-main.h (word64, uword64), support.h: Move definition to
1389 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1392 * Makefile.in: Update dependencies
1393 * interp.c: Do not include.
1395 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1397 * interp.c (address_translation, load_memory, store_memory,
1398 cache_op): Rename to from AddressTranslation et.al., make global,
1401 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1404 * interp.c (SignalException): Rename to signal_exception, make
1407 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1409 * sim-main.h (SignalException, SignalExceptionInterrupt,
1410 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1411 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1412 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1415 * interp.c, support.h: Use.
1417 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1419 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1420 to value_fpr / store_fpr. Add SD argument.
1421 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1422 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1424 * sim-main.h (ValueFPR, StoreFPR): Define.
1426 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1428 * interp.c (sim_engine_run): Check consistency between configure
1429 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1432 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1433 (mips_fpu): Configure WITH_FLOATING_POINT.
1434 (mips_endian): Configure WITH_TARGET_ENDIAN.
1435 * configure: Update.
1437 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439 * configure: Regenerated to track ../common/aclocal.m4 changes.
1441 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1443 * configure: Regenerated.
1445 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1447 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1449 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1451 * gencode.c (print_igen_insn_models): Assume certain architectures
1452 include all mips* instructions.
1453 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1456 * Makefile.in (tmp.igen): Add target. Generate igen input from
1459 * gencode.c (FEATURE_IGEN): Define.
1460 (main): Add --igen option. Generate output in igen format.
1461 (process_instructions): Format output according to igen option.
1462 (print_igen_insn_format): New function.
1463 (print_igen_insn_models): New function.
1464 (process_instructions): Only issue warnings and ignore
1465 instructions when no FEATURE_IGEN.
1467 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1469 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1472 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1474 * configure: Regenerated to track ../common/aclocal.m4 changes.
1476 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1478 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1479 SIM_RESERVED_BITS): Delete, moved to common.
1480 (SIM_EXTRA_CFLAGS): Update.
1482 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1484 * configure.in: Configure non-strict memory alignment.
1485 * configure: Regenerated to track ../common/aclocal.m4 changes.
1487 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489 * configure: Regenerated to track ../common/aclocal.m4 changes.
1491 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1493 * gencode.c (SDBBP,DERET): Added (3900) insns.
1494 (RFE): Turn on for 3900.
1495 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1496 (dsstate): Made global.
1497 (SUBTARGET_R3900): Added.
1498 (CANCELDELAYSLOT): New.
1499 (SignalException): Ignore SystemCall rather than ignore and
1500 terminate. Add DebugBreakPoint handling.
1501 (decode_coproc): New insns RFE, DERET; and new registers Debug
1502 and DEPC protected by SUBTARGET_R3900.
1503 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1505 * Makefile.in,configure.in: Add mips subtarget option.
1506 * configure: Update.
1508 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1510 * gencode.c: Add r3900 (tx39).
1513 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1515 * gencode.c (build_instruction): Don't need to subtract 4 for
1518 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1520 * interp.c: Correct some HASFPU problems.
1522 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1524 * configure: Regenerated to track ../common/aclocal.m4 changes.
1526 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1528 * interp.c (mips_options): Fix samples option short form, should
1531 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1533 * interp.c (sim_info): Enable info code. Was just returning.
1535 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1540 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1544 (build_instruction): Ditto for LL.
1546 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1548 * configure: Regenerated to track ../common/aclocal.m4 changes.
1550 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1552 * configure: Regenerated to track ../common/aclocal.m4 changes.
1555 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1557 * interp.c (sim_open): Add call to sim_analyze_program, update
1560 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1562 * interp.c (sim_kill): Delete.
1563 (sim_create_inferior): Add ABFD argument. Set PC from same.
1564 (sim_load): Move code initializing trap handlers from here.
1565 (sim_open): To here.
1566 (sim_load): Delete, use sim-hload.c.
1568 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1570 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1572 * configure: Regenerated to track ../common/aclocal.m4 changes.
1575 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577 * interp.c (sim_open): Add ABFD argument.
1578 (sim_load): Move call to sim_config from here.
1579 (sim_open): To here. Check return status.
1581 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1583 * gencode.c (build_instruction): Two arg MADD should
1584 not assign result to $0.
1586 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1588 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1589 * sim/mips/configure.in: Regenerate.
1591 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1593 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1594 signed8, unsigned8 et.al. types.
1596 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1597 hosts when selecting subreg.
1599 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1601 * interp.c (sim_engine_run): Reset the ZERO register to zero
1602 regardless of FEATURE_WARN_ZERO.
1603 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1605 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1607 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1608 (SignalException): For BreakPoints ignore any mode bits and just
1610 (SignalException): Always set the CAUSE register.
1612 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1615 exception has been taken.
1617 * interp.c: Implement the ERET and mt/f sr instructions.
1619 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1621 * interp.c (SignalException): Don't bother restarting an
1624 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1626 * interp.c (SignalException): Really take an interrupt.
1627 (interrupt_event): Only deliver interrupts when enabled.
1629 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1631 * interp.c (sim_info): Only print info when verbose.
1632 (sim_info) Use sim_io_printf for output.
1634 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1639 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * interp.c (sim_do_command): Check for common commands if a
1642 simulator specific command fails.
1644 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1646 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1647 and simBE when DEBUG is defined.
1649 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1651 * interp.c (interrupt_event): New function. Pass exception event
1652 onto exception handler.
1654 * configure.in: Check for stdlib.h.
1655 * configure: Regenerate.
1657 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1658 variable declaration.
1659 (build_instruction): Initialize memval1.
1660 (build_instruction): Add UNUSED attribute to byte, bigend,
1662 (build_operands): Ditto.
1664 * interp.c: Fix GCC warnings.
1665 (sim_get_quit_code): Delete.
1667 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1668 * Makefile.in: Ditto.
1669 * configure: Re-generate.
1671 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1673 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675 * interp.c (mips_option_handler): New function parse argumes using
1677 (myname): Replace with STATE_MY_NAME.
1678 (sim_open): Delete check for host endianness - performed by
1680 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1681 (sim_open): Move much of the initialization from here.
1682 (sim_load): To here. After the image has been loaded and
1684 (sim_open): Move ColdReset from here.
1685 (sim_create_inferior): To here.
1686 (sim_open): Make FP check less dependant on host endianness.
1688 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1690 * interp.c (sim_set_callbacks): Delete.
1692 * interp.c (membank, membank_base, membank_size): Replace with
1693 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1694 (sim_open): Remove call to callback->init. gdb/run do this.
1698 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1700 * interp.c (big_endian_p): Delete, replaced by
1701 current_target_byte_order.
1703 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705 * interp.c (host_read_long, host_read_word, host_swap_word,
1706 host_swap_long): Delete. Using common sim-endian.
1707 (sim_fetch_register, sim_store_register): Use H2T.
1708 (pipeline_ticks): Delete. Handled by sim-events.
1710 (sim_engine_run): Update.
1712 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1714 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1716 (SignalException): To here. Signal using sim_engine_halt.
1717 (sim_stop_reason): Delete, moved to common.
1719 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1721 * interp.c (sim_open): Add callback argument.
1722 (sim_set_callbacks): Delete SIM_DESC argument.
1725 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727 * Makefile.in (SIM_OBJS): Add common modules.
1729 * interp.c (sim_set_callbacks): Also set SD callback.
1730 (set_endianness, xfer_*, swap_*): Delete.
1731 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1732 Change to functions using sim-endian macros.
1733 (control_c, sim_stop): Delete, use common version.
1734 (simulate): Convert into.
1735 (sim_engine_run): This function.
1736 (sim_resume): Delete.
1738 * interp.c (simulation): New variable - the simulator object.
1739 (sim_kind): Delete global - merged into simulation.
1740 (sim_load): Cleanup. Move PC assignment from here.
1741 (sim_create_inferior): To here.
1743 * sim-main.h: New file.
1744 * interp.c (sim-main.h): Include.
1746 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1748 * configure: Regenerated to track ../common/aclocal.m4 changes.
1750 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1752 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1754 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1756 * gencode.c (build_instruction): DIV instructions: check
1757 for division by zero and integer overflow before using
1758 host's division operation.
1760 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1762 * Makefile.in (SIM_OBJS): Add sim-load.o.
1763 * interp.c: #include bfd.h.
1764 (target_byte_order): Delete.
1765 (sim_kind, myname, big_endian_p): New static locals.
1766 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1767 after argument parsing. Recognize -E arg, set endianness accordingly.
1768 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1769 load file into simulator. Set PC from bfd.
1770 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1771 (set_endianness): Use big_endian_p instead of target_byte_order.
1773 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775 * interp.c (sim_size): Delete prototype - conflicts with
1776 definition in remote-sim.h. Correct definition.
1778 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1780 * configure: Regenerated to track ../common/aclocal.m4 changes.
1783 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1785 * interp.c (sim_open): New arg `kind'.
1787 * configure: Regenerated to track ../common/aclocal.m4 changes.
1789 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1791 * configure: Regenerated to track ../common/aclocal.m4 changes.
1793 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1795 * interp.c (sim_open): Set optind to 0 before calling getopt.
1797 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1799 * configure: Regenerated to track ../common/aclocal.m4 changes.
1801 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1803 * interp.c : Replace uses of pr_addr with pr_uword64
1804 where the bit length is always 64 independent of SIM_ADDR.
1805 (pr_uword64) : added.
1807 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1809 * configure: Re-generate.
1811 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1813 * configure: Regenerate to track ../common/aclocal.m4 changes.
1815 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1817 * interp.c (sim_open): New SIM_DESC result. Argument is now
1819 (other sim_*): New SIM_DESC argument.
1821 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1823 * interp.c: Fix printing of addresses for non-64-bit targets.
1824 (pr_addr): Add function to print address based on size.
1826 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1828 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1830 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1832 * gencode.c (build_mips16_operands): Correct computation of base
1833 address for extended PC relative instruction.
1835 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1837 * interp.c (mips16_entry): Add support for floating point cases.
1838 (SignalException): Pass floating point cases to mips16_entry.
1839 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1841 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1843 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1844 and then set the state to fmt_uninterpreted.
1845 (COP_SW): Temporarily set the state to fmt_word while calling
1848 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1850 * gencode.c (build_instruction): The high order may be set in the
1851 comparison flags at any ISA level, not just ISA 4.
1853 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1855 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1856 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1857 * configure.in: sinclude ../common/aclocal.m4.
1858 * configure: Regenerated.
1860 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1862 * configure: Rebuild after change to aclocal.m4.
1864 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1866 * configure configure.in Makefile.in: Update to new configure
1867 scheme which is more compatible with WinGDB builds.
1868 * configure.in: Improve comment on how to run autoconf.
1869 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1870 * Makefile.in: Use autoconf substitution to install common
1873 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1875 * gencode.c (build_instruction): Use BigEndianCPU instead of
1878 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1880 * interp.c (sim_monitor): Make output to stdout visible in
1881 wingdb's I/O log window.
1883 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1885 * support.h: Undo previous change to SIGTRAP
1888 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1890 * interp.c (store_word, load_word): New static functions.
1891 (mips16_entry): New static function.
1892 (SignalException): Look for mips16 entry and exit instructions.
1893 (simulate): Use the correct index when setting fpr_state after
1894 doing a pending move.
1896 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1898 * interp.c: Fix byte-swapping code throughout to work on
1899 both little- and big-endian hosts.
1901 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1903 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1904 with gdb/config/i386/xm-windows.h.
1906 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1908 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1909 that messes up arithmetic shifts.
1911 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1913 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1914 SIGTRAP and SIGQUIT for _WIN32.
1916 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1918 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1919 force a 64 bit multiplication.
1920 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1921 destination register is 0, since that is the default mips16 nop
1924 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1926 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1927 (build_endian_shift): Don't check proc64.
1928 (build_instruction): Always set memval to uword64. Cast op2 to
1929 uword64 when shifting it left in memory instructions. Always use
1930 the same code for stores--don't special case proc64.
1932 * gencode.c (build_mips16_operands): Fix base PC value for PC
1934 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1936 * interp.c (simJALDELAYSLOT): Define.
1937 (JALDELAYSLOT): Define.
1938 (INDELAYSLOT, INJALDELAYSLOT): Define.
1939 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1941 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1943 * interp.c (sim_open): add flush_cache as a PMON routine
1944 (sim_monitor): handle flush_cache by ignoring it
1946 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1948 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1950 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1951 (BigEndianMem): Rename to ByteSwapMem and change sense.
1952 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1953 BigEndianMem references to !ByteSwapMem.
1954 (set_endianness): New function, with prototype.
1955 (sim_open): Call set_endianness.
1956 (sim_info): Use simBE instead of BigEndianMem.
1957 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1958 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1959 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1960 ifdefs, keeping the prototype declaration.
1961 (swap_word): Rewrite correctly.
1962 (ColdReset): Delete references to CONFIG. Delete endianness related
1963 code; moved to set_endianness.
1965 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1967 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1968 * interp.c (CHECKHILO): Define away.
1969 (simSIGINT): New macro.
1970 (membank_size): Increase from 1MB to 2MB.
1971 (control_c): New function.
1972 (sim_resume): Rename parameter signal to signal_number. Add local
1973 variable prev. Call signal before and after simulate.
1974 (sim_stop_reason): Add simSIGINT support.
1975 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1977 (sim_warning): Delete call to SignalException. Do call printf_filtered
1979 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1980 a call to sim_warning.
1982 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1984 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1985 16 bit instructions.
1987 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1989 Add support for mips16 (16 bit MIPS implementation):
1990 * gencode.c (inst_type): Add mips16 instruction encoding types.
1991 (GETDATASIZEINSN): Define.
1992 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1993 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1995 (MIPS16_DECODE): New table, for mips16 instructions.
1996 (bitmap_val): New static function.
1997 (struct mips16_op): Define.
1998 (mips16_op_table): New table, for mips16 operands.
1999 (build_mips16_operands): New static function.
2000 (process_instructions): If PC is odd, decode a mips16
2001 instruction. Break out instruction handling into new
2002 build_instruction function.
2003 (build_instruction): New static function, broken out of
2004 process_instructions. Check modifiers rather than flags for SHIFT
2005 bit count and m[ft]{hi,lo} direction.
2006 (usage): Pass program name to fprintf.
2007 (main): Remove unused variable this_option_optind. Change
2008 ``*loptarg++'' to ``loptarg++''.
2009 (my_strtoul): Parenthesize && within ||.
2010 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2011 (simulate): If PC is odd, fetch a 16 bit instruction, and
2012 increment PC by 2 rather than 4.
2013 * configure.in: Add case for mips16*-*-*.
2014 * configure: Rebuild.
2016 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2018 * interp.c: Allow -t to enable tracing in standalone simulator.
2019 Fix garbage output in trace file and error messages.
2021 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2023 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2024 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2025 * configure.in: Simplify using macros in ../common/aclocal.m4.
2026 * configure: Regenerated.
2027 * tconfig.in: New file.
2029 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2031 * interp.c: Fix bugs in 64-bit port.
2032 Use ansi function declarations for msvc compiler.
2033 Initialize and test file pointer in trace code.
2034 Prevent duplicate definition of LAST_EMED_REGNUM.
2036 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2038 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2040 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2042 * interp.c (SignalException): Check for explicit terminating
2044 * gencode.c: Pass instruction value through SignalException()
2045 calls for Trap, Breakpoint and Syscall.
2047 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2049 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2050 only used on those hosts that provide it.
2051 * configure.in: Add sqrt() to list of functions to be checked for.
2052 * config.in: Re-generated.
2053 * configure: Re-generated.
2055 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2057 * gencode.c (process_instructions): Call build_endian_shift when
2058 expanding STORE RIGHT, to fix swr.
2059 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2060 clear the high bits.
2061 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2062 Fix float to int conversions to produce signed values.
2064 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2066 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2067 (process_instructions): Correct handling of nor instruction.
2068 Correct shift count for 32 bit shift instructions. Correct sign
2069 extension for arithmetic shifts to not shift the number of bits in
2070 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2071 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2073 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2074 It's OK to have a mult follow a mult. What's not OK is to have a
2075 mult follow an mfhi.
2076 (Convert): Comment out incorrect rounding code.
2078 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2080 * interp.c (sim_monitor): Improved monitor printf
2081 simulation. Tidied up simulator warnings, and added "--log" option
2082 for directing warning message output.
2083 * gencode.c: Use sim_warning() rather than WARNING macro.
2085 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2087 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2088 getopt1.o, rather than on gencode.c. Link objects together.
2089 Don't link against -liberty.
2090 (gencode.o, getopt.o, getopt1.o): New targets.
2091 * gencode.c: Include <ctype.h> and "ansidecl.h".
2092 (AND): Undefine after including "ansidecl.h".
2093 (ULONG_MAX): Define if not defined.
2094 (OP_*): Don't define macros; now defined in opcode/mips.h.
2095 (main): Call my_strtoul rather than strtoul.
2096 (my_strtoul): New static function.
2098 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2100 * gencode.c (process_instructions): Generate word64 and uword64
2101 instead of `long long' and `unsigned long long' data types.
2102 * interp.c: #include sysdep.h to get signals, and define default
2104 * (Convert): Work around for Visual-C++ compiler bug with type
2106 * support.h: Make things compile under Visual-C++ by using
2107 __int64 instead of `long long'. Change many refs to long long
2108 into word64/uword64 typedefs.
2110 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2112 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2113 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2115 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2116 (AC_PROG_INSTALL): Added.
2117 (AC_PROG_CC): Moved to before configure.host call.
2118 * configure: Rebuilt.
2120 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2122 * configure.in: Define @SIMCONF@ depending on mips target.
2123 * configure: Rebuild.
2124 * Makefile.in (run): Add @SIMCONF@ to control simulator
2126 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2127 * interp.c: Remove some debugging, provide more detailed error
2128 messages, update memory accesses to use LOADDRMASK.
2130 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2132 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2133 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2135 * configure: Rebuild.
2136 * config.in: New file, generated by autoheader.
2137 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2138 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2139 HAVE_ANINT and HAVE_AINT, as appropriate.
2140 * Makefile.in (run): Use @LIBS@ rather than -lm.
2141 (interp.o): Depend upon config.h.
2142 (Makefile): Just rebuild Makefile.
2143 (clean): Remove stamp-h.
2144 (mostlyclean): Make the same as clean, not as distclean.
2145 (config.h, stamp-h): New targets.
2147 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2149 * interp.c (ColdReset): Fix boolean test. Make all simulator
2152 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2154 * interp.c (xfer_direct_word, xfer_direct_long,
2155 swap_direct_word, swap_direct_long, xfer_big_word,
2156 xfer_big_long, xfer_little_word, xfer_little_long,
2157 swap_word,swap_long): Added.
2158 * interp.c (ColdReset): Provide function indirection to
2159 host<->simulated_target transfer routines.
2160 * interp.c (sim_store_register, sim_fetch_register): Updated to
2161 make use of indirected transfer routines.
2163 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2165 * gencode.c (process_instructions): Ensure FP ABS instruction
2167 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2168 system call support.
2170 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2172 * interp.c (sim_do_command): Complain if callback structure not
2175 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2177 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2178 support for Sun hosts.
2179 * Makefile.in (gencode): Ensure the host compiler and libraries
2180 used for cross-hosted build.
2182 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2184 * interp.c, gencode.c: Some more (TODO) tidying.
2186 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2188 * gencode.c, interp.c: Replaced explicit long long references with
2189 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2190 * support.h (SET64LO, SET64HI): Macros added.
2192 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2194 * configure: Regenerate with autoconf 2.7.
2196 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2198 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2199 * support.h: Remove superfluous "1" from #if.
2200 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2202 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2204 * interp.c (StoreFPR): Control UndefinedResult() call on
2205 WARN_RESULT manifest.
2207 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2209 * gencode.c: Tidied instruction decoding, and added FP instruction
2212 * interp.c: Added dineroIII, and BSD profiling support. Also
2213 run-time FP handling.
2215 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2217 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2218 gencode.c, interp.c, support.h: created.
projects / deliverable / binutils-gdb.git / blob