sim/mips/ChangeLog

   1 2007-02-17  Thiemo Seufer  <ths@mips.com>
   2
   3         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
   4         Add mdmx to sim_igen_machine.
   5         (mipsisa64*-*-*): Likewise. Remove dsp.
   6         (mipsisa32*-*-*): Remove dsp.
   7         * configure: Regenerate.
   8
   9 2007-02-13  Thiemo Seufer  <ths@mips.com>
  10
  11         * configure.ac: Add mips*-sde-elf* target.
  12         * configure: Regenerate.
  13
  14 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
  15
  16         * acconfig.h: Remove.
  17         * config.in, configure: Regenerate.
  18
  19 2006-11-07  Thiemo Seufer  <ths@mips.com>
  20
  21         * dsp.igen (do_w_op): Fix compiler warning.
  22
  23 2006-08-29  Thiemo Seufer  <ths@mips.com>
  24             David Ung  <davidu@mips.com>
  25
  26         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
  27         sim_igen_machine.
  28         * configure: Regenerate.
  29         * mips.igen (model): Add smartmips.
  30         (MADDU): Increment ACX if carry.
  31         (do_mult): Clear ACX.
  32         (ROR,RORV): Add smartmips.
  33         (include): Include smartmips.igen.
  34         * sim-main.h (ACX): Set to REGISTERS[89].
  35         * smartmips.igen: New file.
  36
  37 2006-08-29  Thiemo Seufer  <ths@mips.com>
  38             David Ung  <davidu@mips.com>
  39
  40         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
  41         mips3264r2.igen. Add missing dependency rules.
  42         * m16e.igen: Support for mips16e save/restore instructions.
  43
  44 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
  45
  46         * configure: Regenerated.
  47
  48 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
  49
  50         * configure: Regenerated.
  51
  52 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
  53
  54         * configure: Regenerated.
  55
  56 2006-05-15 Chao-ying Fu  <fu@mips.com>
  57
  58         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
  59
  60 2006-04-18  Nick Clifton  <nickc@redhat.com>
  61
  62         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
  63         statement.
  64
  65 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
  66
  67         * configure: Regenerate.
  68
  69 2005-12-14  Chao-ying Fu  <fu@mips.com>
  70
  71         * Makefile.in (SIM_OBJS): Add dsp.o.
  72         (dsp.o): New dependency.
  73         (IGEN_INCLUDE): Add dsp.igen.
  74         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
  75         mipsisa64*-*-*): Add dsp to sim_igen_machine.
  76         * configure: Regenerate.
  77         * mips.igen: Add dsp model and include dsp.igen.
  78         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
  79         because these instructions are extended in DSP ASE.
  80         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
  81         adding 6 DSP accumulator registers and 1 DSP control register.
  82         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
  83         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
  84         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
  85         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
  86         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
  87         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
  88         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
  89         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
  90         DSPCR_CCOND_SMASK): New define.
  91         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
  92         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
  93
  94 2005-07-08  Ian Lance Taylor  <ian@airs.com>
  95
  96         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
  97
  98 2005-06-16  David Ung  <davidu@mips.com>
  99             Nigel Stephens  <nigel@mips.com>
 100
 101         * mips.igen: New mips16e model and include m16e.igen.
 102         (check_u64): Add mips16e tag.
 103         * m16e.igen: New file for MIPS16e instructions.
 104         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 105         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 106         models.
 107         * configure: Regenerate.
 108
 109 2005-05-26  David Ung  <davidu@mips.com>
 110
 111         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 112         tags to all instructions which are applicable to the new ISAs.
 113         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 114         vr.igen.
 115         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 116         instructions.
 117         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 118         to mips.igen.
 119         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 120         * configure: Regenerate.
 121
 122 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 123
 124         * configure: Regenerate.
 125
 126 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 127
 128         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 129         explicit call to AC_CONFIG_HEADER.
 130         * configure: Regenerate.
 131
 132 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 133
 134         * configure.ac: Update to use ../common/common.m4.
 135         * configure: Re-generate.
 136
 137 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 138
 139         * configure: Regenerated to track ../common/aclocal.m4 changes.
 140
 141 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 142
 143         * configure.ac: Rename configure.in, require autoconf 2.59.
 144         * configure: Re-generate.
 145
 146 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 147
 148         * configure: Regenerate for ../common/aclocal.m4 update.
 149
 150 2004-09-24  Monika Chaddha  <monika@acmet.com>
 151
 152         Committed by Andrew Cagney.
 153         * m16.igen (CMP, CMPI): Fix assembler.
 154
 155 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 156
 157         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 158         * configure: Regenerate.
 159
 160 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 161
 162         * configure.in (sim_m16_machine): Include mipsIII.
 163         * configure: Regenerate.
 164
 165 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 166
 167         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 168         from COP0_BADVADDR.
 169         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 170
 171 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 172
 173         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 174
 175 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 176
 177         * mips.igen (check_fmt): Remove.
 178         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 179         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 180         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 181         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 182         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 183         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 184         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 185         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 186         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 187         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 188
 189 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 190
 191         * sb1.igen (check_sbx): New function.
 192         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 193
 194 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 195             Richard Sandiford  <rsandifo@redhat.com>
 196
 197         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 198         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 199         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 200         separate implementations for mipsIV and mipsV.  Use new macros to
 201         determine whether the restrictions apply.
 202
 203 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 204
 205         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 206         (check_mult_hilo): Improve comments.
 207         (check_div_hilo): Likewise.  Also, fork off a new version
 208         to handle mips32/mips64 (since there are no hazards to check
 209         in MIPS32/MIPS64).
 210
 211 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 212
 213         * mips.igen (do_dmultx): Fix check for negative operands.
 214
 215 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 216
 217         * Makefile.in (SHELL): Make sure this is defined.
 218         (various): Use $(SHELL) whenever we invoke move-if-change.
 219
 220 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 221
 222         * cp1.c: Tweak attribution slightly.
 223         * cp1.h: Likewise.
 224         * mdmx.c: Likewise.
 225         * mdmx.igen: Likewise.
 226         * mips3d.igen: Likewise.
 227         * sb1.igen: Likewise.
 228
 229 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 230
 231         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 232         unsigned operands.
 233
 234 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 235
 236         * interp.c (sim_open): Rename _bfd to bfd.
 237         (sim_create_inferior): Ditto.
 238
 239 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 240
 241         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 242
 243 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 244
 245         * mips.igen (EI, DI): Remove.
 246
 247 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 248
 249         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 250
 251 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 252             Andrew Cagney  <ac131313@redhat.com>
 253             Gavin Romig-Koch  <gavin@redhat.com>
 254             Graydon Hoare  <graydon@redhat.com>
 255             Aldy Hernandez  <aldyh@redhat.com>
 256             Dave Brolley  <brolley@redhat.com>
 257             Chris Demetriou  <cgd@broadcom.com>
 258
 259         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 260         (sim_mach_default): New variable.
 261         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 262         Add a new simulator generator, MULTI.
 263         * configure: Regenerate.
 264         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 265         (multi-run.o): New dependency.
 266         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 267         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 268         (tmp-multi): Combine them.
 269         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 270         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 271         (distclean-extra): New rule.
 272         * sim-main.h: Include bfd.h.
 273         (MIPS_MACH): New macro.
 274         * mips.igen (vr4120, vr5400, vr5500): New models.
 275         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 276         * vr.igen: Replace with new version.
 277
 278 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 279
 280         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 281         * configure: Regenerate.
 282
 283 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 284
 285         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 286         * mips.igen: Remove all invocations of check_branch_bug and
 287         mark_branch_bug.
 288
 289 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 290
 291         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 292
 293 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 294
 295         * mips.igen (do_load_double, do_store_double): New functions.
 296         (LDC1, SDC1): Rename to...
 297         (LDC1b, SDC1b): respectively.
 298         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 299
 300 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 301
 302         * cp1.c (fp_recip2): Modify initialization expression so that
 303         GCC will recognize it as constant.
 304
 305 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 306
 307         * mdmx.c (SD_): Delete.
 308         (Unpredictable): Re-define, for now, to directly invoke
 309         unpredictable_action().
 310         (mdmx_acc_op): Fix error in .ob immediate handling.
 311
 312 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 313
 314         * interp.c (sim_firmware_command): Initialize `address'.
 315
 316 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 317
 318         * configure: Regenerated to track ../common/aclocal.m4 changes.
 319
 320 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 321             Ed Satterthwaite  <ehs@broadcom.com>
 322
 323         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 324         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 325         * mips.igen: Include mips3d.igen.
 326         (mips3d): New model name for MIPS-3D ASE instructions.
 327         (CVT.W.fmt): Don't use this instruction for word (source) format
 328         instructions.
 329         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 330         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 331         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 332         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 333         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 334         (RSquareRoot1, RSquareRoot2): New macros.
 335         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 336         (fp_rsqrt2): New functions.
 337         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 338         * configure: Regenerate.
 339
 340 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 341             Ed Satterthwaite  <ehs@broadcom.com>
 342
 343         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 344         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 345         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 346         (convert): Note that this function is not used for paired-single
 347         format conversions.
 348         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 349         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 350         (check_fmt_p): Enable paired-single support.
 351         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 352         (PUU.PS): New instructions.
 353         (CVT.S.fmt): Don't use this instruction for paired-single format
 354         destinations.
 355         * sim-main.h (FP_formats): New value 'fmt_ps.'
 356         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 357         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 358
 359 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 360
 361         * mips.igen: Fix formatting of function calls in
 362         many FP operations.
 363
 364 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 365
 366         * mips.igen (MOVN, MOVZ): Trace result.
 367         (TNEI): Print "tnei" as the opcode name in traces.
 368         (CEIL.W): Add disassembly string for traces.
 369         (RSQRT.fmt): Make location of disassembly string consistent
 370         with other instructions.
 371
 372 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 373
 374         * mips.igen (X): Delete unused function.
 375
 376 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 377
 378         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 379
 380 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 381             Ed Satterthwaite  <ehs@broadcom.com>
 382
 383         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 384         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 385         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 386         (fp_nmsub): New prototypes.
 387         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 388         (NegMultiplySub): New defines.
 389         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 390         (MADD.D, MADD.S): Replace with...
 391         (MADD.fmt): New instruction.
 392         (MSUB.D, MSUB.S): Replace with...
 393         (MSUB.fmt): New instruction.
 394         (NMADD.D, NMADD.S): Replace with...
 395         (NMADD.fmt): New instruction.
 396         (NMSUB.D, MSUB.S): Replace with...
 397         (NMSUB.fmt): New instruction.
 398
 399 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 400             Ed Satterthwaite  <ehs@broadcom.com>
 401
 402         * cp1.c: Fix more comment spelling and formatting.
 403         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 404         (denorm_mode): New function.
 405         (fpu_unary, fpu_binary): Round results after operation, collect
 406         status from rounding operations, and update the FCSR.
 407         (convert): Collect status from integer conversions and rounding
 408         operations, and update the FCSR.  Adjust NaN values that result
 409         from conversions.  Convert to use sim_io_eprintf rather than
 410         fprintf, and remove some debugging code.
 411         * cp1.h (fenr_FS): New define.
 412
 413 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 414
 415         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 416         rounding mode to sim FP rounding mode flag conversion code into...
 417         (rounding_mode): New function.
 418
 419 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 420
 421         * cp1.c: Clean up formatting of a few comments.
 422         (value_fpr): Reformat switch statement.
 423
 424 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 425             Ed Satterthwaite  <ehs@broadcom.com>
 426
 427         * cp1.h: New file.
 428         * sim-main.h: Include cp1.h.
 429         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 430         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 431         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 432         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 433         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 434         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 435         * cp1.c: Don't include sim-fpu.h; already included by
 436         sim-main.h.  Clean up formatting of some comments.
 437         (NaN, Equal, Less): Remove.
 438         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 439         (fp_cmp): New functions.
 440         * mips.igen (do_c_cond_fmt): Remove.
 441         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 442         Compare.  Add result tracing.
 443         (CxC1): Remove, replace with...
 444         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 445         (DMxC1): Remove, replace with...
 446         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 447         (MxC1): Remove, replace with...
 448         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 449
 450 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 451
 452         * sim-main.h (FGRIDX): Remove, replace all uses with...
 453         (FGR_BASE): New macro.
 454         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 455         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 456         (NR_FGR, FGR): Likewise.
 457         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 458         * mips.igen: Likewise.
 459
 460 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 461
 462         * cp1.c: Add an FSF Copyright notice to this file.
 463
 464 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 465             Ed Satterthwaite  <ehs@broadcom.com>
 466
 467         * cp1.c (Infinity): Remove.
 468         * sim-main.h (Infinity): Likewise.
 469
 470         * cp1.c (fp_unary, fp_binary): New functions.
 471         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 472         (fp_sqrt): New functions, implemented in terms of the above.
 473         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 474         (Recip, SquareRoot): Remove (replaced by functions above).
 475         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 476         (fp_recip, fp_sqrt): New prototypes.
 477         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 478         (Recip, SquareRoot): Replace prototypes with #defines which
 479         invoke the functions above.
 480
 481 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 482
 483         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 484         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 485         file, remove PARAMS from prototypes.
 486         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 487         simulator state arguments.
 488         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 489         pass simulator state arguments.
 490         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 491         (store_fpr, convert): Remove 'sd' argument.
 492         (value_fpr): Likewise.  Convert to use 'SD' instead.
 493
 494 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 495
 496         * cp1.c (Min, Max): Remove #if 0'd functions.
 497         * sim-main.h (Min, Max): Remove.
 498
 499 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 500
 501         * cp1.c: fix formatting of switch case and default labels.
 502         * interp.c: Likewise.
 503         * sim-main.c: Likewise.
 504
 505 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 506
 507         * cp1.c: Clean up comments which describe FP formats.
 508          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 509
 510 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 511             Ed Satterthwaite  <ehs@broadcom.com>
 512
 513         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 514         Broadcom SiByte SB-1 processor configurations.
 515         * configure: Regenerate.
 516         * sb1.igen: New file.
 517         * mips.igen: Include sb1.igen.
 518         (sb1): New model.
 519         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 520         * mdmx.igen: Add "sb1" model to all appropriate functions and
 521         instructions.
 522         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 523         (ob_func, ob_acc): Reference the above.
 524         (qh_acc): Adjust to keep the same size as ob_acc.
 525         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 526         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 527
 528 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 529
 530         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 531
 532 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 533             Ed Satterthwaite  <ehs@broadcom.com>
 534
 535         * mips.igen (mdmx): New (pseudo-)model.
 536         * mdmx.c, mdmx.igen: New files.
 537         * Makefile.in (SIM_OBJS): Add mdmx.o.
 538         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 539         New typedefs.
 540         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 541         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 542         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 543         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 544         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 545         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 546         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 547         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 548         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 549         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 550         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 551         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 552         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 553         (qh_fmtsel): New macros.
 554         (_sim_cpu): New member "acc".
 555         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 556         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 557
 558 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 559
 560         * interp.c: Use 'deprecated' rather than 'depreciated.'
 561         * sim-main.h: Likewise.
 562
 563 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 564
 565         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 566         which wouldn't compile anyway.
 567         * sim-main.h (unpredictable_action): New function prototype.
 568         (Unpredictable): Define to call igen function unpredictable().
 569         (NotWordValue): New macro to call igen function not_word_value().
 570         (UndefinedResult): Remove.
 571         * interp.c (undefined_result): Remove.
 572         (unpredictable_action): New function.
 573         * mips.igen (not_word_value, unpredictable): New functions.
 574         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 575         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 576         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 577         NotWordValue() to check for unpredictable inputs, then
 578         Unpredictable() to handle them.
 579
 580 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 581
 582         * mips.igen: Fix formatting of calls to Unpredictable().
 583
 584 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 585
 586         * interp.c (sim_open): Revert previous change.
 587
 588 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 589
 590         * interp.c (sim_open): Disable chunk of code that wrote code in
 591         vector table entries.
 592
 593 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 594
 595         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 596         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 597         unused definitions.
 598
 599 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 600
 601         * cp1.c: Fix many formatting issues.
 602
 603 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 604
 605         * cp1.c (fpu_format_name): New function to replace...
 606         (DOFMT): This.  Delete, and update all callers.
 607         (fpu_rounding_mode_name): New function to replace...
 608         (RMMODE): This.  Delete, and update all callers.
 609
 610 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 611
 612         * interp.c: Move FPU support routines from here to...
 613         * cp1.c: Here.  New file.
 614         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 615         (cp1.o): New target.
 616
 617 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 618
 619         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 620         * mips.igen (mips32, mips64): New models, add to all instructions
 621         and functions as appropriate.
 622         (loadstore_ea, check_u64): New variant for model mips64.
 623         (check_fmt_p): New variant for models mipsV and mips64, remove
 624         mipsV model marking fro other variant.
 625         (SLL) Rename to...
 626         (SLLa) this.
 627         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 628         for mips32 and mips64.
 629         (DCLO, DCLZ): New instructions for mips64.
 630
 631 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 632
 633         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 634         immediate or code as a hex value with the "%#lx" format.
 635         (ANDI): Likewise, and fix printed instruction name.
 636
 637 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 638
 639         * sim-main.h (UndefinedResult, Unpredictable): New macros
 640         which currently do nothing.
 641
 642 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 643
 644         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 645         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 646         (status_CU3): New definitions.
 647
 648         * sim-main.h (ExceptionCause): Add new values for MIPS32
 649         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 650         for DebugBreakPoint and NMIReset to note their status in
 651         MIPS32 and MIPS64.
 652         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 653         (SignalExceptionCacheErr): New exception macros.
 654
 655 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 656
 657         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 658         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 659         is always enabled.
 660         (SignalExceptionCoProcessorUnusable): Take as argument the
 661         unusable coprocessor number.
 662
 663 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 664
 665         * mips.igen: Fix formatting of all SignalException calls.
 666
 667 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 668
 669         * sim-main.h (SIGNEXTEND): Remove.
 670
 671 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 672
 673         * mips.igen: Remove gencode comment from top of file, fix
 674         spelling in another comment.
 675
 676 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 677
 678         * mips.igen (check_fmt, check_fmt_p): New functions to check
 679         whether specific floating point formats are usable.
 680         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 681         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 682         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 683         Use the new functions.
 684         (do_c_cond_fmt): Remove format checks...
 685         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 686
 687 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 688
 689         * mips.igen: Fix formatting of check_fpu calls.
 690
 691 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 692
 693         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 694
 695 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 696
 697         * mips.igen: Remove whitespace at end of lines.
 698
 699 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 700
 701         * mips.igen (loadstore_ea): New function to do effective
 702         address calculations.
 703         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 704         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 705         CACHE): Use loadstore_ea to do effective address computations.
 706
 707 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 708
 709         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 710         * mips.igen (LL, CxC1, MxC1): Likewise.
 711
 712 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 713
 714         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 715         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 716         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 717         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 718         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 719         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 720         Don't split opcode fields by hand, use the opcode field values
 721         provided by igen.
 722
 723 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 724
 725         * mips.igen (do_divu): Fix spacing.
 726
 727         * mips.igen (do_dsllv): Move to be right before DSLLV,
 728         to match the rest of the do_<shift> functions.
 729
 730 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 731
 732         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 733         DSRL32, do_dsrlv): Trace inputs and results.
 734
 735 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 736
 737         * mips.igen (CACHE): Provide instruction-printing string.
 738
 739         * interp.c (signal_exception): Comment tokens after #endif.
 740
 741 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 742
 743         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 744         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 745         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 746         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 747         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 748         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 749         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 750         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 751
 752 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 753
 754         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 755         instruction-printing string.
 756         (LWU): Use '64' as the filter flag.
 757
 758 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 759
 760         * mips.igen (SDXC1): Fix instruction-printing string.
 761
 762 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 763
 764         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 765         filter flags "32,f".
 766
 767 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 768
 769         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 770         as the filter flag.
 771
 772 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 773
 774         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 775         add a comma) so that it more closely match the MIPS ISA
 776         documentation opcode partitioning.
 777         (PREF): Put useful names on opcode fields, and include
 778         instruction-printing string.
 779
 780 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 781
 782         * mips.igen (check_u64): New function which in the future will
 783         check whether 64-bit instructions are usable and signal an
 784         exception if not.  Currently a no-op.
 785         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 786         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 787         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 788         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 789
 790         * mips.igen (check_fpu): New function which in the future will
 791         check whether FPU instructions are usable and signal an exception
 792         if not.  Currently a no-op.
 793         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 794         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 795         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 796         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 797         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 798         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 799         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 800         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 801
 802 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 803
 804         * mips.igen (do_load_left, do_load_right): Move to be immediately
 805         following do_load.
 806         (do_store_left, do_store_right): Move to be immediately following
 807         do_store.
 808
 809 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 810
 811         * mips.igen (mipsV): New model name.  Also, add it to
 812         all instructions and functions where it is appropriate.
 813
 814 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 815
 816         * mips.igen: For all functions and instructions, list model
 817         names that support that instruction one per line.
 818
 819 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 820
 821         * mips.igen: Add some additional comments about supported
 822         models, and about which instructions go where.
 823         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 824         order as is used in the rest of the file.
 825
 826 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 827
 828         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 829         indicating that ALU32_END or ALU64_END are there to check
 830         for overflow.
 831         (DADD): Likewise, but also remove previous comment about
 832         overflow checking.
 833
 834 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 835
 836         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 837         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 838         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 839         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 840         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 841         fields (i.e., add and move commas) so that they more closely
 842         match the MIPS ISA documentation opcode partitioning.
 843
 844 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 845
 846         * mips.igen (ADDI): Print immediate value.
 847         (BREAK): Print code.
 848         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 849         (SLL): Print "nop" specially, and don't run the code
 850         that does the shift for the "nop" case.
 851
 852 2001-11-17  Fred Fish  <fnf@redhat.com>
 853
 854         * sim-main.h (float_operation): Move enum declaration outside
 855         of _sim_cpu struct declaration.
 856
 857 2001-04-12  Jim Blandy  <jimb@redhat.com>
 858
 859         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 860         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 861         set of the FCSR.
 862         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 863         PENDING_FILL, and you can get the intended effect gracefully by
 864         calling PENDING_SCHED directly.
 865
 866 2001-02-23  Ben Elliston  <bje@redhat.com>
 867
 868         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 869         already defined elsewhere.
 870
 871 2001-02-19  Ben Elliston  <bje@redhat.com>
 872
 873         * sim-main.h (sim_monitor): Return an int.
 874         * interp.c (sim_monitor): Add return values.
 875         (signal_exception): Handle error conditions from sim_monitor.
 876
 877 2001-02-08  Ben Elliston  <bje@redhat.com>
 878
 879         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 880         (store_memory): Likewise, pass cia to sim_core_write*.
 881
 882 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 883
 884         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 885         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 886
 887 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 888
 889         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 890         * Makefile.in: Don't delete *.igen when cleaning directory.
 891
 892 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 893
 894         * m16.igen (break): Call SignalException not sim_engine_halt.
 895
 896 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 897
 898         From Jason Eckhardt:
 899         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 900
 901 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 902
 903         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 904
 905 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 906
 907         * mips.igen (do_dmultx): Fix typo.
 908
 909 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 910
 911         * configure: Regenerated to track ../common/aclocal.m4 changes.
 912
 913 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 914
 915         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 916
 917 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 918
 919         * sim-main.h (GPR_CLEAR): Define macro.
 920
 921 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 922
 923         * interp.c (decode_coproc): Output long using %lx and not %s.
 924
 925 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 926
 927         * interp.c (sim_open): Sort & extend dummy memory regions for
 928         --board=jmr3904 for eCos.
 929
 930 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 931
 932         * configure: Regenerated.
 933
 934 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 935
 936         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 937         calls, conditional on the simulator being in verbose mode.
 938
 939 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 940
 941         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 942         cache don't get ReservedInstruction traps.
 943
 944 1999-11-29  Mark Salter  <msalter@cygnus.com>
 945
 946         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 947         to clear status bits in sdisr register. This is how the hardware works.
 948
 949         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 950         being used by cygmon.
 951
 952 1999-11-11  Andrew Haley  <aph@cygnus.com>
 953
 954         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 955         instructions.
 956
 957 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 958
 959         * mips.igen (MULT): Correct previous mis-applied patch.
 960
 961 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 962
 963         * mips.igen (delayslot32): Handle sequence like
 964         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 965         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 966         (MULT): Actually pass the third register...
 967
 968 1999-09-03  Mark Salter  <msalter@cygnus.com>
 969
 970         * interp.c (sim_open): Added more memory aliases for additional
 971         hardware being touched by cygmon on jmr3904 board.
 972
 973 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 974
 975         * configure: Regenerated to track ../common/aclocal.m4 changes.
 976
 977 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 978
 979         * interp.c (sim_store_register): Handle case where client - GDB -
 980         specifies that a 4 byte register is 8 bytes in size.
 981         (sim_fetch_register): Ditto.
 982
 983 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 984
 985         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 986         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 987         (idt_monitor_base): Base address for IDT monitor traps.
 988         (pmon_monitor_base): Ditto for PMON.
 989         (lsipmon_monitor_base): Ditto for LSI PMON.
 990         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 991         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 992         (sim_firmware_command): New function.
 993         (mips_option_handler): Call it for OPTION_FIRMWARE.
 994         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 995         option was given, add no monitor by default.  Add BREAK hooks only if
 996         monitors are also there.
 997
 998 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 999
1000         * interp.c (sim_monitor): Flush output before reading input.
1001
1002 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1003
1004         * tconfig.in (SIM_HANDLES_LMA): Always define.
1005
1006 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1007
1008         From Mark Salter <msalter@cygnus.com>:
1009         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1010         (sim_open): Add setup for BSP board.
1011
1012 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1013
1014         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1015         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1016         them as unimplemented.
1017
1018 1999-05-08  Felix Lee  <flee@cygnus.com>
1019
1020         * configure: Regenerated to track ../common/aclocal.m4 changes.
1021
1022 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1023
1024         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1025
1026 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1027
1028         * configure.in: Any mips64vr5*-*-* target should have
1029         -DTARGET_ENABLE_FR=1.
1030         (default_endian): Any mips64vr*el-*-* target should default to
1031         LITTLE_ENDIAN.
1032         * configure: Re-generate.
1033
1034 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1035
1036         * mips.igen (ldl): Extend from _16_, not 32.
1037
1038 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1039
1040         * interp.c (sim_store_register): Force registers written to by GDB
1041         into an un-interpreted state.
1042
1043 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1044
1045         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1046         CPU, start periodic background I/O polls.
1047         (tx3904sio_poll): New function: periodic I/O poller.
1048
1049 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1050
1051         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1052
1053 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1054
1055         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1056         case statement.
1057
1058 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1059
1060         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1061         (load_word): Call SIM_CORE_SIGNAL hook on error.
1062         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1063         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1064         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1065         * sim-main.h (COP0_BADVADDR): Define.
1066         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1067         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1068         (_sim_cpu): Add exc_* fields to store register value snapshots.
1069         * mips.igen (*): Replace memory-related SignalException* calls
1070         with references to SIM_CORE_SIGNAL hook.
1071
1072         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1073         fix.
1074         * sim-main.c (*): Minor warning cleanups.
1075
1076 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1077
1078         * m16.igen (DADDIU5): Correct type-o.
1079
1080 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1081
1082         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1083         variables.
1084
1085 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1086
1087         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1088         to include path.
1089         (interp.o): Add dependency on itable.h
1090         (oengine.c, gencode): Delete remaining references.
1091         (BUILT_SRC_FROM_GEN): Clean up.
1092
1093 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1094
1095         * vr4run.c: New.
1096         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1097         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1098         tmp-run-hack) : New.
1099         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1100         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1101         Drop the "64" qualifier to get the HACK generator working.
1102         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1103         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1104         qualifier to get the hack generator working.
1105         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1106         (DSLL): Use do_dsll.
1107         (DSLLV): Use do_dsllv.
1108         (DSRA): Use do_dsra.
1109         (DSRL): Use do_dsrl.
1110         (DSRLV): Use do_dsrlv.
1111         (BC1): Move *vr4100 to get the HACK generator working.
1112         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1113         get the HACK generator working.
1114         (MACC) Rename to get the HACK generator working.
1115         (DMACC,MACCS,DMACCS): Add the 64.
1116
1117 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1118
1119         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1120         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1121
1122 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1123
1124     * mips/interp.c (DEBUG): Cleanups.
1125
1126 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1127
1128         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1129         (tx3904sio_tickle): fflush after a stdout character output.
1130
1131 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1132
1133         * interp.c (sim_close): Uninstall modules.
1134
1135 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1136
1137         * sim-main.h, interp.c (sim_monitor): Change to global
1138         function.
1139
1140 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1141
1142         * configure.in (vr4100): Only include vr4100 instructions in
1143         simulator.
1144         * configure: Re-generate.
1145         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1146
1147 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1148
1149         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1150         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1151         true alternative.
1152
1153         * configure.in (sim_default_gen, sim_use_gen): Replace with
1154         sim_gen.
1155         (--enable-sim-igen): Delete config option. Always using IGEN.
1156         * configure: Re-generate.
1157
1158         * Makefile.in (gencode): Kill, kill, kill.
1159         * gencode.c: Ditto.
1160
1161 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1162
1163         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1164         bit mips16 igen simulator.
1165         * configure: Re-generate.
1166
1167         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1168         as part of vr4100 ISA.
1169         * vr.igen: Mark all instructions as 64 bit only.
1170
1171 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1172
1173         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1174         Pacify GCC.
1175
1176 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1177
1178         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1179         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1180         * configure: Re-generate.
1181
1182         * m16.igen (BREAK): Define breakpoint instruction.
1183         (JALX32): Mark instruction as mips16 and not r3900.
1184         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1185
1186         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1187
1188 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1189
1190         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1191         insn as a debug breakpoint.
1192
1193         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1194         pending.slot_size.
1195         (PENDING_SCHED): Clean up trace statement.
1196         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1197         (PENDING_FILL): Delay write by only one cycle.
1198         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1199
1200         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1201         of pending writes.
1202         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1203         32 & 64.
1204         (pending_tick): Move incrementing of index to FOR statement.
1205         (pending_tick): Only update PENDING_OUT after a write has occured.
1206
1207         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1208         build simulator.
1209         * configure: Re-generate.
1210
1211         * interp.c (sim_engine_run OLD): Delete explicit call to
1212         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1213
1214 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1215
1216         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1217         interrupt level number to match changed SignalExceptionInterrupt
1218         macro.
1219
1220 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1221
1222         * interp.c: #include "itable.h" if WITH_IGEN.
1223         (get_insn_name): New function.
1224         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1225         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1226
1227 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1228
1229         * configure: Rebuilt to inhale new common/aclocal.m4.
1230
1231 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1232
1233         * dv-tx3904sio.c: Include sim-assert.h.
1234
1235 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1236
1237         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1238         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1239         Reorganize target-specific sim-hardware checks.
1240         * configure: rebuilt.
1241         * interp.c (sim_open): For tx39 target boards, set
1242         OPERATING_ENVIRONMENT, add tx3904sio devices.
1243         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1244         ROM executables.  Install dv-sockser into sim-modules list.
1245
1246         * dv-tx3904irc.c: Compiler warning clean-up.
1247         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1248         frequent hw-trace messages.
1249
1250 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1251
1252         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1253
1254 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1255
1256         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1257
1258         * vr.igen: New file.
1259         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1260         * mips.igen: Define vr4100 model. Include vr.igen.
1261 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1262
1263         * mips.igen (check_mf_hilo): Correct check.
1264
1265 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1266
1267         * sim-main.h (interrupt_event): Add prototype.
1268
1269         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1270         register_ptr, register_value.
1271         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1272
1273         * sim-main.h (tracefh): Make extern.
1274
1275 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1276
1277         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1278         Reduce unnecessarily high timer event frequency.
1279         * dv-tx3904cpu.c: Ditto for interrupt event.
1280
1281 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1282
1283         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1284         to allay warnings.
1285         (interrupt_event): Made non-static.
1286
1287         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1288         interchange of configuration values for external vs. internal
1289         clock dividers.
1290
1291 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1292
1293         * mips.igen (BREAK): Moved code to here for
1294         simulator-reserved break instructions.
1295         * gencode.c (build_instruction): Ditto.
1296         * interp.c (signal_exception): Code moved from here.  Non-
1297         reserved instructions now use exception vector, rather
1298         than halting sim.
1299         * sim-main.h: Moved magic constants to here.
1300
1301 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1302
1303         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1304         register upon non-zero interrupt event level, clear upon zero
1305         event value.
1306         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1307         by passing zero event value.
1308         (*_io_{read,write}_buffer): Endianness fixes.
1309         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1310         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1311
1312         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1313         serial I/O and timer module at base address 0xFFFF0000.
1314
1315 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1316
1317         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1318         and BigEndianCPU.
1319
1320 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1321
1322         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1323         parts.
1324         * configure: Update.
1325
1326 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1327
1328         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1329         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1330         * configure.in: Include tx3904tmr in hw_device list.
1331         * configure: Rebuilt.
1332         * interp.c (sim_open): Instantiate three timer instances.
1333         Fix address typo of tx3904irc instance.
1334
1335 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1336
1337         * interp.c (signal_exception): SystemCall exception now uses
1338         the exception vector.
1339
1340 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1341
1342         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1343         to allay warnings.
1344
1345 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1346
1347         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1348
1349 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1350
1351         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1352
1353         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1354         sim-main.h. Declare a struct hw_descriptor instead of struct
1355         hw_device_descriptor.
1356
1357 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1358
1359         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1360         right bits and then re-align left hand bytes to correct byte
1361         lanes.  Fix incorrect computation in do_store_left when loading
1362         bytes from second word.
1363
1364 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1365
1366         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1367         * interp.c (sim_open): Only create a device tree when HW is
1368         enabled.
1369
1370         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1371         * interp.c (signal_exception): Ditto.
1372
1373 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1374
1375         * gencode.c: Mark BEGEZALL as LIKELY.
1376
1377 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1378
1379         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1380         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1381
1382 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1383
1384         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1385         modules.  Recognize TX39 target with "mips*tx39" pattern.
1386         * configure: Rebuilt.
1387         * sim-main.h (*): Added many macros defining bits in
1388         TX39 control registers.
1389         (SignalInterrupt): Send actual PC instead of NULL.
1390         (SignalNMIReset): New exception type.
1391         * interp.c (board): New variable for future use to identify
1392         a particular board being simulated.
1393         (mips_option_handler,mips_options): Added "--board" option.
1394         (interrupt_event): Send actual PC.
1395         (sim_open): Make memory layout conditional on board setting.
1396         (signal_exception): Initial implementation of hardware interrupt
1397         handling.  Accept another break instruction variant for simulator
1398         exit.
1399         (decode_coproc): Implement RFE instruction for TX39.
1400         (mips.igen): Decode RFE instruction as such.
1401         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1402         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1403         bbegin to implement memory map.
1404         * dv-tx3904cpu.c: New file.
1405         * dv-tx3904irc.c: New file.
1406
1407 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1408
1409         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1410
1411 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1412
1413         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1414         with calls to check_div_hilo.
1415
1416 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1417
1418         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1419         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1420         Add special r3900 version of do_mult_hilo.
1421         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1422         with calls to check_mult_hilo.
1423         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1424         with calls to check_div_hilo.
1425
1426 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1427
1428         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1429         Document a replacement.
1430
1431 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1432
1433         * interp.c (sim_monitor): Make mon_printf work.
1434
1435 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1436
1437         * sim-main.h (INSN_NAME): New arg `cpu'.
1438
1439 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1440
1441         * configure: Regenerated to track ../common/aclocal.m4 changes.
1442
1443 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1444
1445         * configure: Regenerated to track ../common/aclocal.m4 changes.
1446         * config.in: Ditto.
1447
1448 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1449
1450         * acconfig.h: New file.
1451         * configure.in: Reverted change of Apr 24; use sinclude again.
1452
1453 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1454
1455         * configure: Regenerated to track ../common/aclocal.m4 changes.
1456         * config.in: Ditto.
1457
1458 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1459
1460         * configure.in: Don't call sinclude.
1461
1462 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1463
1464         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1465
1466 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1467
1468         * mips.igen (ERET): Implement.
1469
1470         * interp.c (decode_coproc): Return sign-extended EPC.
1471
1472         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1473
1474         * interp.c (signal_exception): Do not ignore Trap.
1475         (signal_exception): On TRAP, restart at exception address.
1476         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1477         (signal_exception): Update.
1478         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1479         so that TRAP instructions are caught.
1480
1481 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1482
1483         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1484         contains HI/LO access history.
1485         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1486         (HIACCESS, LOACCESS): Delete, replace with
1487         (HIHISTORY, LOHISTORY): New macros.
1488         (CHECKHILO): Delete all, moved to mips.igen
1489
1490         * gencode.c (build_instruction): Do not generate checks for
1491         correct HI/LO register usage.
1492
1493         * interp.c (old_engine_run): Delete checks for correct HI/LO
1494         register usage.
1495
1496         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1497         check_mf_cycles): New functions.
1498         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1499         do_divu, domultx, do_mult, do_multu): Use.
1500
1501         * tx.igen ("madd", "maddu"): Use.
1502
1503 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1504
1505         * mips.igen (DSRAV): Use function do_dsrav.
1506         (SRAV): Use new function do_srav.
1507
1508         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1509         (B): Sign extend 11 bit immediate.
1510         (EXT-B*): Shift 16 bit immediate left by 1.
1511         (ADDIU*): Don't sign extend immediate value.
1512
1513 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1514
1515         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1516
1517         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1518         functions.
1519
1520         * mips.igen (delayslot32, nullify_next_insn): New functions.
1521         (m16.igen): Always include.
1522         (do_*): Add more tracing.
1523
1524         * m16.igen (delayslot16): Add NIA argument, could be called by a
1525         32 bit MIPS16 instruction.
1526
1527         * interp.c (ifetch16): Move function from here.
1528         * sim-main.c (ifetch16): To here.
1529
1530         * sim-main.c (ifetch16, ifetch32): Update to match current
1531         implementations of LH, LW.
1532         (signal_exception): Don't print out incorrect hex value of illegal
1533         instruction.
1534
1535 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1536
1537         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1538         instruction.
1539
1540         * m16.igen: Implement MIPS16 instructions.
1541
1542         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1543         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1544         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1545         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1546         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1547         bodies of corresponding code from 32 bit insn to these.  Also used
1548         by MIPS16 versions of functions.
1549
1550         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1551         (IMEM16): Drop NR argument from macro.
1552
1553 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1554
1555         * Makefile.in (SIM_OBJS): Add sim-main.o.
1556
1557         * sim-main.h (address_translation, load_memory, store_memory,
1558         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1559         as INLINE_SIM_MAIN.
1560         (pr_addr, pr_uword64): Declare.
1561         (sim-main.c): Include when H_REVEALS_MODULE_P.
1562
1563         * interp.c (address_translation, load_memory, store_memory,
1564         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1565         from here.
1566         * sim-main.c: To here. Fix compilation problems.
1567
1568         * configure.in: Enable inlining.
1569         * configure: Re-config.
1570
1571 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1572
1573         * configure: Regenerated to track ../common/aclocal.m4 changes.
1574
1575 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1576
1577         * mips.igen: Include tx.igen.
1578         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1579         * tx.igen: New file, contains MADD and MADDU.
1580
1581         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1582         the hardwired constant `7'.
1583         (store_memory): Ditto.
1584         (LOADDRMASK): Move definition to sim-main.h.
1585
1586         mips.igen (MTC0): Enable for r3900.
1587         (ADDU): Add trace.
1588
1589         mips.igen (do_load_byte): Delete.
1590         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1591         do_store_right): New functions.
1592         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1593
1594         configure.in: Let the tx39 use igen again.
1595         configure: Update.
1596
1597 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1598
1599         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1600         not an address sized quantity.  Return zero for cache sizes.
1601
1602 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1603
1604         * mips.igen (r3900): r3900 does not support 64 bit integer
1605         operations.
1606
1607 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1608
1609         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1610         than igen one.
1611         * configure : Rebuild.
1612
1613 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1614
1615         * configure: Regenerated to track ../common/aclocal.m4 changes.
1616
1617 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1618
1619         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1620
1621 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1622
1623         * configure: Regenerated to track ../common/aclocal.m4 changes.
1624         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1625
1626 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1627
1628         * configure: Regenerated to track ../common/aclocal.m4 changes.
1629
1630 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1631
1632         * interp.c (Max, Min): Comment out functions. Not yet used.
1633
1634 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1635
1636         * configure: Regenerated to track ../common/aclocal.m4 changes.
1637
1638 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1639
1640         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1641         configurable settings for stand-alone simulator.
1642
1643         * configure.in: Added X11 search, just in case.
1644
1645         * configure: Regenerated.
1646
1647 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1648
1649         * interp.c (sim_write, sim_read, load_memory, store_memory):
1650         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1651
1652 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1653
1654         * sim-main.h (GETFCC): Return an unsigned value.
1655
1656 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1657
1658         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1659         (DADD): Result destination is RD not RT.
1660
1661 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1662
1663         * sim-main.h (HIACCESS, LOACCESS): Always define.
1664
1665         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1666
1667         * interp.c (sim_info): Delete.
1668
1669 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1670
1671         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1672         (mips_option_handler): New argument `cpu'.
1673         (sim_open): Update call to sim_add_option_table.
1674
1675 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1676
1677         * mips.igen (CxC1): Add tracing.
1678
1679 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1680
1681         * sim-main.h (Max, Min): Declare.
1682
1683         * interp.c (Max, Min): New functions.
1684
1685         * mips.igen (BC1): Add tracing.
1686
1687 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1688
1689         * interp.c Added memory map for stack in vr4100
1690
1691 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1692
1693         * interp.c (load_memory): Add missing "break"'s.
1694
1695 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1696
1697         * interp.c (sim_store_register, sim_fetch_register): Pass in
1698         length parameter.  Return -1.
1699
1700 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1701
1702         * interp.c: Added hardware init hook, fixed warnings.
1703
1704 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1705
1706         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1707
1708 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1709
1710         * interp.c (ifetch16): New function.
1711
1712         * sim-main.h (IMEM32): Rename IMEM.
1713         (IMEM16_IMMED): Define.
1714         (IMEM16): Define.
1715         (DELAY_SLOT): Update.
1716
1717         * m16run.c (sim_engine_run): New file.
1718
1719         * m16.igen: All instructions except LB.
1720         (LB): Call do_load_byte.
1721         * mips.igen (do_load_byte): New function.
1722         (LB): Call do_load_byte.
1723
1724         * mips.igen: Move spec for insn bit size and high bit from here.
1725         * Makefile.in (tmp-igen, tmp-m16): To here.
1726
1727         * m16.dc: New file, decode mips16 instructions.
1728
1729         * Makefile.in (SIM_NO_ALL): Define.
1730         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1731
1732 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1733
1734         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1735         point unit to 32 bit registers.
1736         * configure: Re-generate.
1737
1738 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1739
1740         * configure.in (sim_use_gen): Make IGEN the default simulator
1741         generator for generic 32 and 64 bit mips targets.
1742         * configure: Re-generate.
1743
1744 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1745
1746         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1747         bitsize.
1748
1749         * interp.c (sim_fetch_register, sim_store_register): Read/write
1750         FGR from correct location.
1751         (sim_open): Set size of FGR's according to
1752         WITH_TARGET_FLOATING_POINT_BITSIZE.
1753
1754         * sim-main.h (FGR): Store floating point registers in a separate
1755         array.
1756
1757 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1758
1759         * configure: Regenerated to track ../common/aclocal.m4 changes.
1760
1761 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1762
1763         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1764
1765         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1766
1767         * interp.c (pending_tick): New function.  Deliver pending writes.
1768
1769         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1770         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1771         it can handle mixed sized quantites and single bits.
1772
1773 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1774
1775         * interp.c (oengine.h): Do not include when building with IGEN.
1776         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1777         (sim_info): Ditto for PROCESSOR_64BIT.
1778         (sim_monitor): Replace ut_reg with unsigned_word.
1779         (*): Ditto for t_reg.
1780         (LOADDRMASK): Define.
1781         (sim_open): Remove defunct check that host FP is IEEE compliant,
1782         using software to emulate floating point.
1783         (value_fpr, ...): Always compile, was conditional on HASFPU.
1784
1785 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1786
1787         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1788         size.
1789
1790         * interp.c (SD, CPU): Define.
1791         (mips_option_handler): Set flags in each CPU.
1792         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1793         (sim_close): Do not clear STATE, deleted anyway.
1794         (sim_write, sim_read): Assume CPU zero's vm should be used for
1795         data transfers.
1796         (sim_create_inferior): Set the PC for all processors.
1797         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1798         argument.
1799         (mips16_entry): Pass correct nr of args to store_word, load_word.
1800         (ColdReset): Cold reset all cpu's.
1801         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1802         (sim_monitor, load_memory, store_memory, signal_exception): Use
1803         `CPU' instead of STATE_CPU.
1804
1805
1806         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1807         SD or CPU_.
1808
1809         * sim-main.h (signal_exception): Add sim_cpu arg.
1810         (SignalException*): Pass both SD and CPU to signal_exception.
1811         * interp.c (signal_exception): Update.
1812
1813         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1814         Ditto
1815         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1816         address_translation): Ditto
1817         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1818
1819 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1820
1821         * configure: Regenerated to track ../common/aclocal.m4 changes.
1822
1823 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1824
1825         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1826
1827         * mips.igen (model): Map processor names onto BFD name.
1828
1829         * sim-main.h (CPU_CIA): Delete.
1830         (SET_CIA, GET_CIA): Define
1831
1832 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1833
1834         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1835         regiser.
1836
1837         * configure.in (default_endian): Configure a big-endian simulator
1838         by default.
1839         * configure: Re-generate.
1840
1841 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1842
1843         * configure: Regenerated to track ../common/aclocal.m4 changes.
1844
1845 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1846
1847         * interp.c (sim_monitor): Handle Densan monitor outbyte
1848         and inbyte functions.
1849
1850 1997-12-29  Felix Lee  <flee@cygnus.com>
1851
1852         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1853
1854 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1855
1856         * Makefile.in (tmp-igen): Arrange for $zero to always be
1857         reset to zero after every instruction.
1858
1859 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1860
1861         * configure: Regenerated to track ../common/aclocal.m4 changes.
1862         * config.in: Ditto.
1863
1864 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1865
1866         * mips.igen (MSUB): Fix to work like MADD.
1867         * gencode.c (MSUB): Similarly.
1868
1869 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1870
1871         * configure: Regenerated to track ../common/aclocal.m4 changes.
1872
1873 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1874
1875         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1876
1877 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1878
1879         * sim-main.h (sim-fpu.h): Include.
1880
1881         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1882         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1883         using host independant sim_fpu module.
1884
1885 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1886
1887         * interp.c (signal_exception): Report internal errors with SIGABRT
1888         not SIGQUIT.
1889
1890         * sim-main.h (C0_CONFIG): New register.
1891         (signal.h): No longer include.
1892
1893         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1894
1895 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1896
1897         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1898
1899 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1900
1901         * mips.igen: Tag vr5000 instructions.
1902         (ANDI): Was missing mipsIV model, fix assembler syntax.
1903         (do_c_cond_fmt): New function.
1904         (C.cond.fmt): Handle mips I-III which do not support CC field
1905         separatly.
1906         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1907         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1908         in IV3.2 spec.
1909         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1910         vr5000 which saves LO in a GPR separatly.
1911
1912         * configure.in (enable-sim-igen): For vr5000, select vr5000
1913         specific instructions.
1914         * configure: Re-generate.
1915
1916 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1917
1918         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1919
1920         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1921         fmt_uninterpreted_64 bit cases to switch.  Convert to
1922         fmt_formatted,
1923
1924         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1925
1926         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1927         as specified in IV3.2 spec.
1928         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1929
1930 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1931
1932         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1933         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1934         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1935         PENDING_FILL versions of instructions.  Simplify.
1936         (X): New function.
1937         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1938         instructions.
1939         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1940         a signed value.
1941         (MTHI, MFHI): Disable code checking HI-LO.
1942
1943         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1944         global.
1945         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1946
1947 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1948
1949         * gencode.c (build_mips16_operands): Replace IPC with cia.
1950
1951         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1952         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1953         IPC to `cia'.
1954         (UndefinedResult): Replace function with macro/function
1955         combination.
1956         (sim_engine_run): Don't save PC in IPC.
1957
1958         * sim-main.h (IPC): Delete.
1959
1960
1961         * interp.c (signal_exception, store_word, load_word,
1962         address_translation, load_memory, store_memory, cache_op,
1963         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1964         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1965         current instruction address - cia - argument.
1966         (sim_read, sim_write): Call address_translation directly.
1967         (sim_engine_run): Rename variable vaddr to cia.
1968         (signal_exception): Pass cia to sim_monitor
1969
1970         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1971         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1972         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1973
1974         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1975         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1976         SIM_ASSERT.
1977
1978         * interp.c (signal_exception): Pass restart address to
1979         sim_engine_restart.
1980
1981         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1982         idecode.o): Add dependency.
1983
1984         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1985         Delete definitions
1986         (DELAY_SLOT): Update NIA not PC with branch address.
1987         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1988
1989         * mips.igen: Use CIA not PC in branch calculations.
1990         (illegal): Call SignalException.
1991         (BEQ, ADDIU): Fix assembler.
1992
1993 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1994
1995         * m16.igen (JALX): Was missing.
1996
1997         * configure.in (enable-sim-igen): New configuration option.
1998         * configure: Re-generate.
1999
2000         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2001
2002         * interp.c (load_memory, store_memory): Delete parameter RAW.
2003         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2004         bypassing {load,store}_memory.
2005
2006         * sim-main.h (ByteSwapMem): Delete definition.
2007
2008         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2009
2010         * interp.c (sim_do_command, sim_commands): Delete mips specific
2011         commands.  Handled by module sim-options.
2012
2013         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2014         (WITH_MODULO_MEMORY): Define.
2015
2016         * interp.c (sim_info): Delete code printing memory size.
2017
2018         * interp.c (mips_size): Nee sim_size, delete function.
2019         (power2): Delete.
2020         (monitor, monitor_base, monitor_size): Delete global variables.
2021         (sim_open, sim_close): Delete code creating monitor and other
2022         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2023         manage memory regions.
2024         (load_memory, store_memory): Use sim-core for memory model.
2025
2026         * interp.c (address_translation): Delete all memory map code
2027         except line forcing 32 bit addresses.
2028
2029 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2030
2031         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2032         trace options.
2033
2034         * interp.c (logfh, logfile): Delete globals.
2035         (sim_open, sim_close): Delete code opening & closing log file.
2036         (mips_option_handler): Delete -l and -n options.
2037         (OPTION mips_options): Ditto.
2038
2039         * interp.c (OPTION mips_options): Rename option trace to dinero.
2040         (mips_option_handler): Update.
2041
2042 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2043
2044         * interp.c (fetch_str): New function.
2045         (sim_monitor): Rewrite using sim_read & sim_write.
2046         (sim_open): Check magic number.
2047         (sim_open): Write monitor vectors into memory using sim_write.
2048         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2049         (sim_read, sim_write): Simplify - transfer data one byte at a
2050         time.
2051         (load_memory, store_memory): Clarify meaning of parameter RAW.
2052
2053         * sim-main.h (isHOST): Defete definition.
2054         (isTARGET): Mark as depreciated.
2055         (address_translation): Delete parameter HOST.
2056
2057         * interp.c (address_translation): Delete parameter HOST.
2058
2059 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2060
2061         * mips.igen:
2062
2063         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2064         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2065
2066 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2067
2068         * mips.igen: Add model filter field to records.
2069
2070 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2071
2072         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2073
2074         interp.c (sim_engine_run): Do not compile function sim_engine_run
2075         when WITH_IGEN == 1.
2076
2077         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2078         target architecture.
2079
2080         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2081         igen. Replace with configuration variables sim_igen_flags /
2082         sim_m16_flags.
2083
2084         * m16.igen: New file.  Copy mips16 insns here.
2085         * mips.igen: From here.
2086
2087 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2088
2089         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2090         to top.
2091         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2092
2093 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2094
2095         * gencode.c (build_instruction): Follow sim_write's lead in using
2096         BigEndianMem instead of !ByteSwapMem.
2097
2098 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2099
2100         * configure.in (sim_gen): Dependent on target, select type of
2101         generator.  Always select old style generator.
2102
2103         configure: Re-generate.
2104
2105         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2106         targets.
2107         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2108         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2109         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2110         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2111         SIM_@sim_gen@_*, set by autoconf.
2112
2113 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2114
2115         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2116
2117         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2118         CURRENT_FLOATING_POINT instead.
2119
2120         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2121         (address_translation): Raise exception InstructionFetch when
2122         translation fails and isINSTRUCTION.
2123
2124         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2125         sim_engine_run): Change type of of vaddr and paddr to
2126         address_word.
2127         (address_translation, prefetch, load_memory, store_memory,
2128         cache_op): Change type of vAddr and pAddr to address_word.
2129
2130         * gencode.c (build_instruction): Change type of vaddr and paddr to
2131         address_word.
2132
2133 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2134
2135         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2136         macro to obtain result of ALU op.
2137
2138 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2139
2140         * interp.c (sim_info): Call profile_print.
2141
2142 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2143
2144         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2145
2146         * sim-main.h (WITH_PROFILE): Do not define, defined in
2147         common/sim-config.h.  Use sim-profile module.
2148         (simPROFILE): Delete defintion.
2149
2150         * interp.c (PROFILE): Delete definition.
2151         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2152         (sim_close): Delete code writing profile histogram.
2153         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2154         Delete.
2155         (sim_engine_run): Delete code profiling the PC.
2156
2157 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2158
2159         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2160
2161         * interp.c (sim_monitor): Make register pointers of type
2162         unsigned_word*.
2163
2164         * sim-main.h: Make registers of type unsigned_word not
2165         signed_word.
2166
2167 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2168
2169         * interp.c (sync_operation): Rename from SyncOperation, make
2170         global, add SD argument.
2171         (prefetch): Rename from Prefetch, make global, add SD argument.
2172         (decode_coproc): Make global.
2173
2174         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2175
2176         * gencode.c (build_instruction): Generate DecodeCoproc not
2177         decode_coproc calls.
2178
2179         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2180         (SizeFGR): Move to sim-main.h
2181         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2182         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2183         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2184         sim-main.h.
2185         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2186         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2187         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2188         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2189         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2190         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2191
2192         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2193         exception.
2194         (sim-alu.h): Include.
2195         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2196         (sim_cia): Typedef to instruction_address.
2197
2198 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2199
2200         * Makefile.in (interp.o): Rename generated file engine.c to
2201         oengine.c.
2202
2203         * interp.c: Update.
2204
2205 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2206
2207         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2208
2209 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2210
2211         * gencode.c (build_instruction): For "FPSQRT", output correct
2212         number of arguments to Recip.
2213
2214 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2215
2216         * Makefile.in (interp.o): Depends on sim-main.h
2217
2218         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2219
2220         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2221         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2222         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2223         STATE, DSSTATE): Define
2224         (GPR, FGRIDX, ..): Define.
2225
2226         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2227         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2228         (GPR, FGRIDX, ...): Delete macros.
2229
2230         * interp.c: Update names to match defines from sim-main.h
2231
2232 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2233
2234         * interp.c (sim_monitor): Add SD argument.
2235         (sim_warning): Delete.  Replace calls with calls to
2236         sim_io_eprintf.
2237         (sim_error): Delete. Replace calls with sim_io_error.
2238         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2239         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2240         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2241         argument.
2242         (mips_size): Rename from sim_size. Add SD argument.
2243
2244         * interp.c (simulator): Delete global variable.
2245         (callback): Delete global variable.
2246         (mips_option_handler, sim_open, sim_write, sim_read,
2247         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2248         sim_size,sim_monitor): Use sim_io_* not callback->*.
2249         (sim_open): ZALLOC simulator struct.
2250         (PROFILE): Do not define.
2251
2252 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2253
2254         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2255         support.h with corresponding code.
2256
2257         * sim-main.h (word64, uword64), support.h: Move definition to
2258         sim-main.h.
2259         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2260
2261         * support.h: Delete
2262         * Makefile.in: Update dependencies
2263         * interp.c: Do not include.
2264
2265 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2266
2267         * interp.c (address_translation, load_memory, store_memory,
2268         cache_op): Rename to from AddressTranslation et.al., make global,
2269         add SD argument
2270
2271         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2272         CacheOp): Define.
2273
2274         * interp.c (SignalException): Rename to signal_exception, make
2275         global.
2276
2277         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2278
2279         * sim-main.h (SignalException, SignalExceptionInterrupt,
2280         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2281         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2282         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2283         Define.
2284
2285         * interp.c, support.h: Use.
2286
2287 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2288
2289         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2290         to value_fpr / store_fpr. Add SD argument.
2291         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2292         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2293
2294         * sim-main.h (ValueFPR, StoreFPR): Define.
2295
2296 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2297
2298         * interp.c (sim_engine_run): Check consistency between configure
2299         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2300         and HASFPU.
2301
2302         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2303         (mips_fpu): Configure WITH_FLOATING_POINT.
2304         (mips_endian): Configure WITH_TARGET_ENDIAN.
2305         * configure: Update.
2306
2307 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2308
2309         * configure: Regenerated to track ../common/aclocal.m4 changes.
2310
2311 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2312
2313         * configure: Regenerated.
2314
2315 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2316
2317         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2318
2319 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2320
2321         * gencode.c (print_igen_insn_models): Assume certain architectures
2322         include all mips* instructions.
2323         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2324         instruction.
2325
2326         * Makefile.in (tmp.igen): Add target. Generate igen input from
2327         gencode file.
2328
2329         * gencode.c (FEATURE_IGEN): Define.
2330         (main): Add --igen option.  Generate output in igen format.
2331         (process_instructions): Format output according to igen option.
2332         (print_igen_insn_format): New function.
2333         (print_igen_insn_models): New function.
2334         (process_instructions): Only issue warnings and ignore
2335         instructions when no FEATURE_IGEN.
2336
2337 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2338
2339         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2340         MIPS targets.
2341
2342 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2343
2344         * configure: Regenerated to track ../common/aclocal.m4 changes.
2345
2346 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2347
2348         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2349         SIM_RESERVED_BITS): Delete, moved to common.
2350         (SIM_EXTRA_CFLAGS): Update.
2351
2352 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2353
2354         * configure.in: Configure non-strict memory alignment.
2355         * configure: Regenerated to track ../common/aclocal.m4 changes.
2356
2357 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2358
2359         * configure: Regenerated to track ../common/aclocal.m4 changes.
2360
2361 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2362
2363         * gencode.c (SDBBP,DERET): Added (3900) insns.
2364         (RFE): Turn on for 3900.
2365         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2366         (dsstate): Made global.
2367         (SUBTARGET_R3900): Added.
2368         (CANCELDELAYSLOT): New.
2369         (SignalException): Ignore SystemCall rather than ignore and
2370         terminate.  Add DebugBreakPoint handling.
2371         (decode_coproc): New insns RFE, DERET; and new registers Debug
2372         and DEPC protected by SUBTARGET_R3900.
2373         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2374         bits explicitly.
2375         * Makefile.in,configure.in: Add mips subtarget option.
2376         * configure: Update.
2377
2378 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2379
2380         * gencode.c: Add r3900 (tx39).
2381
2382
2383 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2384
2385         * gencode.c (build_instruction): Don't need to subtract 4 for
2386         JALR, just 2.
2387
2388 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2389
2390         * interp.c: Correct some HASFPU problems.
2391
2392 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2393
2394         * configure: Regenerated to track ../common/aclocal.m4 changes.
2395
2396 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2397
2398         * interp.c (mips_options): Fix samples option short form, should
2399         be `x'.
2400
2401 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2402
2403         * interp.c (sim_info): Enable info code.  Was just returning.
2404
2405 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2406
2407         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2408         MFC0.
2409
2410 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2411
2412         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2413         constants.
2414         (build_instruction): Ditto for LL.
2415
2416 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2417
2418         * configure: Regenerated to track ../common/aclocal.m4 changes.
2419
2420 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2421
2422         * configure: Regenerated to track ../common/aclocal.m4 changes.
2423         * config.in: Ditto.
2424
2425 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2426
2427         * interp.c (sim_open): Add call to sim_analyze_program, update
2428         call to sim_config.
2429
2430 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2431
2432         * interp.c (sim_kill): Delete.
2433         (sim_create_inferior): Add ABFD argument. Set PC from same.
2434         (sim_load): Move code initializing trap handlers from here.
2435         (sim_open): To here.
2436         (sim_load): Delete, use sim-hload.c.
2437
2438         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2439
2440 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2441
2442         * configure: Regenerated to track ../common/aclocal.m4 changes.
2443         * config.in: Ditto.
2444
2445 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2446
2447         * interp.c (sim_open): Add ABFD argument.
2448         (sim_load): Move call to sim_config from here.
2449         (sim_open): To here.  Check return status.
2450
2451 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2452
2453         * gencode.c (build_instruction): Two arg MADD should
2454         not assign result to $0.
2455
2456 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2457
2458         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2459         * sim/mips/configure.in: Regenerate.
2460
2461 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2462
2463         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2464         signed8, unsigned8 et.al. types.
2465
2466         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2467         hosts when selecting subreg.
2468
2469 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2470
2471         * interp.c (sim_engine_run): Reset the ZERO register to zero
2472         regardless of FEATURE_WARN_ZERO.
2473         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2474
2475 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2476
2477         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2478         (SignalException): For BreakPoints ignore any mode bits and just
2479         save the PC.
2480         (SignalException): Always set the CAUSE register.
2481
2482 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2483
2484         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2485         exception has been taken.
2486
2487         * interp.c: Implement the ERET and mt/f sr instructions.
2488
2489 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2490
2491         * interp.c (SignalException): Don't bother restarting an
2492         interrupt.
2493
2494 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2495
2496         * interp.c (SignalException): Really take an interrupt.
2497         (interrupt_event): Only deliver interrupts when enabled.
2498
2499 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2500
2501         * interp.c (sim_info): Only print info when verbose.
2502         (sim_info) Use sim_io_printf for output.
2503
2504 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2505
2506         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2507         mips architectures.
2508
2509 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2510
2511         * interp.c (sim_do_command): Check for common commands if a
2512         simulator specific command fails.
2513
2514 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2515
2516         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2517         and simBE when DEBUG is defined.
2518
2519 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2520
2521         * interp.c (interrupt_event): New function.  Pass exception event
2522         onto exception handler.
2523
2524         * configure.in: Check for stdlib.h.
2525         * configure: Regenerate.
2526
2527         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2528         variable declaration.
2529         (build_instruction): Initialize memval1.
2530         (build_instruction): Add UNUSED attribute to byte, bigend,
2531         reverse.
2532         (build_operands): Ditto.
2533
2534         * interp.c: Fix GCC warnings.
2535         (sim_get_quit_code): Delete.
2536
2537         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2538         * Makefile.in: Ditto.
2539         * configure: Re-generate.
2540
2541         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2542
2543 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2544
2545         * interp.c (mips_option_handler): New function parse argumes using
2546         sim-options.
2547         (myname): Replace with STATE_MY_NAME.
2548         (sim_open): Delete check for host endianness - performed by
2549         sim_config.
2550         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2551         (sim_open): Move much of the initialization from here.
2552         (sim_load): To here.  After the image has been loaded and
2553         endianness set.
2554         (sim_open): Move ColdReset from here.
2555         (sim_create_inferior): To here.
2556         (sim_open): Make FP check less dependant on host endianness.
2557
2558         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2559         run.
2560         * interp.c (sim_set_callbacks): Delete.
2561
2562         * interp.c (membank, membank_base, membank_size): Replace with
2563         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2564         (sim_open): Remove call to callback->init. gdb/run do this.
2565
2566         * interp.c: Update
2567
2568         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2569
2570         * interp.c (big_endian_p): Delete, replaced by
2571         current_target_byte_order.
2572
2573 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2574
2575         * interp.c (host_read_long, host_read_word, host_swap_word,
2576         host_swap_long): Delete. Using common sim-endian.
2577         (sim_fetch_register, sim_store_register): Use H2T.
2578         (pipeline_ticks): Delete.  Handled by sim-events.
2579         (sim_info): Update.
2580         (sim_engine_run): Update.
2581
2582 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2583
2584         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2585         reason from here.
2586         (SignalException): To here. Signal using sim_engine_halt.
2587         (sim_stop_reason): Delete, moved to common.
2588
2589 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2590
2591         * interp.c (sim_open): Add callback argument.
2592         (sim_set_callbacks): Delete SIM_DESC argument.
2593         (sim_size): Ditto.
2594
2595 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2596
2597         * Makefile.in (SIM_OBJS): Add common modules.
2598
2599         * interp.c (sim_set_callbacks): Also set SD callback.
2600         (set_endianness, xfer_*, swap_*): Delete.
2601         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2602         Change to functions using sim-endian macros.
2603         (control_c, sim_stop): Delete, use common version.
2604         (simulate): Convert into.
2605         (sim_engine_run): This function.
2606         (sim_resume): Delete.
2607
2608         * interp.c (simulation): New variable - the simulator object.
2609         (sim_kind): Delete global - merged into simulation.
2610         (sim_load): Cleanup.  Move PC assignment from here.
2611         (sim_create_inferior): To here.
2612
2613         * sim-main.h: New file.
2614         * interp.c (sim-main.h): Include.
2615
2616 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2617
2618         * configure: Regenerated to track ../common/aclocal.m4 changes.
2619
2620 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2621
2622         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2623
2624 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2625
2626         * gencode.c (build_instruction): DIV instructions: check
2627         for division by zero and integer overflow before using
2628         host's division operation.
2629
2630 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2631
2632         * Makefile.in (SIM_OBJS): Add sim-load.o.
2633         * interp.c: #include bfd.h.
2634         (target_byte_order): Delete.
2635         (sim_kind, myname, big_endian_p): New static locals.
2636         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2637         after argument parsing.  Recognize -E arg, set endianness accordingly.
2638         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2639         load file into simulator.  Set PC from bfd.
2640         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2641         (set_endianness): Use big_endian_p instead of target_byte_order.
2642
2643 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2644
2645         * interp.c (sim_size): Delete prototype - conflicts with
2646         definition in remote-sim.h.  Correct definition.
2647
2648 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2649
2650         * configure: Regenerated to track ../common/aclocal.m4 changes.
2651         * config.in: Ditto.
2652
2653 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2654
2655         * interp.c (sim_open): New arg `kind'.
2656
2657         * configure: Regenerated to track ../common/aclocal.m4 changes.
2658
2659 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2660
2661         * configure: Regenerated to track ../common/aclocal.m4 changes.
2662
2663 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2664
2665         * interp.c (sim_open): Set optind to 0 before calling getopt.
2666
2667 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2668
2669         * configure: Regenerated to track ../common/aclocal.m4 changes.
2670
2671 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2672
2673         * interp.c : Replace uses of pr_addr with pr_uword64
2674         where the bit length is always 64 independent of SIM_ADDR.
2675         (pr_uword64) : added.
2676
2677 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2678
2679         * configure: Re-generate.
2680
2681 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2682
2683         * configure: Regenerate to track ../common/aclocal.m4 changes.
2684
2685 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2686
2687         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2688         in argv form.
2689         (other sim_*): New SIM_DESC argument.
2690
2691 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2692
2693         * interp.c: Fix printing of addresses for non-64-bit targets.
2694         (pr_addr): Add function to print address based on size.
2695
2696 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2697
2698         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2699
2700 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2701
2702         * gencode.c (build_mips16_operands): Correct computation of base
2703         address for extended PC relative instruction.
2704
2705 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2706
2707         * interp.c (mips16_entry): Add support for floating point cases.
2708         (SignalException): Pass floating point cases to mips16_entry.
2709         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2710         registers.
2711         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2712         or fmt_word.
2713         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2714         and then set the state to fmt_uninterpreted.
2715         (COP_SW): Temporarily set the state to fmt_word while calling
2716         ValueFPR.
2717
2718 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2719
2720         * gencode.c (build_instruction): The high order may be set in the
2721         comparison flags at any ISA level, not just ISA 4.
2722
2723 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2724
2725         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2726         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2727         * configure.in: sinclude ../common/aclocal.m4.
2728         * configure: Regenerated.
2729
2730 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2731
2732         * configure: Rebuild after change to aclocal.m4.
2733
2734 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2735
2736         * configure configure.in Makefile.in:  Update to new configure
2737         scheme which is more compatible with WinGDB builds.
2738         * configure.in:  Improve comment on how to run autoconf.
2739         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2740         * Makefile.in:  Use autoconf substitution to install common
2741         makefile fragment.
2742
2743 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2744
2745         * gencode.c (build_instruction): Use BigEndianCPU instead of
2746         ByteSwapMem.
2747
2748 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2749
2750         * interp.c (sim_monitor): Make output to stdout visible in
2751         wingdb's I/O log window.
2752
2753 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2754
2755         * support.h: Undo previous change to SIGTRAP
2756         and SIGQUIT values.
2757
2758 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2759
2760         * interp.c (store_word, load_word): New static functions.
2761         (mips16_entry): New static function.
2762         (SignalException): Look for mips16 entry and exit instructions.
2763         (simulate): Use the correct index when setting fpr_state after
2764         doing a pending move.
2765
2766 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2767
2768         * interp.c: Fix byte-swapping code throughout to work on
2769         both little- and big-endian hosts.
2770
2771 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2772
2773         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2774         with gdb/config/i386/xm-windows.h.
2775
2776 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2777
2778         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2779         that messes up arithmetic shifts.
2780
2781 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2782
2783         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2784         SIGTRAP and SIGQUIT for _WIN32.
2785
2786 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2787
2788         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2789         force a 64 bit multiplication.
2790         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2791         destination register is 0, since that is the default mips16 nop
2792         instruction.
2793
2794 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2795
2796         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2797         (build_endian_shift): Don't check proc64.
2798         (build_instruction): Always set memval to uword64.  Cast op2 to
2799         uword64 when shifting it left in memory instructions.  Always use
2800         the same code for stores--don't special case proc64.
2801
2802         * gencode.c (build_mips16_operands): Fix base PC value for PC
2803         relative operands.
2804         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2805         jal instruction.
2806         * interp.c (simJALDELAYSLOT): Define.
2807         (JALDELAYSLOT): Define.
2808         (INDELAYSLOT, INJALDELAYSLOT): Define.
2809         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2810
2811 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2812
2813         * interp.c (sim_open): add flush_cache as a PMON routine
2814         (sim_monitor): handle flush_cache by ignoring it
2815
2816 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2817
2818         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2819         BigEndianMem.
2820         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2821         (BigEndianMem): Rename to ByteSwapMem and change sense.
2822         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2823         BigEndianMem references to !ByteSwapMem.
2824         (set_endianness): New function, with prototype.
2825         (sim_open): Call set_endianness.
2826         (sim_info): Use simBE instead of BigEndianMem.
2827         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2828         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2829         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2830         ifdefs, keeping the prototype declaration.
2831         (swap_word): Rewrite correctly.
2832         (ColdReset): Delete references to CONFIG.  Delete endianness related
2833         code; moved to set_endianness.
2834
2835 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2836
2837         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2838         * interp.c (CHECKHILO): Define away.
2839         (simSIGINT): New macro.
2840         (membank_size): Increase from 1MB to 2MB.
2841         (control_c): New function.
2842         (sim_resume): Rename parameter signal to signal_number.  Add local
2843         variable prev.  Call signal before and after simulate.
2844         (sim_stop_reason): Add simSIGINT support.
2845         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2846         functions always.
2847         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2848         if logfh is NULL.
2849         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2850         a call to sim_warning.
2851
2852 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2853
2854         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2855         16 bit instructions.
2856
2857 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2858
2859         Add support for mips16 (16 bit MIPS implementation):
2860         * gencode.c (inst_type): Add mips16 instruction encoding types.
2861         (GETDATASIZEINSN): Define.
2862         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2863         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2864         mtlo.
2865         (MIPS16_DECODE): New table, for mips16 instructions.
2866         (bitmap_val): New static function.
2867         (struct mips16_op): Define.
2868         (mips16_op_table): New table, for mips16 operands.
2869         (build_mips16_operands): New static function.
2870         (process_instructions): If PC is odd, decode a mips16
2871         instruction.  Break out instruction handling into new
2872         build_instruction function.
2873         (build_instruction): New static function, broken out of
2874         process_instructions.  Check modifiers rather than flags for SHIFT
2875         bit count and m[ft]{hi,lo} direction.
2876         (usage): Pass program name to fprintf.
2877         (main): Remove unused variable this_option_optind.  Change
2878         ``*loptarg++'' to ``loptarg++''.
2879         (my_strtoul): Parenthesize && within ||.
2880         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2881         (simulate): If PC is odd, fetch a 16 bit instruction, and
2882         increment PC by 2 rather than 4.
2883         * configure.in: Add case for mips16*-*-*.
2884         * configure: Rebuild.
2885
2886 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2887
2888         * interp.c: Allow -t to enable tracing in standalone simulator.
2889         Fix garbage output in trace file and error messages.
2890
2891 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2892
2893         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2894         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2895         * configure.in: Simplify using macros in ../common/aclocal.m4.
2896         * configure: Regenerated.
2897         * tconfig.in: New file.
2898
2899 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2900
2901         * interp.c: Fix bugs in 64-bit port.
2902         Use ansi function declarations for msvc compiler.
2903         Initialize and test file pointer in trace code.
2904         Prevent duplicate definition of LAST_EMED_REGNUM.
2905
2906 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2907
2908         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2909
2910 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2911
2912         * interp.c (SignalException): Check for explicit terminating
2913         breakpoint value.
2914         * gencode.c: Pass instruction value through SignalException()
2915         calls for Trap, Breakpoint and Syscall.
2916
2917 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2918
2919         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2920         only used on those hosts that provide it.
2921         * configure.in: Add sqrt() to list of functions to be checked for.
2922         * config.in: Re-generated.
2923         * configure: Re-generated.
2924
2925 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2926
2927         * gencode.c (process_instructions): Call build_endian_shift when
2928         expanding STORE RIGHT, to fix swr.
2929         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2930         clear the high bits.
2931         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2932         Fix float to int conversions to produce signed values.
2933
2934 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2935
2936         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2937         (process_instructions): Correct handling of nor instruction.
2938         Correct shift count for 32 bit shift instructions. Correct sign
2939         extension for arithmetic shifts to not shift the number of bits in
2940         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2941         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2942         Fix madd.
2943         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2944         It's OK to have a mult follow a mult.  What's not OK is to have a
2945         mult follow an mfhi.
2946         (Convert): Comment out incorrect rounding code.
2947
2948 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2949
2950         * interp.c (sim_monitor): Improved monitor printf
2951         simulation. Tidied up simulator warnings, and added "--log" option
2952         for directing warning message output.
2953         * gencode.c: Use sim_warning() rather than WARNING macro.
2954
2955 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2956
2957         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2958         getopt1.o, rather than on gencode.c.  Link objects together.
2959         Don't link against -liberty.
2960         (gencode.o, getopt.o, getopt1.o): New targets.
2961         * gencode.c: Include <ctype.h> and "ansidecl.h".
2962         (AND): Undefine after including "ansidecl.h".
2963         (ULONG_MAX): Define if not defined.
2964         (OP_*): Don't define macros; now defined in opcode/mips.h.
2965         (main): Call my_strtoul rather than strtoul.
2966         (my_strtoul): New static function.
2967
2968 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2969
2970         * gencode.c (process_instructions):  Generate word64 and uword64
2971         instead of `long long' and `unsigned long long' data types.
2972         * interp.c:  #include sysdep.h to get signals, and define default
2973         for SIGBUS.
2974         * (Convert):  Work around for Visual-C++ compiler bug with type
2975         conversion.
2976         * support.h:  Make things compile under Visual-C++ by using
2977         __int64 instead of `long long'.  Change many refs to long long
2978         into word64/uword64 typedefs.
2979
2980 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2981
2982         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2983         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2984         (docdir): Removed.
2985         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2986         (AC_PROG_INSTALL): Added.
2987         (AC_PROG_CC): Moved to before configure.host call.
2988         * configure: Rebuilt.
2989
2990 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2991
2992         * configure.in: Define @SIMCONF@ depending on mips target.
2993         * configure: Rebuild.
2994         * Makefile.in (run): Add @SIMCONF@ to control simulator
2995         construction.
2996         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2997         * interp.c: Remove some debugging, provide more detailed error
2998         messages, update memory accesses to use LOADDRMASK.
2999
3000 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3001
3002         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3003         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3004         stamp-h.
3005         * configure: Rebuild.
3006         * config.in: New file, generated by autoheader.
3007         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3008         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3009         HAVE_ANINT and HAVE_AINT, as appropriate.
3010         * Makefile.in (run): Use @LIBS@ rather than -lm.
3011         (interp.o): Depend upon config.h.
3012         (Makefile): Just rebuild Makefile.
3013         (clean): Remove stamp-h.
3014         (mostlyclean): Make the same as clean, not as distclean.
3015         (config.h, stamp-h): New targets.
3016
3017 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3018
3019         * interp.c (ColdReset): Fix boolean test. Make all simulator
3020         globals static.
3021
3022 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3023
3024         * interp.c (xfer_direct_word, xfer_direct_long,
3025         swap_direct_word, swap_direct_long, xfer_big_word,
3026         xfer_big_long, xfer_little_word, xfer_little_long,
3027         swap_word,swap_long): Added.
3028         * interp.c (ColdReset): Provide function indirection to
3029         host<->simulated_target transfer routines.
3030         * interp.c (sim_store_register, sim_fetch_register): Updated to
3031         make use of indirected transfer routines.
3032
3033 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3034
3035         * gencode.c (process_instructions): Ensure FP ABS instruction
3036         recognised.
3037         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3038         system call support.
3039
3040 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3041
3042         * interp.c (sim_do_command): Complain if callback structure not
3043         initialised.
3044
3045 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3046
3047         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3048         support for Sun hosts.
3049         * Makefile.in (gencode): Ensure the host compiler and libraries
3050         used for cross-hosted build.
3051
3052 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3053
3054         * interp.c, gencode.c: Some more (TODO) tidying.
3055
3056 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3057
3058         * gencode.c, interp.c: Replaced explicit long long references with
3059         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3060         * support.h (SET64LO, SET64HI): Macros added.
3061
3062 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3063
3064         * configure: Regenerate with autoconf 2.7.
3065
3066 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3067
3068         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3069         * support.h: Remove superfluous "1" from #if.
3070         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3071
3072 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3073
3074         * interp.c (StoreFPR): Control UndefinedResult() call on
3075         WARN_RESULT manifest.
3076
3077 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3078
3079         * gencode.c: Tidied instruction decoding, and added FP instruction
3080         support.
3081
3082         * interp.c: Added dineroIII, and BSD profiling support. Also
3083         run-time FP handling.
3084
3085 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3086
3087         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3088         gencode.c, interp.c, support.h: created.