1 2002-03-02 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (loadstore_ea): New function to do effective
5 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
6 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
7 CACHE): Use loadstore_ea to do effective address computations.
9 2002-03-02 Chris Demetriou <cgd@broadcom.com>
11 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
12 * mips.igen (LL, CxC1, MxC1): Likewise.
14 2002-03-02 Chris Demetriou <cgd@broadcom.com>
16 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
17 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
18 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
19 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
20 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
21 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
22 Don't split opcode fields by hand, use the opcode field values
25 2002-03-01 Chris Demetriou <cgd@broadcom.com>
27 * mips.igen (do_divu): Fix spacing.
29 * mips.igen (do_dsllv): Move to be right before DSLLV,
30 to match the rest of the do_<shift> functions.
32 2002-03-01 Chris Demetriou <cgd@broadcom.com>
34 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
35 DSRL32, do_dsrlv): Trace inputs and results.
37 2002-03-01 Chris Demetriou <cgd@broadcom.com>
39 * mips.igen (CACHE): Provide instruction-printing string.
41 * interp.c (signal_exception): Comment tokens after #endif.
43 2002-02-28 Chris Demetriou <cgd@broadcom.com>
45 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
46 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
47 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
48 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
49 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
50 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
51 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
52 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
54 2002-02-28 Chris Demetriou <cgd@broadcom.com>
56 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
57 instruction-printing string.
58 (LWU): Use '64' as the filter flag.
60 2002-02-28 Chris Demetriou <cgd@broadcom.com>
62 * mips.igen (SDXC1): Fix instruction-printing string.
64 2002-02-28 Chris Demetriou <cgd@broadcom.com>
66 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
69 2002-02-27 Chris Demetriou <cgd@broadcom.com>
71 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
74 2002-02-27 Chris Demetriou <cgd@broadcom.com>
76 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
77 add a comma) so that it more closely match the MIPS ISA
78 documentation opcode partitioning.
79 (PREF): Put useful names on opcode fields, and include
80 instruction-printing string.
82 2002-02-27 Chris Demetriou <cgd@broadcom.com>
84 * mips.igen (check_u64): New function which in the future will
85 check whether 64-bit instructions are usable and signal an
86 exception if not. Currently a no-op.
87 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
88 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
89 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
90 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
92 * mips.igen (check_fpu): New function which in the future will
93 check whether FPU instructions are usable and signal an exception
94 if not. Currently a no-op.
95 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
96 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
97 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
98 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
99 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
100 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
101 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
102 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
104 2002-02-27 Chris Demetriou <cgd@broadcom.com>
106 * mips.igen (do_load_left, do_load_right): Move to be immediately
108 (do_store_left, do_store_right): Move to be immediately following
111 2002-02-27 Chris Demetriou <cgd@broadcom.com>
113 * mips.igen (mipsV): New model name. Also, add it to
114 all instructions and functions where it is appropriate.
116 2002-02-18 Chris Demetriou <cgd@broadcom.com>
118 * mips.igen: For all functions and instructions, list model
119 names that support that instruction one per line.
121 2002-02-11 Chris Demetriou <cgd@broadcom.com>
123 * mips.igen: Add some additional comments about supported
124 models, and about which instructions go where.
125 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
126 order as is used in the rest of the file.
128 2002-02-11 Chris Demetriou <cgd@broadcom.com>
130 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
131 indicating that ALU32_END or ALU64_END are there to check
133 (DADD): Likewise, but also remove previous comment about
136 2002-02-10 Chris Demetriou <cgd@broadcom.com>
138 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
139 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
140 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
141 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
142 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
143 fields (i.e., add and move commas) so that they more closely
144 match the MIPS ISA documentation opcode partitioning.
146 2002-02-10 Chris Demetriou <cgd@broadcom.com>
148 * mips.igen (ADDI): Print immediate value.
150 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
151 (SLL): Print "nop" specially, and don't run the code
152 that does the shift for the "nop" case.
154 2001-11-17 Fred Fish <fnf@redhat.com>
156 * sim-main.h (float_operation): Move enum declaration outside
157 of _sim_cpu struct declaration.
159 2001-04-12 Jim Blandy <jimb@redhat.com>
161 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
162 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
164 * sim-main.h (COCIDX): Remove definition; this isn't supported by
165 PENDING_FILL, and you can get the intended effect gracefully by
166 calling PENDING_SCHED directly.
168 2001-02-23 Ben Elliston <bje@redhat.com>
170 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
171 already defined elsewhere.
173 2001-02-19 Ben Elliston <bje@redhat.com>
175 * sim-main.h (sim_monitor): Return an int.
176 * interp.c (sim_monitor): Add return values.
177 (signal_exception): Handle error conditions from sim_monitor.
179 2001-02-08 Ben Elliston <bje@redhat.com>
181 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
182 (store_memory): Likewise, pass cia to sim_core_write*.
184 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
186 On advice from Chris G. Demetriou <cgd@sibyte.com>:
187 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
189 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
191 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
192 * Makefile.in: Don't delete *.igen when cleaning directory.
194 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
196 * m16.igen (break): Call SignalException not sim_engine_halt.
198 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
201 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
203 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
205 * mips.igen (MxC1, DMxC1): Fix printf formatting.
207 2000-05-24 Michael Hayes <mhayes@cygnus.com>
209 * mips.igen (do_dmultx): Fix typo.
211 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
213 * configure: Regenerated to track ../common/aclocal.m4 changes.
215 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
217 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
219 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
221 * sim-main.h (GPR_CLEAR): Define macro.
223 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
225 * interp.c (decode_coproc): Output long using %lx and not %s.
227 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
229 * interp.c (sim_open): Sort & extend dummy memory regions for
230 --board=jmr3904 for eCos.
232 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
234 * configure: Regenerated.
236 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
238 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
239 calls, conditional on the simulator being in verbose mode.
241 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
243 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
244 cache don't get ReservedInstruction traps.
246 1999-11-29 Mark Salter <msalter@cygnus.com>
248 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
249 to clear status bits in sdisr register. This is how the hardware works.
251 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
252 being used by cygmon.
254 1999-11-11 Andrew Haley <aph@cygnus.com>
256 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
259 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
261 * mips.igen (MULT): Correct previous mis-applied patch.
263 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
265 * mips.igen (delayslot32): Handle sequence like
266 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
267 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
268 (MULT): Actually pass the third register...
270 1999-09-03 Mark Salter <msalter@cygnus.com>
272 * interp.c (sim_open): Added more memory aliases for additional
273 hardware being touched by cygmon on jmr3904 board.
275 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
277 * configure: Regenerated to track ../common/aclocal.m4 changes.
279 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
281 * interp.c (sim_store_register): Handle case where client - GDB -
282 specifies that a 4 byte register is 8 bytes in size.
283 (sim_fetch_register): Ditto.
285 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
287 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
288 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
289 (idt_monitor_base): Base address for IDT monitor traps.
290 (pmon_monitor_base): Ditto for PMON.
291 (lsipmon_monitor_base): Ditto for LSI PMON.
292 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
293 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
294 (sim_firmware_command): New function.
295 (mips_option_handler): Call it for OPTION_FIRMWARE.
296 (sim_open): Allocate memory for idt_monitor region. If "--board"
297 option was given, add no monitor by default. Add BREAK hooks only if
298 monitors are also there.
300 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
302 * interp.c (sim_monitor): Flush output before reading input.
304 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
306 * tconfig.in (SIM_HANDLES_LMA): Always define.
308 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
310 From Mark Salter <msalter@cygnus.com>:
311 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
312 (sim_open): Add setup for BSP board.
314 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
316 * mips.igen (MULT, MULTU): Add syntax for two operand version.
317 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
318 them as unimplemented.
320 1999-05-08 Felix Lee <flee@cygnus.com>
322 * configure: Regenerated to track ../common/aclocal.m4 changes.
324 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
326 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
328 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
330 * configure.in: Any mips64vr5*-*-* target should have
331 -DTARGET_ENABLE_FR=1.
332 (default_endian): Any mips64vr*el-*-* target should default to
334 * configure: Re-generate.
336 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
338 * mips.igen (ldl): Extend from _16_, not 32.
340 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
342 * interp.c (sim_store_register): Force registers written to by GDB
343 into an un-interpreted state.
345 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
347 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
348 CPU, start periodic background I/O polls.
349 (tx3904sio_poll): New function: periodic I/O poller.
351 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
353 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
355 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
357 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
360 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
362 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
363 (load_word): Call SIM_CORE_SIGNAL hook on error.
364 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
365 starting. For exception dispatching, pass PC instead of NULL_CIA.
366 (decode_coproc): Use COP0_BADVADDR to store faulting address.
367 * sim-main.h (COP0_BADVADDR): Define.
368 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
369 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
370 (_sim_cpu): Add exc_* fields to store register value snapshots.
371 * mips.igen (*): Replace memory-related SignalException* calls
372 with references to SIM_CORE_SIGNAL hook.
374 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
376 * sim-main.c (*): Minor warning cleanups.
378 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
380 * m16.igen (DADDIU5): Correct type-o.
382 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
384 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
387 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
389 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
391 (interp.o): Add dependency on itable.h
392 (oengine.c, gencode): Delete remaining references.
393 (BUILT_SRC_FROM_GEN): Clean up.
395 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
398 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
399 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
401 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
402 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
403 Drop the "64" qualifier to get the HACK generator working.
404 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
405 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
406 qualifier to get the hack generator working.
407 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
409 (DSLLV): Use do_dsllv.
412 (DSRLV): Use do_dsrlv.
413 (BC1): Move *vr4100 to get the HACK generator working.
414 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
415 get the HACK generator working.
416 (MACC) Rename to get the HACK generator working.
417 (DMACC,MACCS,DMACCS): Add the 64.
419 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
421 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
422 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
424 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
426 * mips/interp.c (DEBUG): Cleanups.
428 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
430 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
431 (tx3904sio_tickle): fflush after a stdout character output.
433 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
435 * interp.c (sim_close): Uninstall modules.
437 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
439 * sim-main.h, interp.c (sim_monitor): Change to global
442 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
444 * configure.in (vr4100): Only include vr4100 instructions in
446 * configure: Re-generate.
447 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
449 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
451 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
452 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
455 * configure.in (sim_default_gen, sim_use_gen): Replace with
457 (--enable-sim-igen): Delete config option. Always using IGEN.
458 * configure: Re-generate.
460 * Makefile.in (gencode): Kill, kill, kill.
463 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
465 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
466 bit mips16 igen simulator.
467 * configure: Re-generate.
469 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
470 as part of vr4100 ISA.
471 * vr.igen: Mark all instructions as 64 bit only.
473 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
475 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
478 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
480 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
481 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
482 * configure: Re-generate.
484 * m16.igen (BREAK): Define breakpoint instruction.
485 (JALX32): Mark instruction as mips16 and not r3900.
486 * mips.igen (C.cond.fmt): Fix typo in instruction format.
488 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
490 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
492 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
493 insn as a debug breakpoint.
495 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
497 (PENDING_SCHED): Clean up trace statement.
498 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
499 (PENDING_FILL): Delay write by only one cycle.
500 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
502 * sim-main.c (pending_tick): Clean up trace statements. Add trace
504 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
506 (pending_tick): Move incrementing of index to FOR statement.
507 (pending_tick): Only update PENDING_OUT after a write has occured.
509 * configure.in: Add explicit mips-lsi-* target. Use gencode to
511 * configure: Re-generate.
513 * interp.c (sim_engine_run OLD): Delete explicit call to
514 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
516 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
518 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
519 interrupt level number to match changed SignalExceptionInterrupt
522 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
524 * interp.c: #include "itable.h" if WITH_IGEN.
525 (get_insn_name): New function.
526 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
527 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
529 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
531 * configure: Rebuilt to inhale new common/aclocal.m4.
533 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
535 * dv-tx3904sio.c: Include sim-assert.h.
537 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
539 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
540 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
541 Reorganize target-specific sim-hardware checks.
542 * configure: rebuilt.
543 * interp.c (sim_open): For tx39 target boards, set
544 OPERATING_ENVIRONMENT, add tx3904sio devices.
545 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
546 ROM executables. Install dv-sockser into sim-modules list.
548 * dv-tx3904irc.c: Compiler warning clean-up.
549 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
550 frequent hw-trace messages.
552 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
554 * vr.igen (MulAcc): Identify as a vr4100 specific function.
556 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
558 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
561 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
562 * mips.igen: Define vr4100 model. Include vr.igen.
563 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
565 * mips.igen (check_mf_hilo): Correct check.
567 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
569 * sim-main.h (interrupt_event): Add prototype.
571 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
572 register_ptr, register_value.
573 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
575 * sim-main.h (tracefh): Make extern.
577 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
579 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
580 Reduce unnecessarily high timer event frequency.
581 * dv-tx3904cpu.c: Ditto for interrupt event.
583 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
585 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
587 (interrupt_event): Made non-static.
589 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
590 interchange of configuration values for external vs. internal
593 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
595 * mips.igen (BREAK): Moved code to here for
596 simulator-reserved break instructions.
597 * gencode.c (build_instruction): Ditto.
598 * interp.c (signal_exception): Code moved from here. Non-
599 reserved instructions now use exception vector, rather
601 * sim-main.h: Moved magic constants to here.
603 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
605 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
606 register upon non-zero interrupt event level, clear upon zero
608 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
609 by passing zero event value.
610 (*_io_{read,write}_buffer): Endianness fixes.
611 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
612 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
614 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
615 serial I/O and timer module at base address 0xFFFF0000.
617 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
619 * mips.igen (SWC1) : Correct the handling of ReverseEndian
622 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
624 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
628 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
630 * dv-tx3904tmr.c: New file - implements tx3904 timer.
631 * dv-tx3904{irc,cpu}.c: Mild reformatting.
632 * configure.in: Include tx3904tmr in hw_device list.
633 * configure: Rebuilt.
634 * interp.c (sim_open): Instantiate three timer instances.
635 Fix address typo of tx3904irc instance.
637 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
639 * interp.c (signal_exception): SystemCall exception now uses
640 the exception vector.
642 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
644 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
647 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
649 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
651 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
653 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
655 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
656 sim-main.h. Declare a struct hw_descriptor instead of struct
657 hw_device_descriptor.
659 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
661 * mips.igen (do_store_left, do_load_left): Compute nr of left and
662 right bits and then re-align left hand bytes to correct byte
663 lanes. Fix incorrect computation in do_store_left when loading
664 bytes from second word.
666 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
668 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
669 * interp.c (sim_open): Only create a device tree when HW is
672 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
673 * interp.c (signal_exception): Ditto.
675 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
677 * gencode.c: Mark BEGEZALL as LIKELY.
679 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
681 * sim-main.h (ALU32_END): Sign extend 32 bit results.
682 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
684 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
686 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
687 modules. Recognize TX39 target with "mips*tx39" pattern.
688 * configure: Rebuilt.
689 * sim-main.h (*): Added many macros defining bits in
690 TX39 control registers.
691 (SignalInterrupt): Send actual PC instead of NULL.
692 (SignalNMIReset): New exception type.
693 * interp.c (board): New variable for future use to identify
694 a particular board being simulated.
695 (mips_option_handler,mips_options): Added "--board" option.
696 (interrupt_event): Send actual PC.
697 (sim_open): Make memory layout conditional on board setting.
698 (signal_exception): Initial implementation of hardware interrupt
699 handling. Accept another break instruction variant for simulator
701 (decode_coproc): Implement RFE instruction for TX39.
702 (mips.igen): Decode RFE instruction as such.
703 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
704 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
705 bbegin to implement memory map.
706 * dv-tx3904cpu.c: New file.
707 * dv-tx3904irc.c: New file.
709 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
711 * mips.igen (check_mt_hilo): Create a separate r3900 version.
713 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
715 * tx.igen (madd,maddu): Replace calls to check_op_hilo
716 with calls to check_div_hilo.
718 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
720 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
721 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
722 Add special r3900 version of do_mult_hilo.
723 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
724 with calls to check_mult_hilo.
725 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
726 with calls to check_div_hilo.
728 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
730 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
731 Document a replacement.
733 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
735 * interp.c (sim_monitor): Make mon_printf work.
737 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
739 * sim-main.h (INSN_NAME): New arg `cpu'.
741 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
743 * configure: Regenerated to track ../common/aclocal.m4 changes.
745 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
747 * configure: Regenerated to track ../common/aclocal.m4 changes.
750 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
752 * acconfig.h: New file.
753 * configure.in: Reverted change of Apr 24; use sinclude again.
755 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
757 * configure: Regenerated to track ../common/aclocal.m4 changes.
760 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
762 * configure.in: Don't call sinclude.
764 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
766 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
768 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
770 * mips.igen (ERET): Implement.
772 * interp.c (decode_coproc): Return sign-extended EPC.
774 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
776 * interp.c (signal_exception): Do not ignore Trap.
777 (signal_exception): On TRAP, restart at exception address.
778 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
779 (signal_exception): Update.
780 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
781 so that TRAP instructions are caught.
783 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
785 * sim-main.h (struct hilo_access, struct hilo_history): Define,
786 contains HI/LO access history.
787 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
788 (HIACCESS, LOACCESS): Delete, replace with
789 (HIHISTORY, LOHISTORY): New macros.
790 (CHECKHILO): Delete all, moved to mips.igen
792 * gencode.c (build_instruction): Do not generate checks for
793 correct HI/LO register usage.
795 * interp.c (old_engine_run): Delete checks for correct HI/LO
798 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
799 check_mf_cycles): New functions.
800 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
801 do_divu, domultx, do_mult, do_multu): Use.
803 * tx.igen ("madd", "maddu"): Use.
805 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
807 * mips.igen (DSRAV): Use function do_dsrav.
808 (SRAV): Use new function do_srav.
810 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
811 (B): Sign extend 11 bit immediate.
812 (EXT-B*): Shift 16 bit immediate left by 1.
813 (ADDIU*): Don't sign extend immediate value.
815 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
817 * m16run.c (sim_engine_run): Restore CIA after handling an event.
819 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
822 * mips.igen (delayslot32, nullify_next_insn): New functions.
823 (m16.igen): Always include.
824 (do_*): Add more tracing.
826 * m16.igen (delayslot16): Add NIA argument, could be called by a
827 32 bit MIPS16 instruction.
829 * interp.c (ifetch16): Move function from here.
830 * sim-main.c (ifetch16): To here.
832 * sim-main.c (ifetch16, ifetch32): Update to match current
833 implementations of LH, LW.
834 (signal_exception): Don't print out incorrect hex value of illegal
837 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
839 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
842 * m16.igen: Implement MIPS16 instructions.
844 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
845 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
846 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
847 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
848 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
849 bodies of corresponding code from 32 bit insn to these. Also used
850 by MIPS16 versions of functions.
852 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
853 (IMEM16): Drop NR argument from macro.
855 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
857 * Makefile.in (SIM_OBJS): Add sim-main.o.
859 * sim-main.h (address_translation, load_memory, store_memory,
860 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
862 (pr_addr, pr_uword64): Declare.
863 (sim-main.c): Include when H_REVEALS_MODULE_P.
865 * interp.c (address_translation, load_memory, store_memory,
866 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
868 * sim-main.c: To here. Fix compilation problems.
870 * configure.in: Enable inlining.
871 * configure: Re-config.
873 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
875 * configure: Regenerated to track ../common/aclocal.m4 changes.
877 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
879 * mips.igen: Include tx.igen.
880 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
881 * tx.igen: New file, contains MADD and MADDU.
883 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
884 the hardwired constant `7'.
885 (store_memory): Ditto.
886 (LOADDRMASK): Move definition to sim-main.h.
888 mips.igen (MTC0): Enable for r3900.
891 mips.igen (do_load_byte): Delete.
892 (do_load, do_store, do_load_left, do_load_write, do_store_left,
893 do_store_right): New functions.
894 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
896 configure.in: Let the tx39 use igen again.
899 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
901 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
902 not an address sized quantity. Return zero for cache sizes.
904 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
906 * mips.igen (r3900): r3900 does not support 64 bit integer
909 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
911 * configure.in (mipstx39*-*-*): Use gencode simulator rather
913 * configure : Rebuild.
915 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
917 * configure: Regenerated to track ../common/aclocal.m4 changes.
919 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
921 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
923 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
925 * configure: Regenerated to track ../common/aclocal.m4 changes.
926 * config.in: Regenerated to track ../common/aclocal.m4 changes.
928 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
930 * configure: Regenerated to track ../common/aclocal.m4 changes.
932 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
934 * interp.c (Max, Min): Comment out functions. Not yet used.
936 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
938 * configure: Regenerated to track ../common/aclocal.m4 changes.
940 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
942 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
943 configurable settings for stand-alone simulator.
945 * configure.in: Added X11 search, just in case.
947 * configure: Regenerated.
949 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
951 * interp.c (sim_write, sim_read, load_memory, store_memory):
952 Replace sim_core_*_map with read_map, write_map, exec_map resp.
954 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
956 * sim-main.h (GETFCC): Return an unsigned value.
958 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
960 * mips.igen (DIV): Fix check for -1 / MIN_INT.
961 (DADD): Result destination is RD not RT.
963 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
965 * sim-main.h (HIACCESS, LOACCESS): Always define.
967 * mdmx.igen (Maxi, Mini): Rename Max, Min.
969 * interp.c (sim_info): Delete.
971 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
973 * interp.c (DECLARE_OPTION_HANDLER): Use it.
974 (mips_option_handler): New argument `cpu'.
975 (sim_open): Update call to sim_add_option_table.
977 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
979 * mips.igen (CxC1): Add tracing.
981 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
983 * sim-main.h (Max, Min): Declare.
985 * interp.c (Max, Min): New functions.
987 * mips.igen (BC1): Add tracing.
989 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
991 * interp.c Added memory map for stack in vr4100
993 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
995 * interp.c (load_memory): Add missing "break"'s.
997 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
999 * interp.c (sim_store_register, sim_fetch_register): Pass in
1000 length parameter. Return -1.
1002 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1004 * interp.c: Added hardware init hook, fixed warnings.
1006 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1010 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1012 * interp.c (ifetch16): New function.
1014 * sim-main.h (IMEM32): Rename IMEM.
1015 (IMEM16_IMMED): Define.
1017 (DELAY_SLOT): Update.
1019 * m16run.c (sim_engine_run): New file.
1021 * m16.igen: All instructions except LB.
1022 (LB): Call do_load_byte.
1023 * mips.igen (do_load_byte): New function.
1024 (LB): Call do_load_byte.
1026 * mips.igen: Move spec for insn bit size and high bit from here.
1027 * Makefile.in (tmp-igen, tmp-m16): To here.
1029 * m16.dc: New file, decode mips16 instructions.
1031 * Makefile.in (SIM_NO_ALL): Define.
1032 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1034 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1036 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1037 point unit to 32 bit registers.
1038 * configure: Re-generate.
1040 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1042 * configure.in (sim_use_gen): Make IGEN the default simulator
1043 generator for generic 32 and 64 bit mips targets.
1044 * configure: Re-generate.
1046 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1048 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1051 * interp.c (sim_fetch_register, sim_store_register): Read/write
1052 FGR from correct location.
1053 (sim_open): Set size of FGR's according to
1054 WITH_TARGET_FLOATING_POINT_BITSIZE.
1056 * sim-main.h (FGR): Store floating point registers in a separate
1059 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1061 * configure: Regenerated to track ../common/aclocal.m4 changes.
1063 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1065 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1067 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1069 * interp.c (pending_tick): New function. Deliver pending writes.
1071 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1072 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1073 it can handle mixed sized quantites and single bits.
1075 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1077 * interp.c (oengine.h): Do not include when building with IGEN.
1078 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1079 (sim_info): Ditto for PROCESSOR_64BIT.
1080 (sim_monitor): Replace ut_reg with unsigned_word.
1081 (*): Ditto for t_reg.
1082 (LOADDRMASK): Define.
1083 (sim_open): Remove defunct check that host FP is IEEE compliant,
1084 using software to emulate floating point.
1085 (value_fpr, ...): Always compile, was conditional on HASFPU.
1087 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1089 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1092 * interp.c (SD, CPU): Define.
1093 (mips_option_handler): Set flags in each CPU.
1094 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1095 (sim_close): Do not clear STATE, deleted anyway.
1096 (sim_write, sim_read): Assume CPU zero's vm should be used for
1098 (sim_create_inferior): Set the PC for all processors.
1099 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1101 (mips16_entry): Pass correct nr of args to store_word, load_word.
1102 (ColdReset): Cold reset all cpu's.
1103 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1104 (sim_monitor, load_memory, store_memory, signal_exception): Use
1105 `CPU' instead of STATE_CPU.
1108 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1111 * sim-main.h (signal_exception): Add sim_cpu arg.
1112 (SignalException*): Pass both SD and CPU to signal_exception.
1113 * interp.c (signal_exception): Update.
1115 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1117 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1118 address_translation): Ditto
1119 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1121 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1123 * configure: Regenerated to track ../common/aclocal.m4 changes.
1125 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1129 * mips.igen (model): Map processor names onto BFD name.
1131 * sim-main.h (CPU_CIA): Delete.
1132 (SET_CIA, GET_CIA): Define
1134 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1136 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1139 * configure.in (default_endian): Configure a big-endian simulator
1141 * configure: Re-generate.
1143 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1145 * configure: Regenerated to track ../common/aclocal.m4 changes.
1147 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1149 * interp.c (sim_monitor): Handle Densan monitor outbyte
1150 and inbyte functions.
1152 1997-12-29 Felix Lee <flee@cygnus.com>
1154 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1156 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1158 * Makefile.in (tmp-igen): Arrange for $zero to always be
1159 reset to zero after every instruction.
1161 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1163 * configure: Regenerated to track ../common/aclocal.m4 changes.
1166 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1168 * mips.igen (MSUB): Fix to work like MADD.
1169 * gencode.c (MSUB): Similarly.
1171 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1173 * configure: Regenerated to track ../common/aclocal.m4 changes.
1175 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1177 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1179 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1181 * sim-main.h (sim-fpu.h): Include.
1183 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1184 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1185 using host independant sim_fpu module.
1187 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1189 * interp.c (signal_exception): Report internal errors with SIGABRT
1192 * sim-main.h (C0_CONFIG): New register.
1193 (signal.h): No longer include.
1195 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1197 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1199 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1201 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1203 * mips.igen: Tag vr5000 instructions.
1204 (ANDI): Was missing mipsIV model, fix assembler syntax.
1205 (do_c_cond_fmt): New function.
1206 (C.cond.fmt): Handle mips I-III which do not support CC field
1208 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1209 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1211 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1212 vr5000 which saves LO in a GPR separatly.
1214 * configure.in (enable-sim-igen): For vr5000, select vr5000
1215 specific instructions.
1216 * configure: Re-generate.
1218 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1220 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1222 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1223 fmt_uninterpreted_64 bit cases to switch. Convert to
1226 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1228 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1229 as specified in IV3.2 spec.
1230 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1232 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1234 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1235 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1236 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1237 PENDING_FILL versions of instructions. Simplify.
1239 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1241 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1243 (MTHI, MFHI): Disable code checking HI-LO.
1245 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1247 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1249 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1251 * gencode.c (build_mips16_operands): Replace IPC with cia.
1253 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1254 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1256 (UndefinedResult): Replace function with macro/function
1258 (sim_engine_run): Don't save PC in IPC.
1260 * sim-main.h (IPC): Delete.
1263 * interp.c (signal_exception, store_word, load_word,
1264 address_translation, load_memory, store_memory, cache_op,
1265 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1266 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1267 current instruction address - cia - argument.
1268 (sim_read, sim_write): Call address_translation directly.
1269 (sim_engine_run): Rename variable vaddr to cia.
1270 (signal_exception): Pass cia to sim_monitor
1272 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1273 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1274 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1276 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1277 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1280 * interp.c (signal_exception): Pass restart address to
1283 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1284 idecode.o): Add dependency.
1286 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1288 (DELAY_SLOT): Update NIA not PC with branch address.
1289 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1291 * mips.igen: Use CIA not PC in branch calculations.
1292 (illegal): Call SignalException.
1293 (BEQ, ADDIU): Fix assembler.
1295 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297 * m16.igen (JALX): Was missing.
1299 * configure.in (enable-sim-igen): New configuration option.
1300 * configure: Re-generate.
1302 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1304 * interp.c (load_memory, store_memory): Delete parameter RAW.
1305 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1306 bypassing {load,store}_memory.
1308 * sim-main.h (ByteSwapMem): Delete definition.
1310 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1312 * interp.c (sim_do_command, sim_commands): Delete mips specific
1313 commands. Handled by module sim-options.
1315 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1316 (WITH_MODULO_MEMORY): Define.
1318 * interp.c (sim_info): Delete code printing memory size.
1320 * interp.c (mips_size): Nee sim_size, delete function.
1322 (monitor, monitor_base, monitor_size): Delete global variables.
1323 (sim_open, sim_close): Delete code creating monitor and other
1324 memory regions. Use sim-memopts module, via sim_do_commandf, to
1325 manage memory regions.
1326 (load_memory, store_memory): Use sim-core for memory model.
1328 * interp.c (address_translation): Delete all memory map code
1329 except line forcing 32 bit addresses.
1331 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1333 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1336 * interp.c (logfh, logfile): Delete globals.
1337 (sim_open, sim_close): Delete code opening & closing log file.
1338 (mips_option_handler): Delete -l and -n options.
1339 (OPTION mips_options): Ditto.
1341 * interp.c (OPTION mips_options): Rename option trace to dinero.
1342 (mips_option_handler): Update.
1344 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1346 * interp.c (fetch_str): New function.
1347 (sim_monitor): Rewrite using sim_read & sim_write.
1348 (sim_open): Check magic number.
1349 (sim_open): Write monitor vectors into memory using sim_write.
1350 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1351 (sim_read, sim_write): Simplify - transfer data one byte at a
1353 (load_memory, store_memory): Clarify meaning of parameter RAW.
1355 * sim-main.h (isHOST): Defete definition.
1356 (isTARGET): Mark as depreciated.
1357 (address_translation): Delete parameter HOST.
1359 * interp.c (address_translation): Delete parameter HOST.
1361 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1365 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1366 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1368 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1370 * mips.igen: Add model filter field to records.
1372 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1376 interp.c (sim_engine_run): Do not compile function sim_engine_run
1377 when WITH_IGEN == 1.
1379 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1380 target architecture.
1382 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1383 igen. Replace with configuration variables sim_igen_flags /
1386 * m16.igen: New file. Copy mips16 insns here.
1387 * mips.igen: From here.
1389 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1393 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1395 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1397 * gencode.c (build_instruction): Follow sim_write's lead in using
1398 BigEndianMem instead of !ByteSwapMem.
1400 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402 * configure.in (sim_gen): Dependent on target, select type of
1403 generator. Always select old style generator.
1405 configure: Re-generate.
1407 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1409 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1410 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1411 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1412 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1413 SIM_@sim_gen@_*, set by autoconf.
1415 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1417 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1419 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1420 CURRENT_FLOATING_POINT instead.
1422 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1423 (address_translation): Raise exception InstructionFetch when
1424 translation fails and isINSTRUCTION.
1426 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1427 sim_engine_run): Change type of of vaddr and paddr to
1429 (address_translation, prefetch, load_memory, store_memory,
1430 cache_op): Change type of vAddr and pAddr to address_word.
1432 * gencode.c (build_instruction): Change type of vaddr and paddr to
1435 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1438 macro to obtain result of ALU op.
1440 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1442 * interp.c (sim_info): Call profile_print.
1444 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1446 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1448 * sim-main.h (WITH_PROFILE): Do not define, defined in
1449 common/sim-config.h. Use sim-profile module.
1450 (simPROFILE): Delete defintion.
1452 * interp.c (PROFILE): Delete definition.
1453 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1454 (sim_close): Delete code writing profile histogram.
1455 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1457 (sim_engine_run): Delete code profiling the PC.
1459 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1461 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1463 * interp.c (sim_monitor): Make register pointers of type
1466 * sim-main.h: Make registers of type unsigned_word not
1469 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1471 * interp.c (sync_operation): Rename from SyncOperation, make
1472 global, add SD argument.
1473 (prefetch): Rename from Prefetch, make global, add SD argument.
1474 (decode_coproc): Make global.
1476 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1478 * gencode.c (build_instruction): Generate DecodeCoproc not
1479 decode_coproc calls.
1481 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1482 (SizeFGR): Move to sim-main.h
1483 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1484 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1485 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1487 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1488 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1489 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1490 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1491 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1492 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1494 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1496 (sim-alu.h): Include.
1497 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1498 (sim_cia): Typedef to instruction_address.
1500 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502 * Makefile.in (interp.o): Rename generated file engine.c to
1507 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1509 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1511 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513 * gencode.c (build_instruction): For "FPSQRT", output correct
1514 number of arguments to Recip.
1516 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1518 * Makefile.in (interp.o): Depends on sim-main.h
1520 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1522 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1523 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1524 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1525 STATE, DSSTATE): Define
1526 (GPR, FGRIDX, ..): Define.
1528 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1529 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1530 (GPR, FGRIDX, ...): Delete macros.
1532 * interp.c: Update names to match defines from sim-main.h
1534 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536 * interp.c (sim_monitor): Add SD argument.
1537 (sim_warning): Delete. Replace calls with calls to
1539 (sim_error): Delete. Replace calls with sim_io_error.
1540 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1541 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1542 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1544 (mips_size): Rename from sim_size. Add SD argument.
1546 * interp.c (simulator): Delete global variable.
1547 (callback): Delete global variable.
1548 (mips_option_handler, sim_open, sim_write, sim_read,
1549 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1550 sim_size,sim_monitor): Use sim_io_* not callback->*.
1551 (sim_open): ZALLOC simulator struct.
1552 (PROFILE): Do not define.
1554 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1556 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1557 support.h with corresponding code.
1559 * sim-main.h (word64, uword64), support.h: Move definition to
1561 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1564 * Makefile.in: Update dependencies
1565 * interp.c: Do not include.
1567 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569 * interp.c (address_translation, load_memory, store_memory,
1570 cache_op): Rename to from AddressTranslation et.al., make global,
1573 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1576 * interp.c (SignalException): Rename to signal_exception, make
1579 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1581 * sim-main.h (SignalException, SignalExceptionInterrupt,
1582 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1583 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1584 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1587 * interp.c, support.h: Use.
1589 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1592 to value_fpr / store_fpr. Add SD argument.
1593 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1594 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1596 * sim-main.h (ValueFPR, StoreFPR): Define.
1598 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1600 * interp.c (sim_engine_run): Check consistency between configure
1601 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1604 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1605 (mips_fpu): Configure WITH_FLOATING_POINT.
1606 (mips_endian): Configure WITH_TARGET_ENDIAN.
1607 * configure: Update.
1609 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1611 * configure: Regenerated to track ../common/aclocal.m4 changes.
1613 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1615 * configure: Regenerated.
1617 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1619 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1621 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623 * gencode.c (print_igen_insn_models): Assume certain architectures
1624 include all mips* instructions.
1625 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1628 * Makefile.in (tmp.igen): Add target. Generate igen input from
1631 * gencode.c (FEATURE_IGEN): Define.
1632 (main): Add --igen option. Generate output in igen format.
1633 (process_instructions): Format output according to igen option.
1634 (print_igen_insn_format): New function.
1635 (print_igen_insn_models): New function.
1636 (process_instructions): Only issue warnings and ignore
1637 instructions when no FEATURE_IGEN.
1639 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1644 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1646 * configure: Regenerated to track ../common/aclocal.m4 changes.
1648 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1651 SIM_RESERVED_BITS): Delete, moved to common.
1652 (SIM_EXTRA_CFLAGS): Update.
1654 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1656 * configure.in: Configure non-strict memory alignment.
1657 * configure: Regenerated to track ../common/aclocal.m4 changes.
1659 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661 * configure: Regenerated to track ../common/aclocal.m4 changes.
1663 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1665 * gencode.c (SDBBP,DERET): Added (3900) insns.
1666 (RFE): Turn on for 3900.
1667 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1668 (dsstate): Made global.
1669 (SUBTARGET_R3900): Added.
1670 (CANCELDELAYSLOT): New.
1671 (SignalException): Ignore SystemCall rather than ignore and
1672 terminate. Add DebugBreakPoint handling.
1673 (decode_coproc): New insns RFE, DERET; and new registers Debug
1674 and DEPC protected by SUBTARGET_R3900.
1675 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1677 * Makefile.in,configure.in: Add mips subtarget option.
1678 * configure: Update.
1680 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1682 * gencode.c: Add r3900 (tx39).
1685 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1687 * gencode.c (build_instruction): Don't need to subtract 4 for
1690 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1692 * interp.c: Correct some HASFPU problems.
1694 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696 * configure: Regenerated to track ../common/aclocal.m4 changes.
1698 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1700 * interp.c (mips_options): Fix samples option short form, should
1703 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705 * interp.c (sim_info): Enable info code. Was just returning.
1707 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1709 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1712 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1714 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1716 (build_instruction): Ditto for LL.
1718 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1720 * configure: Regenerated to track ../common/aclocal.m4 changes.
1722 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1724 * configure: Regenerated to track ../common/aclocal.m4 changes.
1727 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1729 * interp.c (sim_open): Add call to sim_analyze_program, update
1732 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1734 * interp.c (sim_kill): Delete.
1735 (sim_create_inferior): Add ABFD argument. Set PC from same.
1736 (sim_load): Move code initializing trap handlers from here.
1737 (sim_open): To here.
1738 (sim_load): Delete, use sim-hload.c.
1740 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1742 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744 * configure: Regenerated to track ../common/aclocal.m4 changes.
1747 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1749 * interp.c (sim_open): Add ABFD argument.
1750 (sim_load): Move call to sim_config from here.
1751 (sim_open): To here. Check return status.
1753 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1755 * gencode.c (build_instruction): Two arg MADD should
1756 not assign result to $0.
1758 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1760 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1761 * sim/mips/configure.in: Regenerate.
1763 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1765 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1766 signed8, unsigned8 et.al. types.
1768 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1769 hosts when selecting subreg.
1771 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1773 * interp.c (sim_engine_run): Reset the ZERO register to zero
1774 regardless of FEATURE_WARN_ZERO.
1775 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1777 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1779 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1780 (SignalException): For BreakPoints ignore any mode bits and just
1782 (SignalException): Always set the CAUSE register.
1784 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1786 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1787 exception has been taken.
1789 * interp.c: Implement the ERET and mt/f sr instructions.
1791 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1793 * interp.c (SignalException): Don't bother restarting an
1796 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1798 * interp.c (SignalException): Really take an interrupt.
1799 (interrupt_event): Only deliver interrupts when enabled.
1801 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1803 * interp.c (sim_info): Only print info when verbose.
1804 (sim_info) Use sim_io_printf for output.
1806 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1808 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1811 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1813 * interp.c (sim_do_command): Check for common commands if a
1814 simulator specific command fails.
1816 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1818 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1819 and simBE when DEBUG is defined.
1821 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823 * interp.c (interrupt_event): New function. Pass exception event
1824 onto exception handler.
1826 * configure.in: Check for stdlib.h.
1827 * configure: Regenerate.
1829 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1830 variable declaration.
1831 (build_instruction): Initialize memval1.
1832 (build_instruction): Add UNUSED attribute to byte, bigend,
1834 (build_operands): Ditto.
1836 * interp.c: Fix GCC warnings.
1837 (sim_get_quit_code): Delete.
1839 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1840 * Makefile.in: Ditto.
1841 * configure: Re-generate.
1843 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1845 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1847 * interp.c (mips_option_handler): New function parse argumes using
1849 (myname): Replace with STATE_MY_NAME.
1850 (sim_open): Delete check for host endianness - performed by
1852 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1853 (sim_open): Move much of the initialization from here.
1854 (sim_load): To here. After the image has been loaded and
1856 (sim_open): Move ColdReset from here.
1857 (sim_create_inferior): To here.
1858 (sim_open): Make FP check less dependant on host endianness.
1860 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1862 * interp.c (sim_set_callbacks): Delete.
1864 * interp.c (membank, membank_base, membank_size): Replace with
1865 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1866 (sim_open): Remove call to callback->init. gdb/run do this.
1870 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1872 * interp.c (big_endian_p): Delete, replaced by
1873 current_target_byte_order.
1875 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1877 * interp.c (host_read_long, host_read_word, host_swap_word,
1878 host_swap_long): Delete. Using common sim-endian.
1879 (sim_fetch_register, sim_store_register): Use H2T.
1880 (pipeline_ticks): Delete. Handled by sim-events.
1882 (sim_engine_run): Update.
1884 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1886 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1888 (SignalException): To here. Signal using sim_engine_halt.
1889 (sim_stop_reason): Delete, moved to common.
1891 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1893 * interp.c (sim_open): Add callback argument.
1894 (sim_set_callbacks): Delete SIM_DESC argument.
1897 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1899 * Makefile.in (SIM_OBJS): Add common modules.
1901 * interp.c (sim_set_callbacks): Also set SD callback.
1902 (set_endianness, xfer_*, swap_*): Delete.
1903 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1904 Change to functions using sim-endian macros.
1905 (control_c, sim_stop): Delete, use common version.
1906 (simulate): Convert into.
1907 (sim_engine_run): This function.
1908 (sim_resume): Delete.
1910 * interp.c (simulation): New variable - the simulator object.
1911 (sim_kind): Delete global - merged into simulation.
1912 (sim_load): Cleanup. Move PC assignment from here.
1913 (sim_create_inferior): To here.
1915 * sim-main.h: New file.
1916 * interp.c (sim-main.h): Include.
1918 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1920 * configure: Regenerated to track ../common/aclocal.m4 changes.
1922 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1924 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1926 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1928 * gencode.c (build_instruction): DIV instructions: check
1929 for division by zero and integer overflow before using
1930 host's division operation.
1932 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1934 * Makefile.in (SIM_OBJS): Add sim-load.o.
1935 * interp.c: #include bfd.h.
1936 (target_byte_order): Delete.
1937 (sim_kind, myname, big_endian_p): New static locals.
1938 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1939 after argument parsing. Recognize -E arg, set endianness accordingly.
1940 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1941 load file into simulator. Set PC from bfd.
1942 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1943 (set_endianness): Use big_endian_p instead of target_byte_order.
1945 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1947 * interp.c (sim_size): Delete prototype - conflicts with
1948 definition in remote-sim.h. Correct definition.
1950 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1952 * configure: Regenerated to track ../common/aclocal.m4 changes.
1955 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1957 * interp.c (sim_open): New arg `kind'.
1959 * configure: Regenerated to track ../common/aclocal.m4 changes.
1961 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1963 * configure: Regenerated to track ../common/aclocal.m4 changes.
1965 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1967 * interp.c (sim_open): Set optind to 0 before calling getopt.
1969 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1971 * configure: Regenerated to track ../common/aclocal.m4 changes.
1973 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1975 * interp.c : Replace uses of pr_addr with pr_uword64
1976 where the bit length is always 64 independent of SIM_ADDR.
1977 (pr_uword64) : added.
1979 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1981 * configure: Re-generate.
1983 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1985 * configure: Regenerate to track ../common/aclocal.m4 changes.
1987 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1989 * interp.c (sim_open): New SIM_DESC result. Argument is now
1991 (other sim_*): New SIM_DESC argument.
1993 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1995 * interp.c: Fix printing of addresses for non-64-bit targets.
1996 (pr_addr): Add function to print address based on size.
1998 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2000 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2002 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2004 * gencode.c (build_mips16_operands): Correct computation of base
2005 address for extended PC relative instruction.
2007 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2009 * interp.c (mips16_entry): Add support for floating point cases.
2010 (SignalException): Pass floating point cases to mips16_entry.
2011 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2013 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2015 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2016 and then set the state to fmt_uninterpreted.
2017 (COP_SW): Temporarily set the state to fmt_word while calling
2020 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2022 * gencode.c (build_instruction): The high order may be set in the
2023 comparison flags at any ISA level, not just ISA 4.
2025 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2027 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2028 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2029 * configure.in: sinclude ../common/aclocal.m4.
2030 * configure: Regenerated.
2032 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2034 * configure: Rebuild after change to aclocal.m4.
2036 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2038 * configure configure.in Makefile.in: Update to new configure
2039 scheme which is more compatible with WinGDB builds.
2040 * configure.in: Improve comment on how to run autoconf.
2041 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2042 * Makefile.in: Use autoconf substitution to install common
2045 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2047 * gencode.c (build_instruction): Use BigEndianCPU instead of
2050 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2052 * interp.c (sim_monitor): Make output to stdout visible in
2053 wingdb's I/O log window.
2055 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2057 * support.h: Undo previous change to SIGTRAP
2060 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2062 * interp.c (store_word, load_word): New static functions.
2063 (mips16_entry): New static function.
2064 (SignalException): Look for mips16 entry and exit instructions.
2065 (simulate): Use the correct index when setting fpr_state after
2066 doing a pending move.
2068 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2070 * interp.c: Fix byte-swapping code throughout to work on
2071 both little- and big-endian hosts.
2073 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2075 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2076 with gdb/config/i386/xm-windows.h.
2078 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2080 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2081 that messes up arithmetic shifts.
2083 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2085 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2086 SIGTRAP and SIGQUIT for _WIN32.
2088 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2090 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2091 force a 64 bit multiplication.
2092 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2093 destination register is 0, since that is the default mips16 nop
2096 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2098 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2099 (build_endian_shift): Don't check proc64.
2100 (build_instruction): Always set memval to uword64. Cast op2 to
2101 uword64 when shifting it left in memory instructions. Always use
2102 the same code for stores--don't special case proc64.
2104 * gencode.c (build_mips16_operands): Fix base PC value for PC
2106 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2108 * interp.c (simJALDELAYSLOT): Define.
2109 (JALDELAYSLOT): Define.
2110 (INDELAYSLOT, INJALDELAYSLOT): Define.
2111 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2113 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2115 * interp.c (sim_open): add flush_cache as a PMON routine
2116 (sim_monitor): handle flush_cache by ignoring it
2118 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2120 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2122 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2123 (BigEndianMem): Rename to ByteSwapMem and change sense.
2124 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2125 BigEndianMem references to !ByteSwapMem.
2126 (set_endianness): New function, with prototype.
2127 (sim_open): Call set_endianness.
2128 (sim_info): Use simBE instead of BigEndianMem.
2129 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2130 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2131 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2132 ifdefs, keeping the prototype declaration.
2133 (swap_word): Rewrite correctly.
2134 (ColdReset): Delete references to CONFIG. Delete endianness related
2135 code; moved to set_endianness.
2137 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2139 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2140 * interp.c (CHECKHILO): Define away.
2141 (simSIGINT): New macro.
2142 (membank_size): Increase from 1MB to 2MB.
2143 (control_c): New function.
2144 (sim_resume): Rename parameter signal to signal_number. Add local
2145 variable prev. Call signal before and after simulate.
2146 (sim_stop_reason): Add simSIGINT support.
2147 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2149 (sim_warning): Delete call to SignalException. Do call printf_filtered
2151 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2152 a call to sim_warning.
2154 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2156 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2157 16 bit instructions.
2159 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2161 Add support for mips16 (16 bit MIPS implementation):
2162 * gencode.c (inst_type): Add mips16 instruction encoding types.
2163 (GETDATASIZEINSN): Define.
2164 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2165 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2167 (MIPS16_DECODE): New table, for mips16 instructions.
2168 (bitmap_val): New static function.
2169 (struct mips16_op): Define.
2170 (mips16_op_table): New table, for mips16 operands.
2171 (build_mips16_operands): New static function.
2172 (process_instructions): If PC is odd, decode a mips16
2173 instruction. Break out instruction handling into new
2174 build_instruction function.
2175 (build_instruction): New static function, broken out of
2176 process_instructions. Check modifiers rather than flags for SHIFT
2177 bit count and m[ft]{hi,lo} direction.
2178 (usage): Pass program name to fprintf.
2179 (main): Remove unused variable this_option_optind. Change
2180 ``*loptarg++'' to ``loptarg++''.
2181 (my_strtoul): Parenthesize && within ||.
2182 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2183 (simulate): If PC is odd, fetch a 16 bit instruction, and
2184 increment PC by 2 rather than 4.
2185 * configure.in: Add case for mips16*-*-*.
2186 * configure: Rebuild.
2188 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2190 * interp.c: Allow -t to enable tracing in standalone simulator.
2191 Fix garbage output in trace file and error messages.
2193 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2195 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2196 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2197 * configure.in: Simplify using macros in ../common/aclocal.m4.
2198 * configure: Regenerated.
2199 * tconfig.in: New file.
2201 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2203 * interp.c: Fix bugs in 64-bit port.
2204 Use ansi function declarations for msvc compiler.
2205 Initialize and test file pointer in trace code.
2206 Prevent duplicate definition of LAST_EMED_REGNUM.
2208 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2210 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2212 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2214 * interp.c (SignalException): Check for explicit terminating
2216 * gencode.c: Pass instruction value through SignalException()
2217 calls for Trap, Breakpoint and Syscall.
2219 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2221 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2222 only used on those hosts that provide it.
2223 * configure.in: Add sqrt() to list of functions to be checked for.
2224 * config.in: Re-generated.
2225 * configure: Re-generated.
2227 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2229 * gencode.c (process_instructions): Call build_endian_shift when
2230 expanding STORE RIGHT, to fix swr.
2231 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2232 clear the high bits.
2233 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2234 Fix float to int conversions to produce signed values.
2236 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2238 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2239 (process_instructions): Correct handling of nor instruction.
2240 Correct shift count for 32 bit shift instructions. Correct sign
2241 extension for arithmetic shifts to not shift the number of bits in
2242 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2243 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2245 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2246 It's OK to have a mult follow a mult. What's not OK is to have a
2247 mult follow an mfhi.
2248 (Convert): Comment out incorrect rounding code.
2250 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2252 * interp.c (sim_monitor): Improved monitor printf
2253 simulation. Tidied up simulator warnings, and added "--log" option
2254 for directing warning message output.
2255 * gencode.c: Use sim_warning() rather than WARNING macro.
2257 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2259 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2260 getopt1.o, rather than on gencode.c. Link objects together.
2261 Don't link against -liberty.
2262 (gencode.o, getopt.o, getopt1.o): New targets.
2263 * gencode.c: Include <ctype.h> and "ansidecl.h".
2264 (AND): Undefine after including "ansidecl.h".
2265 (ULONG_MAX): Define if not defined.
2266 (OP_*): Don't define macros; now defined in opcode/mips.h.
2267 (main): Call my_strtoul rather than strtoul.
2268 (my_strtoul): New static function.
2270 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2272 * gencode.c (process_instructions): Generate word64 and uword64
2273 instead of `long long' and `unsigned long long' data types.
2274 * interp.c: #include sysdep.h to get signals, and define default
2276 * (Convert): Work around for Visual-C++ compiler bug with type
2278 * support.h: Make things compile under Visual-C++ by using
2279 __int64 instead of `long long'. Change many refs to long long
2280 into word64/uword64 typedefs.
2282 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2284 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2285 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2287 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2288 (AC_PROG_INSTALL): Added.
2289 (AC_PROG_CC): Moved to before configure.host call.
2290 * configure: Rebuilt.
2292 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2294 * configure.in: Define @SIMCONF@ depending on mips target.
2295 * configure: Rebuild.
2296 * Makefile.in (run): Add @SIMCONF@ to control simulator
2298 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2299 * interp.c: Remove some debugging, provide more detailed error
2300 messages, update memory accesses to use LOADDRMASK.
2302 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2304 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2305 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2307 * configure: Rebuild.
2308 * config.in: New file, generated by autoheader.
2309 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2310 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2311 HAVE_ANINT and HAVE_AINT, as appropriate.
2312 * Makefile.in (run): Use @LIBS@ rather than -lm.
2313 (interp.o): Depend upon config.h.
2314 (Makefile): Just rebuild Makefile.
2315 (clean): Remove stamp-h.
2316 (mostlyclean): Make the same as clean, not as distclean.
2317 (config.h, stamp-h): New targets.
2319 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2321 * interp.c (ColdReset): Fix boolean test. Make all simulator
2324 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2326 * interp.c (xfer_direct_word, xfer_direct_long,
2327 swap_direct_word, swap_direct_long, xfer_big_word,
2328 xfer_big_long, xfer_little_word, xfer_little_long,
2329 swap_word,swap_long): Added.
2330 * interp.c (ColdReset): Provide function indirection to
2331 host<->simulated_target transfer routines.
2332 * interp.c (sim_store_register, sim_fetch_register): Updated to
2333 make use of indirected transfer routines.
2335 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2337 * gencode.c (process_instructions): Ensure FP ABS instruction
2339 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2340 system call support.
2342 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2344 * interp.c (sim_do_command): Complain if callback structure not
2347 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2349 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2350 support for Sun hosts.
2351 * Makefile.in (gencode): Ensure the host compiler and libraries
2352 used for cross-hosted build.
2354 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2356 * interp.c, gencode.c: Some more (TODO) tidying.
2358 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2360 * gencode.c, interp.c: Replaced explicit long long references with
2361 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2362 * support.h (SET64LO, SET64HI): Macros added.
2364 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2366 * configure: Regenerate with autoconf 2.7.
2368 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2370 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2371 * support.h: Remove superfluous "1" from #if.
2372 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2374 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2376 * interp.c (StoreFPR): Control UndefinedResult() call on
2377 WARN_RESULT manifest.
2379 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2381 * gencode.c: Tidied instruction decoding, and added FP instruction
2384 * interp.c: Added dineroIII, and BSD profiling support. Also
2385 run-time FP handling.
2387 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2389 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2390 gencode.c, interp.c, support.h: created.