1 2013-03-26 Mike Frysinger <vapier@gentoo.org>
3 * configure: Regenerate.
5 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
7 * configure.ac: Address use of dv-sockser.o.
8 * tconfig.in: Conditionalize use of dv_sockser_install.
9 * configure: Regenerated.
10 * config.in: Regenerated.
12 2012-10-04 Chao-ying Fu <fu@mips.com>
13 Steve Ellcey <sellcey@mips.com>
15 * mips/mips3264r2.igen (rdhwr): New.
17 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
19 * configure.ac: Always link against dv-sockser.o.
20 * configure: Regenerate.
22 2012-06-15 Joel Brobecker <brobecker@adacore.com>
24 * config.in, configure: Regenerate.
26 2012-05-18 Nick Clifton <nickc@redhat.com>
29 * interp.c: Include config.h before system header files.
31 2012-03-24 Mike Frysinger <vapier@gentoo.org>
33 * aclocal.m4, config.in, configure: Regenerate.
35 2011-12-03 Mike Frysinger <vapier@gentoo.org>
37 * aclocal.m4: New file.
38 * configure: Regenerate.
40 2011-10-19 Mike Frysinger <vapier@gentoo.org>
42 * configure: Regenerate after common/acinclude.m4 update.
44 2011-10-17 Mike Frysinger <vapier@gentoo.org>
46 * configure.ac: Change include to common/acinclude.m4.
48 2011-10-17 Mike Frysinger <vapier@gentoo.org>
50 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
51 call. Replace common.m4 include with SIM_AC_COMMON.
52 * configure: Regenerate.
54 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
56 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
58 (tmp-mach-multi): Exit early when igen fails.
60 2011-07-05 Mike Frysinger <vapier@gentoo.org>
62 * interp.c (sim_do_command): Delete.
64 2011-02-14 Mike Frysinger <vapier@gentoo.org>
66 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
67 (tx3904sio_fifo_reset): Likewise.
68 * interp.c (sim_monitor): Likewise.
70 2010-04-14 Mike Frysinger <vapier@gentoo.org>
72 * interp.c (sim_write): Add const to buffer arg.
74 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
76 * interp.c: Don't include sysdep.h
78 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
80 * configure: Regenerate.
82 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
84 * config.in: Regenerate.
85 * configure: Likewise.
87 * configure: Regenerate.
89 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
91 * configure: Regenerate to track ../common/common.m4 changes.
94 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
95 Daniel Jacobowitz <dan@codesourcery.com>
96 Joseph Myers <joseph@codesourcery.com>
98 * configure: Regenerate.
100 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
102 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
103 that unconditionally allows fmt_ps.
104 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
105 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
106 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
107 filter from 64,f to 32,f.
108 (PREFX): Change filter from 64 to 32.
109 (LDXC1, LUXC1): Provide separate mips32r2 implementations
110 that use do_load_double instead of do_load. Make both LUXC1
111 versions unpredictable if SizeFGR () != 64.
112 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
113 instead of do_store. Remove unused variable. Make both SUXC1
114 versions unpredictable if SizeFGR () != 64.
116 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
118 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
119 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
120 shifts for that case.
122 2007-09-04 Nick Clifton <nickc@redhat.com>
124 * interp.c (options enum): Add OPTION_INFO_MEMORY.
125 (display_mem_info): New static variable.
126 (mips_option_handler): Handle OPTION_INFO_MEMORY.
127 (mips_options): Add info-memory and memory-info.
128 (sim_open): After processing the command line and board
129 specification, check display_mem_info. If it is set then
130 call the real handler for the --memory-info command line
133 2007-08-24 Joel Brobecker <brobecker@adacore.com>
135 * configure.ac: Change license of multi-run.c to GPL version 3.
136 * configure: Regenerate.
138 2007-06-28 Richard Sandiford <richard@codesourcery.com>
140 * configure.ac, configure: Revert last patch.
142 2007-06-26 Richard Sandiford <richard@codesourcery.com>
144 * configure.ac (sim_mipsisa3264_configs): New variable.
145 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
146 every configuration support all four targets, using the triplet to
147 determine the default.
148 * configure: Regenerate.
150 2007-06-25 Richard Sandiford <richard@codesourcery.com>
152 * Makefile.in (m16run.o): New rule.
154 2007-05-15 Thiemo Seufer <ths@mips.com>
156 * mips3264r2.igen (DSHD): Fix compile warning.
158 2007-05-14 Thiemo Seufer <ths@mips.com>
160 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
161 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
162 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
163 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
166 2007-03-01 Thiemo Seufer <ths@mips.com>
168 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
171 2007-02-20 Thiemo Seufer <ths@mips.com>
173 * dsp.igen: Update copyright notice.
174 * dsp2.igen: Fix copyright notice.
176 2007-02-20 Thiemo Seufer <ths@mips.com>
177 Chao-Ying Fu <fu@mips.com>
179 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
180 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
181 Add dsp2 to sim_igen_machine.
182 * configure: Regenerate.
183 * dsp.igen (do_ph_op): Add MUL support when op = 2.
184 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
185 (mulq_rs.ph): Use do_ph_mulq.
186 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
187 * mips.igen: Add dsp2 model and include dsp2.igen.
188 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
189 for *mips32r2, *mips64r2, *dsp.
190 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
191 for *mips32r2, *mips64r2, *dsp2.
192 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
194 2007-02-19 Thiemo Seufer <ths@mips.com>
195 Nigel Stephens <nigel@mips.com>
197 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
198 jumps with hazard barrier.
200 2007-02-19 Thiemo Seufer <ths@mips.com>
201 Nigel Stephens <nigel@mips.com>
203 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
204 after each call to sim_io_write.
206 2007-02-19 Thiemo Seufer <ths@mips.com>
207 Nigel Stephens <nigel@mips.com>
209 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
210 supported by this simulator.
211 (decode_coproc): Recognise additional CP0 Config registers
214 2007-02-19 Thiemo Seufer <ths@mips.com>
215 Nigel Stephens <nigel@mips.com>
216 David Ung <davidu@mips.com>
218 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
219 uninterpreted formats. If fmt is one of the uninterpreted types
220 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
221 fmt_word, and fmt_uninterpreted_64 like fmt_long.
222 (store_fpr): When writing an invalid odd register, set the
223 matching even register to fmt_unknown, not the following register.
224 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
225 the the memory window at offset 0 set by --memory-size command
227 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
229 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
231 (sim_monitor): When returning the memory size to the MIPS
232 application, use the value in STATE_MEM_SIZE, not an arbitrary
234 (cop_lw): Don' mess around with FPR_STATE, just pass
235 fmt_uninterpreted_32 to StoreFPR.
237 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
239 * mips.igen (not_word_value): Single version for mips32, mips64
242 2007-02-19 Thiemo Seufer <ths@mips.com>
243 Nigel Stephens <nigel@mips.com>
245 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
248 2007-02-17 Thiemo Seufer <ths@mips.com>
250 * configure.ac (mips*-sde-elf*): Move in front of generic machine
252 * configure: Regenerate.
254 2007-02-17 Thiemo Seufer <ths@mips.com>
256 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
257 Add mdmx to sim_igen_machine.
258 (mipsisa64*-*-*): Likewise. Remove dsp.
259 (mipsisa32*-*-*): Remove dsp.
260 * configure: Regenerate.
262 2007-02-13 Thiemo Seufer <ths@mips.com>
264 * configure.ac: Add mips*-sde-elf* target.
265 * configure: Regenerate.
267 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
269 * acconfig.h: Remove.
270 * config.in, configure: Regenerate.
272 2006-11-07 Thiemo Seufer <ths@mips.com>
274 * dsp.igen (do_w_op): Fix compiler warning.
276 2006-08-29 Thiemo Seufer <ths@mips.com>
277 David Ung <davidu@mips.com>
279 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
281 * configure: Regenerate.
282 * mips.igen (model): Add smartmips.
283 (MADDU): Increment ACX if carry.
284 (do_mult): Clear ACX.
285 (ROR,RORV): Add smartmips.
286 (include): Include smartmips.igen.
287 * sim-main.h (ACX): Set to REGISTERS[89].
288 * smartmips.igen: New file.
290 2006-08-29 Thiemo Seufer <ths@mips.com>
291 David Ung <davidu@mips.com>
293 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
294 mips3264r2.igen. Add missing dependency rules.
295 * m16e.igen: Support for mips16e save/restore instructions.
297 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
299 * configure: Regenerated.
301 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
303 * configure: Regenerated.
305 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
307 * configure: Regenerated.
309 2006-05-15 Chao-ying Fu <fu@mips.com>
311 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
313 2006-04-18 Nick Clifton <nickc@redhat.com>
315 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
318 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
320 * configure: Regenerate.
322 2005-12-14 Chao-ying Fu <fu@mips.com>
324 * Makefile.in (SIM_OBJS): Add dsp.o.
325 (dsp.o): New dependency.
326 (IGEN_INCLUDE): Add dsp.igen.
327 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
328 mipsisa64*-*-*): Add dsp to sim_igen_machine.
329 * configure: Regenerate.
330 * mips.igen: Add dsp model and include dsp.igen.
331 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
332 because these instructions are extended in DSP ASE.
333 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
334 adding 6 DSP accumulator registers and 1 DSP control register.
335 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
336 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
337 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
338 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
339 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
340 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
341 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
342 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
343 DSPCR_CCOND_SMASK): New define.
344 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
345 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
347 2005-07-08 Ian Lance Taylor <ian@airs.com>
349 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
351 2005-06-16 David Ung <davidu@mips.com>
352 Nigel Stephens <nigel@mips.com>
354 * mips.igen: New mips16e model and include m16e.igen.
355 (check_u64): Add mips16e tag.
356 * m16e.igen: New file for MIPS16e instructions.
357 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
358 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
360 * configure: Regenerate.
362 2005-05-26 David Ung <davidu@mips.com>
364 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
365 tags to all instructions which are applicable to the new ISAs.
366 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
368 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
370 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
372 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
373 * configure: Regenerate.
375 2005-03-23 Mark Kettenis <kettenis@gnu.org>
377 * configure: Regenerate.
379 2005-01-14 Andrew Cagney <cagney@gnu.org>
381 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
382 explicit call to AC_CONFIG_HEADER.
383 * configure: Regenerate.
385 2005-01-12 Andrew Cagney <cagney@gnu.org>
387 * configure.ac: Update to use ../common/common.m4.
388 * configure: Re-generate.
390 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
392 * configure: Regenerated to track ../common/aclocal.m4 changes.
394 2005-01-07 Andrew Cagney <cagney@gnu.org>
396 * configure.ac: Rename configure.in, require autoconf 2.59.
397 * configure: Re-generate.
399 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
401 * configure: Regenerate for ../common/aclocal.m4 update.
403 2004-09-24 Monika Chaddha <monika@acmet.com>
405 Committed by Andrew Cagney.
406 * m16.igen (CMP, CMPI): Fix assembler.
408 2004-08-18 Chris Demetriou <cgd@broadcom.com>
410 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
411 * configure: Regenerate.
413 2004-06-25 Chris Demetriou <cgd@broadcom.com>
415 * configure.in (sim_m16_machine): Include mipsIII.
416 * configure: Regenerate.
418 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
420 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
422 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
424 2004-04-10 Chris Demetriou <cgd@broadcom.com>
426 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
428 2004-04-09 Chris Demetriou <cgd@broadcom.com>
430 * mips.igen (check_fmt): Remove.
431 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
432 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
433 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
434 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
435 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
436 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
437 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
438 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
439 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
440 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
442 2004-04-09 Chris Demetriou <cgd@broadcom.com>
444 * sb1.igen (check_sbx): New function.
445 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
447 2004-03-29 Chris Demetriou <cgd@broadcom.com>
448 Richard Sandiford <rsandifo@redhat.com>
450 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
451 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
452 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
453 separate implementations for mipsIV and mipsV. Use new macros to
454 determine whether the restrictions apply.
456 2004-01-19 Chris Demetriou <cgd@broadcom.com>
458 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
459 (check_mult_hilo): Improve comments.
460 (check_div_hilo): Likewise. Also, fork off a new version
461 to handle mips32/mips64 (since there are no hazards to check
464 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
466 * mips.igen (do_dmultx): Fix check for negative operands.
468 2003-05-16 Ian Lance Taylor <ian@airs.com>
470 * Makefile.in (SHELL): Make sure this is defined.
471 (various): Use $(SHELL) whenever we invoke move-if-change.
473 2003-05-03 Chris Demetriou <cgd@broadcom.com>
475 * cp1.c: Tweak attribution slightly.
478 * mdmx.igen: Likewise.
479 * mips3d.igen: Likewise.
480 * sb1.igen: Likewise.
482 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
484 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
487 2003-02-27 Andrew Cagney <cagney@redhat.com>
489 * interp.c (sim_open): Rename _bfd to bfd.
490 (sim_create_inferior): Ditto.
492 2003-01-14 Chris Demetriou <cgd@broadcom.com>
494 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
496 2003-01-14 Chris Demetriou <cgd@broadcom.com>
498 * mips.igen (EI, DI): Remove.
500 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
502 * Makefile.in (tmp-run-multi): Fix mips16 filter.
504 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
505 Andrew Cagney <ac131313@redhat.com>
506 Gavin Romig-Koch <gavin@redhat.com>
507 Graydon Hoare <graydon@redhat.com>
508 Aldy Hernandez <aldyh@redhat.com>
509 Dave Brolley <brolley@redhat.com>
510 Chris Demetriou <cgd@broadcom.com>
512 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
513 (sim_mach_default): New variable.
514 (mips64vr-*-*, mips64vrel-*-*): New configurations.
515 Add a new simulator generator, MULTI.
516 * configure: Regenerate.
517 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
518 (multi-run.o): New dependency.
519 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
520 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
521 (tmp-multi): Combine them.
522 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
523 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
524 (distclean-extra): New rule.
525 * sim-main.h: Include bfd.h.
526 (MIPS_MACH): New macro.
527 * mips.igen (vr4120, vr5400, vr5500): New models.
528 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
529 * vr.igen: Replace with new version.
531 2003-01-04 Chris Demetriou <cgd@broadcom.com>
533 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
534 * configure: Regenerate.
536 2002-12-31 Chris Demetriou <cgd@broadcom.com>
538 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
539 * mips.igen: Remove all invocations of check_branch_bug and
542 2002-12-16 Chris Demetriou <cgd@broadcom.com>
544 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
546 2002-07-30 Chris Demetriou <cgd@broadcom.com>
548 * mips.igen (do_load_double, do_store_double): New functions.
549 (LDC1, SDC1): Rename to...
550 (LDC1b, SDC1b): respectively.
551 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
553 2002-07-29 Michael Snyder <msnyder@redhat.com>
555 * cp1.c (fp_recip2): Modify initialization expression so that
556 GCC will recognize it as constant.
558 2002-06-18 Chris Demetriou <cgd@broadcom.com>
560 * mdmx.c (SD_): Delete.
561 (Unpredictable): Re-define, for now, to directly invoke
562 unpredictable_action().
563 (mdmx_acc_op): Fix error in .ob immediate handling.
565 2002-06-18 Andrew Cagney <cagney@redhat.com>
567 * interp.c (sim_firmware_command): Initialize `address'.
569 2002-06-16 Andrew Cagney <ac131313@redhat.com>
571 * configure: Regenerated to track ../common/aclocal.m4 changes.
573 2002-06-14 Chris Demetriou <cgd@broadcom.com>
574 Ed Satterthwaite <ehs@broadcom.com>
576 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
577 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
578 * mips.igen: Include mips3d.igen.
579 (mips3d): New model name for MIPS-3D ASE instructions.
580 (CVT.W.fmt): Don't use this instruction for word (source) format
582 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
583 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
584 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
585 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
586 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
587 (RSquareRoot1, RSquareRoot2): New macros.
588 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
589 (fp_rsqrt2): New functions.
590 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
591 * configure: Regenerate.
593 2002-06-13 Chris Demetriou <cgd@broadcom.com>
594 Ed Satterthwaite <ehs@broadcom.com>
596 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
597 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
598 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
599 (convert): Note that this function is not used for paired-single
601 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
602 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
603 (check_fmt_p): Enable paired-single support.
604 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
605 (PUU.PS): New instructions.
606 (CVT.S.fmt): Don't use this instruction for paired-single format
608 * sim-main.h (FP_formats): New value 'fmt_ps.'
609 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
610 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
612 2002-06-12 Chris Demetriou <cgd@broadcom.com>
614 * mips.igen: Fix formatting of function calls in
617 2002-06-12 Chris Demetriou <cgd@broadcom.com>
619 * mips.igen (MOVN, MOVZ): Trace result.
620 (TNEI): Print "tnei" as the opcode name in traces.
621 (CEIL.W): Add disassembly string for traces.
622 (RSQRT.fmt): Make location of disassembly string consistent
623 with other instructions.
625 2002-06-12 Chris Demetriou <cgd@broadcom.com>
627 * mips.igen (X): Delete unused function.
629 2002-06-08 Andrew Cagney <cagney@redhat.com>
631 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
633 2002-06-07 Chris Demetriou <cgd@broadcom.com>
634 Ed Satterthwaite <ehs@broadcom.com>
636 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
637 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
638 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
639 (fp_nmsub): New prototypes.
640 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
641 (NegMultiplySub): New defines.
642 * mips.igen (RSQRT.fmt): Use RSquareRoot().
643 (MADD.D, MADD.S): Replace with...
644 (MADD.fmt): New instruction.
645 (MSUB.D, MSUB.S): Replace with...
646 (MSUB.fmt): New instruction.
647 (NMADD.D, NMADD.S): Replace with...
648 (NMADD.fmt): New instruction.
649 (NMSUB.D, MSUB.S): Replace with...
650 (NMSUB.fmt): New instruction.
652 2002-06-07 Chris Demetriou <cgd@broadcom.com>
653 Ed Satterthwaite <ehs@broadcom.com>
655 * cp1.c: Fix more comment spelling and formatting.
656 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
657 (denorm_mode): New function.
658 (fpu_unary, fpu_binary): Round results after operation, collect
659 status from rounding operations, and update the FCSR.
660 (convert): Collect status from integer conversions and rounding
661 operations, and update the FCSR. Adjust NaN values that result
662 from conversions. Convert to use sim_io_eprintf rather than
663 fprintf, and remove some debugging code.
664 * cp1.h (fenr_FS): New define.
666 2002-06-07 Chris Demetriou <cgd@broadcom.com>
668 * cp1.c (convert): Remove unusable debugging code, and move MIPS
669 rounding mode to sim FP rounding mode flag conversion code into...
670 (rounding_mode): New function.
672 2002-06-07 Chris Demetriou <cgd@broadcom.com>
674 * cp1.c: Clean up formatting of a few comments.
675 (value_fpr): Reformat switch statement.
677 2002-06-06 Chris Demetriou <cgd@broadcom.com>
678 Ed Satterthwaite <ehs@broadcom.com>
681 * sim-main.h: Include cp1.h.
682 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
683 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
684 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
685 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
686 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
687 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
688 * cp1.c: Don't include sim-fpu.h; already included by
689 sim-main.h. Clean up formatting of some comments.
690 (NaN, Equal, Less): Remove.
691 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
692 (fp_cmp): New functions.
693 * mips.igen (do_c_cond_fmt): Remove.
694 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
695 Compare. Add result tracing.
696 (CxC1): Remove, replace with...
697 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
698 (DMxC1): Remove, replace with...
699 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
700 (MxC1): Remove, replace with...
701 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
703 2002-06-04 Chris Demetriou <cgd@broadcom.com>
705 * sim-main.h (FGRIDX): Remove, replace all uses with...
706 (FGR_BASE): New macro.
707 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
708 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
709 (NR_FGR, FGR): Likewise.
710 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
711 * mips.igen: Likewise.
713 2002-06-04 Chris Demetriou <cgd@broadcom.com>
715 * cp1.c: Add an FSF Copyright notice to this file.
717 2002-06-04 Chris Demetriou <cgd@broadcom.com>
718 Ed Satterthwaite <ehs@broadcom.com>
720 * cp1.c (Infinity): Remove.
721 * sim-main.h (Infinity): Likewise.
723 * cp1.c (fp_unary, fp_binary): New functions.
724 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
725 (fp_sqrt): New functions, implemented in terms of the above.
726 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
727 (Recip, SquareRoot): Remove (replaced by functions above).
728 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
729 (fp_recip, fp_sqrt): New prototypes.
730 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
731 (Recip, SquareRoot): Replace prototypes with #defines which
732 invoke the functions above.
734 2002-06-03 Chris Demetriou <cgd@broadcom.com>
736 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
737 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
738 file, remove PARAMS from prototypes.
739 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
740 simulator state arguments.
741 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
742 pass simulator state arguments.
743 * cp1.c (SD): Redefine as CPU_STATE(cpu).
744 (store_fpr, convert): Remove 'sd' argument.
745 (value_fpr): Likewise. Convert to use 'SD' instead.
747 2002-06-03 Chris Demetriou <cgd@broadcom.com>
749 * cp1.c (Min, Max): Remove #if 0'd functions.
750 * sim-main.h (Min, Max): Remove.
752 2002-06-03 Chris Demetriou <cgd@broadcom.com>
754 * cp1.c: fix formatting of switch case and default labels.
755 * interp.c: Likewise.
756 * sim-main.c: Likewise.
758 2002-06-03 Chris Demetriou <cgd@broadcom.com>
760 * cp1.c: Clean up comments which describe FP formats.
761 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
763 2002-06-03 Chris Demetriou <cgd@broadcom.com>
764 Ed Satterthwaite <ehs@broadcom.com>
766 * configure.in (mipsisa64sb1*-*-*): New target for supporting
767 Broadcom SiByte SB-1 processor configurations.
768 * configure: Regenerate.
769 * sb1.igen: New file.
770 * mips.igen: Include sb1.igen.
772 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
773 * mdmx.igen: Add "sb1" model to all appropriate functions and
775 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
776 (ob_func, ob_acc): Reference the above.
777 (qh_acc): Adjust to keep the same size as ob_acc.
778 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
779 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
781 2002-06-03 Chris Demetriou <cgd@broadcom.com>
783 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
785 2002-06-02 Chris Demetriou <cgd@broadcom.com>
786 Ed Satterthwaite <ehs@broadcom.com>
788 * mips.igen (mdmx): New (pseudo-)model.
789 * mdmx.c, mdmx.igen: New files.
790 * Makefile.in (SIM_OBJS): Add mdmx.o.
791 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
793 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
794 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
795 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
796 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
797 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
798 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
799 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
800 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
801 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
802 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
803 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
804 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
805 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
806 (qh_fmtsel): New macros.
807 (_sim_cpu): New member "acc".
808 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
809 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
811 2002-05-01 Chris Demetriou <cgd@broadcom.com>
813 * interp.c: Use 'deprecated' rather than 'depreciated.'
814 * sim-main.h: Likewise.
816 2002-05-01 Chris Demetriou <cgd@broadcom.com>
818 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
819 which wouldn't compile anyway.
820 * sim-main.h (unpredictable_action): New function prototype.
821 (Unpredictable): Define to call igen function unpredictable().
822 (NotWordValue): New macro to call igen function not_word_value().
823 (UndefinedResult): Remove.
824 * interp.c (undefined_result): Remove.
825 (unpredictable_action): New function.
826 * mips.igen (not_word_value, unpredictable): New functions.
827 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
828 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
829 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
830 NotWordValue() to check for unpredictable inputs, then
831 Unpredictable() to handle them.
833 2002-02-24 Chris Demetriou <cgd@broadcom.com>
835 * mips.igen: Fix formatting of calls to Unpredictable().
837 2002-04-20 Andrew Cagney <ac131313@redhat.com>
839 * interp.c (sim_open): Revert previous change.
841 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
843 * interp.c (sim_open): Disable chunk of code that wrote code in
844 vector table entries.
846 2002-03-19 Chris Demetriou <cgd@broadcom.com>
848 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
849 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
852 2002-03-19 Chris Demetriou <cgd@broadcom.com>
854 * cp1.c: Fix many formatting issues.
856 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
858 * cp1.c (fpu_format_name): New function to replace...
859 (DOFMT): This. Delete, and update all callers.
860 (fpu_rounding_mode_name): New function to replace...
861 (RMMODE): This. Delete, and update all callers.
863 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
865 * interp.c: Move FPU support routines from here to...
866 * cp1.c: Here. New file.
867 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
870 2002-03-12 Chris Demetriou <cgd@broadcom.com>
872 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
873 * mips.igen (mips32, mips64): New models, add to all instructions
874 and functions as appropriate.
875 (loadstore_ea, check_u64): New variant for model mips64.
876 (check_fmt_p): New variant for models mipsV and mips64, remove
877 mipsV model marking fro other variant.
880 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
881 for mips32 and mips64.
882 (DCLO, DCLZ): New instructions for mips64.
884 2002-03-07 Chris Demetriou <cgd@broadcom.com>
886 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
887 immediate or code as a hex value with the "%#lx" format.
888 (ANDI): Likewise, and fix printed instruction name.
890 2002-03-05 Chris Demetriou <cgd@broadcom.com>
892 * sim-main.h (UndefinedResult, Unpredictable): New macros
893 which currently do nothing.
895 2002-03-05 Chris Demetriou <cgd@broadcom.com>
897 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
898 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
899 (status_CU3): New definitions.
901 * sim-main.h (ExceptionCause): Add new values for MIPS32
902 and MIPS64: MDMX, MCheck, CacheErr. Update comments
903 for DebugBreakPoint and NMIReset to note their status in
905 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
906 (SignalExceptionCacheErr): New exception macros.
908 2002-03-05 Chris Demetriou <cgd@broadcom.com>
910 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
911 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
913 (SignalExceptionCoProcessorUnusable): Take as argument the
914 unusable coprocessor number.
916 2002-03-05 Chris Demetriou <cgd@broadcom.com>
918 * mips.igen: Fix formatting of all SignalException calls.
920 2002-03-05 Chris Demetriou <cgd@broadcom.com>
922 * sim-main.h (SIGNEXTEND): Remove.
924 2002-03-04 Chris Demetriou <cgd@broadcom.com>
926 * mips.igen: Remove gencode comment from top of file, fix
927 spelling in another comment.
929 2002-03-04 Chris Demetriou <cgd@broadcom.com>
931 * mips.igen (check_fmt, check_fmt_p): New functions to check
932 whether specific floating point formats are usable.
933 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
934 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
935 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
936 Use the new functions.
937 (do_c_cond_fmt): Remove format checks...
938 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
940 2002-03-03 Chris Demetriou <cgd@broadcom.com>
942 * mips.igen: Fix formatting of check_fpu calls.
944 2002-03-03 Chris Demetriou <cgd@broadcom.com>
946 * mips.igen (FLOOR.L.fmt): Store correct destination register.
948 2002-03-03 Chris Demetriou <cgd@broadcom.com>
950 * mips.igen: Remove whitespace at end of lines.
952 2002-03-02 Chris Demetriou <cgd@broadcom.com>
954 * mips.igen (loadstore_ea): New function to do effective
955 address calculations.
956 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
957 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
958 CACHE): Use loadstore_ea to do effective address computations.
960 2002-03-02 Chris Demetriou <cgd@broadcom.com>
962 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
963 * mips.igen (LL, CxC1, MxC1): Likewise.
965 2002-03-02 Chris Demetriou <cgd@broadcom.com>
967 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
968 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
969 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
970 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
971 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
972 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
973 Don't split opcode fields by hand, use the opcode field values
976 2002-03-01 Chris Demetriou <cgd@broadcom.com>
978 * mips.igen (do_divu): Fix spacing.
980 * mips.igen (do_dsllv): Move to be right before DSLLV,
981 to match the rest of the do_<shift> functions.
983 2002-03-01 Chris Demetriou <cgd@broadcom.com>
985 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
986 DSRL32, do_dsrlv): Trace inputs and results.
988 2002-03-01 Chris Demetriou <cgd@broadcom.com>
990 * mips.igen (CACHE): Provide instruction-printing string.
992 * interp.c (signal_exception): Comment tokens after #endif.
994 2002-02-28 Chris Demetriou <cgd@broadcom.com>
996 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
997 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
998 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
999 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1000 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1001 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1002 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1003 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1005 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1007 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1008 instruction-printing string.
1009 (LWU): Use '64' as the filter flag.
1011 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1013 * mips.igen (SDXC1): Fix instruction-printing string.
1015 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1017 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1018 filter flags "32,f".
1020 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1022 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1025 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1027 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1028 add a comma) so that it more closely match the MIPS ISA
1029 documentation opcode partitioning.
1030 (PREF): Put useful names on opcode fields, and include
1031 instruction-printing string.
1033 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1035 * mips.igen (check_u64): New function which in the future will
1036 check whether 64-bit instructions are usable and signal an
1037 exception if not. Currently a no-op.
1038 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1039 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1040 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1041 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1043 * mips.igen (check_fpu): New function which in the future will
1044 check whether FPU instructions are usable and signal an exception
1045 if not. Currently a no-op.
1046 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1047 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1048 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1049 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1050 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1051 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1052 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1053 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1055 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1057 * mips.igen (do_load_left, do_load_right): Move to be immediately
1059 (do_store_left, do_store_right): Move to be immediately following
1062 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1064 * mips.igen (mipsV): New model name. Also, add it to
1065 all instructions and functions where it is appropriate.
1067 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1069 * mips.igen: For all functions and instructions, list model
1070 names that support that instruction one per line.
1072 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1074 * mips.igen: Add some additional comments about supported
1075 models, and about which instructions go where.
1076 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1077 order as is used in the rest of the file.
1079 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1081 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1082 indicating that ALU32_END or ALU64_END are there to check
1084 (DADD): Likewise, but also remove previous comment about
1087 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1089 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1090 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1091 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1092 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1093 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1094 fields (i.e., add and move commas) so that they more closely
1095 match the MIPS ISA documentation opcode partitioning.
1097 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1099 * mips.igen (ADDI): Print immediate value.
1100 (BREAK): Print code.
1101 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1102 (SLL): Print "nop" specially, and don't run the code
1103 that does the shift for the "nop" case.
1105 2001-11-17 Fred Fish <fnf@redhat.com>
1107 * sim-main.h (float_operation): Move enum declaration outside
1108 of _sim_cpu struct declaration.
1110 2001-04-12 Jim Blandy <jimb@redhat.com>
1112 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1113 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1115 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1116 PENDING_FILL, and you can get the intended effect gracefully by
1117 calling PENDING_SCHED directly.
1119 2001-02-23 Ben Elliston <bje@redhat.com>
1121 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1122 already defined elsewhere.
1124 2001-02-19 Ben Elliston <bje@redhat.com>
1126 * sim-main.h (sim_monitor): Return an int.
1127 * interp.c (sim_monitor): Add return values.
1128 (signal_exception): Handle error conditions from sim_monitor.
1130 2001-02-08 Ben Elliston <bje@redhat.com>
1132 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1133 (store_memory): Likewise, pass cia to sim_core_write*.
1135 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1137 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1138 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1140 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1142 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1143 * Makefile.in: Don't delete *.igen when cleaning directory.
1145 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1147 * m16.igen (break): Call SignalException not sim_engine_halt.
1149 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1151 From Jason Eckhardt:
1152 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1154 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1156 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1158 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1160 * mips.igen (do_dmultx): Fix typo.
1162 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1164 * configure: Regenerated to track ../common/aclocal.m4 changes.
1166 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1168 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1170 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1172 * sim-main.h (GPR_CLEAR): Define macro.
1174 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1176 * interp.c (decode_coproc): Output long using %lx and not %s.
1178 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1180 * interp.c (sim_open): Sort & extend dummy memory regions for
1181 --board=jmr3904 for eCos.
1183 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1185 * configure: Regenerated.
1187 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1189 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1190 calls, conditional on the simulator being in verbose mode.
1192 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1194 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1195 cache don't get ReservedInstruction traps.
1197 1999-11-29 Mark Salter <msalter@cygnus.com>
1199 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1200 to clear status bits in sdisr register. This is how the hardware works.
1202 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1203 being used by cygmon.
1205 1999-11-11 Andrew Haley <aph@cygnus.com>
1207 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1210 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1212 * mips.igen (MULT): Correct previous mis-applied patch.
1214 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1216 * mips.igen (delayslot32): Handle sequence like
1217 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1218 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1219 (MULT): Actually pass the third register...
1221 1999-09-03 Mark Salter <msalter@cygnus.com>
1223 * interp.c (sim_open): Added more memory aliases for additional
1224 hardware being touched by cygmon on jmr3904 board.
1226 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1228 * configure: Regenerated to track ../common/aclocal.m4 changes.
1230 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1232 * interp.c (sim_store_register): Handle case where client - GDB -
1233 specifies that a 4 byte register is 8 bytes in size.
1234 (sim_fetch_register): Ditto.
1236 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1238 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1239 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1240 (idt_monitor_base): Base address for IDT monitor traps.
1241 (pmon_monitor_base): Ditto for PMON.
1242 (lsipmon_monitor_base): Ditto for LSI PMON.
1243 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1244 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1245 (sim_firmware_command): New function.
1246 (mips_option_handler): Call it for OPTION_FIRMWARE.
1247 (sim_open): Allocate memory for idt_monitor region. If "--board"
1248 option was given, add no monitor by default. Add BREAK hooks only if
1249 monitors are also there.
1251 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1253 * interp.c (sim_monitor): Flush output before reading input.
1255 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1257 * tconfig.in (SIM_HANDLES_LMA): Always define.
1259 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1261 From Mark Salter <msalter@cygnus.com>:
1262 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1263 (sim_open): Add setup for BSP board.
1265 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1267 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1268 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1269 them as unimplemented.
1271 1999-05-08 Felix Lee <flee@cygnus.com>
1273 * configure: Regenerated to track ../common/aclocal.m4 changes.
1275 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1277 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1279 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1281 * configure.in: Any mips64vr5*-*-* target should have
1282 -DTARGET_ENABLE_FR=1.
1283 (default_endian): Any mips64vr*el-*-* target should default to
1285 * configure: Re-generate.
1287 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1289 * mips.igen (ldl): Extend from _16_, not 32.
1291 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1293 * interp.c (sim_store_register): Force registers written to by GDB
1294 into an un-interpreted state.
1296 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1298 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1299 CPU, start periodic background I/O polls.
1300 (tx3904sio_poll): New function: periodic I/O poller.
1302 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1304 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1306 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1308 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1311 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1313 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1314 (load_word): Call SIM_CORE_SIGNAL hook on error.
1315 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1316 starting. For exception dispatching, pass PC instead of NULL_CIA.
1317 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1318 * sim-main.h (COP0_BADVADDR): Define.
1319 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1320 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1321 (_sim_cpu): Add exc_* fields to store register value snapshots.
1322 * mips.igen (*): Replace memory-related SignalException* calls
1323 with references to SIM_CORE_SIGNAL hook.
1325 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1327 * sim-main.c (*): Minor warning cleanups.
1329 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1331 * m16.igen (DADDIU5): Correct type-o.
1333 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1335 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1338 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1340 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1342 (interp.o): Add dependency on itable.h
1343 (oengine.c, gencode): Delete remaining references.
1344 (BUILT_SRC_FROM_GEN): Clean up.
1346 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1349 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1350 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1351 tmp-run-hack) : New.
1352 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1353 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1354 Drop the "64" qualifier to get the HACK generator working.
1355 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1356 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1357 qualifier to get the hack generator working.
1358 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1359 (DSLL): Use do_dsll.
1360 (DSLLV): Use do_dsllv.
1361 (DSRA): Use do_dsra.
1362 (DSRL): Use do_dsrl.
1363 (DSRLV): Use do_dsrlv.
1364 (BC1): Move *vr4100 to get the HACK generator working.
1365 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1366 get the HACK generator working.
1367 (MACC) Rename to get the HACK generator working.
1368 (DMACC,MACCS,DMACCS): Add the 64.
1370 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1372 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1373 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1375 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1377 * mips/interp.c (DEBUG): Cleanups.
1379 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1381 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1382 (tx3904sio_tickle): fflush after a stdout character output.
1384 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1386 * interp.c (sim_close): Uninstall modules.
1388 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1390 * sim-main.h, interp.c (sim_monitor): Change to global
1393 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1395 * configure.in (vr4100): Only include vr4100 instructions in
1397 * configure: Re-generate.
1398 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1400 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1402 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1403 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1406 * configure.in (sim_default_gen, sim_use_gen): Replace with
1408 (--enable-sim-igen): Delete config option. Always using IGEN.
1409 * configure: Re-generate.
1411 * Makefile.in (gencode): Kill, kill, kill.
1414 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1416 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1417 bit mips16 igen simulator.
1418 * configure: Re-generate.
1420 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1421 as part of vr4100 ISA.
1422 * vr.igen: Mark all instructions as 64 bit only.
1424 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1426 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1429 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1431 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1432 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1433 * configure: Re-generate.
1435 * m16.igen (BREAK): Define breakpoint instruction.
1436 (JALX32): Mark instruction as mips16 and not r3900.
1437 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1439 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1441 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1444 insn as a debug breakpoint.
1446 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1448 (PENDING_SCHED): Clean up trace statement.
1449 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1450 (PENDING_FILL): Delay write by only one cycle.
1451 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1453 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1455 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1457 (pending_tick): Move incrementing of index to FOR statement.
1458 (pending_tick): Only update PENDING_OUT after a write has occured.
1460 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1462 * configure: Re-generate.
1464 * interp.c (sim_engine_run OLD): Delete explicit call to
1465 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1467 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1469 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1470 interrupt level number to match changed SignalExceptionInterrupt
1473 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1475 * interp.c: #include "itable.h" if WITH_IGEN.
1476 (get_insn_name): New function.
1477 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1478 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1480 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1482 * configure: Rebuilt to inhale new common/aclocal.m4.
1484 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1486 * dv-tx3904sio.c: Include sim-assert.h.
1488 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1490 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1491 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1492 Reorganize target-specific sim-hardware checks.
1493 * configure: rebuilt.
1494 * interp.c (sim_open): For tx39 target boards, set
1495 OPERATING_ENVIRONMENT, add tx3904sio devices.
1496 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1497 ROM executables. Install dv-sockser into sim-modules list.
1499 * dv-tx3904irc.c: Compiler warning clean-up.
1500 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1501 frequent hw-trace messages.
1503 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1505 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1507 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1509 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1511 * vr.igen: New file.
1512 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1513 * mips.igen: Define vr4100 model. Include vr.igen.
1514 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1516 * mips.igen (check_mf_hilo): Correct check.
1518 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1520 * sim-main.h (interrupt_event): Add prototype.
1522 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1523 register_ptr, register_value.
1524 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1526 * sim-main.h (tracefh): Make extern.
1528 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1530 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1531 Reduce unnecessarily high timer event frequency.
1532 * dv-tx3904cpu.c: Ditto for interrupt event.
1534 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1536 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1538 (interrupt_event): Made non-static.
1540 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1541 interchange of configuration values for external vs. internal
1544 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1546 * mips.igen (BREAK): Moved code to here for
1547 simulator-reserved break instructions.
1548 * gencode.c (build_instruction): Ditto.
1549 * interp.c (signal_exception): Code moved from here. Non-
1550 reserved instructions now use exception vector, rather
1552 * sim-main.h: Moved magic constants to here.
1554 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1556 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1557 register upon non-zero interrupt event level, clear upon zero
1559 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1560 by passing zero event value.
1561 (*_io_{read,write}_buffer): Endianness fixes.
1562 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1563 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1565 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1566 serial I/O and timer module at base address 0xFFFF0000.
1568 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1570 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1573 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1575 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1577 * configure: Update.
1579 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1581 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1582 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1583 * configure.in: Include tx3904tmr in hw_device list.
1584 * configure: Rebuilt.
1585 * interp.c (sim_open): Instantiate three timer instances.
1586 Fix address typo of tx3904irc instance.
1588 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1590 * interp.c (signal_exception): SystemCall exception now uses
1591 the exception vector.
1593 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1595 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1598 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1600 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1602 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1604 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1606 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1607 sim-main.h. Declare a struct hw_descriptor instead of struct
1608 hw_device_descriptor.
1610 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1612 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1613 right bits and then re-align left hand bytes to correct byte
1614 lanes. Fix incorrect computation in do_store_left when loading
1615 bytes from second word.
1617 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1619 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1620 * interp.c (sim_open): Only create a device tree when HW is
1623 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1624 * interp.c (signal_exception): Ditto.
1626 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1628 * gencode.c: Mark BEGEZALL as LIKELY.
1630 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1632 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1633 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1635 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1637 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1638 modules. Recognize TX39 target with "mips*tx39" pattern.
1639 * configure: Rebuilt.
1640 * sim-main.h (*): Added many macros defining bits in
1641 TX39 control registers.
1642 (SignalInterrupt): Send actual PC instead of NULL.
1643 (SignalNMIReset): New exception type.
1644 * interp.c (board): New variable for future use to identify
1645 a particular board being simulated.
1646 (mips_option_handler,mips_options): Added "--board" option.
1647 (interrupt_event): Send actual PC.
1648 (sim_open): Make memory layout conditional on board setting.
1649 (signal_exception): Initial implementation of hardware interrupt
1650 handling. Accept another break instruction variant for simulator
1652 (decode_coproc): Implement RFE instruction for TX39.
1653 (mips.igen): Decode RFE instruction as such.
1654 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1655 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1656 bbegin to implement memory map.
1657 * dv-tx3904cpu.c: New file.
1658 * dv-tx3904irc.c: New file.
1660 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1662 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1664 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1666 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1667 with calls to check_div_hilo.
1669 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1671 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1672 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1673 Add special r3900 version of do_mult_hilo.
1674 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1675 with calls to check_mult_hilo.
1676 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1677 with calls to check_div_hilo.
1679 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1681 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1682 Document a replacement.
1684 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1686 * interp.c (sim_monitor): Make mon_printf work.
1688 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1690 * sim-main.h (INSN_NAME): New arg `cpu'.
1692 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1694 * configure: Regenerated to track ../common/aclocal.m4 changes.
1696 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1698 * configure: Regenerated to track ../common/aclocal.m4 changes.
1701 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1703 * acconfig.h: New file.
1704 * configure.in: Reverted change of Apr 24; use sinclude again.
1706 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1708 * configure: Regenerated to track ../common/aclocal.m4 changes.
1711 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1713 * configure.in: Don't call sinclude.
1715 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1717 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1719 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1721 * mips.igen (ERET): Implement.
1723 * interp.c (decode_coproc): Return sign-extended EPC.
1725 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1727 * interp.c (signal_exception): Do not ignore Trap.
1728 (signal_exception): On TRAP, restart at exception address.
1729 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1730 (signal_exception): Update.
1731 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1732 so that TRAP instructions are caught.
1734 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1736 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1737 contains HI/LO access history.
1738 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1739 (HIACCESS, LOACCESS): Delete, replace with
1740 (HIHISTORY, LOHISTORY): New macros.
1741 (CHECKHILO): Delete all, moved to mips.igen
1743 * gencode.c (build_instruction): Do not generate checks for
1744 correct HI/LO register usage.
1746 * interp.c (old_engine_run): Delete checks for correct HI/LO
1749 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1750 check_mf_cycles): New functions.
1751 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1752 do_divu, domultx, do_mult, do_multu): Use.
1754 * tx.igen ("madd", "maddu"): Use.
1756 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1758 * mips.igen (DSRAV): Use function do_dsrav.
1759 (SRAV): Use new function do_srav.
1761 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1762 (B): Sign extend 11 bit immediate.
1763 (EXT-B*): Shift 16 bit immediate left by 1.
1764 (ADDIU*): Don't sign extend immediate value.
1766 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1768 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1770 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1773 * mips.igen (delayslot32, nullify_next_insn): New functions.
1774 (m16.igen): Always include.
1775 (do_*): Add more tracing.
1777 * m16.igen (delayslot16): Add NIA argument, could be called by a
1778 32 bit MIPS16 instruction.
1780 * interp.c (ifetch16): Move function from here.
1781 * sim-main.c (ifetch16): To here.
1783 * sim-main.c (ifetch16, ifetch32): Update to match current
1784 implementations of LH, LW.
1785 (signal_exception): Don't print out incorrect hex value of illegal
1788 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1790 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1793 * m16.igen: Implement MIPS16 instructions.
1795 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1796 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1797 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1798 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1799 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1800 bodies of corresponding code from 32 bit insn to these. Also used
1801 by MIPS16 versions of functions.
1803 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1804 (IMEM16): Drop NR argument from macro.
1806 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1808 * Makefile.in (SIM_OBJS): Add sim-main.o.
1810 * sim-main.h (address_translation, load_memory, store_memory,
1811 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1813 (pr_addr, pr_uword64): Declare.
1814 (sim-main.c): Include when H_REVEALS_MODULE_P.
1816 * interp.c (address_translation, load_memory, store_memory,
1817 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1819 * sim-main.c: To here. Fix compilation problems.
1821 * configure.in: Enable inlining.
1822 * configure: Re-config.
1824 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1826 * configure: Regenerated to track ../common/aclocal.m4 changes.
1828 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1830 * mips.igen: Include tx.igen.
1831 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1832 * tx.igen: New file, contains MADD and MADDU.
1834 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1835 the hardwired constant `7'.
1836 (store_memory): Ditto.
1837 (LOADDRMASK): Move definition to sim-main.h.
1839 mips.igen (MTC0): Enable for r3900.
1842 mips.igen (do_load_byte): Delete.
1843 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1844 do_store_right): New functions.
1845 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1847 configure.in: Let the tx39 use igen again.
1850 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1852 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1853 not an address sized quantity. Return zero for cache sizes.
1855 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1857 * mips.igen (r3900): r3900 does not support 64 bit integer
1860 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1862 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1864 * configure : Rebuild.
1866 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868 * configure: Regenerated to track ../common/aclocal.m4 changes.
1870 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1872 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1874 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1876 * configure: Regenerated to track ../common/aclocal.m4 changes.
1877 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1879 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881 * configure: Regenerated to track ../common/aclocal.m4 changes.
1883 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1885 * interp.c (Max, Min): Comment out functions. Not yet used.
1887 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1889 * configure: Regenerated to track ../common/aclocal.m4 changes.
1891 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1893 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1894 configurable settings for stand-alone simulator.
1896 * configure.in: Added X11 search, just in case.
1898 * configure: Regenerated.
1900 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1902 * interp.c (sim_write, sim_read, load_memory, store_memory):
1903 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1905 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1907 * sim-main.h (GETFCC): Return an unsigned value.
1909 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1912 (DADD): Result destination is RD not RT.
1914 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1916 * sim-main.h (HIACCESS, LOACCESS): Always define.
1918 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1920 * interp.c (sim_info): Delete.
1922 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1924 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1925 (mips_option_handler): New argument `cpu'.
1926 (sim_open): Update call to sim_add_option_table.
1928 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1930 * mips.igen (CxC1): Add tracing.
1932 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1934 * sim-main.h (Max, Min): Declare.
1936 * interp.c (Max, Min): New functions.
1938 * mips.igen (BC1): Add tracing.
1940 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1942 * interp.c Added memory map for stack in vr4100
1944 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1946 * interp.c (load_memory): Add missing "break"'s.
1948 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1950 * interp.c (sim_store_register, sim_fetch_register): Pass in
1951 length parameter. Return -1.
1953 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1955 * interp.c: Added hardware init hook, fixed warnings.
1957 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1959 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1961 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1963 * interp.c (ifetch16): New function.
1965 * sim-main.h (IMEM32): Rename IMEM.
1966 (IMEM16_IMMED): Define.
1968 (DELAY_SLOT): Update.
1970 * m16run.c (sim_engine_run): New file.
1972 * m16.igen: All instructions except LB.
1973 (LB): Call do_load_byte.
1974 * mips.igen (do_load_byte): New function.
1975 (LB): Call do_load_byte.
1977 * mips.igen: Move spec for insn bit size and high bit from here.
1978 * Makefile.in (tmp-igen, tmp-m16): To here.
1980 * m16.dc: New file, decode mips16 instructions.
1982 * Makefile.in (SIM_NO_ALL): Define.
1983 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1985 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1988 point unit to 32 bit registers.
1989 * configure: Re-generate.
1991 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1993 * configure.in (sim_use_gen): Make IGEN the default simulator
1994 generator for generic 32 and 64 bit mips targets.
1995 * configure: Re-generate.
1997 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1999 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2002 * interp.c (sim_fetch_register, sim_store_register): Read/write
2003 FGR from correct location.
2004 (sim_open): Set size of FGR's according to
2005 WITH_TARGET_FLOATING_POINT_BITSIZE.
2007 * sim-main.h (FGR): Store floating point registers in a separate
2010 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2012 * configure: Regenerated to track ../common/aclocal.m4 changes.
2014 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2016 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2018 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2020 * interp.c (pending_tick): New function. Deliver pending writes.
2022 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2023 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2024 it can handle mixed sized quantites and single bits.
2026 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2028 * interp.c (oengine.h): Do not include when building with IGEN.
2029 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2030 (sim_info): Ditto for PROCESSOR_64BIT.
2031 (sim_monitor): Replace ut_reg with unsigned_word.
2032 (*): Ditto for t_reg.
2033 (LOADDRMASK): Define.
2034 (sim_open): Remove defunct check that host FP is IEEE compliant,
2035 using software to emulate floating point.
2036 (value_fpr, ...): Always compile, was conditional on HASFPU.
2038 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2040 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2043 * interp.c (SD, CPU): Define.
2044 (mips_option_handler): Set flags in each CPU.
2045 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2046 (sim_close): Do not clear STATE, deleted anyway.
2047 (sim_write, sim_read): Assume CPU zero's vm should be used for
2049 (sim_create_inferior): Set the PC for all processors.
2050 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2052 (mips16_entry): Pass correct nr of args to store_word, load_word.
2053 (ColdReset): Cold reset all cpu's.
2054 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2055 (sim_monitor, load_memory, store_memory, signal_exception): Use
2056 `CPU' instead of STATE_CPU.
2059 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2062 * sim-main.h (signal_exception): Add sim_cpu arg.
2063 (SignalException*): Pass both SD and CPU to signal_exception.
2064 * interp.c (signal_exception): Update.
2066 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2068 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2069 address_translation): Ditto
2070 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2072 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2074 * configure: Regenerated to track ../common/aclocal.m4 changes.
2076 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2078 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2080 * mips.igen (model): Map processor names onto BFD name.
2082 * sim-main.h (CPU_CIA): Delete.
2083 (SET_CIA, GET_CIA): Define
2085 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2087 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2090 * configure.in (default_endian): Configure a big-endian simulator
2092 * configure: Re-generate.
2094 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2096 * configure: Regenerated to track ../common/aclocal.m4 changes.
2098 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2100 * interp.c (sim_monitor): Handle Densan monitor outbyte
2101 and inbyte functions.
2103 1997-12-29 Felix Lee <flee@cygnus.com>
2105 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2107 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2109 * Makefile.in (tmp-igen): Arrange for $zero to always be
2110 reset to zero after every instruction.
2112 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2114 * configure: Regenerated to track ../common/aclocal.m4 changes.
2117 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2119 * mips.igen (MSUB): Fix to work like MADD.
2120 * gencode.c (MSUB): Similarly.
2122 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2124 * configure: Regenerated to track ../common/aclocal.m4 changes.
2126 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2128 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2130 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132 * sim-main.h (sim-fpu.h): Include.
2134 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2135 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2136 using host independant sim_fpu module.
2138 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2140 * interp.c (signal_exception): Report internal errors with SIGABRT
2143 * sim-main.h (C0_CONFIG): New register.
2144 (signal.h): No longer include.
2146 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2148 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2150 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2152 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2154 * mips.igen: Tag vr5000 instructions.
2155 (ANDI): Was missing mipsIV model, fix assembler syntax.
2156 (do_c_cond_fmt): New function.
2157 (C.cond.fmt): Handle mips I-III which do not support CC field
2159 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2160 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2162 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2163 vr5000 which saves LO in a GPR separatly.
2165 * configure.in (enable-sim-igen): For vr5000, select vr5000
2166 specific instructions.
2167 * configure: Re-generate.
2169 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2171 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2173 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2174 fmt_uninterpreted_64 bit cases to switch. Convert to
2177 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2179 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2180 as specified in IV3.2 spec.
2181 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2183 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2186 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2187 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2188 PENDING_FILL versions of instructions. Simplify.
2190 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2192 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2194 (MTHI, MFHI): Disable code checking HI-LO.
2196 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2198 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2200 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2202 * gencode.c (build_mips16_operands): Replace IPC with cia.
2204 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2205 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2207 (UndefinedResult): Replace function with macro/function
2209 (sim_engine_run): Don't save PC in IPC.
2211 * sim-main.h (IPC): Delete.
2214 * interp.c (signal_exception, store_word, load_word,
2215 address_translation, load_memory, store_memory, cache_op,
2216 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2217 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2218 current instruction address - cia - argument.
2219 (sim_read, sim_write): Call address_translation directly.
2220 (sim_engine_run): Rename variable vaddr to cia.
2221 (signal_exception): Pass cia to sim_monitor
2223 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2224 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2225 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2227 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2228 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2231 * interp.c (signal_exception): Pass restart address to
2234 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2235 idecode.o): Add dependency.
2237 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2239 (DELAY_SLOT): Update NIA not PC with branch address.
2240 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2242 * mips.igen: Use CIA not PC in branch calculations.
2243 (illegal): Call SignalException.
2244 (BEQ, ADDIU): Fix assembler.
2246 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2248 * m16.igen (JALX): Was missing.
2250 * configure.in (enable-sim-igen): New configuration option.
2251 * configure: Re-generate.
2253 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2255 * interp.c (load_memory, store_memory): Delete parameter RAW.
2256 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2257 bypassing {load,store}_memory.
2259 * sim-main.h (ByteSwapMem): Delete definition.
2261 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2263 * interp.c (sim_do_command, sim_commands): Delete mips specific
2264 commands. Handled by module sim-options.
2266 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2267 (WITH_MODULO_MEMORY): Define.
2269 * interp.c (sim_info): Delete code printing memory size.
2271 * interp.c (mips_size): Nee sim_size, delete function.
2273 (monitor, monitor_base, monitor_size): Delete global variables.
2274 (sim_open, sim_close): Delete code creating monitor and other
2275 memory regions. Use sim-memopts module, via sim_do_commandf, to
2276 manage memory regions.
2277 (load_memory, store_memory): Use sim-core for memory model.
2279 * interp.c (address_translation): Delete all memory map code
2280 except line forcing 32 bit addresses.
2282 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2284 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2287 * interp.c (logfh, logfile): Delete globals.
2288 (sim_open, sim_close): Delete code opening & closing log file.
2289 (mips_option_handler): Delete -l and -n options.
2290 (OPTION mips_options): Ditto.
2292 * interp.c (OPTION mips_options): Rename option trace to dinero.
2293 (mips_option_handler): Update.
2295 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2297 * interp.c (fetch_str): New function.
2298 (sim_monitor): Rewrite using sim_read & sim_write.
2299 (sim_open): Check magic number.
2300 (sim_open): Write monitor vectors into memory using sim_write.
2301 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2302 (sim_read, sim_write): Simplify - transfer data one byte at a
2304 (load_memory, store_memory): Clarify meaning of parameter RAW.
2306 * sim-main.h (isHOST): Defete definition.
2307 (isTARGET): Mark as depreciated.
2308 (address_translation): Delete parameter HOST.
2310 * interp.c (address_translation): Delete parameter HOST.
2312 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2316 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2317 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2319 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2321 * mips.igen: Add model filter field to records.
2323 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2325 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2327 interp.c (sim_engine_run): Do not compile function sim_engine_run
2328 when WITH_IGEN == 1.
2330 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2331 target architecture.
2333 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2334 igen. Replace with configuration variables sim_igen_flags /
2337 * m16.igen: New file. Copy mips16 insns here.
2338 * mips.igen: From here.
2340 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2342 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2344 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2346 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2348 * gencode.c (build_instruction): Follow sim_write's lead in using
2349 BigEndianMem instead of !ByteSwapMem.
2351 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2353 * configure.in (sim_gen): Dependent on target, select type of
2354 generator. Always select old style generator.
2356 configure: Re-generate.
2358 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2360 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2361 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2362 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2363 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2364 SIM_@sim_gen@_*, set by autoconf.
2366 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2368 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2370 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2371 CURRENT_FLOATING_POINT instead.
2373 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2374 (address_translation): Raise exception InstructionFetch when
2375 translation fails and isINSTRUCTION.
2377 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2378 sim_engine_run): Change type of of vaddr and paddr to
2380 (address_translation, prefetch, load_memory, store_memory,
2381 cache_op): Change type of vAddr and pAddr to address_word.
2383 * gencode.c (build_instruction): Change type of vaddr and paddr to
2386 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2388 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2389 macro to obtain result of ALU op.
2391 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2393 * interp.c (sim_info): Call profile_print.
2395 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2397 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2399 * sim-main.h (WITH_PROFILE): Do not define, defined in
2400 common/sim-config.h. Use sim-profile module.
2401 (simPROFILE): Delete defintion.
2403 * interp.c (PROFILE): Delete definition.
2404 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2405 (sim_close): Delete code writing profile histogram.
2406 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2408 (sim_engine_run): Delete code profiling the PC.
2410 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2412 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2414 * interp.c (sim_monitor): Make register pointers of type
2417 * sim-main.h: Make registers of type unsigned_word not
2420 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2422 * interp.c (sync_operation): Rename from SyncOperation, make
2423 global, add SD argument.
2424 (prefetch): Rename from Prefetch, make global, add SD argument.
2425 (decode_coproc): Make global.
2427 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2429 * gencode.c (build_instruction): Generate DecodeCoproc not
2430 decode_coproc calls.
2432 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2433 (SizeFGR): Move to sim-main.h
2434 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2435 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2436 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2438 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2439 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2440 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2441 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2442 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2443 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2445 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2447 (sim-alu.h): Include.
2448 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2449 (sim_cia): Typedef to instruction_address.
2451 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2453 * Makefile.in (interp.o): Rename generated file engine.c to
2458 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2460 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2462 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2464 * gencode.c (build_instruction): For "FPSQRT", output correct
2465 number of arguments to Recip.
2467 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2469 * Makefile.in (interp.o): Depends on sim-main.h
2471 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2473 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2474 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2475 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2476 STATE, DSSTATE): Define
2477 (GPR, FGRIDX, ..): Define.
2479 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2480 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2481 (GPR, FGRIDX, ...): Delete macros.
2483 * interp.c: Update names to match defines from sim-main.h
2485 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2487 * interp.c (sim_monitor): Add SD argument.
2488 (sim_warning): Delete. Replace calls with calls to
2490 (sim_error): Delete. Replace calls with sim_io_error.
2491 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2492 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2493 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2495 (mips_size): Rename from sim_size. Add SD argument.
2497 * interp.c (simulator): Delete global variable.
2498 (callback): Delete global variable.
2499 (mips_option_handler, sim_open, sim_write, sim_read,
2500 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2501 sim_size,sim_monitor): Use sim_io_* not callback->*.
2502 (sim_open): ZALLOC simulator struct.
2503 (PROFILE): Do not define.
2505 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2507 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2508 support.h with corresponding code.
2510 * sim-main.h (word64, uword64), support.h: Move definition to
2512 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2515 * Makefile.in: Update dependencies
2516 * interp.c: Do not include.
2518 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2520 * interp.c (address_translation, load_memory, store_memory,
2521 cache_op): Rename to from AddressTranslation et.al., make global,
2524 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2527 * interp.c (SignalException): Rename to signal_exception, make
2530 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2532 * sim-main.h (SignalException, SignalExceptionInterrupt,
2533 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2534 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2535 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2538 * interp.c, support.h: Use.
2540 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2542 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2543 to value_fpr / store_fpr. Add SD argument.
2544 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2545 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2547 * sim-main.h (ValueFPR, StoreFPR): Define.
2549 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2551 * interp.c (sim_engine_run): Check consistency between configure
2552 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2555 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2556 (mips_fpu): Configure WITH_FLOATING_POINT.
2557 (mips_endian): Configure WITH_TARGET_ENDIAN.
2558 * configure: Update.
2560 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562 * configure: Regenerated to track ../common/aclocal.m4 changes.
2564 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2566 * configure: Regenerated.
2568 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2570 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2572 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2574 * gencode.c (print_igen_insn_models): Assume certain architectures
2575 include all mips* instructions.
2576 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2579 * Makefile.in (tmp.igen): Add target. Generate igen input from
2582 * gencode.c (FEATURE_IGEN): Define.
2583 (main): Add --igen option. Generate output in igen format.
2584 (process_instructions): Format output according to igen option.
2585 (print_igen_insn_format): New function.
2586 (print_igen_insn_models): New function.
2587 (process_instructions): Only issue warnings and ignore
2588 instructions when no FEATURE_IGEN.
2590 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2592 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2595 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2597 * configure: Regenerated to track ../common/aclocal.m4 changes.
2599 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2601 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2602 SIM_RESERVED_BITS): Delete, moved to common.
2603 (SIM_EXTRA_CFLAGS): Update.
2605 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2607 * configure.in: Configure non-strict memory alignment.
2608 * configure: Regenerated to track ../common/aclocal.m4 changes.
2610 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2612 * configure: Regenerated to track ../common/aclocal.m4 changes.
2614 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2616 * gencode.c (SDBBP,DERET): Added (3900) insns.
2617 (RFE): Turn on for 3900.
2618 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2619 (dsstate): Made global.
2620 (SUBTARGET_R3900): Added.
2621 (CANCELDELAYSLOT): New.
2622 (SignalException): Ignore SystemCall rather than ignore and
2623 terminate. Add DebugBreakPoint handling.
2624 (decode_coproc): New insns RFE, DERET; and new registers Debug
2625 and DEPC protected by SUBTARGET_R3900.
2626 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2628 * Makefile.in,configure.in: Add mips subtarget option.
2629 * configure: Update.
2631 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2633 * gencode.c: Add r3900 (tx39).
2636 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2638 * gencode.c (build_instruction): Don't need to subtract 4 for
2641 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2643 * interp.c: Correct some HASFPU problems.
2645 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2647 * configure: Regenerated to track ../common/aclocal.m4 changes.
2649 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2651 * interp.c (mips_options): Fix samples option short form, should
2654 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2656 * interp.c (sim_info): Enable info code. Was just returning.
2658 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2660 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2663 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2665 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2667 (build_instruction): Ditto for LL.
2669 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2671 * configure: Regenerated to track ../common/aclocal.m4 changes.
2673 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2675 * configure: Regenerated to track ../common/aclocal.m4 changes.
2678 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2680 * interp.c (sim_open): Add call to sim_analyze_program, update
2683 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2685 * interp.c (sim_kill): Delete.
2686 (sim_create_inferior): Add ABFD argument. Set PC from same.
2687 (sim_load): Move code initializing trap handlers from here.
2688 (sim_open): To here.
2689 (sim_load): Delete, use sim-hload.c.
2691 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2693 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2695 * configure: Regenerated to track ../common/aclocal.m4 changes.
2698 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2700 * interp.c (sim_open): Add ABFD argument.
2701 (sim_load): Move call to sim_config from here.
2702 (sim_open): To here. Check return status.
2704 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2706 * gencode.c (build_instruction): Two arg MADD should
2707 not assign result to $0.
2709 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2711 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2712 * sim/mips/configure.in: Regenerate.
2714 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2716 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2717 signed8, unsigned8 et.al. types.
2719 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2720 hosts when selecting subreg.
2722 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2724 * interp.c (sim_engine_run): Reset the ZERO register to zero
2725 regardless of FEATURE_WARN_ZERO.
2726 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2728 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2730 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2731 (SignalException): For BreakPoints ignore any mode bits and just
2733 (SignalException): Always set the CAUSE register.
2735 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2737 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2738 exception has been taken.
2740 * interp.c: Implement the ERET and mt/f sr instructions.
2742 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2744 * interp.c (SignalException): Don't bother restarting an
2747 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2749 * interp.c (SignalException): Really take an interrupt.
2750 (interrupt_event): Only deliver interrupts when enabled.
2752 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2754 * interp.c (sim_info): Only print info when verbose.
2755 (sim_info) Use sim_io_printf for output.
2757 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2759 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2762 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2764 * interp.c (sim_do_command): Check for common commands if a
2765 simulator specific command fails.
2767 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2769 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2770 and simBE when DEBUG is defined.
2772 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2774 * interp.c (interrupt_event): New function. Pass exception event
2775 onto exception handler.
2777 * configure.in: Check for stdlib.h.
2778 * configure: Regenerate.
2780 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2781 variable declaration.
2782 (build_instruction): Initialize memval1.
2783 (build_instruction): Add UNUSED attribute to byte, bigend,
2785 (build_operands): Ditto.
2787 * interp.c: Fix GCC warnings.
2788 (sim_get_quit_code): Delete.
2790 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2791 * Makefile.in: Ditto.
2792 * configure: Re-generate.
2794 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2796 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2798 * interp.c (mips_option_handler): New function parse argumes using
2800 (myname): Replace with STATE_MY_NAME.
2801 (sim_open): Delete check for host endianness - performed by
2803 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2804 (sim_open): Move much of the initialization from here.
2805 (sim_load): To here. After the image has been loaded and
2807 (sim_open): Move ColdReset from here.
2808 (sim_create_inferior): To here.
2809 (sim_open): Make FP check less dependant on host endianness.
2811 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2813 * interp.c (sim_set_callbacks): Delete.
2815 * interp.c (membank, membank_base, membank_size): Replace with
2816 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2817 (sim_open): Remove call to callback->init. gdb/run do this.
2821 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2823 * interp.c (big_endian_p): Delete, replaced by
2824 current_target_byte_order.
2826 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2828 * interp.c (host_read_long, host_read_word, host_swap_word,
2829 host_swap_long): Delete. Using common sim-endian.
2830 (sim_fetch_register, sim_store_register): Use H2T.
2831 (pipeline_ticks): Delete. Handled by sim-events.
2833 (sim_engine_run): Update.
2835 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2837 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2839 (SignalException): To here. Signal using sim_engine_halt.
2840 (sim_stop_reason): Delete, moved to common.
2842 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2844 * interp.c (sim_open): Add callback argument.
2845 (sim_set_callbacks): Delete SIM_DESC argument.
2848 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2850 * Makefile.in (SIM_OBJS): Add common modules.
2852 * interp.c (sim_set_callbacks): Also set SD callback.
2853 (set_endianness, xfer_*, swap_*): Delete.
2854 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2855 Change to functions using sim-endian macros.
2856 (control_c, sim_stop): Delete, use common version.
2857 (simulate): Convert into.
2858 (sim_engine_run): This function.
2859 (sim_resume): Delete.
2861 * interp.c (simulation): New variable - the simulator object.
2862 (sim_kind): Delete global - merged into simulation.
2863 (sim_load): Cleanup. Move PC assignment from here.
2864 (sim_create_inferior): To here.
2866 * sim-main.h: New file.
2867 * interp.c (sim-main.h): Include.
2869 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2871 * configure: Regenerated to track ../common/aclocal.m4 changes.
2873 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2875 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2877 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2879 * gencode.c (build_instruction): DIV instructions: check
2880 for division by zero and integer overflow before using
2881 host's division operation.
2883 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2885 * Makefile.in (SIM_OBJS): Add sim-load.o.
2886 * interp.c: #include bfd.h.
2887 (target_byte_order): Delete.
2888 (sim_kind, myname, big_endian_p): New static locals.
2889 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2890 after argument parsing. Recognize -E arg, set endianness accordingly.
2891 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2892 load file into simulator. Set PC from bfd.
2893 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2894 (set_endianness): Use big_endian_p instead of target_byte_order.
2896 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2898 * interp.c (sim_size): Delete prototype - conflicts with
2899 definition in remote-sim.h. Correct definition.
2901 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2903 * configure: Regenerated to track ../common/aclocal.m4 changes.
2906 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2908 * interp.c (sim_open): New arg `kind'.
2910 * configure: Regenerated to track ../common/aclocal.m4 changes.
2912 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2914 * configure: Regenerated to track ../common/aclocal.m4 changes.
2916 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2918 * interp.c (sim_open): Set optind to 0 before calling getopt.
2920 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2922 * configure: Regenerated to track ../common/aclocal.m4 changes.
2924 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2926 * interp.c : Replace uses of pr_addr with pr_uword64
2927 where the bit length is always 64 independent of SIM_ADDR.
2928 (pr_uword64) : added.
2930 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2932 * configure: Re-generate.
2934 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2936 * configure: Regenerate to track ../common/aclocal.m4 changes.
2938 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2940 * interp.c (sim_open): New SIM_DESC result. Argument is now
2942 (other sim_*): New SIM_DESC argument.
2944 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2946 * interp.c: Fix printing of addresses for non-64-bit targets.
2947 (pr_addr): Add function to print address based on size.
2949 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2951 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2953 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2955 * gencode.c (build_mips16_operands): Correct computation of base
2956 address for extended PC relative instruction.
2958 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2960 * interp.c (mips16_entry): Add support for floating point cases.
2961 (SignalException): Pass floating point cases to mips16_entry.
2962 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2964 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2966 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2967 and then set the state to fmt_uninterpreted.
2968 (COP_SW): Temporarily set the state to fmt_word while calling
2971 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2973 * gencode.c (build_instruction): The high order may be set in the
2974 comparison flags at any ISA level, not just ISA 4.
2976 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2978 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2979 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2980 * configure.in: sinclude ../common/aclocal.m4.
2981 * configure: Regenerated.
2983 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2985 * configure: Rebuild after change to aclocal.m4.
2987 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2989 * configure configure.in Makefile.in: Update to new configure
2990 scheme which is more compatible with WinGDB builds.
2991 * configure.in: Improve comment on how to run autoconf.
2992 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2993 * Makefile.in: Use autoconf substitution to install common
2996 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2998 * gencode.c (build_instruction): Use BigEndianCPU instead of
3001 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3003 * interp.c (sim_monitor): Make output to stdout visible in
3004 wingdb's I/O log window.
3006 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3008 * support.h: Undo previous change to SIGTRAP
3011 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3013 * interp.c (store_word, load_word): New static functions.
3014 (mips16_entry): New static function.
3015 (SignalException): Look for mips16 entry and exit instructions.
3016 (simulate): Use the correct index when setting fpr_state after
3017 doing a pending move.
3019 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3021 * interp.c: Fix byte-swapping code throughout to work on
3022 both little- and big-endian hosts.
3024 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3026 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3027 with gdb/config/i386/xm-windows.h.
3029 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3031 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3032 that messes up arithmetic shifts.
3034 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3036 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3037 SIGTRAP and SIGQUIT for _WIN32.
3039 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3041 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3042 force a 64 bit multiplication.
3043 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3044 destination register is 0, since that is the default mips16 nop
3047 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3049 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3050 (build_endian_shift): Don't check proc64.
3051 (build_instruction): Always set memval to uword64. Cast op2 to
3052 uword64 when shifting it left in memory instructions. Always use
3053 the same code for stores--don't special case proc64.
3055 * gencode.c (build_mips16_operands): Fix base PC value for PC
3057 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3059 * interp.c (simJALDELAYSLOT): Define.
3060 (JALDELAYSLOT): Define.
3061 (INDELAYSLOT, INJALDELAYSLOT): Define.
3062 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3064 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3066 * interp.c (sim_open): add flush_cache as a PMON routine
3067 (sim_monitor): handle flush_cache by ignoring it
3069 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3071 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3073 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3074 (BigEndianMem): Rename to ByteSwapMem and change sense.
3075 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3076 BigEndianMem references to !ByteSwapMem.
3077 (set_endianness): New function, with prototype.
3078 (sim_open): Call set_endianness.
3079 (sim_info): Use simBE instead of BigEndianMem.
3080 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3081 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3082 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3083 ifdefs, keeping the prototype declaration.
3084 (swap_word): Rewrite correctly.
3085 (ColdReset): Delete references to CONFIG. Delete endianness related
3086 code; moved to set_endianness.
3088 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3090 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3091 * interp.c (CHECKHILO): Define away.
3092 (simSIGINT): New macro.
3093 (membank_size): Increase from 1MB to 2MB.
3094 (control_c): New function.
3095 (sim_resume): Rename parameter signal to signal_number. Add local
3096 variable prev. Call signal before and after simulate.
3097 (sim_stop_reason): Add simSIGINT support.
3098 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3100 (sim_warning): Delete call to SignalException. Do call printf_filtered
3102 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3103 a call to sim_warning.
3105 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3107 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3108 16 bit instructions.
3110 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3112 Add support for mips16 (16 bit MIPS implementation):
3113 * gencode.c (inst_type): Add mips16 instruction encoding types.
3114 (GETDATASIZEINSN): Define.
3115 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3116 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3118 (MIPS16_DECODE): New table, for mips16 instructions.
3119 (bitmap_val): New static function.
3120 (struct mips16_op): Define.
3121 (mips16_op_table): New table, for mips16 operands.
3122 (build_mips16_operands): New static function.
3123 (process_instructions): If PC is odd, decode a mips16
3124 instruction. Break out instruction handling into new
3125 build_instruction function.
3126 (build_instruction): New static function, broken out of
3127 process_instructions. Check modifiers rather than flags for SHIFT
3128 bit count and m[ft]{hi,lo} direction.
3129 (usage): Pass program name to fprintf.
3130 (main): Remove unused variable this_option_optind. Change
3131 ``*loptarg++'' to ``loptarg++''.
3132 (my_strtoul): Parenthesize && within ||.
3133 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3134 (simulate): If PC is odd, fetch a 16 bit instruction, and
3135 increment PC by 2 rather than 4.
3136 * configure.in: Add case for mips16*-*-*.
3137 * configure: Rebuild.
3139 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3141 * interp.c: Allow -t to enable tracing in standalone simulator.
3142 Fix garbage output in trace file and error messages.
3144 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3146 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3147 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3148 * configure.in: Simplify using macros in ../common/aclocal.m4.
3149 * configure: Regenerated.
3150 * tconfig.in: New file.
3152 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3154 * interp.c: Fix bugs in 64-bit port.
3155 Use ansi function declarations for msvc compiler.
3156 Initialize and test file pointer in trace code.
3157 Prevent duplicate definition of LAST_EMED_REGNUM.
3159 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3161 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3163 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3165 * interp.c (SignalException): Check for explicit terminating
3167 * gencode.c: Pass instruction value through SignalException()
3168 calls for Trap, Breakpoint and Syscall.
3170 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3172 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3173 only used on those hosts that provide it.
3174 * configure.in: Add sqrt() to list of functions to be checked for.
3175 * config.in: Re-generated.
3176 * configure: Re-generated.
3178 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3180 * gencode.c (process_instructions): Call build_endian_shift when
3181 expanding STORE RIGHT, to fix swr.
3182 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3183 clear the high bits.
3184 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3185 Fix float to int conversions to produce signed values.
3187 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3189 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3190 (process_instructions): Correct handling of nor instruction.
3191 Correct shift count for 32 bit shift instructions. Correct sign
3192 extension for arithmetic shifts to not shift the number of bits in
3193 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3194 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3196 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3197 It's OK to have a mult follow a mult. What's not OK is to have a
3198 mult follow an mfhi.
3199 (Convert): Comment out incorrect rounding code.
3201 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3203 * interp.c (sim_monitor): Improved monitor printf
3204 simulation. Tidied up simulator warnings, and added "--log" option
3205 for directing warning message output.
3206 * gencode.c: Use sim_warning() rather than WARNING macro.
3208 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3210 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3211 getopt1.o, rather than on gencode.c. Link objects together.
3212 Don't link against -liberty.
3213 (gencode.o, getopt.o, getopt1.o): New targets.
3214 * gencode.c: Include <ctype.h> and "ansidecl.h".
3215 (AND): Undefine after including "ansidecl.h".
3216 (ULONG_MAX): Define if not defined.
3217 (OP_*): Don't define macros; now defined in opcode/mips.h.
3218 (main): Call my_strtoul rather than strtoul.
3219 (my_strtoul): New static function.
3221 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3223 * gencode.c (process_instructions): Generate word64 and uword64
3224 instead of `long long' and `unsigned long long' data types.
3225 * interp.c: #include sysdep.h to get signals, and define default
3227 * (Convert): Work around for Visual-C++ compiler bug with type
3229 * support.h: Make things compile under Visual-C++ by using
3230 __int64 instead of `long long'. Change many refs to long long
3231 into word64/uword64 typedefs.
3233 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3235 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3236 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3238 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3239 (AC_PROG_INSTALL): Added.
3240 (AC_PROG_CC): Moved to before configure.host call.
3241 * configure: Rebuilt.
3243 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3245 * configure.in: Define @SIMCONF@ depending on mips target.
3246 * configure: Rebuild.
3247 * Makefile.in (run): Add @SIMCONF@ to control simulator
3249 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3250 * interp.c: Remove some debugging, provide more detailed error
3251 messages, update memory accesses to use LOADDRMASK.
3253 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3255 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3256 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3258 * configure: Rebuild.
3259 * config.in: New file, generated by autoheader.
3260 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3261 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3262 HAVE_ANINT and HAVE_AINT, as appropriate.
3263 * Makefile.in (run): Use @LIBS@ rather than -lm.
3264 (interp.o): Depend upon config.h.
3265 (Makefile): Just rebuild Makefile.
3266 (clean): Remove stamp-h.
3267 (mostlyclean): Make the same as clean, not as distclean.
3268 (config.h, stamp-h): New targets.
3270 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3272 * interp.c (ColdReset): Fix boolean test. Make all simulator
3275 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3277 * interp.c (xfer_direct_word, xfer_direct_long,
3278 swap_direct_word, swap_direct_long, xfer_big_word,
3279 xfer_big_long, xfer_little_word, xfer_little_long,
3280 swap_word,swap_long): Added.
3281 * interp.c (ColdReset): Provide function indirection to
3282 host<->simulated_target transfer routines.
3283 * interp.c (sim_store_register, sim_fetch_register): Updated to
3284 make use of indirected transfer routines.
3286 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3288 * gencode.c (process_instructions): Ensure FP ABS instruction
3290 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3291 system call support.
3293 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3295 * interp.c (sim_do_command): Complain if callback structure not
3298 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3300 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3301 support for Sun hosts.
3302 * Makefile.in (gencode): Ensure the host compiler and libraries
3303 used for cross-hosted build.
3305 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3307 * interp.c, gencode.c: Some more (TODO) tidying.
3309 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3311 * gencode.c, interp.c: Replaced explicit long long references with
3312 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3313 * support.h (SET64LO, SET64HI): Macros added.
3315 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3317 * configure: Regenerate with autoconf 2.7.
3319 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3321 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3322 * support.h: Remove superfluous "1" from #if.
3323 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3325 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3327 * interp.c (StoreFPR): Control UndefinedResult() call on
3328 WARN_RESULT manifest.
3330 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3332 * gencode.c: Tidied instruction decoding, and added FP instruction
3335 * interp.c: Added dineroIII, and BSD profiling support. Also
3336 run-time FP handling.
3338 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3340 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3341 gencode.c, interp.c, support.h: created.