sim/mips/ChangeLog

   1 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
   4         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
   5         file, remove PARAMS from prototypes.
   6         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
   7         simulator state arguments.
   8         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
   9         pass simulator state arguments.
  10         * cp1.c (SD): Redefine as CPU_STATE(cpu).
  11         (store_fpr, convert): Remove 'sd' argument.
  12         (value_fpr): Likewise.  Convert to use 'SD' instead.
  13
  14 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
  15
  16         * cp1.c (Min, Max): Remove #if 0'd functions.
  17         * sim-main.h (Min, Max): Remove.
  18
  19 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
  20
  21         * cp1.c: fix formatting of switch case and default labels.
  22         * interp.c: Likewise.
  23         * sim-main.c: Likewise.
  24
  25 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
  26
  27         * cp1.c: Clean up comments which describe FP formats.
  28          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
  29
  30 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
  31             Ed Satterthwaite  <ehs@broadcom.com>
  32
  33         * configure.in (mipsisa64sb1*-*-*): New target for supporting
  34         Broadcom SiByte SB-1 processor configurations.
  35         * configure: Regenerate.
  36         * sb1.igen: New file.
  37         * mips.igen: Include sb1.igen.
  38         (sb1): New model.
  39         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
  40         * mdmx.igen: Add "sb1" model to all appropriate functions and
  41         instructions.
  42         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
  43         (ob_func, ob_acc): Reference the above.
  44         (qh_acc): Adjust to keep the same size as ob_acc.
  45         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
  46         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
  47
  48 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
  49
  50         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
  51
  52 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
  53             Ed Satterthwaite  <ehs@broadcom.com>
  54
  55         * mips.igen (mdmx): New (pseudo-)model.
  56         * mdmx.c, mdmx.igen: New files.
  57         * Makefile.in (SIM_OBJS): Add mdmx.o.
  58         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
  59         New typedefs.
  60         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
  61         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
  62         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
  63         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
  64         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
  65         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
  66         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
  67         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
  68         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
  69         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
  70         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
  71         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
  72         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
  73         (qh_fmtsel): New macros.
  74         (_sim_cpu): New member "acc".
  75         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
  76         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
  77
  78 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
  79
  80         * interp.c: Use 'deprecated' rather than 'depreciated.'
  81         * sim-main.h: Likewise.
  82
  83 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
  84
  85         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
  86         which wouldn't compile anyway.
  87         * sim-main.h (unpredictable_action): New function prototype.
  88         (Unpredictable): Define to call igen function unpredictable().
  89         (NotWordValue): New macro to call igen function not_word_value().
  90         (UndefinedResult): Remove.
  91         * interp.c (undefined_result): Remove.
  92         (unpredictable_action): New function.
  93         * mips.igen (not_word_value, unpredictable): New functions.
  94         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
  95         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
  96         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
  97         NotWordValue() to check for unpredictable inputs, then
  98         Unpredictable() to handle them.
  99
 100 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 101
 102         * mips.igen: Fix formatting of calls to Unpredictable().
 103
 104 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 105
 106         * interp.c (sim_open): Revert previous change.
 107
 108 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 109
 110         * interp.c (sim_open): Disable chunk of code that wrote code in
 111         vector table entries.
 112
 113 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 114
 115         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 116         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 117         unused definitions.
 118
 119 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 120
 121         * cp1.c: Fix many formatting issues.
 122
 123 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 124
 125         * cp1.c (fpu_format_name): New function to replace...
 126         (DOFMT): This.  Delete, and update all callers.
 127         (fpu_rounding_mode_name): New function to replace...
 128         (RMMODE): This.  Delete, and update all callers.
 129
 130 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 131
 132         * interp.c: Move FPU support routines from here to...
 133         * cp1.c: Here.  New file.
 134         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 135         (cp1.o): New target.
 136
 137 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 138
 139         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 140         * mips.igen (mips32, mips64): New models, add to all instructions
 141         and functions as appropriate.
 142         (loadstore_ea, check_u64): New variant for model mips64.
 143         (check_fmt_p): New variant for models mipsV and mips64, remove
 144         mipsV model marking fro other variant.
 145         (SLL) Rename to...
 146         (SLLa) this.
 147         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 148         for mips32 and mips64.
 149         (DCLO, DCLZ): New instructions for mips64.
 150
 151 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 152
 153         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 154         immediate or code as a hex value with the "%#lx" format.
 155         (ANDI): Likewise, and fix printed instruction name.
 156
 157 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 158
 159         * sim-main.h (UndefinedResult, Unpredictable): New macros
 160         which currently do nothing.
 161
 162 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 163
 164         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 165         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 166         (status_CU3): New definitions.
 167
 168         * sim-main.h (ExceptionCause): Add new values for MIPS32
 169         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 170         for DebugBreakPoint and NMIReset to note their status in
 171         MIPS32 and MIPS64.
 172         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 173         (SignalExceptionCacheErr): New exception macros.
 174
 175 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 176
 177         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 178         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 179         is always enabled.
 180         (SignalExceptionCoProcessorUnusable): Take as argument the
 181         unusable coprocessor number.
 182
 183 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 184
 185         * mips.igen: Fix formatting of all SignalException calls.
 186
 187 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 188
 189         * sim-main.h (SIGNEXTEND): Remove.
 190
 191 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 192
 193         * mips.igen: Remove gencode comment from top of file, fix
 194         spelling in another comment.
 195
 196 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 197
 198         * mips.igen (check_fmt, check_fmt_p): New functions to check
 199         whether specific floating point formats are usable.
 200         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 201         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 202         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 203         Use the new functions.
 204         (do_c_cond_fmt): Remove format checks...
 205         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 206
 207 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 208
 209         * mips.igen: Fix formatting of check_fpu calls.
 210
 211 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 212
 213         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 214
 215 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 216
 217         * mips.igen: Remove whitespace at end of lines.
 218
 219 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 220
 221         * mips.igen (loadstore_ea): New function to do effective
 222         address calculations.
 223         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 224         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 225         CACHE): Use loadstore_ea to do effective address computations.
 226
 227 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 228
 229         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 230         * mips.igen (LL, CxC1, MxC1): Likewise.
 231
 232 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 233
 234         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 235         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 236         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 237         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 238         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 239         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 240         Don't split opcode fields by hand, use the opcode field values
 241         provided by igen.
 242
 243 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 244
 245         * mips.igen (do_divu): Fix spacing.
 246
 247         * mips.igen (do_dsllv): Move to be right before DSLLV,
 248         to match the rest of the do_<shift> functions.
 249
 250 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 251
 252         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 253         DSRL32, do_dsrlv): Trace inputs and results.
 254
 255 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 256
 257         * mips.igen (CACHE): Provide instruction-printing string.
 258
 259         * interp.c (signal_exception): Comment tokens after #endif.
 260
 261 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 262
 263         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 264         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 265         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 266         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 267         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 268         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 269         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 270         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 271
 272 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 273
 274         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 275         instruction-printing string.
 276         (LWU): Use '64' as the filter flag.
 277
 278 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 279
 280         * mips.igen (SDXC1): Fix instruction-printing string.
 281
 282 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 283
 284         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 285         filter flags "32,f".
 286
 287 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 288
 289         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 290         as the filter flag.
 291
 292 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 293
 294         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 295         add a comma) so that it more closely match the MIPS ISA
 296         documentation opcode partitioning.
 297         (PREF): Put useful names on opcode fields, and include
 298         instruction-printing string.
 299
 300 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 301
 302         * mips.igen (check_u64): New function which in the future will
 303         check whether 64-bit instructions are usable and signal an
 304         exception if not.  Currently a no-op.
 305         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 306         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 307         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 308         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 309
 310         * mips.igen (check_fpu): New function which in the future will
 311         check whether FPU instructions are usable and signal an exception
 312         if not.  Currently a no-op.
 313         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 314         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 315         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 316         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 317         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 318         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 319         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 320         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 321
 322 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 323
 324         * mips.igen (do_load_left, do_load_right): Move to be immediately
 325         following do_load.
 326         (do_store_left, do_store_right): Move to be immediately following
 327         do_store.
 328
 329 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 330
 331         * mips.igen (mipsV): New model name.  Also, add it to
 332         all instructions and functions where it is appropriate.
 333
 334 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 335
 336         * mips.igen: For all functions and instructions, list model
 337         names that support that instruction one per line.
 338
 339 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 340
 341         * mips.igen: Add some additional comments about supported
 342         models, and about which instructions go where.
 343         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 344         order as is used in the rest of the file.
 345
 346 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 347
 348         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 349         indicating that ALU32_END or ALU64_END are there to check
 350         for overflow.
 351         (DADD): Likewise, but also remove previous comment about
 352         overflow checking.
 353
 354 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 355
 356         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 357         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 358         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 359         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 360         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 361         fields (i.e., add and move commas) so that they more closely
 362         match the MIPS ISA documentation opcode partitioning.
 363
 364 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 365
 366         * mips.igen (ADDI): Print immediate value.
 367         (BREAK): Print code.
 368         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 369         (SLL): Print "nop" specially, and don't run the code
 370         that does the shift for the "nop" case.
 371
 372 2001-11-17  Fred Fish  <fnf@redhat.com>
 373
 374         * sim-main.h (float_operation): Move enum declaration outside
 375         of _sim_cpu struct declaration.
 376
 377 2001-04-12  Jim Blandy  <jimb@redhat.com>
 378
 379         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 380         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 381         set of the FCSR.
 382         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 383         PENDING_FILL, and you can get the intended effect gracefully by
 384         calling PENDING_SCHED directly.
 385
 386 2001-02-23  Ben Elliston  <bje@redhat.com>
 387
 388         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 389         already defined elsewhere.
 390
 391 2001-02-19  Ben Elliston  <bje@redhat.com>
 392
 393         * sim-main.h (sim_monitor): Return an int.
 394         * interp.c (sim_monitor): Add return values.
 395         (signal_exception): Handle error conditions from sim_monitor.
 396
 397 2001-02-08  Ben Elliston  <bje@redhat.com>
 398
 399         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 400         (store_memory): Likewise, pass cia to sim_core_write*.
 401
 402 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 403
 404         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 405         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 406
 407 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 408
 409         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 410         * Makefile.in: Don't delete *.igen when cleaning directory.
 411
 412 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 413
 414         * m16.igen (break): Call SignalException not sim_engine_halt.
 415
 416 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 417
 418         From Jason Eckhardt:
 419         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 420
 421 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 422
 423         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 424
 425 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 426
 427         * mips.igen (do_dmultx): Fix typo.
 428
 429 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 430
 431         * configure: Regenerated to track ../common/aclocal.m4 changes.
 432
 433 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 434
 435         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 436
 437 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 438
 439         * sim-main.h (GPR_CLEAR): Define macro.
 440
 441 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 442
 443         * interp.c (decode_coproc): Output long using %lx and not %s.
 444
 445 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 446
 447         * interp.c (sim_open): Sort & extend dummy memory regions for
 448         --board=jmr3904 for eCos.
 449
 450 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 451
 452         * configure: Regenerated.
 453
 454 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 455
 456         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 457         calls, conditional on the simulator being in verbose mode.
 458
 459 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 460
 461         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 462         cache don't get ReservedInstruction traps.
 463
 464 1999-11-29  Mark Salter  <msalter@cygnus.com>
 465
 466         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 467         to clear status bits in sdisr register. This is how the hardware works.
 468
 469         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 470         being used by cygmon.
 471
 472 1999-11-11  Andrew Haley  <aph@cygnus.com>
 473
 474         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 475         instructions.
 476
 477 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 478
 479         * mips.igen (MULT): Correct previous mis-applied patch.
 480
 481 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 482
 483         * mips.igen (delayslot32): Handle sequence like
 484         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 485         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 486         (MULT): Actually pass the third register...
 487
 488 1999-09-03  Mark Salter  <msalter@cygnus.com>
 489
 490         * interp.c (sim_open): Added more memory aliases for additional
 491         hardware being touched by cygmon on jmr3904 board.
 492
 493 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 494
 495         * configure: Regenerated to track ../common/aclocal.m4 changes.
 496
 497 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 498
 499         * interp.c (sim_store_register): Handle case where client - GDB -
 500         specifies that a 4 byte register is 8 bytes in size.
 501         (sim_fetch_register): Ditto.
 502
 503 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 504
 505         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 506         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 507         (idt_monitor_base): Base address for IDT monitor traps.
 508         (pmon_monitor_base): Ditto for PMON.
 509         (lsipmon_monitor_base): Ditto for LSI PMON.
 510         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 511         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 512         (sim_firmware_command): New function.
 513         (mips_option_handler): Call it for OPTION_FIRMWARE.
 514         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 515         option was given, add no monitor by default.  Add BREAK hooks only if
 516         monitors are also there.
 517
 518 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 519
 520         * interp.c (sim_monitor): Flush output before reading input.
 521
 522 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 523
 524         * tconfig.in (SIM_HANDLES_LMA): Always define.
 525
 526 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 527
 528         From Mark Salter <msalter@cygnus.com>:
 529         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 530         (sim_open): Add setup for BSP board.
 531
 532 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 533
 534         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 535         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 536         them as unimplemented.
 537
 538 1999-05-08  Felix Lee  <flee@cygnus.com>
 539
 540         * configure: Regenerated to track ../common/aclocal.m4 changes.
 541
 542 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 543
 544         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 545
 546 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 547
 548         * configure.in: Any mips64vr5*-*-* target should have
 549         -DTARGET_ENABLE_FR=1.
 550         (default_endian): Any mips64vr*el-*-* target should default to
 551         LITTLE_ENDIAN.
 552         * configure: Re-generate.
 553
 554 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 555
 556         * mips.igen (ldl): Extend from _16_, not 32.
 557
 558 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 559
 560         * interp.c (sim_store_register): Force registers written to by GDB
 561         into an un-interpreted state.
 562
 563 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 564
 565         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 566         CPU, start periodic background I/O polls.
 567         (tx3904sio_poll): New function: periodic I/O poller.
 568
 569 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 570
 571         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 572
 573 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 574
 575         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 576         case statement.
 577
 578 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 579
 580         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 581         (load_word): Call SIM_CORE_SIGNAL hook on error.
 582         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 583         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 584         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 585         * sim-main.h (COP0_BADVADDR): Define.
 586         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 587         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 588         (_sim_cpu): Add exc_* fields to store register value snapshots.
 589         * mips.igen (*): Replace memory-related SignalException* calls
 590         with references to SIM_CORE_SIGNAL hook.
 591
 592         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 593         fix.
 594         * sim-main.c (*): Minor warning cleanups.
 595
 596 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 597
 598         * m16.igen (DADDIU5): Correct type-o.
 599
 600 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 601
 602         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 603         variables.
 604
 605 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 606
 607         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 608         to include path.
 609         (interp.o): Add dependency on itable.h
 610         (oengine.c, gencode): Delete remaining references.
 611         (BUILT_SRC_FROM_GEN): Clean up.
 612
 613 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 614
 615         * vr4run.c: New.
 616         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 617         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 618         tmp-run-hack) : New.
 619         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 620         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 621         Drop the "64" qualifier to get the HACK generator working.
 622         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 623         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 624         qualifier to get the hack generator working.
 625         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 626         (DSLL): Use do_dsll.
 627         (DSLLV): Use do_dsllv.
 628         (DSRA): Use do_dsra.
 629         (DSRL): Use do_dsrl.
 630         (DSRLV): Use do_dsrlv.
 631         (BC1): Move *vr4100 to get the HACK generator working.
 632         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 633         get the HACK generator working.
 634         (MACC) Rename to get the HACK generator working.
 635         (DMACC,MACCS,DMACCS): Add the 64.
 636
 637 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 638
 639         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 640         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 641
 642 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 643
 644     * mips/interp.c (DEBUG): Cleanups.
 645
 646 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 647
 648         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 649         (tx3904sio_tickle): fflush after a stdout character output.
 650
 651 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 652
 653         * interp.c (sim_close): Uninstall modules.
 654
 655 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 656
 657         * sim-main.h, interp.c (sim_monitor): Change to global
 658         function.
 659
 660 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 661
 662         * configure.in (vr4100): Only include vr4100 instructions in
 663         simulator.
 664         * configure: Re-generate.
 665         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 666
 667 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 668
 669         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 670         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 671         true alternative.
 672
 673         * configure.in (sim_default_gen, sim_use_gen): Replace with
 674         sim_gen.
 675         (--enable-sim-igen): Delete config option. Always using IGEN.
 676         * configure: Re-generate.
 677
 678         * Makefile.in (gencode): Kill, kill, kill.
 679         * gencode.c: Ditto.
 680
 681 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 682
 683         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 684         bit mips16 igen simulator.
 685         * configure: Re-generate.
 686
 687         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 688         as part of vr4100 ISA.
 689         * vr.igen: Mark all instructions as 64 bit only.
 690
 691 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 692
 693         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 694         Pacify GCC.
 695
 696 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 697
 698         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 699         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 700         * configure: Re-generate.
 701
 702         * m16.igen (BREAK): Define breakpoint instruction.
 703         (JALX32): Mark instruction as mips16 and not r3900.
 704         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 705
 706         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 707
 708 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 709
 710         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 711         insn as a debug breakpoint.
 712
 713         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 714         pending.slot_size.
 715         (PENDING_SCHED): Clean up trace statement.
 716         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 717         (PENDING_FILL): Delay write by only one cycle.
 718         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 719
 720         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 721         of pending writes.
 722         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 723         32 & 64.
 724         (pending_tick): Move incrementing of index to FOR statement.
 725         (pending_tick): Only update PENDING_OUT after a write has occured.
 726
 727         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 728         build simulator.
 729         * configure: Re-generate.
 730
 731         * interp.c (sim_engine_run OLD): Delete explicit call to
 732         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 733
 734 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 735
 736         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 737         interrupt level number to match changed SignalExceptionInterrupt
 738         macro.
 739
 740 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 741
 742         * interp.c: #include "itable.h" if WITH_IGEN.
 743         (get_insn_name): New function.
 744         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 745         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 746
 747 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 748
 749         * configure: Rebuilt to inhale new common/aclocal.m4.
 750
 751 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 752
 753         * dv-tx3904sio.c: Include sim-assert.h.
 754
 755 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 756
 757         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 758         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 759         Reorganize target-specific sim-hardware checks.
 760         * configure: rebuilt.
 761         * interp.c (sim_open): For tx39 target boards, set
 762         OPERATING_ENVIRONMENT, add tx3904sio devices.
 763         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 764         ROM executables.  Install dv-sockser into sim-modules list.
 765
 766         * dv-tx3904irc.c: Compiler warning clean-up.
 767         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 768         frequent hw-trace messages.
 769
 770 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 771
 772         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 773
 774 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 775
 776         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 777
 778         * vr.igen: New file.
 779         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 780         * mips.igen: Define vr4100 model. Include vr.igen.
 781 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 782
 783         * mips.igen (check_mf_hilo): Correct check.
 784
 785 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 786
 787         * sim-main.h (interrupt_event): Add prototype.
 788
 789         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 790         register_ptr, register_value.
 791         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 792
 793         * sim-main.h (tracefh): Make extern.
 794
 795 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 796
 797         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 798         Reduce unnecessarily high timer event frequency.
 799         * dv-tx3904cpu.c: Ditto for interrupt event.
 800
 801 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 802
 803         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 804         to allay warnings.
 805         (interrupt_event): Made non-static.
 806
 807         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 808         interchange of configuration values for external vs. internal
 809         clock dividers.
 810
 811 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 812
 813         * mips.igen (BREAK): Moved code to here for
 814         simulator-reserved break instructions.
 815         * gencode.c (build_instruction): Ditto.
 816         * interp.c (signal_exception): Code moved from here.  Non-
 817         reserved instructions now use exception vector, rather
 818         than halting sim.
 819         * sim-main.h: Moved magic constants to here.
 820
 821 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 822
 823         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 824         register upon non-zero interrupt event level, clear upon zero
 825         event value.
 826         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 827         by passing zero event value.
 828         (*_io_{read,write}_buffer): Endianness fixes.
 829         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 830         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 831
 832         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 833         serial I/O and timer module at base address 0xFFFF0000.
 834
 835 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 836
 837         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 838         and BigEndianCPU.
 839
 840 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 841
 842         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 843         parts.
 844         * configure: Update.
 845
 846 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 847
 848         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 849         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 850         * configure.in: Include tx3904tmr in hw_device list.
 851         * configure: Rebuilt.
 852         * interp.c (sim_open): Instantiate three timer instances.
 853         Fix address typo of tx3904irc instance.
 854
 855 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 856
 857         * interp.c (signal_exception): SystemCall exception now uses
 858         the exception vector.
 859
 860 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 861
 862         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 863         to allay warnings.
 864
 865 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 866
 867         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 868
 869 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 870
 871         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 872
 873         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 874         sim-main.h. Declare a struct hw_descriptor instead of struct
 875         hw_device_descriptor.
 876
 877 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 878
 879         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 880         right bits and then re-align left hand bytes to correct byte
 881         lanes.  Fix incorrect computation in do_store_left when loading
 882         bytes from second word.
 883
 884 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 885
 886         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 887         * interp.c (sim_open): Only create a device tree when HW is
 888         enabled.
 889
 890         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 891         * interp.c (signal_exception): Ditto.
 892
 893 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 894
 895         * gencode.c: Mark BEGEZALL as LIKELY.
 896
 897 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 898
 899         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 900         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 901
 902 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 903
 904         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 905         modules.  Recognize TX39 target with "mips*tx39" pattern.
 906         * configure: Rebuilt.
 907         * sim-main.h (*): Added many macros defining bits in
 908         TX39 control registers.
 909         (SignalInterrupt): Send actual PC instead of NULL.
 910         (SignalNMIReset): New exception type.
 911         * interp.c (board): New variable for future use to identify
 912         a particular board being simulated.
 913         (mips_option_handler,mips_options): Added "--board" option.
 914         (interrupt_event): Send actual PC.
 915         (sim_open): Make memory layout conditional on board setting.
 916         (signal_exception): Initial implementation of hardware interrupt
 917         handling.  Accept another break instruction variant for simulator
 918         exit.
 919         (decode_coproc): Implement RFE instruction for TX39.
 920         (mips.igen): Decode RFE instruction as such.
 921         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 922         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 923         bbegin to implement memory map.
 924         * dv-tx3904cpu.c: New file.
 925         * dv-tx3904irc.c: New file.
 926
 927 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 928
 929         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 930
 931 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 932
 933         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 934         with calls to check_div_hilo.
 935
 936 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 937
 938         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 939         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 940         Add special r3900 version of do_mult_hilo.
 941         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 942         with calls to check_mult_hilo.
 943         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 944         with calls to check_div_hilo.
 945
 946 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 947
 948         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 949         Document a replacement.
 950
 951 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 952
 953         * interp.c (sim_monitor): Make mon_printf work.
 954
 955 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 956
 957         * sim-main.h (INSN_NAME): New arg `cpu'.
 958
 959 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 960
 961         * configure: Regenerated to track ../common/aclocal.m4 changes.
 962
 963 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 964
 965         * configure: Regenerated to track ../common/aclocal.m4 changes.
 966         * config.in: Ditto.
 967
 968 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 969
 970         * acconfig.h: New file.
 971         * configure.in: Reverted change of Apr 24; use sinclude again.
 972
 973 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 974
 975         * configure: Regenerated to track ../common/aclocal.m4 changes.
 976         * config.in: Ditto.
 977
 978 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 979
 980         * configure.in: Don't call sinclude.
 981
 982 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 983
 984         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 985
 986 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 987
 988         * mips.igen (ERET): Implement.
 989
 990         * interp.c (decode_coproc): Return sign-extended EPC.
 991
 992         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 993
 994         * interp.c (signal_exception): Do not ignore Trap.
 995         (signal_exception): On TRAP, restart at exception address.
 996         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 997         (signal_exception): Update.
 998         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 999         so that TRAP instructions are caught.
1000
1001 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1002
1003         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1004         contains HI/LO access history.
1005         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1006         (HIACCESS, LOACCESS): Delete, replace with
1007         (HIHISTORY, LOHISTORY): New macros.
1008         (CHECKHILO): Delete all, moved to mips.igen
1009
1010         * gencode.c (build_instruction): Do not generate checks for
1011         correct HI/LO register usage.
1012
1013         * interp.c (old_engine_run): Delete checks for correct HI/LO
1014         register usage.
1015
1016         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1017         check_mf_cycles): New functions.
1018         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1019         do_divu, domultx, do_mult, do_multu): Use.
1020
1021         * tx.igen ("madd", "maddu"): Use.
1022
1023 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1024
1025         * mips.igen (DSRAV): Use function do_dsrav.
1026         (SRAV): Use new function do_srav.
1027
1028         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1029         (B): Sign extend 11 bit immediate.
1030         (EXT-B*): Shift 16 bit immediate left by 1.
1031         (ADDIU*): Don't sign extend immediate value.
1032
1033 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1034
1035         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1036
1037         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1038         functions.
1039
1040         * mips.igen (delayslot32, nullify_next_insn): New functions.
1041         (m16.igen): Always include.
1042         (do_*): Add more tracing.
1043
1044         * m16.igen (delayslot16): Add NIA argument, could be called by a
1045         32 bit MIPS16 instruction.
1046
1047         * interp.c (ifetch16): Move function from here.
1048         * sim-main.c (ifetch16): To here.
1049
1050         * sim-main.c (ifetch16, ifetch32): Update to match current
1051         implementations of LH, LW.
1052         (signal_exception): Don't print out incorrect hex value of illegal
1053         instruction.
1054
1055 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1056
1057         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1058         instruction.
1059
1060         * m16.igen: Implement MIPS16 instructions.
1061
1062         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1063         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1064         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1065         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1066         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1067         bodies of corresponding code from 32 bit insn to these.  Also used
1068         by MIPS16 versions of functions.
1069
1070         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1071         (IMEM16): Drop NR argument from macro.
1072
1073 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1074
1075         * Makefile.in (SIM_OBJS): Add sim-main.o.
1076
1077         * sim-main.h (address_translation, load_memory, store_memory,
1078         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1079         as INLINE_SIM_MAIN.
1080         (pr_addr, pr_uword64): Declare.
1081         (sim-main.c): Include when H_REVEALS_MODULE_P.
1082
1083         * interp.c (address_translation, load_memory, store_memory,
1084         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1085         from here.
1086         * sim-main.c: To here. Fix compilation problems.
1087
1088         * configure.in: Enable inlining.
1089         * configure: Re-config.
1090
1091 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1092
1093         * configure: Regenerated to track ../common/aclocal.m4 changes.
1094
1095 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1096
1097         * mips.igen: Include tx.igen.
1098         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1099         * tx.igen: New file, contains MADD and MADDU.
1100
1101         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1102         the hardwired constant `7'.
1103         (store_memory): Ditto.
1104         (LOADDRMASK): Move definition to sim-main.h.
1105
1106         mips.igen (MTC0): Enable for r3900.
1107         (ADDU): Add trace.
1108
1109         mips.igen (do_load_byte): Delete.
1110         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1111         do_store_right): New functions.
1112         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1113
1114         configure.in: Let the tx39 use igen again.
1115         configure: Update.
1116
1117 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1118
1119         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1120         not an address sized quantity.  Return zero for cache sizes.
1121
1122 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1123
1124         * mips.igen (r3900): r3900 does not support 64 bit integer
1125         operations.
1126
1127 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1128
1129         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1130         than igen one.
1131         * configure : Rebuild.
1132
1133 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1134
1135         * configure: Regenerated to track ../common/aclocal.m4 changes.
1136
1137 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1138
1139         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1140
1141 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1142
1143         * configure: Regenerated to track ../common/aclocal.m4 changes.
1144         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1145
1146 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1147
1148         * configure: Regenerated to track ../common/aclocal.m4 changes.
1149
1150 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1151
1152         * interp.c (Max, Min): Comment out functions. Not yet used.
1153
1154 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1155
1156         * configure: Regenerated to track ../common/aclocal.m4 changes.
1157
1158 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1159
1160         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1161         configurable settings for stand-alone simulator.
1162
1163         * configure.in: Added X11 search, just in case.
1164
1165         * configure: Regenerated.
1166
1167 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1168
1169         * interp.c (sim_write, sim_read, load_memory, store_memory):
1170         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1171
1172 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1173
1174         * sim-main.h (GETFCC): Return an unsigned value.
1175
1176 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1177
1178         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1179         (DADD): Result destination is RD not RT.
1180
1181 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1182
1183         * sim-main.h (HIACCESS, LOACCESS): Always define.
1184
1185         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1186
1187         * interp.c (sim_info): Delete.
1188
1189 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1190
1191         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1192         (mips_option_handler): New argument `cpu'.
1193         (sim_open): Update call to sim_add_option_table.
1194
1195 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1196
1197         * mips.igen (CxC1): Add tracing.
1198
1199 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1200
1201         * sim-main.h (Max, Min): Declare.
1202
1203         * interp.c (Max, Min): New functions.
1204
1205         * mips.igen (BC1): Add tracing.
1206
1207 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1208
1209         * interp.c Added memory map for stack in vr4100
1210
1211 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1212
1213         * interp.c (load_memory): Add missing "break"'s.
1214
1215 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1216
1217         * interp.c (sim_store_register, sim_fetch_register): Pass in
1218         length parameter.  Return -1.
1219
1220 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1221
1222         * interp.c: Added hardware init hook, fixed warnings.
1223
1224 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1225
1226         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1227
1228 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1229
1230         * interp.c (ifetch16): New function.
1231
1232         * sim-main.h (IMEM32): Rename IMEM.
1233         (IMEM16_IMMED): Define.
1234         (IMEM16): Define.
1235         (DELAY_SLOT): Update.
1236
1237         * m16run.c (sim_engine_run): New file.
1238
1239         * m16.igen: All instructions except LB.
1240         (LB): Call do_load_byte.
1241         * mips.igen (do_load_byte): New function.
1242         (LB): Call do_load_byte.
1243
1244         * mips.igen: Move spec for insn bit size and high bit from here.
1245         * Makefile.in (tmp-igen, tmp-m16): To here.
1246
1247         * m16.dc: New file, decode mips16 instructions.
1248
1249         * Makefile.in (SIM_NO_ALL): Define.
1250         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1251
1252 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1253
1254         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1255         point unit to 32 bit registers.
1256         * configure: Re-generate.
1257
1258 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1259
1260         * configure.in (sim_use_gen): Make IGEN the default simulator
1261         generator for generic 32 and 64 bit mips targets.
1262         * configure: Re-generate.
1263
1264 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1265
1266         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1267         bitsize.
1268
1269         * interp.c (sim_fetch_register, sim_store_register): Read/write
1270         FGR from correct location.
1271         (sim_open): Set size of FGR's according to
1272         WITH_TARGET_FLOATING_POINT_BITSIZE.
1273
1274         * sim-main.h (FGR): Store floating point registers in a separate
1275         array.
1276
1277 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1278
1279         * configure: Regenerated to track ../common/aclocal.m4 changes.
1280
1281 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1282
1283         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1284
1285         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1286
1287         * interp.c (pending_tick): New function.  Deliver pending writes.
1288
1289         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1290         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1291         it can handle mixed sized quantites and single bits.
1292
1293 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1294
1295         * interp.c (oengine.h): Do not include when building with IGEN.
1296         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1297         (sim_info): Ditto for PROCESSOR_64BIT.
1298         (sim_monitor): Replace ut_reg with unsigned_word.
1299         (*): Ditto for t_reg.
1300         (LOADDRMASK): Define.
1301         (sim_open): Remove defunct check that host FP is IEEE compliant,
1302         using software to emulate floating point.
1303         (value_fpr, ...): Always compile, was conditional on HASFPU.
1304
1305 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1306
1307         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1308         size.
1309
1310         * interp.c (SD, CPU): Define.
1311         (mips_option_handler): Set flags in each CPU.
1312         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1313         (sim_close): Do not clear STATE, deleted anyway.
1314         (sim_write, sim_read): Assume CPU zero's vm should be used for
1315         data transfers.
1316         (sim_create_inferior): Set the PC for all processors.
1317         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1318         argument.
1319         (mips16_entry): Pass correct nr of args to store_word, load_word.
1320         (ColdReset): Cold reset all cpu's.
1321         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1322         (sim_monitor, load_memory, store_memory, signal_exception): Use
1323         `CPU' instead of STATE_CPU.
1324
1325
1326         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1327         SD or CPU_.
1328
1329         * sim-main.h (signal_exception): Add sim_cpu arg.
1330         (SignalException*): Pass both SD and CPU to signal_exception.
1331         * interp.c (signal_exception): Update.
1332
1333         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1334         Ditto
1335         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1336         address_translation): Ditto
1337         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1338
1339 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1340
1341         * configure: Regenerated to track ../common/aclocal.m4 changes.
1342
1343 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1344
1345         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1346
1347         * mips.igen (model): Map processor names onto BFD name.
1348
1349         * sim-main.h (CPU_CIA): Delete.
1350         (SET_CIA, GET_CIA): Define
1351
1352 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1353
1354         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1355         regiser.
1356
1357         * configure.in (default_endian): Configure a big-endian simulator
1358         by default.
1359         * configure: Re-generate.
1360
1361 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1362
1363         * configure: Regenerated to track ../common/aclocal.m4 changes.
1364
1365 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1366
1367         * interp.c (sim_monitor): Handle Densan monitor outbyte
1368         and inbyte functions.
1369
1370 1997-12-29  Felix Lee  <flee@cygnus.com>
1371
1372         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1373
1374 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1375
1376         * Makefile.in (tmp-igen): Arrange for $zero to always be
1377         reset to zero after every instruction.
1378
1379 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1380
1381         * configure: Regenerated to track ../common/aclocal.m4 changes.
1382         * config.in: Ditto.
1383
1384 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1385
1386         * mips.igen (MSUB): Fix to work like MADD.
1387         * gencode.c (MSUB): Similarly.
1388
1389 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1390
1391         * configure: Regenerated to track ../common/aclocal.m4 changes.
1392
1393 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1394
1395         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1396
1397 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1398
1399         * sim-main.h (sim-fpu.h): Include.
1400
1401         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1402         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1403         using host independant sim_fpu module.
1404
1405 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1406
1407         * interp.c (signal_exception): Report internal errors with SIGABRT
1408         not SIGQUIT.
1409
1410         * sim-main.h (C0_CONFIG): New register.
1411         (signal.h): No longer include.
1412
1413         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1414
1415 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1416
1417         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1418
1419 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1420
1421         * mips.igen: Tag vr5000 instructions.
1422         (ANDI): Was missing mipsIV model, fix assembler syntax.
1423         (do_c_cond_fmt): New function.
1424         (C.cond.fmt): Handle mips I-III which do not support CC field
1425         separatly.
1426         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1427         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1428         in IV3.2 spec.
1429         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1430         vr5000 which saves LO in a GPR separatly.
1431
1432         * configure.in (enable-sim-igen): For vr5000, select vr5000
1433         specific instructions.
1434         * configure: Re-generate.
1435
1436 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1437
1438         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1439
1440         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1441         fmt_uninterpreted_64 bit cases to switch.  Convert to
1442         fmt_formatted,
1443
1444         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1445
1446         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1447         as specified in IV3.2 spec.
1448         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1449
1450 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1451
1452         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1453         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1454         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1455         PENDING_FILL versions of instructions.  Simplify.
1456         (X): New function.
1457         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1458         instructions.
1459         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1460         a signed value.
1461         (MTHI, MFHI): Disable code checking HI-LO.
1462
1463         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1464         global.
1465         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1466
1467 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1468
1469         * gencode.c (build_mips16_operands): Replace IPC with cia.
1470
1471         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1472         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1473         IPC to `cia'.
1474         (UndefinedResult): Replace function with macro/function
1475         combination.
1476         (sim_engine_run): Don't save PC in IPC.
1477
1478         * sim-main.h (IPC): Delete.
1479
1480
1481         * interp.c (signal_exception, store_word, load_word,
1482         address_translation, load_memory, store_memory, cache_op,
1483         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1484         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1485         current instruction address - cia - argument.
1486         (sim_read, sim_write): Call address_translation directly.
1487         (sim_engine_run): Rename variable vaddr to cia.
1488         (signal_exception): Pass cia to sim_monitor
1489
1490         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1491         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1492         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1493
1494         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1495         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1496         SIM_ASSERT.
1497
1498         * interp.c (signal_exception): Pass restart address to
1499         sim_engine_restart.
1500
1501         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1502         idecode.o): Add dependency.
1503
1504         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1505         Delete definitions
1506         (DELAY_SLOT): Update NIA not PC with branch address.
1507         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1508
1509         * mips.igen: Use CIA not PC in branch calculations.
1510         (illegal): Call SignalException.
1511         (BEQ, ADDIU): Fix assembler.
1512
1513 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1514
1515         * m16.igen (JALX): Was missing.
1516
1517         * configure.in (enable-sim-igen): New configuration option.
1518         * configure: Re-generate.
1519
1520         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1521
1522         * interp.c (load_memory, store_memory): Delete parameter RAW.
1523         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1524         bypassing {load,store}_memory.
1525
1526         * sim-main.h (ByteSwapMem): Delete definition.
1527
1528         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1529
1530         * interp.c (sim_do_command, sim_commands): Delete mips specific
1531         commands.  Handled by module sim-options.
1532
1533         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1534         (WITH_MODULO_MEMORY): Define.
1535
1536         * interp.c (sim_info): Delete code printing memory size.
1537
1538         * interp.c (mips_size): Nee sim_size, delete function.
1539         (power2): Delete.
1540         (monitor, monitor_base, monitor_size): Delete global variables.
1541         (sim_open, sim_close): Delete code creating monitor and other
1542         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1543         manage memory regions.
1544         (load_memory, store_memory): Use sim-core for memory model.
1545
1546         * interp.c (address_translation): Delete all memory map code
1547         except line forcing 32 bit addresses.
1548
1549 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1550
1551         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1552         trace options.
1553
1554         * interp.c (logfh, logfile): Delete globals.
1555         (sim_open, sim_close): Delete code opening & closing log file.
1556         (mips_option_handler): Delete -l and -n options.
1557         (OPTION mips_options): Ditto.
1558
1559         * interp.c (OPTION mips_options): Rename option trace to dinero.
1560         (mips_option_handler): Update.
1561
1562 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1563
1564         * interp.c (fetch_str): New function.
1565         (sim_monitor): Rewrite using sim_read & sim_write.
1566         (sim_open): Check magic number.
1567         (sim_open): Write monitor vectors into memory using sim_write.
1568         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1569         (sim_read, sim_write): Simplify - transfer data one byte at a
1570         time.
1571         (load_memory, store_memory): Clarify meaning of parameter RAW.
1572
1573         * sim-main.h (isHOST): Defete definition.
1574         (isTARGET): Mark as depreciated.
1575         (address_translation): Delete parameter HOST.
1576
1577         * interp.c (address_translation): Delete parameter HOST.
1578
1579 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1580
1581         * mips.igen:
1582
1583         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1584         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1585
1586 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1587
1588         * mips.igen: Add model filter field to records.
1589
1590 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1591
1592         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1593
1594         interp.c (sim_engine_run): Do not compile function sim_engine_run
1595         when WITH_IGEN == 1.
1596
1597         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1598         target architecture.
1599
1600         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1601         igen. Replace with configuration variables sim_igen_flags /
1602         sim_m16_flags.
1603
1604         * m16.igen: New file.  Copy mips16 insns here.
1605         * mips.igen: From here.
1606
1607 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1608
1609         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1610         to top.
1611         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1612
1613 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1614
1615         * gencode.c (build_instruction): Follow sim_write's lead in using
1616         BigEndianMem instead of !ByteSwapMem.
1617
1618 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1619
1620         * configure.in (sim_gen): Dependent on target, select type of
1621         generator.  Always select old style generator.
1622
1623         configure: Re-generate.
1624
1625         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1626         targets.
1627         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1628         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1629         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1630         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1631         SIM_@sim_gen@_*, set by autoconf.
1632
1633 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1634
1635         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1636
1637         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1638         CURRENT_FLOATING_POINT instead.
1639
1640         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1641         (address_translation): Raise exception InstructionFetch when
1642         translation fails and isINSTRUCTION.
1643
1644         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1645         sim_engine_run): Change type of of vaddr and paddr to
1646         address_word.
1647         (address_translation, prefetch, load_memory, store_memory,
1648         cache_op): Change type of vAddr and pAddr to address_word.
1649
1650         * gencode.c (build_instruction): Change type of vaddr and paddr to
1651         address_word.
1652
1653 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1656         macro to obtain result of ALU op.
1657
1658 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1659
1660         * interp.c (sim_info): Call profile_print.
1661
1662 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1663
1664         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1665
1666         * sim-main.h (WITH_PROFILE): Do not define, defined in
1667         common/sim-config.h.  Use sim-profile module.
1668         (simPROFILE): Delete defintion.
1669
1670         * interp.c (PROFILE): Delete definition.
1671         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1672         (sim_close): Delete code writing profile histogram.
1673         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1674         Delete.
1675         (sim_engine_run): Delete code profiling the PC.
1676
1677 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1678
1679         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1680
1681         * interp.c (sim_monitor): Make register pointers of type
1682         unsigned_word*.
1683
1684         * sim-main.h: Make registers of type unsigned_word not
1685         signed_word.
1686
1687 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1688
1689         * interp.c (sync_operation): Rename from SyncOperation, make
1690         global, add SD argument.
1691         (prefetch): Rename from Prefetch, make global, add SD argument.
1692         (decode_coproc): Make global.
1693
1694         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1695
1696         * gencode.c (build_instruction): Generate DecodeCoproc not
1697         decode_coproc calls.
1698
1699         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1700         (SizeFGR): Move to sim-main.h
1701         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1702         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1703         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1704         sim-main.h.
1705         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1706         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1707         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1708         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1709         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1710         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1711
1712         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1713         exception.
1714         (sim-alu.h): Include.
1715         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1716         (sim_cia): Typedef to instruction_address.
1717
1718 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1719
1720         * Makefile.in (interp.o): Rename generated file engine.c to
1721         oengine.c.
1722
1723         * interp.c: Update.
1724
1725 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1726
1727         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1728
1729 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1730
1731         * gencode.c (build_instruction): For "FPSQRT", output correct
1732         number of arguments to Recip.
1733
1734 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * Makefile.in (interp.o): Depends on sim-main.h
1737
1738         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1739
1740         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1741         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1742         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1743         STATE, DSSTATE): Define
1744         (GPR, FGRIDX, ..): Define.
1745
1746         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1747         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1748         (GPR, FGRIDX, ...): Delete macros.
1749
1750         * interp.c: Update names to match defines from sim-main.h
1751
1752 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1753
1754         * interp.c (sim_monitor): Add SD argument.
1755         (sim_warning): Delete.  Replace calls with calls to
1756         sim_io_eprintf.
1757         (sim_error): Delete. Replace calls with sim_io_error.
1758         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1759         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1760         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1761         argument.
1762         (mips_size): Rename from sim_size. Add SD argument.
1763
1764         * interp.c (simulator): Delete global variable.
1765         (callback): Delete global variable.
1766         (mips_option_handler, sim_open, sim_write, sim_read,
1767         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1768         sim_size,sim_monitor): Use sim_io_* not callback->*.
1769         (sim_open): ZALLOC simulator struct.
1770         (PROFILE): Do not define.
1771
1772 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1773
1774         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1775         support.h with corresponding code.
1776
1777         * sim-main.h (word64, uword64), support.h: Move definition to
1778         sim-main.h.
1779         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1780
1781         * support.h: Delete
1782         * Makefile.in: Update dependencies
1783         * interp.c: Do not include.
1784
1785 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1786
1787         * interp.c (address_translation, load_memory, store_memory,
1788         cache_op): Rename to from AddressTranslation et.al., make global,
1789         add SD argument
1790
1791         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1792         CacheOp): Define.
1793
1794         * interp.c (SignalException): Rename to signal_exception, make
1795         global.
1796
1797         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1798
1799         * sim-main.h (SignalException, SignalExceptionInterrupt,
1800         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1801         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1802         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1803         Define.
1804
1805         * interp.c, support.h: Use.
1806
1807 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1808
1809         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1810         to value_fpr / store_fpr. Add SD argument.
1811         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1812         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1813
1814         * sim-main.h (ValueFPR, StoreFPR): Define.
1815
1816 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1817
1818         * interp.c (sim_engine_run): Check consistency between configure
1819         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1820         and HASFPU.
1821
1822         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1823         (mips_fpu): Configure WITH_FLOATING_POINT.
1824         (mips_endian): Configure WITH_TARGET_ENDIAN.
1825         * configure: Update.
1826
1827 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1828
1829         * configure: Regenerated to track ../common/aclocal.m4 changes.
1830
1831 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1832
1833         * configure: Regenerated.
1834
1835 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1836
1837         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1838
1839 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1840
1841         * gencode.c (print_igen_insn_models): Assume certain architectures
1842         include all mips* instructions.
1843         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1844         instruction.
1845
1846         * Makefile.in (tmp.igen): Add target. Generate igen input from
1847         gencode file.
1848
1849         * gencode.c (FEATURE_IGEN): Define.
1850         (main): Add --igen option.  Generate output in igen format.
1851         (process_instructions): Format output according to igen option.
1852         (print_igen_insn_format): New function.
1853         (print_igen_insn_models): New function.
1854         (process_instructions): Only issue warnings and ignore
1855         instructions when no FEATURE_IGEN.
1856
1857 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1858
1859         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1860         MIPS targets.
1861
1862 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1863
1864         * configure: Regenerated to track ../common/aclocal.m4 changes.
1865
1866 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1867
1868         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1869         SIM_RESERVED_BITS): Delete, moved to common.
1870         (SIM_EXTRA_CFLAGS): Update.
1871
1872 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1873
1874         * configure.in: Configure non-strict memory alignment.
1875         * configure: Regenerated to track ../common/aclocal.m4 changes.
1876
1877 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1878
1879         * configure: Regenerated to track ../common/aclocal.m4 changes.
1880
1881 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1882
1883         * gencode.c (SDBBP,DERET): Added (3900) insns.
1884         (RFE): Turn on for 3900.
1885         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1886         (dsstate): Made global.
1887         (SUBTARGET_R3900): Added.
1888         (CANCELDELAYSLOT): New.
1889         (SignalException): Ignore SystemCall rather than ignore and
1890         terminate.  Add DebugBreakPoint handling.
1891         (decode_coproc): New insns RFE, DERET; and new registers Debug
1892         and DEPC protected by SUBTARGET_R3900.
1893         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1894         bits explicitly.
1895         * Makefile.in,configure.in: Add mips subtarget option.
1896         * configure: Update.
1897
1898 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1899
1900         * gencode.c: Add r3900 (tx39).
1901
1902
1903 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1904
1905         * gencode.c (build_instruction): Don't need to subtract 4 for
1906         JALR, just 2.
1907
1908 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1909
1910         * interp.c: Correct some HASFPU problems.
1911
1912 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1913
1914         * configure: Regenerated to track ../common/aclocal.m4 changes.
1915
1916 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1917
1918         * interp.c (mips_options): Fix samples option short form, should
1919         be `x'.
1920
1921 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1922
1923         * interp.c (sim_info): Enable info code.  Was just returning.
1924
1925 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1926
1927         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1928         MFC0.
1929
1930 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1931
1932         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1933         constants.
1934         (build_instruction): Ditto for LL.
1935
1936 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1937
1938         * configure: Regenerated to track ../common/aclocal.m4 changes.
1939
1940 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1941
1942         * configure: Regenerated to track ../common/aclocal.m4 changes.
1943         * config.in: Ditto.
1944
1945 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1946
1947         * interp.c (sim_open): Add call to sim_analyze_program, update
1948         call to sim_config.
1949
1950 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1951
1952         * interp.c (sim_kill): Delete.
1953         (sim_create_inferior): Add ABFD argument. Set PC from same.
1954         (sim_load): Move code initializing trap handlers from here.
1955         (sim_open): To here.
1956         (sim_load): Delete, use sim-hload.c.
1957
1958         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1959
1960 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1961
1962         * configure: Regenerated to track ../common/aclocal.m4 changes.
1963         * config.in: Ditto.
1964
1965 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1966
1967         * interp.c (sim_open): Add ABFD argument.
1968         (sim_load): Move call to sim_config from here.
1969         (sim_open): To here.  Check return status.
1970
1971 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1972
1973         * gencode.c (build_instruction): Two arg MADD should
1974         not assign result to $0.
1975
1976 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1977
1978         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1979         * sim/mips/configure.in: Regenerate.
1980
1981 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1982
1983         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1984         signed8, unsigned8 et.al. types.
1985
1986         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1987         hosts when selecting subreg.
1988
1989 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1990
1991         * interp.c (sim_engine_run): Reset the ZERO register to zero
1992         regardless of FEATURE_WARN_ZERO.
1993         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1994
1995 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1996
1997         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1998         (SignalException): For BreakPoints ignore any mode bits and just
1999         save the PC.
2000         (SignalException): Always set the CAUSE register.
2001
2002 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2003
2004         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2005         exception has been taken.
2006
2007         * interp.c: Implement the ERET and mt/f sr instructions.
2008
2009 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2010
2011         * interp.c (SignalException): Don't bother restarting an
2012         interrupt.
2013
2014 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2015
2016         * interp.c (SignalException): Really take an interrupt.
2017         (interrupt_event): Only deliver interrupts when enabled.
2018
2019 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2020
2021         * interp.c (sim_info): Only print info when verbose.
2022         (sim_info) Use sim_io_printf for output.
2023
2024 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2025
2026         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2027         mips architectures.
2028
2029 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2030
2031         * interp.c (sim_do_command): Check for common commands if a
2032         simulator specific command fails.
2033
2034 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2035
2036         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2037         and simBE when DEBUG is defined.
2038
2039 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2040
2041         * interp.c (interrupt_event): New function.  Pass exception event
2042         onto exception handler.
2043
2044         * configure.in: Check for stdlib.h.
2045         * configure: Regenerate.
2046
2047         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2048         variable declaration.
2049         (build_instruction): Initialize memval1.
2050         (build_instruction): Add UNUSED attribute to byte, bigend,
2051         reverse.
2052         (build_operands): Ditto.
2053
2054         * interp.c: Fix GCC warnings.
2055         (sim_get_quit_code): Delete.
2056
2057         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2058         * Makefile.in: Ditto.
2059         * configure: Re-generate.
2060
2061         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2062
2063 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2064
2065         * interp.c (mips_option_handler): New function parse argumes using
2066         sim-options.
2067         (myname): Replace with STATE_MY_NAME.
2068         (sim_open): Delete check for host endianness - performed by
2069         sim_config.
2070         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2071         (sim_open): Move much of the initialization from here.
2072         (sim_load): To here.  After the image has been loaded and
2073         endianness set.
2074         (sim_open): Move ColdReset from here.
2075         (sim_create_inferior): To here.
2076         (sim_open): Make FP check less dependant on host endianness.
2077
2078         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2079         run.
2080         * interp.c (sim_set_callbacks): Delete.
2081
2082         * interp.c (membank, membank_base, membank_size): Replace with
2083         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2084         (sim_open): Remove call to callback->init. gdb/run do this.
2085
2086         * interp.c: Update
2087
2088         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2089
2090         * interp.c (big_endian_p): Delete, replaced by
2091         current_target_byte_order.
2092
2093 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2094
2095         * interp.c (host_read_long, host_read_word, host_swap_word,
2096         host_swap_long): Delete. Using common sim-endian.
2097         (sim_fetch_register, sim_store_register): Use H2T.
2098         (pipeline_ticks): Delete.  Handled by sim-events.
2099         (sim_info): Update.
2100         (sim_engine_run): Update.
2101
2102 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2103
2104         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2105         reason from here.
2106         (SignalException): To here. Signal using sim_engine_halt.
2107         (sim_stop_reason): Delete, moved to common.
2108
2109 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2110
2111         * interp.c (sim_open): Add callback argument.
2112         (sim_set_callbacks): Delete SIM_DESC argument.
2113         (sim_size): Ditto.
2114
2115 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2116
2117         * Makefile.in (SIM_OBJS): Add common modules.
2118
2119         * interp.c (sim_set_callbacks): Also set SD callback.
2120         (set_endianness, xfer_*, swap_*): Delete.
2121         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2122         Change to functions using sim-endian macros.
2123         (control_c, sim_stop): Delete, use common version.
2124         (simulate): Convert into.
2125         (sim_engine_run): This function.
2126         (sim_resume): Delete.
2127
2128         * interp.c (simulation): New variable - the simulator object.
2129         (sim_kind): Delete global - merged into simulation.
2130         (sim_load): Cleanup.  Move PC assignment from here.
2131         (sim_create_inferior): To here.
2132
2133         * sim-main.h: New file.
2134         * interp.c (sim-main.h): Include.
2135
2136 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2137
2138         * configure: Regenerated to track ../common/aclocal.m4 changes.
2139
2140 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2141
2142         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2143
2144 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2145
2146         * gencode.c (build_instruction): DIV instructions: check
2147         for division by zero and integer overflow before using
2148         host's division operation.
2149
2150 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2151
2152         * Makefile.in (SIM_OBJS): Add sim-load.o.
2153         * interp.c: #include bfd.h.
2154         (target_byte_order): Delete.
2155         (sim_kind, myname, big_endian_p): New static locals.
2156         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2157         after argument parsing.  Recognize -E arg, set endianness accordingly.
2158         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2159         load file into simulator.  Set PC from bfd.
2160         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2161         (set_endianness): Use big_endian_p instead of target_byte_order.
2162
2163 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2164
2165         * interp.c (sim_size): Delete prototype - conflicts with
2166         definition in remote-sim.h.  Correct definition.
2167
2168 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2169
2170         * configure: Regenerated to track ../common/aclocal.m4 changes.
2171         * config.in: Ditto.
2172
2173 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2174
2175         * interp.c (sim_open): New arg `kind'.
2176
2177         * configure: Regenerated to track ../common/aclocal.m4 changes.
2178
2179 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2180
2181         * configure: Regenerated to track ../common/aclocal.m4 changes.
2182
2183 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2184
2185         * interp.c (sim_open): Set optind to 0 before calling getopt.
2186
2187 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2188
2189         * configure: Regenerated to track ../common/aclocal.m4 changes.
2190
2191 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2192
2193         * interp.c : Replace uses of pr_addr with pr_uword64
2194         where the bit length is always 64 independent of SIM_ADDR.
2195         (pr_uword64) : added.
2196
2197 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2198
2199         * configure: Re-generate.
2200
2201 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2202
2203         * configure: Regenerate to track ../common/aclocal.m4 changes.
2204
2205 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2206
2207         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2208         in argv form.
2209         (other sim_*): New SIM_DESC argument.
2210
2211 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2212
2213         * interp.c: Fix printing of addresses for non-64-bit targets.
2214         (pr_addr): Add function to print address based on size.
2215
2216 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2217
2218         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2219
2220 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2221
2222         * gencode.c (build_mips16_operands): Correct computation of base
2223         address for extended PC relative instruction.
2224
2225 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2226
2227         * interp.c (mips16_entry): Add support for floating point cases.
2228         (SignalException): Pass floating point cases to mips16_entry.
2229         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2230         registers.
2231         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2232         or fmt_word.
2233         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2234         and then set the state to fmt_uninterpreted.
2235         (COP_SW): Temporarily set the state to fmt_word while calling
2236         ValueFPR.
2237
2238 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2239
2240         * gencode.c (build_instruction): The high order may be set in the
2241         comparison flags at any ISA level, not just ISA 4.
2242
2243 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2244
2245         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2246         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2247         * configure.in: sinclude ../common/aclocal.m4.
2248         * configure: Regenerated.
2249
2250 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2251
2252         * configure: Rebuild after change to aclocal.m4.
2253
2254 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2255
2256         * configure configure.in Makefile.in:  Update to new configure
2257         scheme which is more compatible with WinGDB builds.
2258         * configure.in:  Improve comment on how to run autoconf.
2259         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2260         * Makefile.in:  Use autoconf substitution to install common
2261         makefile fragment.
2262
2263 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2264
2265         * gencode.c (build_instruction): Use BigEndianCPU instead of
2266         ByteSwapMem.
2267
2268 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2269
2270         * interp.c (sim_monitor): Make output to stdout visible in
2271         wingdb's I/O log window.
2272
2273 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2274
2275         * support.h: Undo previous change to SIGTRAP
2276         and SIGQUIT values.
2277
2278 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2279
2280         * interp.c (store_word, load_word): New static functions.
2281         (mips16_entry): New static function.
2282         (SignalException): Look for mips16 entry and exit instructions.
2283         (simulate): Use the correct index when setting fpr_state after
2284         doing a pending move.
2285
2286 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2287
2288         * interp.c: Fix byte-swapping code throughout to work on
2289         both little- and big-endian hosts.
2290
2291 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2292
2293         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2294         with gdb/config/i386/xm-windows.h.
2295
2296 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2297
2298         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2299         that messes up arithmetic shifts.
2300
2301 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2302
2303         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2304         SIGTRAP and SIGQUIT for _WIN32.
2305
2306 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2307
2308         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2309         force a 64 bit multiplication.
2310         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2311         destination register is 0, since that is the default mips16 nop
2312         instruction.
2313
2314 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2315
2316         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2317         (build_endian_shift): Don't check proc64.
2318         (build_instruction): Always set memval to uword64.  Cast op2 to
2319         uword64 when shifting it left in memory instructions.  Always use
2320         the same code for stores--don't special case proc64.
2321
2322         * gencode.c (build_mips16_operands): Fix base PC value for PC
2323         relative operands.
2324         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2325         jal instruction.
2326         * interp.c (simJALDELAYSLOT): Define.
2327         (JALDELAYSLOT): Define.
2328         (INDELAYSLOT, INJALDELAYSLOT): Define.
2329         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2330
2331 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2332
2333         * interp.c (sim_open): add flush_cache as a PMON routine
2334         (sim_monitor): handle flush_cache by ignoring it
2335
2336 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2337
2338         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2339         BigEndianMem.
2340         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2341         (BigEndianMem): Rename to ByteSwapMem and change sense.
2342         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2343         BigEndianMem references to !ByteSwapMem.
2344         (set_endianness): New function, with prototype.
2345         (sim_open): Call set_endianness.
2346         (sim_info): Use simBE instead of BigEndianMem.
2347         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2348         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2349         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2350         ifdefs, keeping the prototype declaration.
2351         (swap_word): Rewrite correctly.
2352         (ColdReset): Delete references to CONFIG.  Delete endianness related
2353         code; moved to set_endianness.
2354
2355 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2356
2357         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2358         * interp.c (CHECKHILO): Define away.
2359         (simSIGINT): New macro.
2360         (membank_size): Increase from 1MB to 2MB.
2361         (control_c): New function.
2362         (sim_resume): Rename parameter signal to signal_number.  Add local
2363         variable prev.  Call signal before and after simulate.
2364         (sim_stop_reason): Add simSIGINT support.
2365         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2366         functions always.
2367         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2368         if logfh is NULL.
2369         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2370         a call to sim_warning.
2371
2372 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2373
2374         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2375         16 bit instructions.
2376
2377 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2378
2379         Add support for mips16 (16 bit MIPS implementation):
2380         * gencode.c (inst_type): Add mips16 instruction encoding types.
2381         (GETDATASIZEINSN): Define.
2382         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2383         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2384         mtlo.
2385         (MIPS16_DECODE): New table, for mips16 instructions.
2386         (bitmap_val): New static function.
2387         (struct mips16_op): Define.
2388         (mips16_op_table): New table, for mips16 operands.
2389         (build_mips16_operands): New static function.
2390         (process_instructions): If PC is odd, decode a mips16
2391         instruction.  Break out instruction handling into new
2392         build_instruction function.
2393         (build_instruction): New static function, broken out of
2394         process_instructions.  Check modifiers rather than flags for SHIFT
2395         bit count and m[ft]{hi,lo} direction.
2396         (usage): Pass program name to fprintf.
2397         (main): Remove unused variable this_option_optind.  Change
2398         ``*loptarg++'' to ``loptarg++''.
2399         (my_strtoul): Parenthesize && within ||.
2400         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2401         (simulate): If PC is odd, fetch a 16 bit instruction, and
2402         increment PC by 2 rather than 4.
2403         * configure.in: Add case for mips16*-*-*.
2404         * configure: Rebuild.
2405
2406 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2407
2408         * interp.c: Allow -t to enable tracing in standalone simulator.
2409         Fix garbage output in trace file and error messages.
2410
2411 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2412
2413         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2414         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2415         * configure.in: Simplify using macros in ../common/aclocal.m4.
2416         * configure: Regenerated.
2417         * tconfig.in: New file.
2418
2419 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2420
2421         * interp.c: Fix bugs in 64-bit port.
2422         Use ansi function declarations for msvc compiler.
2423         Initialize and test file pointer in trace code.
2424         Prevent duplicate definition of LAST_EMED_REGNUM.
2425
2426 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2427
2428         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2429
2430 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2431
2432         * interp.c (SignalException): Check for explicit terminating
2433         breakpoint value.
2434         * gencode.c: Pass instruction value through SignalException()
2435         calls for Trap, Breakpoint and Syscall.
2436
2437 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2438
2439         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2440         only used on those hosts that provide it.
2441         * configure.in: Add sqrt() to list of functions to be checked for.
2442         * config.in: Re-generated.
2443         * configure: Re-generated.
2444
2445 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2446
2447         * gencode.c (process_instructions): Call build_endian_shift when
2448         expanding STORE RIGHT, to fix swr.
2449         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2450         clear the high bits.
2451         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2452         Fix float to int conversions to produce signed values.
2453
2454 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2455
2456         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2457         (process_instructions): Correct handling of nor instruction.
2458         Correct shift count for 32 bit shift instructions. Correct sign
2459         extension for arithmetic shifts to not shift the number of bits in
2460         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2461         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2462         Fix madd.
2463         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2464         It's OK to have a mult follow a mult.  What's not OK is to have a
2465         mult follow an mfhi.
2466         (Convert): Comment out incorrect rounding code.
2467
2468 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2469
2470         * interp.c (sim_monitor): Improved monitor printf
2471         simulation. Tidied up simulator warnings, and added "--log" option
2472         for directing warning message output.
2473         * gencode.c: Use sim_warning() rather than WARNING macro.
2474
2475 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2476
2477         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2478         getopt1.o, rather than on gencode.c.  Link objects together.
2479         Don't link against -liberty.
2480         (gencode.o, getopt.o, getopt1.o): New targets.
2481         * gencode.c: Include <ctype.h> and "ansidecl.h".
2482         (AND): Undefine after including "ansidecl.h".
2483         (ULONG_MAX): Define if not defined.
2484         (OP_*): Don't define macros; now defined in opcode/mips.h.
2485         (main): Call my_strtoul rather than strtoul.
2486         (my_strtoul): New static function.
2487
2488 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2489
2490         * gencode.c (process_instructions):  Generate word64 and uword64
2491         instead of `long long' and `unsigned long long' data types.
2492         * interp.c:  #include sysdep.h to get signals, and define default
2493         for SIGBUS.
2494         * (Convert):  Work around for Visual-C++ compiler bug with type
2495         conversion.
2496         * support.h:  Make things compile under Visual-C++ by using
2497         __int64 instead of `long long'.  Change many refs to long long
2498         into word64/uword64 typedefs.
2499
2500 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2501
2502         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2503         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2504         (docdir): Removed.
2505         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2506         (AC_PROG_INSTALL): Added.
2507         (AC_PROG_CC): Moved to before configure.host call.
2508         * configure: Rebuilt.
2509
2510 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2511
2512         * configure.in: Define @SIMCONF@ depending on mips target.
2513         * configure: Rebuild.
2514         * Makefile.in (run): Add @SIMCONF@ to control simulator
2515         construction.
2516         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2517         * interp.c: Remove some debugging, provide more detailed error
2518         messages, update memory accesses to use LOADDRMASK.
2519
2520 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2521
2522         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2523         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2524         stamp-h.
2525         * configure: Rebuild.
2526         * config.in: New file, generated by autoheader.
2527         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2528         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2529         HAVE_ANINT and HAVE_AINT, as appropriate.
2530         * Makefile.in (run): Use @LIBS@ rather than -lm.
2531         (interp.o): Depend upon config.h.
2532         (Makefile): Just rebuild Makefile.
2533         (clean): Remove stamp-h.
2534         (mostlyclean): Make the same as clean, not as distclean.
2535         (config.h, stamp-h): New targets.
2536
2537 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2538
2539         * interp.c (ColdReset): Fix boolean test. Make all simulator
2540         globals static.
2541
2542 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2543
2544         * interp.c (xfer_direct_word, xfer_direct_long,
2545         swap_direct_word, swap_direct_long, xfer_big_word,
2546         xfer_big_long, xfer_little_word, xfer_little_long,
2547         swap_word,swap_long): Added.
2548         * interp.c (ColdReset): Provide function indirection to
2549         host<->simulated_target transfer routines.
2550         * interp.c (sim_store_register, sim_fetch_register): Updated to
2551         make use of indirected transfer routines.
2552
2553 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2554
2555         * gencode.c (process_instructions): Ensure FP ABS instruction
2556         recognised.
2557         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2558         system call support.
2559
2560 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2561
2562         * interp.c (sim_do_command): Complain if callback structure not
2563         initialised.
2564
2565 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2566
2567         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2568         support for Sun hosts.
2569         * Makefile.in (gencode): Ensure the host compiler and libraries
2570         used for cross-hosted build.
2571
2572 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2573
2574         * interp.c, gencode.c: Some more (TODO) tidying.
2575
2576 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2577
2578         * gencode.c, interp.c: Replaced explicit long long references with
2579         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2580         * support.h (SET64LO, SET64HI): Macros added.
2581
2582 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2583
2584         * configure: Regenerate with autoconf 2.7.
2585
2586 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2587
2588         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2589         * support.h: Remove superfluous "1" from #if.
2590         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2591
2592 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2593
2594         * interp.c (StoreFPR): Control UndefinedResult() call on
2595         WARN_RESULT manifest.
2596
2597 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2598
2599         * gencode.c: Tidied instruction decoding, and added FP instruction
2600         support.
2601
2602         * interp.c: Added dineroIII, and BSD profiling support. Also
2603         run-time FP handling.
2604
2605 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2606
2607         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2608         gencode.c, interp.c, support.h: created.