1 2015-12-24 Mike Frysinger <vapier@gentoo.org>
3 * tconfig.h (SIM_HANDLES_LMA): Delete.
5 2015-12-24 Mike Frysinger <vapier@gentoo.org>
7 * sim-main.h (WITH_WATCHPOINTS): Delete.
9 2015-12-24 Mike Frysinger <vapier@gentoo.org>
11 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
13 2015-12-24 Mike Frysinger <vapier@gentoo.org>
15 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
17 2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
19 * micromips.igen (process_isa_mode): Fix left shift of negative
22 2015-11-17 Mike Frysinger <vapier@gentoo.org>
24 * sim-main.h (WITH_MODULO_MEMORY): Delete.
26 2015-11-15 Mike Frysinger <vapier@gentoo.org>
28 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
30 2015-11-14 Mike Frysinger <vapier@gentoo.org>
32 * interp.c (sim_close): Rename to ...
33 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
35 * sim-main.h (mips_sim_close): Declare.
36 (SIM_CLOSE_HOOK): Define.
38 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
39 Ali Lown <ali.lown@imgtec.com>
41 * Makefile.in (tmp-micromips): New rule.
42 (tmp-mach-multi): Add support for micromips.
43 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
44 that works for both mips64 and micromips64.
45 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
47 Add build support for micromips.
48 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
49 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
50 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
51 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
52 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
53 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
54 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
55 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
56 Refactored instruction code to use these functions.
57 * dsp2.igen: Refactored instruction code to use the new functions.
58 * interp.c (decode_coproc): Refactored to work with any instruction
60 (isa_mode): New variable
61 (RSVD_INSTRUCTION): Changed to 0x00000039.
62 * m16.igen (BREAK16): Refactored instruction to use do_break16.
63 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
64 * micromips.dc: New file.
65 * micromips.igen: New file.
66 * micromips16.dc: New file.
67 * micromipsdsp.igen: New file.
68 * micromipsrun.c: New file.
69 * mips.igen (do_swc1): Changed to work with any instruction encoding.
70 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
71 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
72 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
73 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
74 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
75 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
76 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
77 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
78 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
79 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
80 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
81 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
82 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
83 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
84 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
85 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
86 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
87 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
89 Refactored instruction code to use these functions.
90 (RSVD): Changed to use new reserved instruction.
91 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
92 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
93 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
94 do_store_double): Added micromips32 and micromips64 models.
95 Added include for micromips.igen and micromipsdsp.igen
96 Add micromips32 and micromips64 models.
97 (DecodeCoproc): Updated to use new macro definition.
98 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
99 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
100 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
101 Refactored instruction code to use these functions.
102 * sim-main.h (CP0_operation): New enum.
103 (DecodeCoproc): Updated macro.
104 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
105 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
106 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
107 ISA_MODE_MICROMIPS): New defines.
108 (sim_state): Add isa_mode field.
110 2015-06-23 Mike Frysinger <vapier@gentoo.org>
112 * configure: Regenerate.
114 2015-06-12 Mike Frysinger <vapier@gentoo.org>
116 * configure.ac: Change configure.in to configure.ac.
117 * configure: Regenerate.
119 2015-06-12 Mike Frysinger <vapier@gentoo.org>
121 * configure: Regenerate.
123 2015-06-12 Mike Frysinger <vapier@gentoo.org>
125 * interp.c [TRACE]: Delete.
126 (TRACE): Change to WITH_TRACE_ANY_P.
127 [!WITH_TRACE_ANY_P] (open_trace): Define.
128 (mips_option_handler, open_trace, sim_close, dotrace):
129 Change defined(TRACE) to WITH_TRACE_ANY_P.
130 (sim_open): Delete TRACE ifdef check.
131 * sim-main.c (load_memory): Delete TRACE ifdef check.
132 (store_memory): Likewise.
133 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
134 [!WITH_TRACE_ANY_P] (dotrace): Define.
136 2015-04-18 Mike Frysinger <vapier@gentoo.org>
138 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
141 2015-04-18 Mike Frysinger <vapier@gentoo.org>
143 * sim-main.h (SIM_CPU): Delete.
145 2015-04-18 Mike Frysinger <vapier@gentoo.org>
147 * sim-main.h (sim_cia): Delete.
149 2015-04-17 Mike Frysinger <vapier@gentoo.org>
151 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
153 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
154 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
155 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
156 CIA_SET to CPU_PC_SET.
157 * sim-main.h (CIA_GET, CIA_SET): Delete.
159 2015-04-15 Mike Frysinger <vapier@gentoo.org>
161 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
162 * sim-main.h (STATE_CPU): Delete.
164 2015-04-13 Mike Frysinger <vapier@gentoo.org>
166 * configure: Regenerate.
168 2015-04-13 Mike Frysinger <vapier@gentoo.org>
170 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
171 * interp.c (mips_pc_get, mips_pc_set): New functions.
172 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
173 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
174 (sim_pc_get): Delete.
175 * sim-main.h (SIM_CPU): Define.
176 (struct sim_state): Change cpu to an array of pointers.
179 2015-04-13 Mike Frysinger <vapier@gentoo.org>
181 * interp.c (mips_option_handler, open_trace, sim_close,
182 sim_write, sim_read, sim_store_register, sim_fetch_register,
183 sim_create_inferior, pr_addr, pr_uword64): Convert old style
185 (sim_open): Convert old style prototype. Change casts with
186 sim_write to unsigned char *.
187 (fetch_str): Change null to unsigned char, and change cast to
189 (sim_monitor): Change c & ch to unsigned char. Change cast to
192 2015-04-12 Mike Frysinger <vapier@gentoo.org>
194 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
196 2015-04-06 Mike Frysinger <vapier@gentoo.org>
198 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
200 2015-04-01 Mike Frysinger <vapier@gentoo.org>
202 * tconfig.h (SIM_HAVE_PROFILE): Delete.
204 2015-03-31 Mike Frysinger <vapier@gentoo.org>
206 * config.in, configure: Regenerate.
208 2015-03-24 Mike Frysinger <vapier@gentoo.org>
210 * interp.c (sim_pc_get): New function.
212 2015-03-24 Mike Frysinger <vapier@gentoo.org>
214 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
215 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
217 2015-03-24 Mike Frysinger <vapier@gentoo.org>
219 * configure: Regenerate.
221 2015-03-23 Mike Frysinger <vapier@gentoo.org>
223 * configure: Regenerate.
225 2015-03-23 Mike Frysinger <vapier@gentoo.org>
227 * configure: Regenerate.
228 * configure.ac (mips_extra_objs): Delete.
229 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
230 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
232 2015-03-23 Mike Frysinger <vapier@gentoo.org>
234 * configure: Regenerate.
235 * configure.ac: Delete sim_hw checks for dv-sockser.
237 2015-03-16 Mike Frysinger <vapier@gentoo.org>
239 * config.in, configure: Regenerate.
240 * tconfig.in: Rename file ...
241 * tconfig.h: ... here.
243 2015-03-15 Mike Frysinger <vapier@gentoo.org>
245 * tconfig.in: Delete includes.
246 [HAVE_DV_SOCKSER]: Delete.
248 2015-03-14 Mike Frysinger <vapier@gentoo.org>
250 * Makefile.in (SIM_RUN_OBJS): Delete.
252 2015-03-14 Mike Frysinger <vapier@gentoo.org>
254 * configure.ac (AC_CHECK_HEADERS): Delete.
255 * aclocal.m4, configure: Regenerate.
257 2014-08-19 Alan Modra <amodra@gmail.com>
259 * configure: Regenerate.
261 2014-08-15 Roland McGrath <mcgrathr@google.com>
263 * configure: Regenerate.
264 * config.in: Regenerate.
266 2014-03-04 Mike Frysinger <vapier@gentoo.org>
268 * configure: Regenerate.
270 2013-09-23 Alan Modra <amodra@gmail.com>
272 * configure: Regenerate.
274 2013-06-03 Mike Frysinger <vapier@gentoo.org>
276 * aclocal.m4, configure: Regenerate.
278 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
280 * configure: Rebuild.
282 2013-03-26 Mike Frysinger <vapier@gentoo.org>
284 * configure: Regenerate.
286 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
288 * configure.ac: Address use of dv-sockser.o.
289 * tconfig.in: Conditionalize use of dv_sockser_install.
290 * configure: Regenerated.
291 * config.in: Regenerated.
293 2012-10-04 Chao-ying Fu <fu@mips.com>
294 Steve Ellcey <sellcey@mips.com>
296 * mips/mips3264r2.igen (rdhwr): New.
298 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
300 * configure.ac: Always link against dv-sockser.o.
301 * configure: Regenerate.
303 2012-06-15 Joel Brobecker <brobecker@adacore.com>
305 * config.in, configure: Regenerate.
307 2012-05-18 Nick Clifton <nickc@redhat.com>
310 * interp.c: Include config.h before system header files.
312 2012-03-24 Mike Frysinger <vapier@gentoo.org>
314 * aclocal.m4, config.in, configure: Regenerate.
316 2011-12-03 Mike Frysinger <vapier@gentoo.org>
318 * aclocal.m4: New file.
319 * configure: Regenerate.
321 2011-10-19 Mike Frysinger <vapier@gentoo.org>
323 * configure: Regenerate after common/acinclude.m4 update.
325 2011-10-17 Mike Frysinger <vapier@gentoo.org>
327 * configure.ac: Change include to common/acinclude.m4.
329 2011-10-17 Mike Frysinger <vapier@gentoo.org>
331 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
332 call. Replace common.m4 include with SIM_AC_COMMON.
333 * configure: Regenerate.
335 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
337 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
339 (tmp-mach-multi): Exit early when igen fails.
341 2011-07-05 Mike Frysinger <vapier@gentoo.org>
343 * interp.c (sim_do_command): Delete.
345 2011-02-14 Mike Frysinger <vapier@gentoo.org>
347 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
348 (tx3904sio_fifo_reset): Likewise.
349 * interp.c (sim_monitor): Likewise.
351 2010-04-14 Mike Frysinger <vapier@gentoo.org>
353 * interp.c (sim_write): Add const to buffer arg.
355 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
357 * interp.c: Don't include sysdep.h
359 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
361 * configure: Regenerate.
363 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
365 * config.in: Regenerate.
366 * configure: Likewise.
368 * configure: Regenerate.
370 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
372 * configure: Regenerate to track ../common/common.m4 changes.
375 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
376 Daniel Jacobowitz <dan@codesourcery.com>
377 Joseph Myers <joseph@codesourcery.com>
379 * configure: Regenerate.
381 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
383 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
384 that unconditionally allows fmt_ps.
385 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
386 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
387 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
388 filter from 64,f to 32,f.
389 (PREFX): Change filter from 64 to 32.
390 (LDXC1, LUXC1): Provide separate mips32r2 implementations
391 that use do_load_double instead of do_load. Make both LUXC1
392 versions unpredictable if SizeFGR () != 64.
393 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
394 instead of do_store. Remove unused variable. Make both SUXC1
395 versions unpredictable if SizeFGR () != 64.
397 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
399 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
400 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
401 shifts for that case.
403 2007-09-04 Nick Clifton <nickc@redhat.com>
405 * interp.c (options enum): Add OPTION_INFO_MEMORY.
406 (display_mem_info): New static variable.
407 (mips_option_handler): Handle OPTION_INFO_MEMORY.
408 (mips_options): Add info-memory and memory-info.
409 (sim_open): After processing the command line and board
410 specification, check display_mem_info. If it is set then
411 call the real handler for the --memory-info command line
414 2007-08-24 Joel Brobecker <brobecker@adacore.com>
416 * configure.ac: Change license of multi-run.c to GPL version 3.
417 * configure: Regenerate.
419 2007-06-28 Richard Sandiford <richard@codesourcery.com>
421 * configure.ac, configure: Revert last patch.
423 2007-06-26 Richard Sandiford <richard@codesourcery.com>
425 * configure.ac (sim_mipsisa3264_configs): New variable.
426 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
427 every configuration support all four targets, using the triplet to
428 determine the default.
429 * configure: Regenerate.
431 2007-06-25 Richard Sandiford <richard@codesourcery.com>
433 * Makefile.in (m16run.o): New rule.
435 2007-05-15 Thiemo Seufer <ths@mips.com>
437 * mips3264r2.igen (DSHD): Fix compile warning.
439 2007-05-14 Thiemo Seufer <ths@mips.com>
441 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
442 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
443 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
444 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
447 2007-03-01 Thiemo Seufer <ths@mips.com>
449 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
452 2007-02-20 Thiemo Seufer <ths@mips.com>
454 * dsp.igen: Update copyright notice.
455 * dsp2.igen: Fix copyright notice.
457 2007-02-20 Thiemo Seufer <ths@mips.com>
458 Chao-Ying Fu <fu@mips.com>
460 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
461 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
462 Add dsp2 to sim_igen_machine.
463 * configure: Regenerate.
464 * dsp.igen (do_ph_op): Add MUL support when op = 2.
465 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
466 (mulq_rs.ph): Use do_ph_mulq.
467 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
468 * mips.igen: Add dsp2 model and include dsp2.igen.
469 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
470 for *mips32r2, *mips64r2, *dsp.
471 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
472 for *mips32r2, *mips64r2, *dsp2.
473 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
475 2007-02-19 Thiemo Seufer <ths@mips.com>
476 Nigel Stephens <nigel@mips.com>
478 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
479 jumps with hazard barrier.
481 2007-02-19 Thiemo Seufer <ths@mips.com>
482 Nigel Stephens <nigel@mips.com>
484 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
485 after each call to sim_io_write.
487 2007-02-19 Thiemo Seufer <ths@mips.com>
488 Nigel Stephens <nigel@mips.com>
490 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
491 supported by this simulator.
492 (decode_coproc): Recognise additional CP0 Config registers
495 2007-02-19 Thiemo Seufer <ths@mips.com>
496 Nigel Stephens <nigel@mips.com>
497 David Ung <davidu@mips.com>
499 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
500 uninterpreted formats. If fmt is one of the uninterpreted types
501 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
502 fmt_word, and fmt_uninterpreted_64 like fmt_long.
503 (store_fpr): When writing an invalid odd register, set the
504 matching even register to fmt_unknown, not the following register.
505 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
506 the the memory window at offset 0 set by --memory-size command
508 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
510 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
512 (sim_monitor): When returning the memory size to the MIPS
513 application, use the value in STATE_MEM_SIZE, not an arbitrary
515 (cop_lw): Don' mess around with FPR_STATE, just pass
516 fmt_uninterpreted_32 to StoreFPR.
518 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
520 * mips.igen (not_word_value): Single version for mips32, mips64
523 2007-02-19 Thiemo Seufer <ths@mips.com>
524 Nigel Stephens <nigel@mips.com>
526 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
529 2007-02-17 Thiemo Seufer <ths@mips.com>
531 * configure.ac (mips*-sde-elf*): Move in front of generic machine
533 * configure: Regenerate.
535 2007-02-17 Thiemo Seufer <ths@mips.com>
537 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
538 Add mdmx to sim_igen_machine.
539 (mipsisa64*-*-*): Likewise. Remove dsp.
540 (mipsisa32*-*-*): Remove dsp.
541 * configure: Regenerate.
543 2007-02-13 Thiemo Seufer <ths@mips.com>
545 * configure.ac: Add mips*-sde-elf* target.
546 * configure: Regenerate.
548 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
550 * acconfig.h: Remove.
551 * config.in, configure: Regenerate.
553 2006-11-07 Thiemo Seufer <ths@mips.com>
555 * dsp.igen (do_w_op): Fix compiler warning.
557 2006-08-29 Thiemo Seufer <ths@mips.com>
558 David Ung <davidu@mips.com>
560 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
562 * configure: Regenerate.
563 * mips.igen (model): Add smartmips.
564 (MADDU): Increment ACX if carry.
565 (do_mult): Clear ACX.
566 (ROR,RORV): Add smartmips.
567 (include): Include smartmips.igen.
568 * sim-main.h (ACX): Set to REGISTERS[89].
569 * smartmips.igen: New file.
571 2006-08-29 Thiemo Seufer <ths@mips.com>
572 David Ung <davidu@mips.com>
574 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
575 mips3264r2.igen. Add missing dependency rules.
576 * m16e.igen: Support for mips16e save/restore instructions.
578 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
580 * configure: Regenerated.
582 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
584 * configure: Regenerated.
586 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
588 * configure: Regenerated.
590 2006-05-15 Chao-ying Fu <fu@mips.com>
592 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
594 2006-04-18 Nick Clifton <nickc@redhat.com>
596 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
599 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
601 * configure: Regenerate.
603 2005-12-14 Chao-ying Fu <fu@mips.com>
605 * Makefile.in (SIM_OBJS): Add dsp.o.
606 (dsp.o): New dependency.
607 (IGEN_INCLUDE): Add dsp.igen.
608 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
609 mipsisa64*-*-*): Add dsp to sim_igen_machine.
610 * configure: Regenerate.
611 * mips.igen: Add dsp model and include dsp.igen.
612 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
613 because these instructions are extended in DSP ASE.
614 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
615 adding 6 DSP accumulator registers and 1 DSP control register.
616 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
617 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
618 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
619 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
620 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
621 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
622 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
623 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
624 DSPCR_CCOND_SMASK): New define.
625 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
626 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
628 2005-07-08 Ian Lance Taylor <ian@airs.com>
630 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
632 2005-06-16 David Ung <davidu@mips.com>
633 Nigel Stephens <nigel@mips.com>
635 * mips.igen: New mips16e model and include m16e.igen.
636 (check_u64): Add mips16e tag.
637 * m16e.igen: New file for MIPS16e instructions.
638 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
639 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
641 * configure: Regenerate.
643 2005-05-26 David Ung <davidu@mips.com>
645 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
646 tags to all instructions which are applicable to the new ISAs.
647 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
649 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
651 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
653 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
654 * configure: Regenerate.
656 2005-03-23 Mark Kettenis <kettenis@gnu.org>
658 * configure: Regenerate.
660 2005-01-14 Andrew Cagney <cagney@gnu.org>
662 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
663 explicit call to AC_CONFIG_HEADER.
664 * configure: Regenerate.
666 2005-01-12 Andrew Cagney <cagney@gnu.org>
668 * configure.ac: Update to use ../common/common.m4.
669 * configure: Re-generate.
671 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
673 * configure: Regenerated to track ../common/aclocal.m4 changes.
675 2005-01-07 Andrew Cagney <cagney@gnu.org>
677 * configure.ac: Rename configure.in, require autoconf 2.59.
678 * configure: Re-generate.
680 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
682 * configure: Regenerate for ../common/aclocal.m4 update.
684 2004-09-24 Monika Chaddha <monika@acmet.com>
686 Committed by Andrew Cagney.
687 * m16.igen (CMP, CMPI): Fix assembler.
689 2004-08-18 Chris Demetriou <cgd@broadcom.com>
691 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
692 * configure: Regenerate.
694 2004-06-25 Chris Demetriou <cgd@broadcom.com>
696 * configure.in (sim_m16_machine): Include mipsIII.
697 * configure: Regenerate.
699 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
701 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
703 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
705 2004-04-10 Chris Demetriou <cgd@broadcom.com>
707 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
709 2004-04-09 Chris Demetriou <cgd@broadcom.com>
711 * mips.igen (check_fmt): Remove.
712 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
713 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
714 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
715 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
716 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
717 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
718 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
719 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
720 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
721 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
723 2004-04-09 Chris Demetriou <cgd@broadcom.com>
725 * sb1.igen (check_sbx): New function.
726 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
728 2004-03-29 Chris Demetriou <cgd@broadcom.com>
729 Richard Sandiford <rsandifo@redhat.com>
731 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
732 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
733 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
734 separate implementations for mipsIV and mipsV. Use new macros to
735 determine whether the restrictions apply.
737 2004-01-19 Chris Demetriou <cgd@broadcom.com>
739 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
740 (check_mult_hilo): Improve comments.
741 (check_div_hilo): Likewise. Also, fork off a new version
742 to handle mips32/mips64 (since there are no hazards to check
745 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
747 * mips.igen (do_dmultx): Fix check for negative operands.
749 2003-05-16 Ian Lance Taylor <ian@airs.com>
751 * Makefile.in (SHELL): Make sure this is defined.
752 (various): Use $(SHELL) whenever we invoke move-if-change.
754 2003-05-03 Chris Demetriou <cgd@broadcom.com>
756 * cp1.c: Tweak attribution slightly.
759 * mdmx.igen: Likewise.
760 * mips3d.igen: Likewise.
761 * sb1.igen: Likewise.
763 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
765 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
768 2003-02-27 Andrew Cagney <cagney@redhat.com>
770 * interp.c (sim_open): Rename _bfd to bfd.
771 (sim_create_inferior): Ditto.
773 2003-01-14 Chris Demetriou <cgd@broadcom.com>
775 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
777 2003-01-14 Chris Demetriou <cgd@broadcom.com>
779 * mips.igen (EI, DI): Remove.
781 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
783 * Makefile.in (tmp-run-multi): Fix mips16 filter.
785 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
786 Andrew Cagney <ac131313@redhat.com>
787 Gavin Romig-Koch <gavin@redhat.com>
788 Graydon Hoare <graydon@redhat.com>
789 Aldy Hernandez <aldyh@redhat.com>
790 Dave Brolley <brolley@redhat.com>
791 Chris Demetriou <cgd@broadcom.com>
793 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
794 (sim_mach_default): New variable.
795 (mips64vr-*-*, mips64vrel-*-*): New configurations.
796 Add a new simulator generator, MULTI.
797 * configure: Regenerate.
798 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
799 (multi-run.o): New dependency.
800 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
801 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
802 (tmp-multi): Combine them.
803 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
804 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
805 (distclean-extra): New rule.
806 * sim-main.h: Include bfd.h.
807 (MIPS_MACH): New macro.
808 * mips.igen (vr4120, vr5400, vr5500): New models.
809 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
810 * vr.igen: Replace with new version.
812 2003-01-04 Chris Demetriou <cgd@broadcom.com>
814 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
815 * configure: Regenerate.
817 2002-12-31 Chris Demetriou <cgd@broadcom.com>
819 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
820 * mips.igen: Remove all invocations of check_branch_bug and
823 2002-12-16 Chris Demetriou <cgd@broadcom.com>
825 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
827 2002-07-30 Chris Demetriou <cgd@broadcom.com>
829 * mips.igen (do_load_double, do_store_double): New functions.
830 (LDC1, SDC1): Rename to...
831 (LDC1b, SDC1b): respectively.
832 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
834 2002-07-29 Michael Snyder <msnyder@redhat.com>
836 * cp1.c (fp_recip2): Modify initialization expression so that
837 GCC will recognize it as constant.
839 2002-06-18 Chris Demetriou <cgd@broadcom.com>
841 * mdmx.c (SD_): Delete.
842 (Unpredictable): Re-define, for now, to directly invoke
843 unpredictable_action().
844 (mdmx_acc_op): Fix error in .ob immediate handling.
846 2002-06-18 Andrew Cagney <cagney@redhat.com>
848 * interp.c (sim_firmware_command): Initialize `address'.
850 2002-06-16 Andrew Cagney <ac131313@redhat.com>
852 * configure: Regenerated to track ../common/aclocal.m4 changes.
854 2002-06-14 Chris Demetriou <cgd@broadcom.com>
855 Ed Satterthwaite <ehs@broadcom.com>
857 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
858 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
859 * mips.igen: Include mips3d.igen.
860 (mips3d): New model name for MIPS-3D ASE instructions.
861 (CVT.W.fmt): Don't use this instruction for word (source) format
863 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
864 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
865 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
866 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
867 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
868 (RSquareRoot1, RSquareRoot2): New macros.
869 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
870 (fp_rsqrt2): New functions.
871 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
872 * configure: Regenerate.
874 2002-06-13 Chris Demetriou <cgd@broadcom.com>
875 Ed Satterthwaite <ehs@broadcom.com>
877 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
878 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
879 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
880 (convert): Note that this function is not used for paired-single
882 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
883 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
884 (check_fmt_p): Enable paired-single support.
885 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
886 (PUU.PS): New instructions.
887 (CVT.S.fmt): Don't use this instruction for paired-single format
889 * sim-main.h (FP_formats): New value 'fmt_ps.'
890 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
891 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
893 2002-06-12 Chris Demetriou <cgd@broadcom.com>
895 * mips.igen: Fix formatting of function calls in
898 2002-06-12 Chris Demetriou <cgd@broadcom.com>
900 * mips.igen (MOVN, MOVZ): Trace result.
901 (TNEI): Print "tnei" as the opcode name in traces.
902 (CEIL.W): Add disassembly string for traces.
903 (RSQRT.fmt): Make location of disassembly string consistent
904 with other instructions.
906 2002-06-12 Chris Demetriou <cgd@broadcom.com>
908 * mips.igen (X): Delete unused function.
910 2002-06-08 Andrew Cagney <cagney@redhat.com>
912 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
914 2002-06-07 Chris Demetriou <cgd@broadcom.com>
915 Ed Satterthwaite <ehs@broadcom.com>
917 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
918 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
919 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
920 (fp_nmsub): New prototypes.
921 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
922 (NegMultiplySub): New defines.
923 * mips.igen (RSQRT.fmt): Use RSquareRoot().
924 (MADD.D, MADD.S): Replace with...
925 (MADD.fmt): New instruction.
926 (MSUB.D, MSUB.S): Replace with...
927 (MSUB.fmt): New instruction.
928 (NMADD.D, NMADD.S): Replace with...
929 (NMADD.fmt): New instruction.
930 (NMSUB.D, MSUB.S): Replace with...
931 (NMSUB.fmt): New instruction.
933 2002-06-07 Chris Demetriou <cgd@broadcom.com>
934 Ed Satterthwaite <ehs@broadcom.com>
936 * cp1.c: Fix more comment spelling and formatting.
937 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
938 (denorm_mode): New function.
939 (fpu_unary, fpu_binary): Round results after operation, collect
940 status from rounding operations, and update the FCSR.
941 (convert): Collect status from integer conversions and rounding
942 operations, and update the FCSR. Adjust NaN values that result
943 from conversions. Convert to use sim_io_eprintf rather than
944 fprintf, and remove some debugging code.
945 * cp1.h (fenr_FS): New define.
947 2002-06-07 Chris Demetriou <cgd@broadcom.com>
949 * cp1.c (convert): Remove unusable debugging code, and move MIPS
950 rounding mode to sim FP rounding mode flag conversion code into...
951 (rounding_mode): New function.
953 2002-06-07 Chris Demetriou <cgd@broadcom.com>
955 * cp1.c: Clean up formatting of a few comments.
956 (value_fpr): Reformat switch statement.
958 2002-06-06 Chris Demetriou <cgd@broadcom.com>
959 Ed Satterthwaite <ehs@broadcom.com>
962 * sim-main.h: Include cp1.h.
963 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
964 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
965 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
966 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
967 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
968 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
969 * cp1.c: Don't include sim-fpu.h; already included by
970 sim-main.h. Clean up formatting of some comments.
971 (NaN, Equal, Less): Remove.
972 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
973 (fp_cmp): New functions.
974 * mips.igen (do_c_cond_fmt): Remove.
975 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
976 Compare. Add result tracing.
977 (CxC1): Remove, replace with...
978 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
979 (DMxC1): Remove, replace with...
980 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
981 (MxC1): Remove, replace with...
982 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
984 2002-06-04 Chris Demetriou <cgd@broadcom.com>
986 * sim-main.h (FGRIDX): Remove, replace all uses with...
987 (FGR_BASE): New macro.
988 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
989 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
990 (NR_FGR, FGR): Likewise.
991 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
992 * mips.igen: Likewise.
994 2002-06-04 Chris Demetriou <cgd@broadcom.com>
996 * cp1.c: Add an FSF Copyright notice to this file.
998 2002-06-04 Chris Demetriou <cgd@broadcom.com>
999 Ed Satterthwaite <ehs@broadcom.com>
1001 * cp1.c (Infinity): Remove.
1002 * sim-main.h (Infinity): Likewise.
1004 * cp1.c (fp_unary, fp_binary): New functions.
1005 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1006 (fp_sqrt): New functions, implemented in terms of the above.
1007 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1008 (Recip, SquareRoot): Remove (replaced by functions above).
1009 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1010 (fp_recip, fp_sqrt): New prototypes.
1011 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1012 (Recip, SquareRoot): Replace prototypes with #defines which
1013 invoke the functions above.
1015 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1017 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1018 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1019 file, remove PARAMS from prototypes.
1020 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1021 simulator state arguments.
1022 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1023 pass simulator state arguments.
1024 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1025 (store_fpr, convert): Remove 'sd' argument.
1026 (value_fpr): Likewise. Convert to use 'SD' instead.
1028 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1030 * cp1.c (Min, Max): Remove #if 0'd functions.
1031 * sim-main.h (Min, Max): Remove.
1033 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1035 * cp1.c: fix formatting of switch case and default labels.
1036 * interp.c: Likewise.
1037 * sim-main.c: Likewise.
1039 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1041 * cp1.c: Clean up comments which describe FP formats.
1042 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1044 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1045 Ed Satterthwaite <ehs@broadcom.com>
1047 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1048 Broadcom SiByte SB-1 processor configurations.
1049 * configure: Regenerate.
1050 * sb1.igen: New file.
1051 * mips.igen: Include sb1.igen.
1053 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1054 * mdmx.igen: Add "sb1" model to all appropriate functions and
1056 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1057 (ob_func, ob_acc): Reference the above.
1058 (qh_acc): Adjust to keep the same size as ob_acc.
1059 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1060 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1062 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1064 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1066 2002-06-02 Chris Demetriou <cgd@broadcom.com>
1067 Ed Satterthwaite <ehs@broadcom.com>
1069 * mips.igen (mdmx): New (pseudo-)model.
1070 * mdmx.c, mdmx.igen: New files.
1071 * Makefile.in (SIM_OBJS): Add mdmx.o.
1072 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1074 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1075 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1076 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1077 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1078 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1079 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1080 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1081 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1082 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1083 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1084 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1085 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1086 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1087 (qh_fmtsel): New macros.
1088 (_sim_cpu): New member "acc".
1089 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1090 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1092 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1094 * interp.c: Use 'deprecated' rather than 'depreciated.'
1095 * sim-main.h: Likewise.
1097 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1099 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1100 which wouldn't compile anyway.
1101 * sim-main.h (unpredictable_action): New function prototype.
1102 (Unpredictable): Define to call igen function unpredictable().
1103 (NotWordValue): New macro to call igen function not_word_value().
1104 (UndefinedResult): Remove.
1105 * interp.c (undefined_result): Remove.
1106 (unpredictable_action): New function.
1107 * mips.igen (not_word_value, unpredictable): New functions.
1108 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1109 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1110 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1111 NotWordValue() to check for unpredictable inputs, then
1112 Unpredictable() to handle them.
1114 2002-02-24 Chris Demetriou <cgd@broadcom.com>
1116 * mips.igen: Fix formatting of calls to Unpredictable().
1118 2002-04-20 Andrew Cagney <ac131313@redhat.com>
1120 * interp.c (sim_open): Revert previous change.
1122 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
1124 * interp.c (sim_open): Disable chunk of code that wrote code in
1125 vector table entries.
1127 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1129 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1130 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1133 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1135 * cp1.c: Fix many formatting issues.
1137 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1139 * cp1.c (fpu_format_name): New function to replace...
1140 (DOFMT): This. Delete, and update all callers.
1141 (fpu_rounding_mode_name): New function to replace...
1142 (RMMODE): This. Delete, and update all callers.
1144 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1146 * interp.c: Move FPU support routines from here to...
1147 * cp1.c: Here. New file.
1148 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1149 (cp1.o): New target.
1151 2002-03-12 Chris Demetriou <cgd@broadcom.com>
1153 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1154 * mips.igen (mips32, mips64): New models, add to all instructions
1155 and functions as appropriate.
1156 (loadstore_ea, check_u64): New variant for model mips64.
1157 (check_fmt_p): New variant for models mipsV and mips64, remove
1158 mipsV model marking fro other variant.
1161 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1162 for mips32 and mips64.
1163 (DCLO, DCLZ): New instructions for mips64.
1165 2002-03-07 Chris Demetriou <cgd@broadcom.com>
1167 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1168 immediate or code as a hex value with the "%#lx" format.
1169 (ANDI): Likewise, and fix printed instruction name.
1171 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1173 * sim-main.h (UndefinedResult, Unpredictable): New macros
1174 which currently do nothing.
1176 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1178 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1179 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1180 (status_CU3): New definitions.
1182 * sim-main.h (ExceptionCause): Add new values for MIPS32
1183 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1184 for DebugBreakPoint and NMIReset to note their status in
1186 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1187 (SignalExceptionCacheErr): New exception macros.
1189 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1191 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1192 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1194 (SignalExceptionCoProcessorUnusable): Take as argument the
1195 unusable coprocessor number.
1197 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1199 * mips.igen: Fix formatting of all SignalException calls.
1201 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1203 * sim-main.h (SIGNEXTEND): Remove.
1205 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1207 * mips.igen: Remove gencode comment from top of file, fix
1208 spelling in another comment.
1210 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1212 * mips.igen (check_fmt, check_fmt_p): New functions to check
1213 whether specific floating point formats are usable.
1214 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1215 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1216 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1217 Use the new functions.
1218 (do_c_cond_fmt): Remove format checks...
1219 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1221 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1223 * mips.igen: Fix formatting of check_fpu calls.
1225 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1227 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1229 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1231 * mips.igen: Remove whitespace at end of lines.
1233 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1235 * mips.igen (loadstore_ea): New function to do effective
1236 address calculations.
1237 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1238 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1239 CACHE): Use loadstore_ea to do effective address computations.
1241 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1243 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1244 * mips.igen (LL, CxC1, MxC1): Likewise.
1246 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1248 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1249 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1250 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1251 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1252 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1253 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1254 Don't split opcode fields by hand, use the opcode field values
1257 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1259 * mips.igen (do_divu): Fix spacing.
1261 * mips.igen (do_dsllv): Move to be right before DSLLV,
1262 to match the rest of the do_<shift> functions.
1264 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1266 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1267 DSRL32, do_dsrlv): Trace inputs and results.
1269 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1271 * mips.igen (CACHE): Provide instruction-printing string.
1273 * interp.c (signal_exception): Comment tokens after #endif.
1275 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1277 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1278 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1279 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1280 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1281 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1282 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1283 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1284 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1286 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1288 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1289 instruction-printing string.
1290 (LWU): Use '64' as the filter flag.
1292 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1294 * mips.igen (SDXC1): Fix instruction-printing string.
1296 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1298 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1299 filter flags "32,f".
1301 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1303 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1306 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1308 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1309 add a comma) so that it more closely match the MIPS ISA
1310 documentation opcode partitioning.
1311 (PREF): Put useful names on opcode fields, and include
1312 instruction-printing string.
1314 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1316 * mips.igen (check_u64): New function which in the future will
1317 check whether 64-bit instructions are usable and signal an
1318 exception if not. Currently a no-op.
1319 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1320 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1321 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1322 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1324 * mips.igen (check_fpu): New function which in the future will
1325 check whether FPU instructions are usable and signal an exception
1326 if not. Currently a no-op.
1327 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1328 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1329 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1330 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1331 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1332 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1333 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1334 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1336 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1338 * mips.igen (do_load_left, do_load_right): Move to be immediately
1340 (do_store_left, do_store_right): Move to be immediately following
1343 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1345 * mips.igen (mipsV): New model name. Also, add it to
1346 all instructions and functions where it is appropriate.
1348 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1350 * mips.igen: For all functions and instructions, list model
1351 names that support that instruction one per line.
1353 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1355 * mips.igen: Add some additional comments about supported
1356 models, and about which instructions go where.
1357 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1358 order as is used in the rest of the file.
1360 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1362 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1363 indicating that ALU32_END or ALU64_END are there to check
1365 (DADD): Likewise, but also remove previous comment about
1368 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1370 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1371 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1372 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1373 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1374 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1375 fields (i.e., add and move commas) so that they more closely
1376 match the MIPS ISA documentation opcode partitioning.
1378 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1380 * mips.igen (ADDI): Print immediate value.
1381 (BREAK): Print code.
1382 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1383 (SLL): Print "nop" specially, and don't run the code
1384 that does the shift for the "nop" case.
1386 2001-11-17 Fred Fish <fnf@redhat.com>
1388 * sim-main.h (float_operation): Move enum declaration outside
1389 of _sim_cpu struct declaration.
1391 2001-04-12 Jim Blandy <jimb@redhat.com>
1393 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1394 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1396 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1397 PENDING_FILL, and you can get the intended effect gracefully by
1398 calling PENDING_SCHED directly.
1400 2001-02-23 Ben Elliston <bje@redhat.com>
1402 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1403 already defined elsewhere.
1405 2001-02-19 Ben Elliston <bje@redhat.com>
1407 * sim-main.h (sim_monitor): Return an int.
1408 * interp.c (sim_monitor): Add return values.
1409 (signal_exception): Handle error conditions from sim_monitor.
1411 2001-02-08 Ben Elliston <bje@redhat.com>
1413 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1414 (store_memory): Likewise, pass cia to sim_core_write*.
1416 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1418 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1419 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1421 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1423 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1424 * Makefile.in: Don't delete *.igen when cleaning directory.
1426 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1428 * m16.igen (break): Call SignalException not sim_engine_halt.
1430 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1432 From Jason Eckhardt:
1433 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1435 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1437 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1439 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1441 * mips.igen (do_dmultx): Fix typo.
1443 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1445 * configure: Regenerated to track ../common/aclocal.m4 changes.
1447 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1449 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1451 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1453 * sim-main.h (GPR_CLEAR): Define macro.
1455 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1457 * interp.c (decode_coproc): Output long using %lx and not %s.
1459 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1461 * interp.c (sim_open): Sort & extend dummy memory regions for
1462 --board=jmr3904 for eCos.
1464 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1466 * configure: Regenerated.
1468 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1470 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1471 calls, conditional on the simulator being in verbose mode.
1473 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1475 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1476 cache don't get ReservedInstruction traps.
1478 1999-11-29 Mark Salter <msalter@cygnus.com>
1480 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1481 to clear status bits in sdisr register. This is how the hardware works.
1483 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1484 being used by cygmon.
1486 1999-11-11 Andrew Haley <aph@cygnus.com>
1488 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1491 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1493 * mips.igen (MULT): Correct previous mis-applied patch.
1495 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1497 * mips.igen (delayslot32): Handle sequence like
1498 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1499 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1500 (MULT): Actually pass the third register...
1502 1999-09-03 Mark Salter <msalter@cygnus.com>
1504 * interp.c (sim_open): Added more memory aliases for additional
1505 hardware being touched by cygmon on jmr3904 board.
1507 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1509 * configure: Regenerated to track ../common/aclocal.m4 changes.
1511 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1513 * interp.c (sim_store_register): Handle case where client - GDB -
1514 specifies that a 4 byte register is 8 bytes in size.
1515 (sim_fetch_register): Ditto.
1517 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1519 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1520 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1521 (idt_monitor_base): Base address for IDT monitor traps.
1522 (pmon_monitor_base): Ditto for PMON.
1523 (lsipmon_monitor_base): Ditto for LSI PMON.
1524 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1525 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1526 (sim_firmware_command): New function.
1527 (mips_option_handler): Call it for OPTION_FIRMWARE.
1528 (sim_open): Allocate memory for idt_monitor region. If "--board"
1529 option was given, add no monitor by default. Add BREAK hooks only if
1530 monitors are also there.
1532 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1534 * interp.c (sim_monitor): Flush output before reading input.
1536 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1538 * tconfig.in (SIM_HANDLES_LMA): Always define.
1540 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1542 From Mark Salter <msalter@cygnus.com>:
1543 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1544 (sim_open): Add setup for BSP board.
1546 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1548 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1549 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1550 them as unimplemented.
1552 1999-05-08 Felix Lee <flee@cygnus.com>
1554 * configure: Regenerated to track ../common/aclocal.m4 changes.
1556 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1558 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1560 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1562 * configure.in: Any mips64vr5*-*-* target should have
1563 -DTARGET_ENABLE_FR=1.
1564 (default_endian): Any mips64vr*el-*-* target should default to
1566 * configure: Re-generate.
1568 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1570 * mips.igen (ldl): Extend from _16_, not 32.
1572 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1574 * interp.c (sim_store_register): Force registers written to by GDB
1575 into an un-interpreted state.
1577 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1579 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1580 CPU, start periodic background I/O polls.
1581 (tx3904sio_poll): New function: periodic I/O poller.
1583 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1585 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1587 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1589 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1592 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1594 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1595 (load_word): Call SIM_CORE_SIGNAL hook on error.
1596 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1597 starting. For exception dispatching, pass PC instead of NULL_CIA.
1598 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1599 * sim-main.h (COP0_BADVADDR): Define.
1600 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1601 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1602 (_sim_cpu): Add exc_* fields to store register value snapshots.
1603 * mips.igen (*): Replace memory-related SignalException* calls
1604 with references to SIM_CORE_SIGNAL hook.
1606 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1608 * sim-main.c (*): Minor warning cleanups.
1610 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1612 * m16.igen (DADDIU5): Correct type-o.
1614 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1616 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1619 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1621 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1623 (interp.o): Add dependency on itable.h
1624 (oengine.c, gencode): Delete remaining references.
1625 (BUILT_SRC_FROM_GEN): Clean up.
1627 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1630 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1631 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1632 tmp-run-hack) : New.
1633 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1634 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1635 Drop the "64" qualifier to get the HACK generator working.
1636 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1637 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1638 qualifier to get the hack generator working.
1639 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1640 (DSLL): Use do_dsll.
1641 (DSLLV): Use do_dsllv.
1642 (DSRA): Use do_dsra.
1643 (DSRL): Use do_dsrl.
1644 (DSRLV): Use do_dsrlv.
1645 (BC1): Move *vr4100 to get the HACK generator working.
1646 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1647 get the HACK generator working.
1648 (MACC) Rename to get the HACK generator working.
1649 (DMACC,MACCS,DMACCS): Add the 64.
1651 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1653 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1654 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1656 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1658 * mips/interp.c (DEBUG): Cleanups.
1660 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1662 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1663 (tx3904sio_tickle): fflush after a stdout character output.
1665 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1667 * interp.c (sim_close): Uninstall modules.
1669 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1671 * sim-main.h, interp.c (sim_monitor): Change to global
1674 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676 * configure.in (vr4100): Only include vr4100 instructions in
1678 * configure: Re-generate.
1679 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1681 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1683 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1684 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1687 * configure.in (sim_default_gen, sim_use_gen): Replace with
1689 (--enable-sim-igen): Delete config option. Always using IGEN.
1690 * configure: Re-generate.
1692 * Makefile.in (gencode): Kill, kill, kill.
1695 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1697 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1698 bit mips16 igen simulator.
1699 * configure: Re-generate.
1701 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1702 as part of vr4100 ISA.
1703 * vr.igen: Mark all instructions as 64 bit only.
1705 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1707 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1710 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1712 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1713 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1714 * configure: Re-generate.
1716 * m16.igen (BREAK): Define breakpoint instruction.
1717 (JALX32): Mark instruction as mips16 and not r3900.
1718 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1720 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1722 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1724 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1725 insn as a debug breakpoint.
1727 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1729 (PENDING_SCHED): Clean up trace statement.
1730 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1731 (PENDING_FILL): Delay write by only one cycle.
1732 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1734 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1736 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1738 (pending_tick): Move incrementing of index to FOR statement.
1739 (pending_tick): Only update PENDING_OUT after a write has occured.
1741 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1743 * configure: Re-generate.
1745 * interp.c (sim_engine_run OLD): Delete explicit call to
1746 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1748 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1750 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1751 interrupt level number to match changed SignalExceptionInterrupt
1754 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1756 * interp.c: #include "itable.h" if WITH_IGEN.
1757 (get_insn_name): New function.
1758 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1759 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1761 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1763 * configure: Rebuilt to inhale new common/aclocal.m4.
1765 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1767 * dv-tx3904sio.c: Include sim-assert.h.
1769 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1771 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1772 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1773 Reorganize target-specific sim-hardware checks.
1774 * configure: rebuilt.
1775 * interp.c (sim_open): For tx39 target boards, set
1776 OPERATING_ENVIRONMENT, add tx3904sio devices.
1777 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1778 ROM executables. Install dv-sockser into sim-modules list.
1780 * dv-tx3904irc.c: Compiler warning clean-up.
1781 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1782 frequent hw-trace messages.
1784 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1788 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1790 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1792 * vr.igen: New file.
1793 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1794 * mips.igen: Define vr4100 model. Include vr.igen.
1795 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1797 * mips.igen (check_mf_hilo): Correct check.
1799 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1801 * sim-main.h (interrupt_event): Add prototype.
1803 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1804 register_ptr, register_value.
1805 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1807 * sim-main.h (tracefh): Make extern.
1809 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1811 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1812 Reduce unnecessarily high timer event frequency.
1813 * dv-tx3904cpu.c: Ditto for interrupt event.
1815 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1817 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1819 (interrupt_event): Made non-static.
1821 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1822 interchange of configuration values for external vs. internal
1825 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1827 * mips.igen (BREAK): Moved code to here for
1828 simulator-reserved break instructions.
1829 * gencode.c (build_instruction): Ditto.
1830 * interp.c (signal_exception): Code moved from here. Non-
1831 reserved instructions now use exception vector, rather
1833 * sim-main.h: Moved magic constants to here.
1835 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1837 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1838 register upon non-zero interrupt event level, clear upon zero
1840 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1841 by passing zero event value.
1842 (*_io_{read,write}_buffer): Endianness fixes.
1843 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1844 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1846 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1847 serial I/O and timer module at base address 0xFFFF0000.
1849 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1851 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1854 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1856 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1858 * configure: Update.
1860 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1862 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1863 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1864 * configure.in: Include tx3904tmr in hw_device list.
1865 * configure: Rebuilt.
1866 * interp.c (sim_open): Instantiate three timer instances.
1867 Fix address typo of tx3904irc instance.
1869 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1871 * interp.c (signal_exception): SystemCall exception now uses
1872 the exception vector.
1874 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1876 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1879 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1883 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1885 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1887 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1888 sim-main.h. Declare a struct hw_descriptor instead of struct
1889 hw_device_descriptor.
1891 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1893 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1894 right bits and then re-align left hand bytes to correct byte
1895 lanes. Fix incorrect computation in do_store_left when loading
1896 bytes from second word.
1898 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1900 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1901 * interp.c (sim_open): Only create a device tree when HW is
1904 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1905 * interp.c (signal_exception): Ditto.
1907 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1909 * gencode.c: Mark BEGEZALL as LIKELY.
1911 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1913 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1914 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1916 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1918 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1919 modules. Recognize TX39 target with "mips*tx39" pattern.
1920 * configure: Rebuilt.
1921 * sim-main.h (*): Added many macros defining bits in
1922 TX39 control registers.
1923 (SignalInterrupt): Send actual PC instead of NULL.
1924 (SignalNMIReset): New exception type.
1925 * interp.c (board): New variable for future use to identify
1926 a particular board being simulated.
1927 (mips_option_handler,mips_options): Added "--board" option.
1928 (interrupt_event): Send actual PC.
1929 (sim_open): Make memory layout conditional on board setting.
1930 (signal_exception): Initial implementation of hardware interrupt
1931 handling. Accept another break instruction variant for simulator
1933 (decode_coproc): Implement RFE instruction for TX39.
1934 (mips.igen): Decode RFE instruction as such.
1935 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1936 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1937 bbegin to implement memory map.
1938 * dv-tx3904cpu.c: New file.
1939 * dv-tx3904irc.c: New file.
1941 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1943 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1945 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1947 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1948 with calls to check_div_hilo.
1950 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1952 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1953 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1954 Add special r3900 version of do_mult_hilo.
1955 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1956 with calls to check_mult_hilo.
1957 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1958 with calls to check_div_hilo.
1960 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1962 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1963 Document a replacement.
1965 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1967 * interp.c (sim_monitor): Make mon_printf work.
1969 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1971 * sim-main.h (INSN_NAME): New arg `cpu'.
1973 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1975 * configure: Regenerated to track ../common/aclocal.m4 changes.
1977 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1979 * configure: Regenerated to track ../common/aclocal.m4 changes.
1982 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1984 * acconfig.h: New file.
1985 * configure.in: Reverted change of Apr 24; use sinclude again.
1987 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1989 * configure: Regenerated to track ../common/aclocal.m4 changes.
1992 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1994 * configure.in: Don't call sinclude.
1996 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1998 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2000 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2002 * mips.igen (ERET): Implement.
2004 * interp.c (decode_coproc): Return sign-extended EPC.
2006 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2008 * interp.c (signal_exception): Do not ignore Trap.
2009 (signal_exception): On TRAP, restart at exception address.
2010 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2011 (signal_exception): Update.
2012 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2013 so that TRAP instructions are caught.
2015 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2017 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2018 contains HI/LO access history.
2019 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2020 (HIACCESS, LOACCESS): Delete, replace with
2021 (HIHISTORY, LOHISTORY): New macros.
2022 (CHECKHILO): Delete all, moved to mips.igen
2024 * gencode.c (build_instruction): Do not generate checks for
2025 correct HI/LO register usage.
2027 * interp.c (old_engine_run): Delete checks for correct HI/LO
2030 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2031 check_mf_cycles): New functions.
2032 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2033 do_divu, domultx, do_mult, do_multu): Use.
2035 * tx.igen ("madd", "maddu"): Use.
2037 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2039 * mips.igen (DSRAV): Use function do_dsrav.
2040 (SRAV): Use new function do_srav.
2042 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2043 (B): Sign extend 11 bit immediate.
2044 (EXT-B*): Shift 16 bit immediate left by 1.
2045 (ADDIU*): Don't sign extend immediate value.
2047 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2049 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2051 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2054 * mips.igen (delayslot32, nullify_next_insn): New functions.
2055 (m16.igen): Always include.
2056 (do_*): Add more tracing.
2058 * m16.igen (delayslot16): Add NIA argument, could be called by a
2059 32 bit MIPS16 instruction.
2061 * interp.c (ifetch16): Move function from here.
2062 * sim-main.c (ifetch16): To here.
2064 * sim-main.c (ifetch16, ifetch32): Update to match current
2065 implementations of LH, LW.
2066 (signal_exception): Don't print out incorrect hex value of illegal
2069 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2071 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2074 * m16.igen: Implement MIPS16 instructions.
2076 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2077 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2078 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2079 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2080 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2081 bodies of corresponding code from 32 bit insn to these. Also used
2082 by MIPS16 versions of functions.
2084 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2085 (IMEM16): Drop NR argument from macro.
2087 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2089 * Makefile.in (SIM_OBJS): Add sim-main.o.
2091 * sim-main.h (address_translation, load_memory, store_memory,
2092 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2094 (pr_addr, pr_uword64): Declare.
2095 (sim-main.c): Include when H_REVEALS_MODULE_P.
2097 * interp.c (address_translation, load_memory, store_memory,
2098 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2100 * sim-main.c: To here. Fix compilation problems.
2102 * configure.in: Enable inlining.
2103 * configure: Re-config.
2105 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2107 * configure: Regenerated to track ../common/aclocal.m4 changes.
2109 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2111 * mips.igen: Include tx.igen.
2112 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2113 * tx.igen: New file, contains MADD and MADDU.
2115 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2116 the hardwired constant `7'.
2117 (store_memory): Ditto.
2118 (LOADDRMASK): Move definition to sim-main.h.
2120 mips.igen (MTC0): Enable for r3900.
2123 mips.igen (do_load_byte): Delete.
2124 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2125 do_store_right): New functions.
2126 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2128 configure.in: Let the tx39 use igen again.
2131 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2133 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2134 not an address sized quantity. Return zero for cache sizes.
2136 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2138 * mips.igen (r3900): r3900 does not support 64 bit integer
2141 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2143 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2145 * configure : Rebuild.
2147 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2149 * configure: Regenerated to track ../common/aclocal.m4 changes.
2151 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2153 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2155 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2157 * configure: Regenerated to track ../common/aclocal.m4 changes.
2158 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2160 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162 * configure: Regenerated to track ../common/aclocal.m4 changes.
2164 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2166 * interp.c (Max, Min): Comment out functions. Not yet used.
2168 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2170 * configure: Regenerated to track ../common/aclocal.m4 changes.
2172 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2174 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2175 configurable settings for stand-alone simulator.
2177 * configure.in: Added X11 search, just in case.
2179 * configure: Regenerated.
2181 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2183 * interp.c (sim_write, sim_read, load_memory, store_memory):
2184 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2186 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2188 * sim-main.h (GETFCC): Return an unsigned value.
2190 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2192 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2193 (DADD): Result destination is RD not RT.
2195 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2197 * sim-main.h (HIACCESS, LOACCESS): Always define.
2199 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2201 * interp.c (sim_info): Delete.
2203 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2205 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2206 (mips_option_handler): New argument `cpu'.
2207 (sim_open): Update call to sim_add_option_table.
2209 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2211 * mips.igen (CxC1): Add tracing.
2213 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2215 * sim-main.h (Max, Min): Declare.
2217 * interp.c (Max, Min): New functions.
2219 * mips.igen (BC1): Add tracing.
2221 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
2223 * interp.c Added memory map for stack in vr4100
2225 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2227 * interp.c (load_memory): Add missing "break"'s.
2229 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2231 * interp.c (sim_store_register, sim_fetch_register): Pass in
2232 length parameter. Return -1.
2234 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2236 * interp.c: Added hardware init hook, fixed warnings.
2238 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2240 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2242 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2244 * interp.c (ifetch16): New function.
2246 * sim-main.h (IMEM32): Rename IMEM.
2247 (IMEM16_IMMED): Define.
2249 (DELAY_SLOT): Update.
2251 * m16run.c (sim_engine_run): New file.
2253 * m16.igen: All instructions except LB.
2254 (LB): Call do_load_byte.
2255 * mips.igen (do_load_byte): New function.
2256 (LB): Call do_load_byte.
2258 * mips.igen: Move spec for insn bit size and high bit from here.
2259 * Makefile.in (tmp-igen, tmp-m16): To here.
2261 * m16.dc: New file, decode mips16 instructions.
2263 * Makefile.in (SIM_NO_ALL): Define.
2264 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2266 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2268 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2269 point unit to 32 bit registers.
2270 * configure: Re-generate.
2272 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2274 * configure.in (sim_use_gen): Make IGEN the default simulator
2275 generator for generic 32 and 64 bit mips targets.
2276 * configure: Re-generate.
2278 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2280 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2283 * interp.c (sim_fetch_register, sim_store_register): Read/write
2284 FGR from correct location.
2285 (sim_open): Set size of FGR's according to
2286 WITH_TARGET_FLOATING_POINT_BITSIZE.
2288 * sim-main.h (FGR): Store floating point registers in a separate
2291 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2293 * configure: Regenerated to track ../common/aclocal.m4 changes.
2295 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2297 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2299 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2301 * interp.c (pending_tick): New function. Deliver pending writes.
2303 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2304 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2305 it can handle mixed sized quantites and single bits.
2307 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2309 * interp.c (oengine.h): Do not include when building with IGEN.
2310 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2311 (sim_info): Ditto for PROCESSOR_64BIT.
2312 (sim_monitor): Replace ut_reg with unsigned_word.
2313 (*): Ditto for t_reg.
2314 (LOADDRMASK): Define.
2315 (sim_open): Remove defunct check that host FP is IEEE compliant,
2316 using software to emulate floating point.
2317 (value_fpr, ...): Always compile, was conditional on HASFPU.
2319 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2321 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2324 * interp.c (SD, CPU): Define.
2325 (mips_option_handler): Set flags in each CPU.
2326 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2327 (sim_close): Do not clear STATE, deleted anyway.
2328 (sim_write, sim_read): Assume CPU zero's vm should be used for
2330 (sim_create_inferior): Set the PC for all processors.
2331 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2333 (mips16_entry): Pass correct nr of args to store_word, load_word.
2334 (ColdReset): Cold reset all cpu's.
2335 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2336 (sim_monitor, load_memory, store_memory, signal_exception): Use
2337 `CPU' instead of STATE_CPU.
2340 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2343 * sim-main.h (signal_exception): Add sim_cpu arg.
2344 (SignalException*): Pass both SD and CPU to signal_exception.
2345 * interp.c (signal_exception): Update.
2347 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2349 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2350 address_translation): Ditto
2351 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2353 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2355 * configure: Regenerated to track ../common/aclocal.m4 changes.
2357 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2359 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2361 * mips.igen (model): Map processor names onto BFD name.
2363 * sim-main.h (CPU_CIA): Delete.
2364 (SET_CIA, GET_CIA): Define
2366 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2368 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2371 * configure.in (default_endian): Configure a big-endian simulator
2373 * configure: Re-generate.
2375 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2377 * configure: Regenerated to track ../common/aclocal.m4 changes.
2379 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2381 * interp.c (sim_monitor): Handle Densan monitor outbyte
2382 and inbyte functions.
2384 1997-12-29 Felix Lee <flee@cygnus.com>
2386 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2388 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2390 * Makefile.in (tmp-igen): Arrange for $zero to always be
2391 reset to zero after every instruction.
2393 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2395 * configure: Regenerated to track ../common/aclocal.m4 changes.
2398 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2400 * mips.igen (MSUB): Fix to work like MADD.
2401 * gencode.c (MSUB): Similarly.
2403 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2405 * configure: Regenerated to track ../common/aclocal.m4 changes.
2407 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2409 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2411 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2413 * sim-main.h (sim-fpu.h): Include.
2415 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2416 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2417 using host independant sim_fpu module.
2419 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2421 * interp.c (signal_exception): Report internal errors with SIGABRT
2424 * sim-main.h (C0_CONFIG): New register.
2425 (signal.h): No longer include.
2427 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2429 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2431 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2433 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2435 * mips.igen: Tag vr5000 instructions.
2436 (ANDI): Was missing mipsIV model, fix assembler syntax.
2437 (do_c_cond_fmt): New function.
2438 (C.cond.fmt): Handle mips I-III which do not support CC field
2440 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2441 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2443 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2444 vr5000 which saves LO in a GPR separatly.
2446 * configure.in (enable-sim-igen): For vr5000, select vr5000
2447 specific instructions.
2448 * configure: Re-generate.
2450 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2452 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2454 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2455 fmt_uninterpreted_64 bit cases to switch. Convert to
2458 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2460 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2461 as specified in IV3.2 spec.
2462 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2464 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2466 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2467 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2468 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2469 PENDING_FILL versions of instructions. Simplify.
2471 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2473 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2475 (MTHI, MFHI): Disable code checking HI-LO.
2477 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2479 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2481 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2483 * gencode.c (build_mips16_operands): Replace IPC with cia.
2485 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2486 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2488 (UndefinedResult): Replace function with macro/function
2490 (sim_engine_run): Don't save PC in IPC.
2492 * sim-main.h (IPC): Delete.
2495 * interp.c (signal_exception, store_word, load_word,
2496 address_translation, load_memory, store_memory, cache_op,
2497 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2498 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2499 current instruction address - cia - argument.
2500 (sim_read, sim_write): Call address_translation directly.
2501 (sim_engine_run): Rename variable vaddr to cia.
2502 (signal_exception): Pass cia to sim_monitor
2504 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2505 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2506 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2508 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2509 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2512 * interp.c (signal_exception): Pass restart address to
2515 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2516 idecode.o): Add dependency.
2518 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2520 (DELAY_SLOT): Update NIA not PC with branch address.
2521 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2523 * mips.igen: Use CIA not PC in branch calculations.
2524 (illegal): Call SignalException.
2525 (BEQ, ADDIU): Fix assembler.
2527 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2529 * m16.igen (JALX): Was missing.
2531 * configure.in (enable-sim-igen): New configuration option.
2532 * configure: Re-generate.
2534 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2536 * interp.c (load_memory, store_memory): Delete parameter RAW.
2537 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2538 bypassing {load,store}_memory.
2540 * sim-main.h (ByteSwapMem): Delete definition.
2542 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2544 * interp.c (sim_do_command, sim_commands): Delete mips specific
2545 commands. Handled by module sim-options.
2547 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2548 (WITH_MODULO_MEMORY): Define.
2550 * interp.c (sim_info): Delete code printing memory size.
2552 * interp.c (mips_size): Nee sim_size, delete function.
2554 (monitor, monitor_base, monitor_size): Delete global variables.
2555 (sim_open, sim_close): Delete code creating monitor and other
2556 memory regions. Use sim-memopts module, via sim_do_commandf, to
2557 manage memory regions.
2558 (load_memory, store_memory): Use sim-core for memory model.
2560 * interp.c (address_translation): Delete all memory map code
2561 except line forcing 32 bit addresses.
2563 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2565 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2568 * interp.c (logfh, logfile): Delete globals.
2569 (sim_open, sim_close): Delete code opening & closing log file.
2570 (mips_option_handler): Delete -l and -n options.
2571 (OPTION mips_options): Ditto.
2573 * interp.c (OPTION mips_options): Rename option trace to dinero.
2574 (mips_option_handler): Update.
2576 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2578 * interp.c (fetch_str): New function.
2579 (sim_monitor): Rewrite using sim_read & sim_write.
2580 (sim_open): Check magic number.
2581 (sim_open): Write monitor vectors into memory using sim_write.
2582 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2583 (sim_read, sim_write): Simplify - transfer data one byte at a
2585 (load_memory, store_memory): Clarify meaning of parameter RAW.
2587 * sim-main.h (isHOST): Defete definition.
2588 (isTARGET): Mark as depreciated.
2589 (address_translation): Delete parameter HOST.
2591 * interp.c (address_translation): Delete parameter HOST.
2593 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2597 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2598 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2600 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2602 * mips.igen: Add model filter field to records.
2604 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2606 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2608 interp.c (sim_engine_run): Do not compile function sim_engine_run
2609 when WITH_IGEN == 1.
2611 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2612 target architecture.
2614 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2615 igen. Replace with configuration variables sim_igen_flags /
2618 * m16.igen: New file. Copy mips16 insns here.
2619 * mips.igen: From here.
2621 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2623 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2625 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2627 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2629 * gencode.c (build_instruction): Follow sim_write's lead in using
2630 BigEndianMem instead of !ByteSwapMem.
2632 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2634 * configure.in (sim_gen): Dependent on target, select type of
2635 generator. Always select old style generator.
2637 configure: Re-generate.
2639 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2641 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2642 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2643 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2644 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2645 SIM_@sim_gen@_*, set by autoconf.
2647 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2649 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2651 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2652 CURRENT_FLOATING_POINT instead.
2654 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2655 (address_translation): Raise exception InstructionFetch when
2656 translation fails and isINSTRUCTION.
2658 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2659 sim_engine_run): Change type of of vaddr and paddr to
2661 (address_translation, prefetch, load_memory, store_memory,
2662 cache_op): Change type of vAddr and pAddr to address_word.
2664 * gencode.c (build_instruction): Change type of vaddr and paddr to
2667 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2669 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2670 macro to obtain result of ALU op.
2672 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2674 * interp.c (sim_info): Call profile_print.
2676 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2678 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2680 * sim-main.h (WITH_PROFILE): Do not define, defined in
2681 common/sim-config.h. Use sim-profile module.
2682 (simPROFILE): Delete defintion.
2684 * interp.c (PROFILE): Delete definition.
2685 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2686 (sim_close): Delete code writing profile histogram.
2687 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2689 (sim_engine_run): Delete code profiling the PC.
2691 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2693 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2695 * interp.c (sim_monitor): Make register pointers of type
2698 * sim-main.h: Make registers of type unsigned_word not
2701 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2703 * interp.c (sync_operation): Rename from SyncOperation, make
2704 global, add SD argument.
2705 (prefetch): Rename from Prefetch, make global, add SD argument.
2706 (decode_coproc): Make global.
2708 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2710 * gencode.c (build_instruction): Generate DecodeCoproc not
2711 decode_coproc calls.
2713 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2714 (SizeFGR): Move to sim-main.h
2715 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2716 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2717 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2719 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2720 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2721 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2722 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2723 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2724 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2726 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2728 (sim-alu.h): Include.
2729 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2730 (sim_cia): Typedef to instruction_address.
2732 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2734 * Makefile.in (interp.o): Rename generated file engine.c to
2739 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2741 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2743 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2745 * gencode.c (build_instruction): For "FPSQRT", output correct
2746 number of arguments to Recip.
2748 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2750 * Makefile.in (interp.o): Depends on sim-main.h
2752 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2754 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2755 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2756 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2757 STATE, DSSTATE): Define
2758 (GPR, FGRIDX, ..): Define.
2760 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2761 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2762 (GPR, FGRIDX, ...): Delete macros.
2764 * interp.c: Update names to match defines from sim-main.h
2766 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2768 * interp.c (sim_monitor): Add SD argument.
2769 (sim_warning): Delete. Replace calls with calls to
2771 (sim_error): Delete. Replace calls with sim_io_error.
2772 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2773 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2774 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2776 (mips_size): Rename from sim_size. Add SD argument.
2778 * interp.c (simulator): Delete global variable.
2779 (callback): Delete global variable.
2780 (mips_option_handler, sim_open, sim_write, sim_read,
2781 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2782 sim_size,sim_monitor): Use sim_io_* not callback->*.
2783 (sim_open): ZALLOC simulator struct.
2784 (PROFILE): Do not define.
2786 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2788 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2789 support.h with corresponding code.
2791 * sim-main.h (word64, uword64), support.h: Move definition to
2793 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2796 * Makefile.in: Update dependencies
2797 * interp.c: Do not include.
2799 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2801 * interp.c (address_translation, load_memory, store_memory,
2802 cache_op): Rename to from AddressTranslation et.al., make global,
2805 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2808 * interp.c (SignalException): Rename to signal_exception, make
2811 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2813 * sim-main.h (SignalException, SignalExceptionInterrupt,
2814 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2815 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2816 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2819 * interp.c, support.h: Use.
2821 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2823 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2824 to value_fpr / store_fpr. Add SD argument.
2825 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2826 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2828 * sim-main.h (ValueFPR, StoreFPR): Define.
2830 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2832 * interp.c (sim_engine_run): Check consistency between configure
2833 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2836 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2837 (mips_fpu): Configure WITH_FLOATING_POINT.
2838 (mips_endian): Configure WITH_TARGET_ENDIAN.
2839 * configure: Update.
2841 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2843 * configure: Regenerated to track ../common/aclocal.m4 changes.
2845 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2847 * configure: Regenerated.
2849 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2851 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2853 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2855 * gencode.c (print_igen_insn_models): Assume certain architectures
2856 include all mips* instructions.
2857 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2860 * Makefile.in (tmp.igen): Add target. Generate igen input from
2863 * gencode.c (FEATURE_IGEN): Define.
2864 (main): Add --igen option. Generate output in igen format.
2865 (process_instructions): Format output according to igen option.
2866 (print_igen_insn_format): New function.
2867 (print_igen_insn_models): New function.
2868 (process_instructions): Only issue warnings and ignore
2869 instructions when no FEATURE_IGEN.
2871 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2873 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2876 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2878 * configure: Regenerated to track ../common/aclocal.m4 changes.
2880 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2882 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2883 SIM_RESERVED_BITS): Delete, moved to common.
2884 (SIM_EXTRA_CFLAGS): Update.
2886 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2888 * configure.in: Configure non-strict memory alignment.
2889 * configure: Regenerated to track ../common/aclocal.m4 changes.
2891 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2893 * configure: Regenerated to track ../common/aclocal.m4 changes.
2895 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2897 * gencode.c (SDBBP,DERET): Added (3900) insns.
2898 (RFE): Turn on for 3900.
2899 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2900 (dsstate): Made global.
2901 (SUBTARGET_R3900): Added.
2902 (CANCELDELAYSLOT): New.
2903 (SignalException): Ignore SystemCall rather than ignore and
2904 terminate. Add DebugBreakPoint handling.
2905 (decode_coproc): New insns RFE, DERET; and new registers Debug
2906 and DEPC protected by SUBTARGET_R3900.
2907 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2909 * Makefile.in,configure.in: Add mips subtarget option.
2910 * configure: Update.
2912 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2914 * gencode.c: Add r3900 (tx39).
2917 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2919 * gencode.c (build_instruction): Don't need to subtract 4 for
2922 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2924 * interp.c: Correct some HASFPU problems.
2926 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2928 * configure: Regenerated to track ../common/aclocal.m4 changes.
2930 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2932 * interp.c (mips_options): Fix samples option short form, should
2935 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2937 * interp.c (sim_info): Enable info code. Was just returning.
2939 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2941 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2944 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2946 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2948 (build_instruction): Ditto for LL.
2950 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2952 * configure: Regenerated to track ../common/aclocal.m4 changes.
2954 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2956 * configure: Regenerated to track ../common/aclocal.m4 changes.
2959 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2961 * interp.c (sim_open): Add call to sim_analyze_program, update
2964 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2966 * interp.c (sim_kill): Delete.
2967 (sim_create_inferior): Add ABFD argument. Set PC from same.
2968 (sim_load): Move code initializing trap handlers from here.
2969 (sim_open): To here.
2970 (sim_load): Delete, use sim-hload.c.
2972 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2974 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2976 * configure: Regenerated to track ../common/aclocal.m4 changes.
2979 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2981 * interp.c (sim_open): Add ABFD argument.
2982 (sim_load): Move call to sim_config from here.
2983 (sim_open): To here. Check return status.
2985 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2987 * gencode.c (build_instruction): Two arg MADD should
2988 not assign result to $0.
2990 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2992 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2993 * sim/mips/configure.in: Regenerate.
2995 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2997 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2998 signed8, unsigned8 et.al. types.
3000 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3001 hosts when selecting subreg.
3003 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3005 * interp.c (sim_engine_run): Reset the ZERO register to zero
3006 regardless of FEATURE_WARN_ZERO.
3007 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3009 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3011 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3012 (SignalException): For BreakPoints ignore any mode bits and just
3014 (SignalException): Always set the CAUSE register.
3016 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3018 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3019 exception has been taken.
3021 * interp.c: Implement the ERET and mt/f sr instructions.
3023 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3025 * interp.c (SignalException): Don't bother restarting an
3028 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030 * interp.c (SignalException): Really take an interrupt.
3031 (interrupt_event): Only deliver interrupts when enabled.
3033 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3035 * interp.c (sim_info): Only print info when verbose.
3036 (sim_info) Use sim_io_printf for output.
3038 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3040 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3043 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3045 * interp.c (sim_do_command): Check for common commands if a
3046 simulator specific command fails.
3048 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3050 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3051 and simBE when DEBUG is defined.
3053 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3055 * interp.c (interrupt_event): New function. Pass exception event
3056 onto exception handler.
3058 * configure.in: Check for stdlib.h.
3059 * configure: Regenerate.
3061 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3062 variable declaration.
3063 (build_instruction): Initialize memval1.
3064 (build_instruction): Add UNUSED attribute to byte, bigend,
3066 (build_operands): Ditto.
3068 * interp.c: Fix GCC warnings.
3069 (sim_get_quit_code): Delete.
3071 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3072 * Makefile.in: Ditto.
3073 * configure: Re-generate.
3075 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3077 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3079 * interp.c (mips_option_handler): New function parse argumes using
3081 (myname): Replace with STATE_MY_NAME.
3082 (sim_open): Delete check for host endianness - performed by
3084 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3085 (sim_open): Move much of the initialization from here.
3086 (sim_load): To here. After the image has been loaded and
3088 (sim_open): Move ColdReset from here.
3089 (sim_create_inferior): To here.
3090 (sim_open): Make FP check less dependant on host endianness.
3092 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3094 * interp.c (sim_set_callbacks): Delete.
3096 * interp.c (membank, membank_base, membank_size): Replace with
3097 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3098 (sim_open): Remove call to callback->init. gdb/run do this.
3102 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3104 * interp.c (big_endian_p): Delete, replaced by
3105 current_target_byte_order.
3107 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3109 * interp.c (host_read_long, host_read_word, host_swap_word,
3110 host_swap_long): Delete. Using common sim-endian.
3111 (sim_fetch_register, sim_store_register): Use H2T.
3112 (pipeline_ticks): Delete. Handled by sim-events.
3114 (sim_engine_run): Update.
3116 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3118 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3120 (SignalException): To here. Signal using sim_engine_halt.
3121 (sim_stop_reason): Delete, moved to common.
3123 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3125 * interp.c (sim_open): Add callback argument.
3126 (sim_set_callbacks): Delete SIM_DESC argument.
3129 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3131 * Makefile.in (SIM_OBJS): Add common modules.
3133 * interp.c (sim_set_callbacks): Also set SD callback.
3134 (set_endianness, xfer_*, swap_*): Delete.
3135 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3136 Change to functions using sim-endian macros.
3137 (control_c, sim_stop): Delete, use common version.
3138 (simulate): Convert into.
3139 (sim_engine_run): This function.
3140 (sim_resume): Delete.
3142 * interp.c (simulation): New variable - the simulator object.
3143 (sim_kind): Delete global - merged into simulation.
3144 (sim_load): Cleanup. Move PC assignment from here.
3145 (sim_create_inferior): To here.
3147 * sim-main.h: New file.
3148 * interp.c (sim-main.h): Include.
3150 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3152 * configure: Regenerated to track ../common/aclocal.m4 changes.
3154 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3156 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3158 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3160 * gencode.c (build_instruction): DIV instructions: check
3161 for division by zero and integer overflow before using
3162 host's division operation.
3164 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3166 * Makefile.in (SIM_OBJS): Add sim-load.o.
3167 * interp.c: #include bfd.h.
3168 (target_byte_order): Delete.
3169 (sim_kind, myname, big_endian_p): New static locals.
3170 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3171 after argument parsing. Recognize -E arg, set endianness accordingly.
3172 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3173 load file into simulator. Set PC from bfd.
3174 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3175 (set_endianness): Use big_endian_p instead of target_byte_order.
3177 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3179 * interp.c (sim_size): Delete prototype - conflicts with
3180 definition in remote-sim.h. Correct definition.
3182 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3184 * configure: Regenerated to track ../common/aclocal.m4 changes.
3187 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3189 * interp.c (sim_open): New arg `kind'.
3191 * configure: Regenerated to track ../common/aclocal.m4 changes.
3193 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3195 * configure: Regenerated to track ../common/aclocal.m4 changes.
3197 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3199 * interp.c (sim_open): Set optind to 0 before calling getopt.
3201 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3203 * configure: Regenerated to track ../common/aclocal.m4 changes.
3205 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3207 * interp.c : Replace uses of pr_addr with pr_uword64
3208 where the bit length is always 64 independent of SIM_ADDR.
3209 (pr_uword64) : added.
3211 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3213 * configure: Re-generate.
3215 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3217 * configure: Regenerate to track ../common/aclocal.m4 changes.
3219 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3221 * interp.c (sim_open): New SIM_DESC result. Argument is now
3223 (other sim_*): New SIM_DESC argument.
3225 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3227 * interp.c: Fix printing of addresses for non-64-bit targets.
3228 (pr_addr): Add function to print address based on size.
3230 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3232 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3234 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3236 * gencode.c (build_mips16_operands): Correct computation of base
3237 address for extended PC relative instruction.
3239 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3241 * interp.c (mips16_entry): Add support for floating point cases.
3242 (SignalException): Pass floating point cases to mips16_entry.
3243 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3245 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3247 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3248 and then set the state to fmt_uninterpreted.
3249 (COP_SW): Temporarily set the state to fmt_word while calling
3252 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3254 * gencode.c (build_instruction): The high order may be set in the
3255 comparison flags at any ISA level, not just ISA 4.
3257 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3259 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3260 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3261 * configure.in: sinclude ../common/aclocal.m4.
3262 * configure: Regenerated.
3264 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3266 * configure: Rebuild after change to aclocal.m4.
3268 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3270 * configure configure.in Makefile.in: Update to new configure
3271 scheme which is more compatible with WinGDB builds.
3272 * configure.in: Improve comment on how to run autoconf.
3273 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3274 * Makefile.in: Use autoconf substitution to install common
3277 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3279 * gencode.c (build_instruction): Use BigEndianCPU instead of
3282 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3284 * interp.c (sim_monitor): Make output to stdout visible in
3285 wingdb's I/O log window.
3287 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3289 * support.h: Undo previous change to SIGTRAP
3292 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3294 * interp.c (store_word, load_word): New static functions.
3295 (mips16_entry): New static function.
3296 (SignalException): Look for mips16 entry and exit instructions.
3297 (simulate): Use the correct index when setting fpr_state after
3298 doing a pending move.
3300 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3302 * interp.c: Fix byte-swapping code throughout to work on
3303 both little- and big-endian hosts.
3305 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3307 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3308 with gdb/config/i386/xm-windows.h.
3310 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3312 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3313 that messes up arithmetic shifts.
3315 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3317 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3318 SIGTRAP and SIGQUIT for _WIN32.
3320 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3322 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3323 force a 64 bit multiplication.
3324 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3325 destination register is 0, since that is the default mips16 nop
3328 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3330 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3331 (build_endian_shift): Don't check proc64.
3332 (build_instruction): Always set memval to uword64. Cast op2 to
3333 uword64 when shifting it left in memory instructions. Always use
3334 the same code for stores--don't special case proc64.
3336 * gencode.c (build_mips16_operands): Fix base PC value for PC
3338 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3340 * interp.c (simJALDELAYSLOT): Define.
3341 (JALDELAYSLOT): Define.
3342 (INDELAYSLOT, INJALDELAYSLOT): Define.
3343 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3345 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3347 * interp.c (sim_open): add flush_cache as a PMON routine
3348 (sim_monitor): handle flush_cache by ignoring it
3350 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3352 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3354 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3355 (BigEndianMem): Rename to ByteSwapMem and change sense.
3356 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3357 BigEndianMem references to !ByteSwapMem.
3358 (set_endianness): New function, with prototype.
3359 (sim_open): Call set_endianness.
3360 (sim_info): Use simBE instead of BigEndianMem.
3361 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3362 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3363 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3364 ifdefs, keeping the prototype declaration.
3365 (swap_word): Rewrite correctly.
3366 (ColdReset): Delete references to CONFIG. Delete endianness related
3367 code; moved to set_endianness.
3369 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3371 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3372 * interp.c (CHECKHILO): Define away.
3373 (simSIGINT): New macro.
3374 (membank_size): Increase from 1MB to 2MB.
3375 (control_c): New function.
3376 (sim_resume): Rename parameter signal to signal_number. Add local
3377 variable prev. Call signal before and after simulate.
3378 (sim_stop_reason): Add simSIGINT support.
3379 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3381 (sim_warning): Delete call to SignalException. Do call printf_filtered
3383 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3384 a call to sim_warning.
3386 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3388 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3389 16 bit instructions.
3391 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3393 Add support for mips16 (16 bit MIPS implementation):
3394 * gencode.c (inst_type): Add mips16 instruction encoding types.
3395 (GETDATASIZEINSN): Define.
3396 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3397 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3399 (MIPS16_DECODE): New table, for mips16 instructions.
3400 (bitmap_val): New static function.
3401 (struct mips16_op): Define.
3402 (mips16_op_table): New table, for mips16 operands.
3403 (build_mips16_operands): New static function.
3404 (process_instructions): If PC is odd, decode a mips16
3405 instruction. Break out instruction handling into new
3406 build_instruction function.
3407 (build_instruction): New static function, broken out of
3408 process_instructions. Check modifiers rather than flags for SHIFT
3409 bit count and m[ft]{hi,lo} direction.
3410 (usage): Pass program name to fprintf.
3411 (main): Remove unused variable this_option_optind. Change
3412 ``*loptarg++'' to ``loptarg++''.
3413 (my_strtoul): Parenthesize && within ||.
3414 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3415 (simulate): If PC is odd, fetch a 16 bit instruction, and
3416 increment PC by 2 rather than 4.
3417 * configure.in: Add case for mips16*-*-*.
3418 * configure: Rebuild.
3420 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3422 * interp.c: Allow -t to enable tracing in standalone simulator.
3423 Fix garbage output in trace file and error messages.
3425 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3427 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3428 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3429 * configure.in: Simplify using macros in ../common/aclocal.m4.
3430 * configure: Regenerated.
3431 * tconfig.in: New file.
3433 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3435 * interp.c: Fix bugs in 64-bit port.
3436 Use ansi function declarations for msvc compiler.
3437 Initialize and test file pointer in trace code.
3438 Prevent duplicate definition of LAST_EMED_REGNUM.
3440 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3442 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3444 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3446 * interp.c (SignalException): Check for explicit terminating
3448 * gencode.c: Pass instruction value through SignalException()
3449 calls for Trap, Breakpoint and Syscall.
3451 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3453 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3454 only used on those hosts that provide it.
3455 * configure.in: Add sqrt() to list of functions to be checked for.
3456 * config.in: Re-generated.
3457 * configure: Re-generated.
3459 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3461 * gencode.c (process_instructions): Call build_endian_shift when
3462 expanding STORE RIGHT, to fix swr.
3463 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3464 clear the high bits.
3465 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3466 Fix float to int conversions to produce signed values.
3468 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3470 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3471 (process_instructions): Correct handling of nor instruction.
3472 Correct shift count for 32 bit shift instructions. Correct sign
3473 extension for arithmetic shifts to not shift the number of bits in
3474 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3475 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3477 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3478 It's OK to have a mult follow a mult. What's not OK is to have a
3479 mult follow an mfhi.
3480 (Convert): Comment out incorrect rounding code.
3482 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3484 * interp.c (sim_monitor): Improved monitor printf
3485 simulation. Tidied up simulator warnings, and added "--log" option
3486 for directing warning message output.
3487 * gencode.c: Use sim_warning() rather than WARNING macro.
3489 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3491 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3492 getopt1.o, rather than on gencode.c. Link objects together.
3493 Don't link against -liberty.
3494 (gencode.o, getopt.o, getopt1.o): New targets.
3495 * gencode.c: Include <ctype.h> and "ansidecl.h".
3496 (AND): Undefine after including "ansidecl.h".
3497 (ULONG_MAX): Define if not defined.
3498 (OP_*): Don't define macros; now defined in opcode/mips.h.
3499 (main): Call my_strtoul rather than strtoul.
3500 (my_strtoul): New static function.
3502 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3504 * gencode.c (process_instructions): Generate word64 and uword64
3505 instead of `long long' and `unsigned long long' data types.
3506 * interp.c: #include sysdep.h to get signals, and define default
3508 * (Convert): Work around for Visual-C++ compiler bug with type
3510 * support.h: Make things compile under Visual-C++ by using
3511 __int64 instead of `long long'. Change many refs to long long
3512 into word64/uword64 typedefs.
3514 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3516 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3517 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3519 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3520 (AC_PROG_INSTALL): Added.
3521 (AC_PROG_CC): Moved to before configure.host call.
3522 * configure: Rebuilt.
3524 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3526 * configure.in: Define @SIMCONF@ depending on mips target.
3527 * configure: Rebuild.
3528 * Makefile.in (run): Add @SIMCONF@ to control simulator
3530 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3531 * interp.c: Remove some debugging, provide more detailed error
3532 messages, update memory accesses to use LOADDRMASK.
3534 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3536 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3537 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3539 * configure: Rebuild.
3540 * config.in: New file, generated by autoheader.
3541 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3542 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3543 HAVE_ANINT and HAVE_AINT, as appropriate.
3544 * Makefile.in (run): Use @LIBS@ rather than -lm.
3545 (interp.o): Depend upon config.h.
3546 (Makefile): Just rebuild Makefile.
3547 (clean): Remove stamp-h.
3548 (mostlyclean): Make the same as clean, not as distclean.
3549 (config.h, stamp-h): New targets.
3551 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3553 * interp.c (ColdReset): Fix boolean test. Make all simulator
3556 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3558 * interp.c (xfer_direct_word, xfer_direct_long,
3559 swap_direct_word, swap_direct_long, xfer_big_word,
3560 xfer_big_long, xfer_little_word, xfer_little_long,
3561 swap_word,swap_long): Added.
3562 * interp.c (ColdReset): Provide function indirection to
3563 host<->simulated_target transfer routines.
3564 * interp.c (sim_store_register, sim_fetch_register): Updated to
3565 make use of indirected transfer routines.
3567 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3569 * gencode.c (process_instructions): Ensure FP ABS instruction
3571 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3572 system call support.
3574 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3576 * interp.c (sim_do_command): Complain if callback structure not
3579 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3581 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3582 support for Sun hosts.
3583 * Makefile.in (gencode): Ensure the host compiler and libraries
3584 used for cross-hosted build.
3586 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3588 * interp.c, gencode.c: Some more (TODO) tidying.
3590 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3592 * gencode.c, interp.c: Replaced explicit long long references with
3593 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3594 * support.h (SET64LO, SET64HI): Macros added.
3596 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3598 * configure: Regenerate with autoconf 2.7.
3600 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3602 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3603 * support.h: Remove superfluous "1" from #if.
3604 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3606 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3608 * interp.c (StoreFPR): Control UndefinedResult() call on
3609 WARN_RESULT manifest.
3611 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3613 * gencode.c: Tidied instruction decoding, and added FP instruction
3616 * interp.c: Added dineroIII, and BSD profiling support. Also
3617 run-time FP handling.
3619 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3621 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3622 gencode.c, interp.c, support.h: created.