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This commit was generated by cvs2svn to track changes on a CVS vendor
[deliverable/binutils-gdb.git] / sim / mips / ChangeLog
1 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
2
3 From Jason Eckhardt:
4 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
5
6 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
7
8 * mips.igen (MxC1, DMxC1): Fix printf formatting.
9
10 2000-05-24 Michael Hayes <mhayes@cygnus.com>
11
12 * mips.igen (do_dmultx): Fix typo.
13
14 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
15
16 * configure: Regenerated to track ../common/aclocal.m4 changes.
17
18 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
19
20 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
21
22 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
23
24 * sim-main.h (GPR_CLEAR): Define macro.
25
26 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
27
28 * interp.c (decode_coproc): Output long using %lx and not %s.
29
30 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
31
32 * interp.c (sim_open): Sort & extend dummy memory regions for
33 --board=jmr3904 for eCos.
34
35 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
36
37 * configure: Regenerated.
38
39 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
40
41 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
42 calls, conditional on the simulator being in verbose mode.
43
44 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
45
46 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
47 cache don't get ReservedInstruction traps.
48
49 1999-11-29 Mark Salter <msalter@cygnus.com>
50
51 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
52 to clear status bits in sdisr register. This is how the hardware works.
53
54 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
55 being used by cygmon.
56
57 1999-11-11 Andrew Haley <aph@cygnus.com>
58
59 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
60 instructions.
61
62 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
63
64 * mips.igen (MULT): Correct previous mis-applied patch.
65
66 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
67
68 * mips.igen (delayslot32): Handle sequence like
69 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
70 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
71 (MULT): Actually pass the third register...
72
73 1999-09-03 Mark Salter <msalter@cygnus.com>
74
75 * interp.c (sim_open): Added more memory aliases for additional
76 hardware being touched by cygmon on jmr3904 board.
77
78 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
79
80 * configure: Regenerated to track ../common/aclocal.m4 changes.
81
82 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
83
84 * interp.c (sim_store_register): Handle case where client - GDB -
85 specifies that a 4 byte register is 8 bytes in size.
86 (sim_fetch_register): Ditto.
87
88 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
89
90 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
91 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
92 (idt_monitor_base): Base address for IDT monitor traps.
93 (pmon_monitor_base): Ditto for PMON.
94 (lsipmon_monitor_base): Ditto for LSI PMON.
95 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
96 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
97 (sim_firmware_command): New function.
98 (mips_option_handler): Call it for OPTION_FIRMWARE.
99 (sim_open): Allocate memory for idt_monitor region. If "--board"
100 option was given, add no monitor by default. Add BREAK hooks only if
101 monitors are also there.
102
103 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
104
105 * interp.c (sim_monitor): Flush output before reading input.
106
107 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
108
109 * tconfig.in (SIM_HANDLES_LMA): Always define.
110
111 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
112
113 From Mark Salter <msalter@cygnus.com>:
114 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
115 (sim_open): Add setup for BSP board.
116
117 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
118
119 * mips.igen (MULT, MULTU): Add syntax for two operand version.
120 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
121 them as unimplemented.
122
123 1999-05-08 Felix Lee <flee@cygnus.com>
124
125 * configure: Regenerated to track ../common/aclocal.m4 changes.
126
127 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
128
129 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
130
131 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
132
133 * configure.in: Any mips64vr5*-*-* target should have
134 -DTARGET_ENABLE_FR=1.
135 (default_endian): Any mips64vr*el-*-* target should default to
136 LITTLE_ENDIAN.
137 * configure: Re-generate.
138
139 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
140
141 * mips.igen (ldl): Extend from _16_, not 32.
142
143 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
144
145 * interp.c (sim_store_register): Force registers written to by GDB
146 into an un-interpreted state.
147
148 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
149
150 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
151 CPU, start periodic background I/O polls.
152 (tx3904sio_poll): New function: periodic I/O poller.
153
154 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
155
156 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
157
158 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
159
160 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
161 case statement.
162
163 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
164
165 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
166 (load_word): Call SIM_CORE_SIGNAL hook on error.
167 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
168 starting. For exception dispatching, pass PC instead of NULL_CIA.
169 (decode_coproc): Use COP0_BADVADDR to store faulting address.
170 * sim-main.h (COP0_BADVADDR): Define.
171 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
172 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
173 (_sim_cpu): Add exc_* fields to store register value snapshots.
174 * mips.igen (*): Replace memory-related SignalException* calls
175 with references to SIM_CORE_SIGNAL hook.
176
177 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
178 fix.
179 * sim-main.c (*): Minor warning cleanups.
180
181 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
182
183 * m16.igen (DADDIU5): Correct type-o.
184
185 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
186
187 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
188 variables.
189
190 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
191
192 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
193 to include path.
194 (interp.o): Add dependency on itable.h
195 (oengine.c, gencode): Delete remaining references.
196 (BUILT_SRC_FROM_GEN): Clean up.
197
198 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
199
200 * vr4run.c: New.
201 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
202 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
203 tmp-run-hack) : New.
204 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
205 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
206 Drop the "64" qualifier to get the HACK generator working.
207 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
208 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
209 qualifier to get the hack generator working.
210 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
211 (DSLL): Use do_dsll.
212 (DSLLV): Use do_dsllv.
213 (DSRA): Use do_dsra.
214 (DSRL): Use do_dsrl.
215 (DSRLV): Use do_dsrlv.
216 (BC1): Move *vr4100 to get the HACK generator working.
217 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
218 get the HACK generator working.
219 (MACC) Rename to get the HACK generator working.
220 (DMACC,MACCS,DMACCS): Add the 64.
221
222 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
223
224 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
225 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
226
227 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
228
229 * mips/interp.c (DEBUG): Cleanups.
230
231 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
232
233 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
234 (tx3904sio_tickle): fflush after a stdout character output.
235
236 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
237
238 * interp.c (sim_close): Uninstall modules.
239
240 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
241
242 * sim-main.h, interp.c (sim_monitor): Change to global
243 function.
244
245 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
246
247 * configure.in (vr4100): Only include vr4100 instructions in
248 simulator.
249 * configure: Re-generate.
250 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
251
252 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
253
254 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
255 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
256 true alternative.
257
258 * configure.in (sim_default_gen, sim_use_gen): Replace with
259 sim_gen.
260 (--enable-sim-igen): Delete config option. Always using IGEN.
261 * configure: Re-generate.
262
263 * Makefile.in (gencode): Kill, kill, kill.
264 * gencode.c: Ditto.
265
266 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
267
268 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
269 bit mips16 igen simulator.
270 * configure: Re-generate.
271
272 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
273 as part of vr4100 ISA.
274 * vr.igen: Mark all instructions as 64 bit only.
275
276 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
277
278 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
279 Pacify GCC.
280
281 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
282
283 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
284 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
285 * configure: Re-generate.
286
287 * m16.igen (BREAK): Define breakpoint instruction.
288 (JALX32): Mark instruction as mips16 and not r3900.
289 * mips.igen (C.cond.fmt): Fix typo in instruction format.
290
291 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
292
293 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
294
295 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
296 insn as a debug breakpoint.
297
298 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
299 pending.slot_size.
300 (PENDING_SCHED): Clean up trace statement.
301 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
302 (PENDING_FILL): Delay write by only one cycle.
303 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
304
305 * sim-main.c (pending_tick): Clean up trace statements. Add trace
306 of pending writes.
307 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
308 32 & 64.
309 (pending_tick): Move incrementing of index to FOR statement.
310 (pending_tick): Only update PENDING_OUT after a write has occured.
311
312 * configure.in: Add explicit mips-lsi-* target. Use gencode to
313 build simulator.
314 * configure: Re-generate.
315
316 * interp.c (sim_engine_run OLD): Delete explicit call to
317 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
318
319 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
320
321 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
322 interrupt level number to match changed SignalExceptionInterrupt
323 macro.
324
325 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
326
327 * interp.c: #include "itable.h" if WITH_IGEN.
328 (get_insn_name): New function.
329 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
330 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
331
332 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
333
334 * configure: Rebuilt to inhale new common/aclocal.m4.
335
336 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
337
338 * dv-tx3904sio.c: Include sim-assert.h.
339
340 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
341
342 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
343 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
344 Reorganize target-specific sim-hardware checks.
345 * configure: rebuilt.
346 * interp.c (sim_open): For tx39 target boards, set
347 OPERATING_ENVIRONMENT, add tx3904sio devices.
348 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
349 ROM executables. Install dv-sockser into sim-modules list.
350
351 * dv-tx3904irc.c: Compiler warning clean-up.
352 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
353 frequent hw-trace messages.
354
355 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
356
357 * vr.igen (MulAcc): Identify as a vr4100 specific function.
358
359 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
360
361 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
362
363 * vr.igen: New file.
364 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
365 * mips.igen: Define vr4100 model. Include vr.igen.
366 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
367
368 * mips.igen (check_mf_hilo): Correct check.
369
370 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
371
372 * sim-main.h (interrupt_event): Add prototype.
373
374 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
375 register_ptr, register_value.
376 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
377
378 * sim-main.h (tracefh): Make extern.
379
380 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
381
382 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
383 Reduce unnecessarily high timer event frequency.
384 * dv-tx3904cpu.c: Ditto for interrupt event.
385
386 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
387
388 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
389 to allay warnings.
390 (interrupt_event): Made non-static.
391
392 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
393 interchange of configuration values for external vs. internal
394 clock dividers.
395
396 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
397
398 * mips.igen (BREAK): Moved code to here for
399 simulator-reserved break instructions.
400 * gencode.c (build_instruction): Ditto.
401 * interp.c (signal_exception): Code moved from here. Non-
402 reserved instructions now use exception vector, rather
403 than halting sim.
404 * sim-main.h: Moved magic constants to here.
405
406 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
407
408 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
409 register upon non-zero interrupt event level, clear upon zero
410 event value.
411 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
412 by passing zero event value.
413 (*_io_{read,write}_buffer): Endianness fixes.
414 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
415 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
416
417 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
418 serial I/O and timer module at base address 0xFFFF0000.
419
420 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
421
422 * mips.igen (SWC1) : Correct the handling of ReverseEndian
423 and BigEndianCPU.
424
425 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
426
427 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
428 parts.
429 * configure: Update.
430
431 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
432
433 * dv-tx3904tmr.c: New file - implements tx3904 timer.
434 * dv-tx3904{irc,cpu}.c: Mild reformatting.
435 * configure.in: Include tx3904tmr in hw_device list.
436 * configure: Rebuilt.
437 * interp.c (sim_open): Instantiate three timer instances.
438 Fix address typo of tx3904irc instance.
439
440 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
441
442 * interp.c (signal_exception): SystemCall exception now uses
443 the exception vector.
444
445 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
446
447 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
448 to allay warnings.
449
450 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
451
452 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
453
454 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
455
456 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
457
458 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
459 sim-main.h. Declare a struct hw_descriptor instead of struct
460 hw_device_descriptor.
461
462 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
463
464 * mips.igen (do_store_left, do_load_left): Compute nr of left and
465 right bits and then re-align left hand bytes to correct byte
466 lanes. Fix incorrect computation in do_store_left when loading
467 bytes from second word.
468
469 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
470
471 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
472 * interp.c (sim_open): Only create a device tree when HW is
473 enabled.
474
475 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
476 * interp.c (signal_exception): Ditto.
477
478 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
479
480 * gencode.c: Mark BEGEZALL as LIKELY.
481
482 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
483
484 * sim-main.h (ALU32_END): Sign extend 32 bit results.
485 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
486
487 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
488
489 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
490 modules. Recognize TX39 target with "mips*tx39" pattern.
491 * configure: Rebuilt.
492 * sim-main.h (*): Added many macros defining bits in
493 TX39 control registers.
494 (SignalInterrupt): Send actual PC instead of NULL.
495 (SignalNMIReset): New exception type.
496 * interp.c (board): New variable for future use to identify
497 a particular board being simulated.
498 (mips_option_handler,mips_options): Added "--board" option.
499 (interrupt_event): Send actual PC.
500 (sim_open): Make memory layout conditional on board setting.
501 (signal_exception): Initial implementation of hardware interrupt
502 handling. Accept another break instruction variant for simulator
503 exit.
504 (decode_coproc): Implement RFE instruction for TX39.
505 (mips.igen): Decode RFE instruction as such.
506 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
507 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
508 bbegin to implement memory map.
509 * dv-tx3904cpu.c: New file.
510 * dv-tx3904irc.c: New file.
511
512 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
513
514 * mips.igen (check_mt_hilo): Create a separate r3900 version.
515
516 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
517
518 * tx.igen (madd,maddu): Replace calls to check_op_hilo
519 with calls to check_div_hilo.
520
521 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
522
523 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
524 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
525 Add special r3900 version of do_mult_hilo.
526 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
527 with calls to check_mult_hilo.
528 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
529 with calls to check_div_hilo.
530
531 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
532
533 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
534 Document a replacement.
535
536 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
537
538 * interp.c (sim_monitor): Make mon_printf work.
539
540 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
541
542 * sim-main.h (INSN_NAME): New arg `cpu'.
543
544 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
545
546 * configure: Regenerated to track ../common/aclocal.m4 changes.
547
548 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
549
550 * configure: Regenerated to track ../common/aclocal.m4 changes.
551 * config.in: Ditto.
552
553 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
554
555 * acconfig.h: New file.
556 * configure.in: Reverted change of Apr 24; use sinclude again.
557
558 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
559
560 * configure: Regenerated to track ../common/aclocal.m4 changes.
561 * config.in: Ditto.
562
563 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
564
565 * configure.in: Don't call sinclude.
566
567 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
568
569 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
570
571 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
572
573 * mips.igen (ERET): Implement.
574
575 * interp.c (decode_coproc): Return sign-extended EPC.
576
577 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
578
579 * interp.c (signal_exception): Do not ignore Trap.
580 (signal_exception): On TRAP, restart at exception address.
581 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
582 (signal_exception): Update.
583 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
584 so that TRAP instructions are caught.
585
586 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
587
588 * sim-main.h (struct hilo_access, struct hilo_history): Define,
589 contains HI/LO access history.
590 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
591 (HIACCESS, LOACCESS): Delete, replace with
592 (HIHISTORY, LOHISTORY): New macros.
593 (CHECKHILO): Delete all, moved to mips.igen
594
595 * gencode.c (build_instruction): Do not generate checks for
596 correct HI/LO register usage.
597
598 * interp.c (old_engine_run): Delete checks for correct HI/LO
599 register usage.
600
601 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
602 check_mf_cycles): New functions.
603 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
604 do_divu, domultx, do_mult, do_multu): Use.
605
606 * tx.igen ("madd", "maddu"): Use.
607
608 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
609
610 * mips.igen (DSRAV): Use function do_dsrav.
611 (SRAV): Use new function do_srav.
612
613 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
614 (B): Sign extend 11 bit immediate.
615 (EXT-B*): Shift 16 bit immediate left by 1.
616 (ADDIU*): Don't sign extend immediate value.
617
618 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
619
620 * m16run.c (sim_engine_run): Restore CIA after handling an event.
621
622 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
623 functions.
624
625 * mips.igen (delayslot32, nullify_next_insn): New functions.
626 (m16.igen): Always include.
627 (do_*): Add more tracing.
628
629 * m16.igen (delayslot16): Add NIA argument, could be called by a
630 32 bit MIPS16 instruction.
631
632 * interp.c (ifetch16): Move function from here.
633 * sim-main.c (ifetch16): To here.
634
635 * sim-main.c (ifetch16, ifetch32): Update to match current
636 implementations of LH, LW.
637 (signal_exception): Don't print out incorrect hex value of illegal
638 instruction.
639
640 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
641
642 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
643 instruction.
644
645 * m16.igen: Implement MIPS16 instructions.
646
647 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
648 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
649 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
650 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
651 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
652 bodies of corresponding code from 32 bit insn to these. Also used
653 by MIPS16 versions of functions.
654
655 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
656 (IMEM16): Drop NR argument from macro.
657
658 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
659
660 * Makefile.in (SIM_OBJS): Add sim-main.o.
661
662 * sim-main.h (address_translation, load_memory, store_memory,
663 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
664 as INLINE_SIM_MAIN.
665 (pr_addr, pr_uword64): Declare.
666 (sim-main.c): Include when H_REVEALS_MODULE_P.
667
668 * interp.c (address_translation, load_memory, store_memory,
669 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
670 from here.
671 * sim-main.c: To here. Fix compilation problems.
672
673 * configure.in: Enable inlining.
674 * configure: Re-config.
675
676 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
677
678 * configure: Regenerated to track ../common/aclocal.m4 changes.
679
680 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
681
682 * mips.igen: Include tx.igen.
683 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
684 * tx.igen: New file, contains MADD and MADDU.
685
686 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
687 the hardwired constant `7'.
688 (store_memory): Ditto.
689 (LOADDRMASK): Move definition to sim-main.h.
690
691 mips.igen (MTC0): Enable for r3900.
692 (ADDU): Add trace.
693
694 mips.igen (do_load_byte): Delete.
695 (do_load, do_store, do_load_left, do_load_write, do_store_left,
696 do_store_right): New functions.
697 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
698
699 configure.in: Let the tx39 use igen again.
700 configure: Update.
701
702 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
703
704 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
705 not an address sized quantity. Return zero for cache sizes.
706
707 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
708
709 * mips.igen (r3900): r3900 does not support 64 bit integer
710 operations.
711
712 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
713
714 * configure.in (mipstx39*-*-*): Use gencode simulator rather
715 than igen one.
716 * configure : Rebuild.
717
718 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
719
720 * configure: Regenerated to track ../common/aclocal.m4 changes.
721
722 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
723
724 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
725
726 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
727
728 * configure: Regenerated to track ../common/aclocal.m4 changes.
729 * config.in: Regenerated to track ../common/aclocal.m4 changes.
730
731 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
732
733 * configure: Regenerated to track ../common/aclocal.m4 changes.
734
735 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
736
737 * interp.c (Max, Min): Comment out functions. Not yet used.
738
739 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
740
741 * configure: Regenerated to track ../common/aclocal.m4 changes.
742
743 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
744
745 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
746 configurable settings for stand-alone simulator.
747
748 * configure.in: Added X11 search, just in case.
749
750 * configure: Regenerated.
751
752 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * interp.c (sim_write, sim_read, load_memory, store_memory):
755 Replace sim_core_*_map with read_map, write_map, exec_map resp.
756
757 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
758
759 * sim-main.h (GETFCC): Return an unsigned value.
760
761 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
762
763 * mips.igen (DIV): Fix check for -1 / MIN_INT.
764 (DADD): Result destination is RD not RT.
765
766 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
767
768 * sim-main.h (HIACCESS, LOACCESS): Always define.
769
770 * mdmx.igen (Maxi, Mini): Rename Max, Min.
771
772 * interp.c (sim_info): Delete.
773
774 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
775
776 * interp.c (DECLARE_OPTION_HANDLER): Use it.
777 (mips_option_handler): New argument `cpu'.
778 (sim_open): Update call to sim_add_option_table.
779
780 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
781
782 * mips.igen (CxC1): Add tracing.
783
784 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
785
786 * sim-main.h (Max, Min): Declare.
787
788 * interp.c (Max, Min): New functions.
789
790 * mips.igen (BC1): Add tracing.
791
792 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
793
794 * interp.c Added memory map for stack in vr4100
795
796 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
797
798 * interp.c (load_memory): Add missing "break"'s.
799
800 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
801
802 * interp.c (sim_store_register, sim_fetch_register): Pass in
803 length parameter. Return -1.
804
805 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
806
807 * interp.c: Added hardware init hook, fixed warnings.
808
809 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
810
811 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
812
813 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
814
815 * interp.c (ifetch16): New function.
816
817 * sim-main.h (IMEM32): Rename IMEM.
818 (IMEM16_IMMED): Define.
819 (IMEM16): Define.
820 (DELAY_SLOT): Update.
821
822 * m16run.c (sim_engine_run): New file.
823
824 * m16.igen: All instructions except LB.
825 (LB): Call do_load_byte.
826 * mips.igen (do_load_byte): New function.
827 (LB): Call do_load_byte.
828
829 * mips.igen: Move spec for insn bit size and high bit from here.
830 * Makefile.in (tmp-igen, tmp-m16): To here.
831
832 * m16.dc: New file, decode mips16 instructions.
833
834 * Makefile.in (SIM_NO_ALL): Define.
835 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
836
837 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
838
839 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
840 point unit to 32 bit registers.
841 * configure: Re-generate.
842
843 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
844
845 * configure.in (sim_use_gen): Make IGEN the default simulator
846 generator for generic 32 and 64 bit mips targets.
847 * configure: Re-generate.
848
849 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
850
851 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
852 bitsize.
853
854 * interp.c (sim_fetch_register, sim_store_register): Read/write
855 FGR from correct location.
856 (sim_open): Set size of FGR's according to
857 WITH_TARGET_FLOATING_POINT_BITSIZE.
858
859 * sim-main.h (FGR): Store floating point registers in a separate
860 array.
861
862 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
863
864 * configure: Regenerated to track ../common/aclocal.m4 changes.
865
866 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
867
868 * interp.c (ColdReset): Call PENDING_INVALIDATE.
869
870 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
871
872 * interp.c (pending_tick): New function. Deliver pending writes.
873
874 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
875 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
876 it can handle mixed sized quantites and single bits.
877
878 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
879
880 * interp.c (oengine.h): Do not include when building with IGEN.
881 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
882 (sim_info): Ditto for PROCESSOR_64BIT.
883 (sim_monitor): Replace ut_reg with unsigned_word.
884 (*): Ditto for t_reg.
885 (LOADDRMASK): Define.
886 (sim_open): Remove defunct check that host FP is IEEE compliant,
887 using software to emulate floating point.
888 (value_fpr, ...): Always compile, was conditional on HASFPU.
889
890 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
891
892 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
893 size.
894
895 * interp.c (SD, CPU): Define.
896 (mips_option_handler): Set flags in each CPU.
897 (interrupt_event): Assume CPU 0 is the one being iterrupted.
898 (sim_close): Do not clear STATE, deleted anyway.
899 (sim_write, sim_read): Assume CPU zero's vm should be used for
900 data transfers.
901 (sim_create_inferior): Set the PC for all processors.
902 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
903 argument.
904 (mips16_entry): Pass correct nr of args to store_word, load_word.
905 (ColdReset): Cold reset all cpu's.
906 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
907 (sim_monitor, load_memory, store_memory, signal_exception): Use
908 `CPU' instead of STATE_CPU.
909
910
911 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
912 SD or CPU_.
913
914 * sim-main.h (signal_exception): Add sim_cpu arg.
915 (SignalException*): Pass both SD and CPU to signal_exception.
916 * interp.c (signal_exception): Update.
917
918 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
919 Ditto
920 (sync_operation, prefetch, cache_op, store_memory, load_memory,
921 address_translation): Ditto
922 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
923
924 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
925
926 * configure: Regenerated to track ../common/aclocal.m4 changes.
927
928 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
929
930 * interp.c (sim_engine_run): Add `nr_cpus' argument.
931
932 * mips.igen (model): Map processor names onto BFD name.
933
934 * sim-main.h (CPU_CIA): Delete.
935 (SET_CIA, GET_CIA): Define
936
937 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
938
939 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
940 regiser.
941
942 * configure.in (default_endian): Configure a big-endian simulator
943 by default.
944 * configure: Re-generate.
945
946 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
947
948 * configure: Regenerated to track ../common/aclocal.m4 changes.
949
950 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
951
952 * interp.c (sim_monitor): Handle Densan monitor outbyte
953 and inbyte functions.
954
955 1997-12-29 Felix Lee <flee@cygnus.com>
956
957 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
958
959 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
960
961 * Makefile.in (tmp-igen): Arrange for $zero to always be
962 reset to zero after every instruction.
963
964 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
965
966 * configure: Regenerated to track ../common/aclocal.m4 changes.
967 * config.in: Ditto.
968
969 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
970
971 * mips.igen (MSUB): Fix to work like MADD.
972 * gencode.c (MSUB): Similarly.
973
974 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
975
976 * configure: Regenerated to track ../common/aclocal.m4 changes.
977
978 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
979
980 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
981
982 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
983
984 * sim-main.h (sim-fpu.h): Include.
985
986 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
987 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
988 using host independant sim_fpu module.
989
990 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
991
992 * interp.c (signal_exception): Report internal errors with SIGABRT
993 not SIGQUIT.
994
995 * sim-main.h (C0_CONFIG): New register.
996 (signal.h): No longer include.
997
998 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
999
1000 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1001
1002 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1003
1004 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1005
1006 * mips.igen: Tag vr5000 instructions.
1007 (ANDI): Was missing mipsIV model, fix assembler syntax.
1008 (do_c_cond_fmt): New function.
1009 (C.cond.fmt): Handle mips I-III which do not support CC field
1010 separatly.
1011 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1012 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1013 in IV3.2 spec.
1014 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1015 vr5000 which saves LO in a GPR separatly.
1016
1017 * configure.in (enable-sim-igen): For vr5000, select vr5000
1018 specific instructions.
1019 * configure: Re-generate.
1020
1021 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1022
1023 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1024
1025 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1026 fmt_uninterpreted_64 bit cases to switch. Convert to
1027 fmt_formatted,
1028
1029 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1030
1031 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1032 as specified in IV3.2 spec.
1033 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1034
1035 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1036
1037 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1038 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1039 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1040 PENDING_FILL versions of instructions. Simplify.
1041 (X): New function.
1042 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1043 instructions.
1044 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1045 a signed value.
1046 (MTHI, MFHI): Disable code checking HI-LO.
1047
1048 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1049 global.
1050 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1051
1052 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1053
1054 * gencode.c (build_mips16_operands): Replace IPC with cia.
1055
1056 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1057 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1058 IPC to `cia'.
1059 (UndefinedResult): Replace function with macro/function
1060 combination.
1061 (sim_engine_run): Don't save PC in IPC.
1062
1063 * sim-main.h (IPC): Delete.
1064
1065
1066 * interp.c (signal_exception, store_word, load_word,
1067 address_translation, load_memory, store_memory, cache_op,
1068 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1069 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1070 current instruction address - cia - argument.
1071 (sim_read, sim_write): Call address_translation directly.
1072 (sim_engine_run): Rename variable vaddr to cia.
1073 (signal_exception): Pass cia to sim_monitor
1074
1075 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1076 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1077 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1078
1079 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1080 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1081 SIM_ASSERT.
1082
1083 * interp.c (signal_exception): Pass restart address to
1084 sim_engine_restart.
1085
1086 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1087 idecode.o): Add dependency.
1088
1089 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1090 Delete definitions
1091 (DELAY_SLOT): Update NIA not PC with branch address.
1092 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1093
1094 * mips.igen: Use CIA not PC in branch calculations.
1095 (illegal): Call SignalException.
1096 (BEQ, ADDIU): Fix assembler.
1097
1098 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1099
1100 * m16.igen (JALX): Was missing.
1101
1102 * configure.in (enable-sim-igen): New configuration option.
1103 * configure: Re-generate.
1104
1105 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1106
1107 * interp.c (load_memory, store_memory): Delete parameter RAW.
1108 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1109 bypassing {load,store}_memory.
1110
1111 * sim-main.h (ByteSwapMem): Delete definition.
1112
1113 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1114
1115 * interp.c (sim_do_command, sim_commands): Delete mips specific
1116 commands. Handled by module sim-options.
1117
1118 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1119 (WITH_MODULO_MEMORY): Define.
1120
1121 * interp.c (sim_info): Delete code printing memory size.
1122
1123 * interp.c (mips_size): Nee sim_size, delete function.
1124 (power2): Delete.
1125 (monitor, monitor_base, monitor_size): Delete global variables.
1126 (sim_open, sim_close): Delete code creating monitor and other
1127 memory regions. Use sim-memopts module, via sim_do_commandf, to
1128 manage memory regions.
1129 (load_memory, store_memory): Use sim-core for memory model.
1130
1131 * interp.c (address_translation): Delete all memory map code
1132 except line forcing 32 bit addresses.
1133
1134 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1135
1136 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1137 trace options.
1138
1139 * interp.c (logfh, logfile): Delete globals.
1140 (sim_open, sim_close): Delete code opening & closing log file.
1141 (mips_option_handler): Delete -l and -n options.
1142 (OPTION mips_options): Ditto.
1143
1144 * interp.c (OPTION mips_options): Rename option trace to dinero.
1145 (mips_option_handler): Update.
1146
1147 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1148
1149 * interp.c (fetch_str): New function.
1150 (sim_monitor): Rewrite using sim_read & sim_write.
1151 (sim_open): Check magic number.
1152 (sim_open): Write monitor vectors into memory using sim_write.
1153 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1154 (sim_read, sim_write): Simplify - transfer data one byte at a
1155 time.
1156 (load_memory, store_memory): Clarify meaning of parameter RAW.
1157
1158 * sim-main.h (isHOST): Defete definition.
1159 (isTARGET): Mark as depreciated.
1160 (address_translation): Delete parameter HOST.
1161
1162 * interp.c (address_translation): Delete parameter HOST.
1163
1164 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1165
1166 * mips.igen:
1167
1168 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1169 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1170
1171 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1172
1173 * mips.igen: Add model filter field to records.
1174
1175 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1178
1179 interp.c (sim_engine_run): Do not compile function sim_engine_run
1180 when WITH_IGEN == 1.
1181
1182 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1183 target architecture.
1184
1185 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1186 igen. Replace with configuration variables sim_igen_flags /
1187 sim_m16_flags.
1188
1189 * m16.igen: New file. Copy mips16 insns here.
1190 * mips.igen: From here.
1191
1192 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1193
1194 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1195 to top.
1196 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1197
1198 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1199
1200 * gencode.c (build_instruction): Follow sim_write's lead in using
1201 BigEndianMem instead of !ByteSwapMem.
1202
1203 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1204
1205 * configure.in (sim_gen): Dependent on target, select type of
1206 generator. Always select old style generator.
1207
1208 configure: Re-generate.
1209
1210 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1211 targets.
1212 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1213 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1214 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1215 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1216 SIM_@sim_gen@_*, set by autoconf.
1217
1218 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219
1220 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1221
1222 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1223 CURRENT_FLOATING_POINT instead.
1224
1225 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1226 (address_translation): Raise exception InstructionFetch when
1227 translation fails and isINSTRUCTION.
1228
1229 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1230 sim_engine_run): Change type of of vaddr and paddr to
1231 address_word.
1232 (address_translation, prefetch, load_memory, store_memory,
1233 cache_op): Change type of vAddr and pAddr to address_word.
1234
1235 * gencode.c (build_instruction): Change type of vaddr and paddr to
1236 address_word.
1237
1238 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1241 macro to obtain result of ALU op.
1242
1243 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1244
1245 * interp.c (sim_info): Call profile_print.
1246
1247 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1248
1249 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1250
1251 * sim-main.h (WITH_PROFILE): Do not define, defined in
1252 common/sim-config.h. Use sim-profile module.
1253 (simPROFILE): Delete defintion.
1254
1255 * interp.c (PROFILE): Delete definition.
1256 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1257 (sim_close): Delete code writing profile histogram.
1258 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1259 Delete.
1260 (sim_engine_run): Delete code profiling the PC.
1261
1262 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1265
1266 * interp.c (sim_monitor): Make register pointers of type
1267 unsigned_word*.
1268
1269 * sim-main.h: Make registers of type unsigned_word not
1270 signed_word.
1271
1272 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1273
1274 * interp.c (sync_operation): Rename from SyncOperation, make
1275 global, add SD argument.
1276 (prefetch): Rename from Prefetch, make global, add SD argument.
1277 (decode_coproc): Make global.
1278
1279 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1280
1281 * gencode.c (build_instruction): Generate DecodeCoproc not
1282 decode_coproc calls.
1283
1284 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1285 (SizeFGR): Move to sim-main.h
1286 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1287 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1288 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1289 sim-main.h.
1290 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1291 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1292 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1293 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1294 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1295 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1296
1297 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1298 exception.
1299 (sim-alu.h): Include.
1300 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1301 (sim_cia): Typedef to instruction_address.
1302
1303 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1304
1305 * Makefile.in (interp.o): Rename generated file engine.c to
1306 oengine.c.
1307
1308 * interp.c: Update.
1309
1310 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1311
1312 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1313
1314 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * gencode.c (build_instruction): For "FPSQRT", output correct
1317 number of arguments to Recip.
1318
1319 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1320
1321 * Makefile.in (interp.o): Depends on sim-main.h
1322
1323 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1324
1325 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1326 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1327 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1328 STATE, DSSTATE): Define
1329 (GPR, FGRIDX, ..): Define.
1330
1331 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1332 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1333 (GPR, FGRIDX, ...): Delete macros.
1334
1335 * interp.c: Update names to match defines from sim-main.h
1336
1337 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1338
1339 * interp.c (sim_monitor): Add SD argument.
1340 (sim_warning): Delete. Replace calls with calls to
1341 sim_io_eprintf.
1342 (sim_error): Delete. Replace calls with sim_io_error.
1343 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1344 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1345 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1346 argument.
1347 (mips_size): Rename from sim_size. Add SD argument.
1348
1349 * interp.c (simulator): Delete global variable.
1350 (callback): Delete global variable.
1351 (mips_option_handler, sim_open, sim_write, sim_read,
1352 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1353 sim_size,sim_monitor): Use sim_io_* not callback->*.
1354 (sim_open): ZALLOC simulator struct.
1355 (PROFILE): Do not define.
1356
1357 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1358
1359 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1360 support.h with corresponding code.
1361
1362 * sim-main.h (word64, uword64), support.h: Move definition to
1363 sim-main.h.
1364 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1365
1366 * support.h: Delete
1367 * Makefile.in: Update dependencies
1368 * interp.c: Do not include.
1369
1370 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1371
1372 * interp.c (address_translation, load_memory, store_memory,
1373 cache_op): Rename to from AddressTranslation et.al., make global,
1374 add SD argument
1375
1376 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1377 CacheOp): Define.
1378
1379 * interp.c (SignalException): Rename to signal_exception, make
1380 global.
1381
1382 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1383
1384 * sim-main.h (SignalException, SignalExceptionInterrupt,
1385 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1386 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1387 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1388 Define.
1389
1390 * interp.c, support.h: Use.
1391
1392 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1395 to value_fpr / store_fpr. Add SD argument.
1396 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1397 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1398
1399 * sim-main.h (ValueFPR, StoreFPR): Define.
1400
1401 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * interp.c (sim_engine_run): Check consistency between configure
1404 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1405 and HASFPU.
1406
1407 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1408 (mips_fpu): Configure WITH_FLOATING_POINT.
1409 (mips_endian): Configure WITH_TARGET_ENDIAN.
1410 * configure: Update.
1411
1412 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1413
1414 * configure: Regenerated to track ../common/aclocal.m4 changes.
1415
1416 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1417
1418 * configure: Regenerated.
1419
1420 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1421
1422 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1423
1424 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1425
1426 * gencode.c (print_igen_insn_models): Assume certain architectures
1427 include all mips* instructions.
1428 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1429 instruction.
1430
1431 * Makefile.in (tmp.igen): Add target. Generate igen input from
1432 gencode file.
1433
1434 * gencode.c (FEATURE_IGEN): Define.
1435 (main): Add --igen option. Generate output in igen format.
1436 (process_instructions): Format output according to igen option.
1437 (print_igen_insn_format): New function.
1438 (print_igen_insn_models): New function.
1439 (process_instructions): Only issue warnings and ignore
1440 instructions when no FEATURE_IGEN.
1441
1442 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1445 MIPS targets.
1446
1447 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1448
1449 * configure: Regenerated to track ../common/aclocal.m4 changes.
1450
1451 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1452
1453 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1454 SIM_RESERVED_BITS): Delete, moved to common.
1455 (SIM_EXTRA_CFLAGS): Update.
1456
1457 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1458
1459 * configure.in: Configure non-strict memory alignment.
1460 * configure: Regenerated to track ../common/aclocal.m4 changes.
1461
1462 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * configure: Regenerated to track ../common/aclocal.m4 changes.
1465
1466 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1467
1468 * gencode.c (SDBBP,DERET): Added (3900) insns.
1469 (RFE): Turn on for 3900.
1470 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1471 (dsstate): Made global.
1472 (SUBTARGET_R3900): Added.
1473 (CANCELDELAYSLOT): New.
1474 (SignalException): Ignore SystemCall rather than ignore and
1475 terminate. Add DebugBreakPoint handling.
1476 (decode_coproc): New insns RFE, DERET; and new registers Debug
1477 and DEPC protected by SUBTARGET_R3900.
1478 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1479 bits explicitly.
1480 * Makefile.in,configure.in: Add mips subtarget option.
1481 * configure: Update.
1482
1483 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1484
1485 * gencode.c: Add r3900 (tx39).
1486
1487
1488 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1489
1490 * gencode.c (build_instruction): Don't need to subtract 4 for
1491 JALR, just 2.
1492
1493 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1494
1495 * interp.c: Correct some HASFPU problems.
1496
1497 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * configure: Regenerated to track ../common/aclocal.m4 changes.
1500
1501 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * interp.c (mips_options): Fix samples option short form, should
1504 be `x'.
1505
1506 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * interp.c (sim_info): Enable info code. Was just returning.
1509
1510 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1511
1512 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1513 MFC0.
1514
1515 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1518 constants.
1519 (build_instruction): Ditto for LL.
1520
1521 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1522
1523 * configure: Regenerated to track ../common/aclocal.m4 changes.
1524
1525 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1526
1527 * configure: Regenerated to track ../common/aclocal.m4 changes.
1528 * config.in: Ditto.
1529
1530 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1531
1532 * interp.c (sim_open): Add call to sim_analyze_program, update
1533 call to sim_config.
1534
1535 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536
1537 * interp.c (sim_kill): Delete.
1538 (sim_create_inferior): Add ABFD argument. Set PC from same.
1539 (sim_load): Move code initializing trap handlers from here.
1540 (sim_open): To here.
1541 (sim_load): Delete, use sim-hload.c.
1542
1543 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1544
1545 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1546
1547 * configure: Regenerated to track ../common/aclocal.m4 changes.
1548 * config.in: Ditto.
1549
1550 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * interp.c (sim_open): Add ABFD argument.
1553 (sim_load): Move call to sim_config from here.
1554 (sim_open): To here. Check return status.
1555
1556 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1557
1558 * gencode.c (build_instruction): Two arg MADD should
1559 not assign result to $0.
1560
1561 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1562
1563 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1564 * sim/mips/configure.in: Regenerate.
1565
1566 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1567
1568 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1569 signed8, unsigned8 et.al. types.
1570
1571 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1572 hosts when selecting subreg.
1573
1574 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1575
1576 * interp.c (sim_engine_run): Reset the ZERO register to zero
1577 regardless of FEATURE_WARN_ZERO.
1578 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1579
1580 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1581
1582 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1583 (SignalException): For BreakPoints ignore any mode bits and just
1584 save the PC.
1585 (SignalException): Always set the CAUSE register.
1586
1587 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588
1589 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1590 exception has been taken.
1591
1592 * interp.c: Implement the ERET and mt/f sr instructions.
1593
1594 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595
1596 * interp.c (SignalException): Don't bother restarting an
1597 interrupt.
1598
1599 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1600
1601 * interp.c (SignalException): Really take an interrupt.
1602 (interrupt_event): Only deliver interrupts when enabled.
1603
1604 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605
1606 * interp.c (sim_info): Only print info when verbose.
1607 (sim_info) Use sim_io_printf for output.
1608
1609 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1610
1611 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1612 mips architectures.
1613
1614 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1615
1616 * interp.c (sim_do_command): Check for common commands if a
1617 simulator specific command fails.
1618
1619 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1620
1621 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1622 and simBE when DEBUG is defined.
1623
1624 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625
1626 * interp.c (interrupt_event): New function. Pass exception event
1627 onto exception handler.
1628
1629 * configure.in: Check for stdlib.h.
1630 * configure: Regenerate.
1631
1632 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1633 variable declaration.
1634 (build_instruction): Initialize memval1.
1635 (build_instruction): Add UNUSED attribute to byte, bigend,
1636 reverse.
1637 (build_operands): Ditto.
1638
1639 * interp.c: Fix GCC warnings.
1640 (sim_get_quit_code): Delete.
1641
1642 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1643 * Makefile.in: Ditto.
1644 * configure: Re-generate.
1645
1646 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1647
1648 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * interp.c (mips_option_handler): New function parse argumes using
1651 sim-options.
1652 (myname): Replace with STATE_MY_NAME.
1653 (sim_open): Delete check for host endianness - performed by
1654 sim_config.
1655 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1656 (sim_open): Move much of the initialization from here.
1657 (sim_load): To here. After the image has been loaded and
1658 endianness set.
1659 (sim_open): Move ColdReset from here.
1660 (sim_create_inferior): To here.
1661 (sim_open): Make FP check less dependant on host endianness.
1662
1663 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1664 run.
1665 * interp.c (sim_set_callbacks): Delete.
1666
1667 * interp.c (membank, membank_base, membank_size): Replace with
1668 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1669 (sim_open): Remove call to callback->init. gdb/run do this.
1670
1671 * interp.c: Update
1672
1673 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1674
1675 * interp.c (big_endian_p): Delete, replaced by
1676 current_target_byte_order.
1677
1678 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1679
1680 * interp.c (host_read_long, host_read_word, host_swap_word,
1681 host_swap_long): Delete. Using common sim-endian.
1682 (sim_fetch_register, sim_store_register): Use H2T.
1683 (pipeline_ticks): Delete. Handled by sim-events.
1684 (sim_info): Update.
1685 (sim_engine_run): Update.
1686
1687 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1688
1689 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1690 reason from here.
1691 (SignalException): To here. Signal using sim_engine_halt.
1692 (sim_stop_reason): Delete, moved to common.
1693
1694 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1695
1696 * interp.c (sim_open): Add callback argument.
1697 (sim_set_callbacks): Delete SIM_DESC argument.
1698 (sim_size): Ditto.
1699
1700 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1701
1702 * Makefile.in (SIM_OBJS): Add common modules.
1703
1704 * interp.c (sim_set_callbacks): Also set SD callback.
1705 (set_endianness, xfer_*, swap_*): Delete.
1706 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1707 Change to functions using sim-endian macros.
1708 (control_c, sim_stop): Delete, use common version.
1709 (simulate): Convert into.
1710 (sim_engine_run): This function.
1711 (sim_resume): Delete.
1712
1713 * interp.c (simulation): New variable - the simulator object.
1714 (sim_kind): Delete global - merged into simulation.
1715 (sim_load): Cleanup. Move PC assignment from here.
1716 (sim_create_inferior): To here.
1717
1718 * sim-main.h: New file.
1719 * interp.c (sim-main.h): Include.
1720
1721 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1722
1723 * configure: Regenerated to track ../common/aclocal.m4 changes.
1724
1725 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1726
1727 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1728
1729 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1730
1731 * gencode.c (build_instruction): DIV instructions: check
1732 for division by zero and integer overflow before using
1733 host's division operation.
1734
1735 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1736
1737 * Makefile.in (SIM_OBJS): Add sim-load.o.
1738 * interp.c: #include bfd.h.
1739 (target_byte_order): Delete.
1740 (sim_kind, myname, big_endian_p): New static locals.
1741 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1742 after argument parsing. Recognize -E arg, set endianness accordingly.
1743 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1744 load file into simulator. Set PC from bfd.
1745 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1746 (set_endianness): Use big_endian_p instead of target_byte_order.
1747
1748 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1749
1750 * interp.c (sim_size): Delete prototype - conflicts with
1751 definition in remote-sim.h. Correct definition.
1752
1753 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1754
1755 * configure: Regenerated to track ../common/aclocal.m4 changes.
1756 * config.in: Ditto.
1757
1758 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1759
1760 * interp.c (sim_open): New arg `kind'.
1761
1762 * configure: Regenerated to track ../common/aclocal.m4 changes.
1763
1764 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1765
1766 * configure: Regenerated to track ../common/aclocal.m4 changes.
1767
1768 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1769
1770 * interp.c (sim_open): Set optind to 0 before calling getopt.
1771
1772 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1773
1774 * configure: Regenerated to track ../common/aclocal.m4 changes.
1775
1776 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1777
1778 * interp.c : Replace uses of pr_addr with pr_uword64
1779 where the bit length is always 64 independent of SIM_ADDR.
1780 (pr_uword64) : added.
1781
1782 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1783
1784 * configure: Re-generate.
1785
1786 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1787
1788 * configure: Regenerate to track ../common/aclocal.m4 changes.
1789
1790 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1791
1792 * interp.c (sim_open): New SIM_DESC result. Argument is now
1793 in argv form.
1794 (other sim_*): New SIM_DESC argument.
1795
1796 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1797
1798 * interp.c: Fix printing of addresses for non-64-bit targets.
1799 (pr_addr): Add function to print address based on size.
1800
1801 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1802
1803 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1804
1805 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1806
1807 * gencode.c (build_mips16_operands): Correct computation of base
1808 address for extended PC relative instruction.
1809
1810 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1811
1812 * interp.c (mips16_entry): Add support for floating point cases.
1813 (SignalException): Pass floating point cases to mips16_entry.
1814 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1815 registers.
1816 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1817 or fmt_word.
1818 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1819 and then set the state to fmt_uninterpreted.
1820 (COP_SW): Temporarily set the state to fmt_word while calling
1821 ValueFPR.
1822
1823 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1824
1825 * gencode.c (build_instruction): The high order may be set in the
1826 comparison flags at any ISA level, not just ISA 4.
1827
1828 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1829
1830 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1831 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1832 * configure.in: sinclude ../common/aclocal.m4.
1833 * configure: Regenerated.
1834
1835 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1836
1837 * configure: Rebuild after change to aclocal.m4.
1838
1839 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1840
1841 * configure configure.in Makefile.in: Update to new configure
1842 scheme which is more compatible with WinGDB builds.
1843 * configure.in: Improve comment on how to run autoconf.
1844 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1845 * Makefile.in: Use autoconf substitution to install common
1846 makefile fragment.
1847
1848 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1849
1850 * gencode.c (build_instruction): Use BigEndianCPU instead of
1851 ByteSwapMem.
1852
1853 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1854
1855 * interp.c (sim_monitor): Make output to stdout visible in
1856 wingdb's I/O log window.
1857
1858 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1859
1860 * support.h: Undo previous change to SIGTRAP
1861 and SIGQUIT values.
1862
1863 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1864
1865 * interp.c (store_word, load_word): New static functions.
1866 (mips16_entry): New static function.
1867 (SignalException): Look for mips16 entry and exit instructions.
1868 (simulate): Use the correct index when setting fpr_state after
1869 doing a pending move.
1870
1871 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1872
1873 * interp.c: Fix byte-swapping code throughout to work on
1874 both little- and big-endian hosts.
1875
1876 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1877
1878 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1879 with gdb/config/i386/xm-windows.h.
1880
1881 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1882
1883 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1884 that messes up arithmetic shifts.
1885
1886 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1887
1888 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1889 SIGTRAP and SIGQUIT for _WIN32.
1890
1891 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1892
1893 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1894 force a 64 bit multiplication.
1895 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1896 destination register is 0, since that is the default mips16 nop
1897 instruction.
1898
1899 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1900
1901 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1902 (build_endian_shift): Don't check proc64.
1903 (build_instruction): Always set memval to uword64. Cast op2 to
1904 uword64 when shifting it left in memory instructions. Always use
1905 the same code for stores--don't special case proc64.
1906
1907 * gencode.c (build_mips16_operands): Fix base PC value for PC
1908 relative operands.
1909 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1910 jal instruction.
1911 * interp.c (simJALDELAYSLOT): Define.
1912 (JALDELAYSLOT): Define.
1913 (INDELAYSLOT, INJALDELAYSLOT): Define.
1914 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1915
1916 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1917
1918 * interp.c (sim_open): add flush_cache as a PMON routine
1919 (sim_monitor): handle flush_cache by ignoring it
1920
1921 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1922
1923 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1924 BigEndianMem.
1925 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1926 (BigEndianMem): Rename to ByteSwapMem and change sense.
1927 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1928 BigEndianMem references to !ByteSwapMem.
1929 (set_endianness): New function, with prototype.
1930 (sim_open): Call set_endianness.
1931 (sim_info): Use simBE instead of BigEndianMem.
1932 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1933 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1934 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1935 ifdefs, keeping the prototype declaration.
1936 (swap_word): Rewrite correctly.
1937 (ColdReset): Delete references to CONFIG. Delete endianness related
1938 code; moved to set_endianness.
1939
1940 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1941
1942 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1943 * interp.c (CHECKHILO): Define away.
1944 (simSIGINT): New macro.
1945 (membank_size): Increase from 1MB to 2MB.
1946 (control_c): New function.
1947 (sim_resume): Rename parameter signal to signal_number. Add local
1948 variable prev. Call signal before and after simulate.
1949 (sim_stop_reason): Add simSIGINT support.
1950 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1951 functions always.
1952 (sim_warning): Delete call to SignalException. Do call printf_filtered
1953 if logfh is NULL.
1954 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1955 a call to sim_warning.
1956
1957 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1958
1959 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1960 16 bit instructions.
1961
1962 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1963
1964 Add support for mips16 (16 bit MIPS implementation):
1965 * gencode.c (inst_type): Add mips16 instruction encoding types.
1966 (GETDATASIZEINSN): Define.
1967 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1968 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1969 mtlo.
1970 (MIPS16_DECODE): New table, for mips16 instructions.
1971 (bitmap_val): New static function.
1972 (struct mips16_op): Define.
1973 (mips16_op_table): New table, for mips16 operands.
1974 (build_mips16_operands): New static function.
1975 (process_instructions): If PC is odd, decode a mips16
1976 instruction. Break out instruction handling into new
1977 build_instruction function.
1978 (build_instruction): New static function, broken out of
1979 process_instructions. Check modifiers rather than flags for SHIFT
1980 bit count and m[ft]{hi,lo} direction.
1981 (usage): Pass program name to fprintf.
1982 (main): Remove unused variable this_option_optind. Change
1983 ``*loptarg++'' to ``loptarg++''.
1984 (my_strtoul): Parenthesize && within ||.
1985 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1986 (simulate): If PC is odd, fetch a 16 bit instruction, and
1987 increment PC by 2 rather than 4.
1988 * configure.in: Add case for mips16*-*-*.
1989 * configure: Rebuild.
1990
1991 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1992
1993 * interp.c: Allow -t to enable tracing in standalone simulator.
1994 Fix garbage output in trace file and error messages.
1995
1996 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1997
1998 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1999 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2000 * configure.in: Simplify using macros in ../common/aclocal.m4.
2001 * configure: Regenerated.
2002 * tconfig.in: New file.
2003
2004 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2005
2006 * interp.c: Fix bugs in 64-bit port.
2007 Use ansi function declarations for msvc compiler.
2008 Initialize and test file pointer in trace code.
2009 Prevent duplicate definition of LAST_EMED_REGNUM.
2010
2011 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2012
2013 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2014
2015 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2016
2017 * interp.c (SignalException): Check for explicit terminating
2018 breakpoint value.
2019 * gencode.c: Pass instruction value through SignalException()
2020 calls for Trap, Breakpoint and Syscall.
2021
2022 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2023
2024 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2025 only used on those hosts that provide it.
2026 * configure.in: Add sqrt() to list of functions to be checked for.
2027 * config.in: Re-generated.
2028 * configure: Re-generated.
2029
2030 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2031
2032 * gencode.c (process_instructions): Call build_endian_shift when
2033 expanding STORE RIGHT, to fix swr.
2034 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2035 clear the high bits.
2036 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2037 Fix float to int conversions to produce signed values.
2038
2039 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2040
2041 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2042 (process_instructions): Correct handling of nor instruction.
2043 Correct shift count for 32 bit shift instructions. Correct sign
2044 extension for arithmetic shifts to not shift the number of bits in
2045 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2046 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2047 Fix madd.
2048 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2049 It's OK to have a mult follow a mult. What's not OK is to have a
2050 mult follow an mfhi.
2051 (Convert): Comment out incorrect rounding code.
2052
2053 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2054
2055 * interp.c (sim_monitor): Improved monitor printf
2056 simulation. Tidied up simulator warnings, and added "--log" option
2057 for directing warning message output.
2058 * gencode.c: Use sim_warning() rather than WARNING macro.
2059
2060 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2061
2062 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2063 getopt1.o, rather than on gencode.c. Link objects together.
2064 Don't link against -liberty.
2065 (gencode.o, getopt.o, getopt1.o): New targets.
2066 * gencode.c: Include <ctype.h> and "ansidecl.h".
2067 (AND): Undefine after including "ansidecl.h".
2068 (ULONG_MAX): Define if not defined.
2069 (OP_*): Don't define macros; now defined in opcode/mips.h.
2070 (main): Call my_strtoul rather than strtoul.
2071 (my_strtoul): New static function.
2072
2073 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2074
2075 * gencode.c (process_instructions): Generate word64 and uword64
2076 instead of `long long' and `unsigned long long' data types.
2077 * interp.c: #include sysdep.h to get signals, and define default
2078 for SIGBUS.
2079 * (Convert): Work around for Visual-C++ compiler bug with type
2080 conversion.
2081 * support.h: Make things compile under Visual-C++ by using
2082 __int64 instead of `long long'. Change many refs to long long
2083 into word64/uword64 typedefs.
2084
2085 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2086
2087 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2088 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2089 (docdir): Removed.
2090 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2091 (AC_PROG_INSTALL): Added.
2092 (AC_PROG_CC): Moved to before configure.host call.
2093 * configure: Rebuilt.
2094
2095 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2096
2097 * configure.in: Define @SIMCONF@ depending on mips target.
2098 * configure: Rebuild.
2099 * Makefile.in (run): Add @SIMCONF@ to control simulator
2100 construction.
2101 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2102 * interp.c: Remove some debugging, provide more detailed error
2103 messages, update memory accesses to use LOADDRMASK.
2104
2105 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2106
2107 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2108 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2109 stamp-h.
2110 * configure: Rebuild.
2111 * config.in: New file, generated by autoheader.
2112 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2113 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2114 HAVE_ANINT and HAVE_AINT, as appropriate.
2115 * Makefile.in (run): Use @LIBS@ rather than -lm.
2116 (interp.o): Depend upon config.h.
2117 (Makefile): Just rebuild Makefile.
2118 (clean): Remove stamp-h.
2119 (mostlyclean): Make the same as clean, not as distclean.
2120 (config.h, stamp-h): New targets.
2121
2122 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2123
2124 * interp.c (ColdReset): Fix boolean test. Make all simulator
2125 globals static.
2126
2127 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2128
2129 * interp.c (xfer_direct_word, xfer_direct_long,
2130 swap_direct_word, swap_direct_long, xfer_big_word,
2131 xfer_big_long, xfer_little_word, xfer_little_long,
2132 swap_word,swap_long): Added.
2133 * interp.c (ColdReset): Provide function indirection to
2134 host<->simulated_target transfer routines.
2135 * interp.c (sim_store_register, sim_fetch_register): Updated to
2136 make use of indirected transfer routines.
2137
2138 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2139
2140 * gencode.c (process_instructions): Ensure FP ABS instruction
2141 recognised.
2142 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2143 system call support.
2144
2145 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2146
2147 * interp.c (sim_do_command): Complain if callback structure not
2148 initialised.
2149
2150 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2151
2152 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2153 support for Sun hosts.
2154 * Makefile.in (gencode): Ensure the host compiler and libraries
2155 used for cross-hosted build.
2156
2157 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2158
2159 * interp.c, gencode.c: Some more (TODO) tidying.
2160
2161 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2162
2163 * gencode.c, interp.c: Replaced explicit long long references with
2164 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2165 * support.h (SET64LO, SET64HI): Macros added.
2166
2167 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2168
2169 * configure: Regenerate with autoconf 2.7.
2170
2171 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2172
2173 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2174 * support.h: Remove superfluous "1" from #if.
2175 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2176
2177 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2178
2179 * interp.c (StoreFPR): Control UndefinedResult() call on
2180 WARN_RESULT manifest.
2181
2182 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2183
2184 * gencode.c: Tidied instruction decoding, and added FP instruction
2185 support.
2186
2187 * interp.c: Added dineroIII, and BSD profiling support. Also
2188 run-time FP handling.
2189
2190 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2191
2192 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2193 gencode.c, interp.c, support.h: created.
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