1 2011-10-19 Mike Frysinger <vapier@gentoo.org>
3 * configure: Regenerate after common/acinclude.m4 update.
5 2011-10-17 Mike Frysinger <vapier@gentoo.org>
7 * configure.ac: Change include to common/acinclude.m4.
9 2011-10-17 Mike Frysinger <vapier@gentoo.org>
11 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
12 call. Replace common.m4 include with SIM_AC_COMMON.
13 * configure: Regenerate.
15 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
17 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
19 (tmp-mach-multi): Exit early when igen fails.
21 2011-07-05 Mike Frysinger <vapier@gentoo.org>
23 * interp.c (sim_do_command): Delete.
25 2011-02-14 Mike Frysinger <vapier@gentoo.org>
27 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
28 (tx3904sio_fifo_reset): Likewise.
29 * interp.c (sim_monitor): Likewise.
31 2010-04-14 Mike Frysinger <vapier@gentoo.org>
33 * interp.c (sim_write): Add const to buffer arg.
35 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
37 * interp.c: Don't include sysdep.h
39 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
41 * configure: Regenerate.
43 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
45 * config.in: Regenerate.
46 * configure: Likewise.
48 * configure: Regenerate.
50 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
52 * configure: Regenerate to track ../common/common.m4 changes.
55 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
56 Daniel Jacobowitz <dan@codesourcery.com>
57 Joseph Myers <joseph@codesourcery.com>
59 * configure: Regenerate.
61 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
63 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
64 that unconditionally allows fmt_ps.
65 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
66 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
67 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
68 filter from 64,f to 32,f.
69 (PREFX): Change filter from 64 to 32.
70 (LDXC1, LUXC1): Provide separate mips32r2 implementations
71 that use do_load_double instead of do_load. Make both LUXC1
72 versions unpredictable if SizeFGR () != 64.
73 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
74 instead of do_store. Remove unused variable. Make both SUXC1
75 versions unpredictable if SizeFGR () != 64.
77 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
79 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
80 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
83 2007-09-04 Nick Clifton <nickc@redhat.com>
85 * interp.c (options enum): Add OPTION_INFO_MEMORY.
86 (display_mem_info): New static variable.
87 (mips_option_handler): Handle OPTION_INFO_MEMORY.
88 (mips_options): Add info-memory and memory-info.
89 (sim_open): After processing the command line and board
90 specification, check display_mem_info. If it is set then
91 call the real handler for the --memory-info command line
94 2007-08-24 Joel Brobecker <brobecker@adacore.com>
96 * configure.ac: Change license of multi-run.c to GPL version 3.
97 * configure: Regenerate.
99 2007-06-28 Richard Sandiford <richard@codesourcery.com>
101 * configure.ac, configure: Revert last patch.
103 2007-06-26 Richard Sandiford <richard@codesourcery.com>
105 * configure.ac (sim_mipsisa3264_configs): New variable.
106 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
107 every configuration support all four targets, using the triplet to
108 determine the default.
109 * configure: Regenerate.
111 2007-06-25 Richard Sandiford <richard@codesourcery.com>
113 * Makefile.in (m16run.o): New rule.
115 2007-05-15 Thiemo Seufer <ths@mips.com>
117 * mips3264r2.igen (DSHD): Fix compile warning.
119 2007-05-14 Thiemo Seufer <ths@mips.com>
121 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
122 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
123 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
124 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
127 2007-03-01 Thiemo Seufer <ths@mips.com>
129 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
132 2007-02-20 Thiemo Seufer <ths@mips.com>
134 * dsp.igen: Update copyright notice.
135 * dsp2.igen: Fix copyright notice.
137 2007-02-20 Thiemo Seufer <ths@mips.com>
138 Chao-Ying Fu <fu@mips.com>
140 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
141 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
142 Add dsp2 to sim_igen_machine.
143 * configure: Regenerate.
144 * dsp.igen (do_ph_op): Add MUL support when op = 2.
145 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
146 (mulq_rs.ph): Use do_ph_mulq.
147 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
148 * mips.igen: Add dsp2 model and include dsp2.igen.
149 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
150 for *mips32r2, *mips64r2, *dsp.
151 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
152 for *mips32r2, *mips64r2, *dsp2.
153 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
155 2007-02-19 Thiemo Seufer <ths@mips.com>
156 Nigel Stephens <nigel@mips.com>
158 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
159 jumps with hazard barrier.
161 2007-02-19 Thiemo Seufer <ths@mips.com>
162 Nigel Stephens <nigel@mips.com>
164 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
165 after each call to sim_io_write.
167 2007-02-19 Thiemo Seufer <ths@mips.com>
168 Nigel Stephens <nigel@mips.com>
170 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
171 supported by this simulator.
172 (decode_coproc): Recognise additional CP0 Config registers
175 2007-02-19 Thiemo Seufer <ths@mips.com>
176 Nigel Stephens <nigel@mips.com>
177 David Ung <davidu@mips.com>
179 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
180 uninterpreted formats. If fmt is one of the uninterpreted types
181 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
182 fmt_word, and fmt_uninterpreted_64 like fmt_long.
183 (store_fpr): When writing an invalid odd register, set the
184 matching even register to fmt_unknown, not the following register.
185 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
186 the the memory window at offset 0 set by --memory-size command
188 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
190 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
192 (sim_monitor): When returning the memory size to the MIPS
193 application, use the value in STATE_MEM_SIZE, not an arbitrary
195 (cop_lw): Don' mess around with FPR_STATE, just pass
196 fmt_uninterpreted_32 to StoreFPR.
198 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
200 * mips.igen (not_word_value): Single version for mips32, mips64
203 2007-02-19 Thiemo Seufer <ths@mips.com>
204 Nigel Stephens <nigel@mips.com>
206 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
209 2007-02-17 Thiemo Seufer <ths@mips.com>
211 * configure.ac (mips*-sde-elf*): Move in front of generic machine
213 * configure: Regenerate.
215 2007-02-17 Thiemo Seufer <ths@mips.com>
217 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
218 Add mdmx to sim_igen_machine.
219 (mipsisa64*-*-*): Likewise. Remove dsp.
220 (mipsisa32*-*-*): Remove dsp.
221 * configure: Regenerate.
223 2007-02-13 Thiemo Seufer <ths@mips.com>
225 * configure.ac: Add mips*-sde-elf* target.
226 * configure: Regenerate.
228 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
230 * acconfig.h: Remove.
231 * config.in, configure: Regenerate.
233 2006-11-07 Thiemo Seufer <ths@mips.com>
235 * dsp.igen (do_w_op): Fix compiler warning.
237 2006-08-29 Thiemo Seufer <ths@mips.com>
238 David Ung <davidu@mips.com>
240 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
242 * configure: Regenerate.
243 * mips.igen (model): Add smartmips.
244 (MADDU): Increment ACX if carry.
245 (do_mult): Clear ACX.
246 (ROR,RORV): Add smartmips.
247 (include): Include smartmips.igen.
248 * sim-main.h (ACX): Set to REGISTERS[89].
249 * smartmips.igen: New file.
251 2006-08-29 Thiemo Seufer <ths@mips.com>
252 David Ung <davidu@mips.com>
254 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
255 mips3264r2.igen. Add missing dependency rules.
256 * m16e.igen: Support for mips16e save/restore instructions.
258 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
260 * configure: Regenerated.
262 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
264 * configure: Regenerated.
266 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
268 * configure: Regenerated.
270 2006-05-15 Chao-ying Fu <fu@mips.com>
272 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
274 2006-04-18 Nick Clifton <nickc@redhat.com>
276 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
279 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
281 * configure: Regenerate.
283 2005-12-14 Chao-ying Fu <fu@mips.com>
285 * Makefile.in (SIM_OBJS): Add dsp.o.
286 (dsp.o): New dependency.
287 (IGEN_INCLUDE): Add dsp.igen.
288 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
289 mipsisa64*-*-*): Add dsp to sim_igen_machine.
290 * configure: Regenerate.
291 * mips.igen: Add dsp model and include dsp.igen.
292 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
293 because these instructions are extended in DSP ASE.
294 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
295 adding 6 DSP accumulator registers and 1 DSP control register.
296 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
297 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
298 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
299 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
300 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
301 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
302 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
303 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
304 DSPCR_CCOND_SMASK): New define.
305 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
306 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
308 2005-07-08 Ian Lance Taylor <ian@airs.com>
310 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
312 2005-06-16 David Ung <davidu@mips.com>
313 Nigel Stephens <nigel@mips.com>
315 * mips.igen: New mips16e model and include m16e.igen.
316 (check_u64): Add mips16e tag.
317 * m16e.igen: New file for MIPS16e instructions.
318 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
319 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
321 * configure: Regenerate.
323 2005-05-26 David Ung <davidu@mips.com>
325 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
326 tags to all instructions which are applicable to the new ISAs.
327 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
329 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
331 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
333 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
334 * configure: Regenerate.
336 2005-03-23 Mark Kettenis <kettenis@gnu.org>
338 * configure: Regenerate.
340 2005-01-14 Andrew Cagney <cagney@gnu.org>
342 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
343 explicit call to AC_CONFIG_HEADER.
344 * configure: Regenerate.
346 2005-01-12 Andrew Cagney <cagney@gnu.org>
348 * configure.ac: Update to use ../common/common.m4.
349 * configure: Re-generate.
351 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
353 * configure: Regenerated to track ../common/aclocal.m4 changes.
355 2005-01-07 Andrew Cagney <cagney@gnu.org>
357 * configure.ac: Rename configure.in, require autoconf 2.59.
358 * configure: Re-generate.
360 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
362 * configure: Regenerate for ../common/aclocal.m4 update.
364 2004-09-24 Monika Chaddha <monika@acmet.com>
366 Committed by Andrew Cagney.
367 * m16.igen (CMP, CMPI): Fix assembler.
369 2004-08-18 Chris Demetriou <cgd@broadcom.com>
371 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
372 * configure: Regenerate.
374 2004-06-25 Chris Demetriou <cgd@broadcom.com>
376 * configure.in (sim_m16_machine): Include mipsIII.
377 * configure: Regenerate.
379 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
381 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
383 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
385 2004-04-10 Chris Demetriou <cgd@broadcom.com>
387 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
389 2004-04-09 Chris Demetriou <cgd@broadcom.com>
391 * mips.igen (check_fmt): Remove.
392 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
393 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
394 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
395 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
396 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
397 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
398 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
399 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
400 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
401 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
403 2004-04-09 Chris Demetriou <cgd@broadcom.com>
405 * sb1.igen (check_sbx): New function.
406 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
408 2004-03-29 Chris Demetriou <cgd@broadcom.com>
409 Richard Sandiford <rsandifo@redhat.com>
411 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
412 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
413 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
414 separate implementations for mipsIV and mipsV. Use new macros to
415 determine whether the restrictions apply.
417 2004-01-19 Chris Demetriou <cgd@broadcom.com>
419 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
420 (check_mult_hilo): Improve comments.
421 (check_div_hilo): Likewise. Also, fork off a new version
422 to handle mips32/mips64 (since there are no hazards to check
425 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
427 * mips.igen (do_dmultx): Fix check for negative operands.
429 2003-05-16 Ian Lance Taylor <ian@airs.com>
431 * Makefile.in (SHELL): Make sure this is defined.
432 (various): Use $(SHELL) whenever we invoke move-if-change.
434 2003-05-03 Chris Demetriou <cgd@broadcom.com>
436 * cp1.c: Tweak attribution slightly.
439 * mdmx.igen: Likewise.
440 * mips3d.igen: Likewise.
441 * sb1.igen: Likewise.
443 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
445 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
448 2003-02-27 Andrew Cagney <cagney@redhat.com>
450 * interp.c (sim_open): Rename _bfd to bfd.
451 (sim_create_inferior): Ditto.
453 2003-01-14 Chris Demetriou <cgd@broadcom.com>
455 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
457 2003-01-14 Chris Demetriou <cgd@broadcom.com>
459 * mips.igen (EI, DI): Remove.
461 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
463 * Makefile.in (tmp-run-multi): Fix mips16 filter.
465 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
466 Andrew Cagney <ac131313@redhat.com>
467 Gavin Romig-Koch <gavin@redhat.com>
468 Graydon Hoare <graydon@redhat.com>
469 Aldy Hernandez <aldyh@redhat.com>
470 Dave Brolley <brolley@redhat.com>
471 Chris Demetriou <cgd@broadcom.com>
473 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
474 (sim_mach_default): New variable.
475 (mips64vr-*-*, mips64vrel-*-*): New configurations.
476 Add a new simulator generator, MULTI.
477 * configure: Regenerate.
478 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
479 (multi-run.o): New dependency.
480 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
481 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
482 (tmp-multi): Combine them.
483 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
484 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
485 (distclean-extra): New rule.
486 * sim-main.h: Include bfd.h.
487 (MIPS_MACH): New macro.
488 * mips.igen (vr4120, vr5400, vr5500): New models.
489 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
490 * vr.igen: Replace with new version.
492 2003-01-04 Chris Demetriou <cgd@broadcom.com>
494 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
495 * configure: Regenerate.
497 2002-12-31 Chris Demetriou <cgd@broadcom.com>
499 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
500 * mips.igen: Remove all invocations of check_branch_bug and
503 2002-12-16 Chris Demetriou <cgd@broadcom.com>
505 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
507 2002-07-30 Chris Demetriou <cgd@broadcom.com>
509 * mips.igen (do_load_double, do_store_double): New functions.
510 (LDC1, SDC1): Rename to...
511 (LDC1b, SDC1b): respectively.
512 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
514 2002-07-29 Michael Snyder <msnyder@redhat.com>
516 * cp1.c (fp_recip2): Modify initialization expression so that
517 GCC will recognize it as constant.
519 2002-06-18 Chris Demetriou <cgd@broadcom.com>
521 * mdmx.c (SD_): Delete.
522 (Unpredictable): Re-define, for now, to directly invoke
523 unpredictable_action().
524 (mdmx_acc_op): Fix error in .ob immediate handling.
526 2002-06-18 Andrew Cagney <cagney@redhat.com>
528 * interp.c (sim_firmware_command): Initialize `address'.
530 2002-06-16 Andrew Cagney <ac131313@redhat.com>
532 * configure: Regenerated to track ../common/aclocal.m4 changes.
534 2002-06-14 Chris Demetriou <cgd@broadcom.com>
535 Ed Satterthwaite <ehs@broadcom.com>
537 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
538 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
539 * mips.igen: Include mips3d.igen.
540 (mips3d): New model name for MIPS-3D ASE instructions.
541 (CVT.W.fmt): Don't use this instruction for word (source) format
543 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
544 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
545 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
546 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
547 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
548 (RSquareRoot1, RSquareRoot2): New macros.
549 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
550 (fp_rsqrt2): New functions.
551 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
552 * configure: Regenerate.
554 2002-06-13 Chris Demetriou <cgd@broadcom.com>
555 Ed Satterthwaite <ehs@broadcom.com>
557 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
558 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
559 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
560 (convert): Note that this function is not used for paired-single
562 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
563 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
564 (check_fmt_p): Enable paired-single support.
565 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
566 (PUU.PS): New instructions.
567 (CVT.S.fmt): Don't use this instruction for paired-single format
569 * sim-main.h (FP_formats): New value 'fmt_ps.'
570 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
571 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
573 2002-06-12 Chris Demetriou <cgd@broadcom.com>
575 * mips.igen: Fix formatting of function calls in
578 2002-06-12 Chris Demetriou <cgd@broadcom.com>
580 * mips.igen (MOVN, MOVZ): Trace result.
581 (TNEI): Print "tnei" as the opcode name in traces.
582 (CEIL.W): Add disassembly string for traces.
583 (RSQRT.fmt): Make location of disassembly string consistent
584 with other instructions.
586 2002-06-12 Chris Demetriou <cgd@broadcom.com>
588 * mips.igen (X): Delete unused function.
590 2002-06-08 Andrew Cagney <cagney@redhat.com>
592 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
594 2002-06-07 Chris Demetriou <cgd@broadcom.com>
595 Ed Satterthwaite <ehs@broadcom.com>
597 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
598 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
599 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
600 (fp_nmsub): New prototypes.
601 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
602 (NegMultiplySub): New defines.
603 * mips.igen (RSQRT.fmt): Use RSquareRoot().
604 (MADD.D, MADD.S): Replace with...
605 (MADD.fmt): New instruction.
606 (MSUB.D, MSUB.S): Replace with...
607 (MSUB.fmt): New instruction.
608 (NMADD.D, NMADD.S): Replace with...
609 (NMADD.fmt): New instruction.
610 (NMSUB.D, MSUB.S): Replace with...
611 (NMSUB.fmt): New instruction.
613 2002-06-07 Chris Demetriou <cgd@broadcom.com>
614 Ed Satterthwaite <ehs@broadcom.com>
616 * cp1.c: Fix more comment spelling and formatting.
617 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
618 (denorm_mode): New function.
619 (fpu_unary, fpu_binary): Round results after operation, collect
620 status from rounding operations, and update the FCSR.
621 (convert): Collect status from integer conversions and rounding
622 operations, and update the FCSR. Adjust NaN values that result
623 from conversions. Convert to use sim_io_eprintf rather than
624 fprintf, and remove some debugging code.
625 * cp1.h (fenr_FS): New define.
627 2002-06-07 Chris Demetriou <cgd@broadcom.com>
629 * cp1.c (convert): Remove unusable debugging code, and move MIPS
630 rounding mode to sim FP rounding mode flag conversion code into...
631 (rounding_mode): New function.
633 2002-06-07 Chris Demetriou <cgd@broadcom.com>
635 * cp1.c: Clean up formatting of a few comments.
636 (value_fpr): Reformat switch statement.
638 2002-06-06 Chris Demetriou <cgd@broadcom.com>
639 Ed Satterthwaite <ehs@broadcom.com>
642 * sim-main.h: Include cp1.h.
643 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
644 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
645 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
646 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
647 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
648 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
649 * cp1.c: Don't include sim-fpu.h; already included by
650 sim-main.h. Clean up formatting of some comments.
651 (NaN, Equal, Less): Remove.
652 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
653 (fp_cmp): New functions.
654 * mips.igen (do_c_cond_fmt): Remove.
655 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
656 Compare. Add result tracing.
657 (CxC1): Remove, replace with...
658 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
659 (DMxC1): Remove, replace with...
660 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
661 (MxC1): Remove, replace with...
662 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
664 2002-06-04 Chris Demetriou <cgd@broadcom.com>
666 * sim-main.h (FGRIDX): Remove, replace all uses with...
667 (FGR_BASE): New macro.
668 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
669 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
670 (NR_FGR, FGR): Likewise.
671 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
672 * mips.igen: Likewise.
674 2002-06-04 Chris Demetriou <cgd@broadcom.com>
676 * cp1.c: Add an FSF Copyright notice to this file.
678 2002-06-04 Chris Demetriou <cgd@broadcom.com>
679 Ed Satterthwaite <ehs@broadcom.com>
681 * cp1.c (Infinity): Remove.
682 * sim-main.h (Infinity): Likewise.
684 * cp1.c (fp_unary, fp_binary): New functions.
685 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
686 (fp_sqrt): New functions, implemented in terms of the above.
687 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
688 (Recip, SquareRoot): Remove (replaced by functions above).
689 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
690 (fp_recip, fp_sqrt): New prototypes.
691 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
692 (Recip, SquareRoot): Replace prototypes with #defines which
693 invoke the functions above.
695 2002-06-03 Chris Demetriou <cgd@broadcom.com>
697 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
698 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
699 file, remove PARAMS from prototypes.
700 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
701 simulator state arguments.
702 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
703 pass simulator state arguments.
704 * cp1.c (SD): Redefine as CPU_STATE(cpu).
705 (store_fpr, convert): Remove 'sd' argument.
706 (value_fpr): Likewise. Convert to use 'SD' instead.
708 2002-06-03 Chris Demetriou <cgd@broadcom.com>
710 * cp1.c (Min, Max): Remove #if 0'd functions.
711 * sim-main.h (Min, Max): Remove.
713 2002-06-03 Chris Demetriou <cgd@broadcom.com>
715 * cp1.c: fix formatting of switch case and default labels.
716 * interp.c: Likewise.
717 * sim-main.c: Likewise.
719 2002-06-03 Chris Demetriou <cgd@broadcom.com>
721 * cp1.c: Clean up comments which describe FP formats.
722 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
724 2002-06-03 Chris Demetriou <cgd@broadcom.com>
725 Ed Satterthwaite <ehs@broadcom.com>
727 * configure.in (mipsisa64sb1*-*-*): New target for supporting
728 Broadcom SiByte SB-1 processor configurations.
729 * configure: Regenerate.
730 * sb1.igen: New file.
731 * mips.igen: Include sb1.igen.
733 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
734 * mdmx.igen: Add "sb1" model to all appropriate functions and
736 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
737 (ob_func, ob_acc): Reference the above.
738 (qh_acc): Adjust to keep the same size as ob_acc.
739 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
740 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
742 2002-06-03 Chris Demetriou <cgd@broadcom.com>
744 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
746 2002-06-02 Chris Demetriou <cgd@broadcom.com>
747 Ed Satterthwaite <ehs@broadcom.com>
749 * mips.igen (mdmx): New (pseudo-)model.
750 * mdmx.c, mdmx.igen: New files.
751 * Makefile.in (SIM_OBJS): Add mdmx.o.
752 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
754 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
755 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
756 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
757 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
758 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
759 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
760 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
761 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
762 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
763 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
764 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
765 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
766 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
767 (qh_fmtsel): New macros.
768 (_sim_cpu): New member "acc".
769 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
770 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
772 2002-05-01 Chris Demetriou <cgd@broadcom.com>
774 * interp.c: Use 'deprecated' rather than 'depreciated.'
775 * sim-main.h: Likewise.
777 2002-05-01 Chris Demetriou <cgd@broadcom.com>
779 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
780 which wouldn't compile anyway.
781 * sim-main.h (unpredictable_action): New function prototype.
782 (Unpredictable): Define to call igen function unpredictable().
783 (NotWordValue): New macro to call igen function not_word_value().
784 (UndefinedResult): Remove.
785 * interp.c (undefined_result): Remove.
786 (unpredictable_action): New function.
787 * mips.igen (not_word_value, unpredictable): New functions.
788 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
789 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
790 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
791 NotWordValue() to check for unpredictable inputs, then
792 Unpredictable() to handle them.
794 2002-02-24 Chris Demetriou <cgd@broadcom.com>
796 * mips.igen: Fix formatting of calls to Unpredictable().
798 2002-04-20 Andrew Cagney <ac131313@redhat.com>
800 * interp.c (sim_open): Revert previous change.
802 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
804 * interp.c (sim_open): Disable chunk of code that wrote code in
805 vector table entries.
807 2002-03-19 Chris Demetriou <cgd@broadcom.com>
809 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
810 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
813 2002-03-19 Chris Demetriou <cgd@broadcom.com>
815 * cp1.c: Fix many formatting issues.
817 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
819 * cp1.c (fpu_format_name): New function to replace...
820 (DOFMT): This. Delete, and update all callers.
821 (fpu_rounding_mode_name): New function to replace...
822 (RMMODE): This. Delete, and update all callers.
824 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
826 * interp.c: Move FPU support routines from here to...
827 * cp1.c: Here. New file.
828 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
831 2002-03-12 Chris Demetriou <cgd@broadcom.com>
833 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
834 * mips.igen (mips32, mips64): New models, add to all instructions
835 and functions as appropriate.
836 (loadstore_ea, check_u64): New variant for model mips64.
837 (check_fmt_p): New variant for models mipsV and mips64, remove
838 mipsV model marking fro other variant.
841 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
842 for mips32 and mips64.
843 (DCLO, DCLZ): New instructions for mips64.
845 2002-03-07 Chris Demetriou <cgd@broadcom.com>
847 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
848 immediate or code as a hex value with the "%#lx" format.
849 (ANDI): Likewise, and fix printed instruction name.
851 2002-03-05 Chris Demetriou <cgd@broadcom.com>
853 * sim-main.h (UndefinedResult, Unpredictable): New macros
854 which currently do nothing.
856 2002-03-05 Chris Demetriou <cgd@broadcom.com>
858 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
859 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
860 (status_CU3): New definitions.
862 * sim-main.h (ExceptionCause): Add new values for MIPS32
863 and MIPS64: MDMX, MCheck, CacheErr. Update comments
864 for DebugBreakPoint and NMIReset to note their status in
866 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
867 (SignalExceptionCacheErr): New exception macros.
869 2002-03-05 Chris Demetriou <cgd@broadcom.com>
871 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
872 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
874 (SignalExceptionCoProcessorUnusable): Take as argument the
875 unusable coprocessor number.
877 2002-03-05 Chris Demetriou <cgd@broadcom.com>
879 * mips.igen: Fix formatting of all SignalException calls.
881 2002-03-05 Chris Demetriou <cgd@broadcom.com>
883 * sim-main.h (SIGNEXTEND): Remove.
885 2002-03-04 Chris Demetriou <cgd@broadcom.com>
887 * mips.igen: Remove gencode comment from top of file, fix
888 spelling in another comment.
890 2002-03-04 Chris Demetriou <cgd@broadcom.com>
892 * mips.igen (check_fmt, check_fmt_p): New functions to check
893 whether specific floating point formats are usable.
894 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
895 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
896 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
897 Use the new functions.
898 (do_c_cond_fmt): Remove format checks...
899 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
901 2002-03-03 Chris Demetriou <cgd@broadcom.com>
903 * mips.igen: Fix formatting of check_fpu calls.
905 2002-03-03 Chris Demetriou <cgd@broadcom.com>
907 * mips.igen (FLOOR.L.fmt): Store correct destination register.
909 2002-03-03 Chris Demetriou <cgd@broadcom.com>
911 * mips.igen: Remove whitespace at end of lines.
913 2002-03-02 Chris Demetriou <cgd@broadcom.com>
915 * mips.igen (loadstore_ea): New function to do effective
916 address calculations.
917 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
918 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
919 CACHE): Use loadstore_ea to do effective address computations.
921 2002-03-02 Chris Demetriou <cgd@broadcom.com>
923 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
924 * mips.igen (LL, CxC1, MxC1): Likewise.
926 2002-03-02 Chris Demetriou <cgd@broadcom.com>
928 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
929 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
930 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
931 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
932 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
933 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
934 Don't split opcode fields by hand, use the opcode field values
937 2002-03-01 Chris Demetriou <cgd@broadcom.com>
939 * mips.igen (do_divu): Fix spacing.
941 * mips.igen (do_dsllv): Move to be right before DSLLV,
942 to match the rest of the do_<shift> functions.
944 2002-03-01 Chris Demetriou <cgd@broadcom.com>
946 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
947 DSRL32, do_dsrlv): Trace inputs and results.
949 2002-03-01 Chris Demetriou <cgd@broadcom.com>
951 * mips.igen (CACHE): Provide instruction-printing string.
953 * interp.c (signal_exception): Comment tokens after #endif.
955 2002-02-28 Chris Demetriou <cgd@broadcom.com>
957 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
958 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
959 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
960 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
961 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
962 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
963 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
964 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
966 2002-02-28 Chris Demetriou <cgd@broadcom.com>
968 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
969 instruction-printing string.
970 (LWU): Use '64' as the filter flag.
972 2002-02-28 Chris Demetriou <cgd@broadcom.com>
974 * mips.igen (SDXC1): Fix instruction-printing string.
976 2002-02-28 Chris Demetriou <cgd@broadcom.com>
978 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
981 2002-02-27 Chris Demetriou <cgd@broadcom.com>
983 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
986 2002-02-27 Chris Demetriou <cgd@broadcom.com>
988 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
989 add a comma) so that it more closely match the MIPS ISA
990 documentation opcode partitioning.
991 (PREF): Put useful names on opcode fields, and include
992 instruction-printing string.
994 2002-02-27 Chris Demetriou <cgd@broadcom.com>
996 * mips.igen (check_u64): New function which in the future will
997 check whether 64-bit instructions are usable and signal an
998 exception if not. Currently a no-op.
999 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1000 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1001 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1002 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1004 * mips.igen (check_fpu): New function which in the future will
1005 check whether FPU instructions are usable and signal an exception
1006 if not. Currently a no-op.
1007 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1008 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1009 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1010 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1011 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1012 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1013 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1014 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1016 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1018 * mips.igen (do_load_left, do_load_right): Move to be immediately
1020 (do_store_left, do_store_right): Move to be immediately following
1023 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1025 * mips.igen (mipsV): New model name. Also, add it to
1026 all instructions and functions where it is appropriate.
1028 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1030 * mips.igen: For all functions and instructions, list model
1031 names that support that instruction one per line.
1033 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1035 * mips.igen: Add some additional comments about supported
1036 models, and about which instructions go where.
1037 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1038 order as is used in the rest of the file.
1040 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1042 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1043 indicating that ALU32_END or ALU64_END are there to check
1045 (DADD): Likewise, but also remove previous comment about
1048 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1050 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1051 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1052 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1053 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1054 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1055 fields (i.e., add and move commas) so that they more closely
1056 match the MIPS ISA documentation opcode partitioning.
1058 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1060 * mips.igen (ADDI): Print immediate value.
1061 (BREAK): Print code.
1062 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1063 (SLL): Print "nop" specially, and don't run the code
1064 that does the shift for the "nop" case.
1066 2001-11-17 Fred Fish <fnf@redhat.com>
1068 * sim-main.h (float_operation): Move enum declaration outside
1069 of _sim_cpu struct declaration.
1071 2001-04-12 Jim Blandy <jimb@redhat.com>
1073 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1074 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1076 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1077 PENDING_FILL, and you can get the intended effect gracefully by
1078 calling PENDING_SCHED directly.
1080 2001-02-23 Ben Elliston <bje@redhat.com>
1082 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1083 already defined elsewhere.
1085 2001-02-19 Ben Elliston <bje@redhat.com>
1087 * sim-main.h (sim_monitor): Return an int.
1088 * interp.c (sim_monitor): Add return values.
1089 (signal_exception): Handle error conditions from sim_monitor.
1091 2001-02-08 Ben Elliston <bje@redhat.com>
1093 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1094 (store_memory): Likewise, pass cia to sim_core_write*.
1096 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1098 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1099 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1101 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1103 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1104 * Makefile.in: Don't delete *.igen when cleaning directory.
1106 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1108 * m16.igen (break): Call SignalException not sim_engine_halt.
1110 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1112 From Jason Eckhardt:
1113 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1115 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1117 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1119 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1121 * mips.igen (do_dmultx): Fix typo.
1123 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1125 * configure: Regenerated to track ../common/aclocal.m4 changes.
1127 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1129 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1131 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1133 * sim-main.h (GPR_CLEAR): Define macro.
1135 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1137 * interp.c (decode_coproc): Output long using %lx and not %s.
1139 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1141 * interp.c (sim_open): Sort & extend dummy memory regions for
1142 --board=jmr3904 for eCos.
1144 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1146 * configure: Regenerated.
1148 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1150 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1151 calls, conditional on the simulator being in verbose mode.
1153 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1155 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1156 cache don't get ReservedInstruction traps.
1158 1999-11-29 Mark Salter <msalter@cygnus.com>
1160 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1161 to clear status bits in sdisr register. This is how the hardware works.
1163 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1164 being used by cygmon.
1166 1999-11-11 Andrew Haley <aph@cygnus.com>
1168 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1171 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1173 * mips.igen (MULT): Correct previous mis-applied patch.
1175 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1177 * mips.igen (delayslot32): Handle sequence like
1178 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1179 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1180 (MULT): Actually pass the third register...
1182 1999-09-03 Mark Salter <msalter@cygnus.com>
1184 * interp.c (sim_open): Added more memory aliases for additional
1185 hardware being touched by cygmon on jmr3904 board.
1187 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1189 * configure: Regenerated to track ../common/aclocal.m4 changes.
1191 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1193 * interp.c (sim_store_register): Handle case where client - GDB -
1194 specifies that a 4 byte register is 8 bytes in size.
1195 (sim_fetch_register): Ditto.
1197 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1199 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1200 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1201 (idt_monitor_base): Base address for IDT monitor traps.
1202 (pmon_monitor_base): Ditto for PMON.
1203 (lsipmon_monitor_base): Ditto for LSI PMON.
1204 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1205 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1206 (sim_firmware_command): New function.
1207 (mips_option_handler): Call it for OPTION_FIRMWARE.
1208 (sim_open): Allocate memory for idt_monitor region. If "--board"
1209 option was given, add no monitor by default. Add BREAK hooks only if
1210 monitors are also there.
1212 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1214 * interp.c (sim_monitor): Flush output before reading input.
1216 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1218 * tconfig.in (SIM_HANDLES_LMA): Always define.
1220 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1222 From Mark Salter <msalter@cygnus.com>:
1223 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1224 (sim_open): Add setup for BSP board.
1226 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1228 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1229 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1230 them as unimplemented.
1232 1999-05-08 Felix Lee <flee@cygnus.com>
1234 * configure: Regenerated to track ../common/aclocal.m4 changes.
1236 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1238 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1240 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1242 * configure.in: Any mips64vr5*-*-* target should have
1243 -DTARGET_ENABLE_FR=1.
1244 (default_endian): Any mips64vr*el-*-* target should default to
1246 * configure: Re-generate.
1248 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1250 * mips.igen (ldl): Extend from _16_, not 32.
1252 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1254 * interp.c (sim_store_register): Force registers written to by GDB
1255 into an un-interpreted state.
1257 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1259 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1260 CPU, start periodic background I/O polls.
1261 (tx3904sio_poll): New function: periodic I/O poller.
1263 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1265 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1267 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1269 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1272 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1274 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1275 (load_word): Call SIM_CORE_SIGNAL hook on error.
1276 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1277 starting. For exception dispatching, pass PC instead of NULL_CIA.
1278 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1279 * sim-main.h (COP0_BADVADDR): Define.
1280 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1281 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1282 (_sim_cpu): Add exc_* fields to store register value snapshots.
1283 * mips.igen (*): Replace memory-related SignalException* calls
1284 with references to SIM_CORE_SIGNAL hook.
1286 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1288 * sim-main.c (*): Minor warning cleanups.
1290 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1292 * m16.igen (DADDIU5): Correct type-o.
1294 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1296 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1299 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1301 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1303 (interp.o): Add dependency on itable.h
1304 (oengine.c, gencode): Delete remaining references.
1305 (BUILT_SRC_FROM_GEN): Clean up.
1307 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1310 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1311 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1312 tmp-run-hack) : New.
1313 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1314 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1315 Drop the "64" qualifier to get the HACK generator working.
1316 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1317 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1318 qualifier to get the hack generator working.
1319 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1320 (DSLL): Use do_dsll.
1321 (DSLLV): Use do_dsllv.
1322 (DSRA): Use do_dsra.
1323 (DSRL): Use do_dsrl.
1324 (DSRLV): Use do_dsrlv.
1325 (BC1): Move *vr4100 to get the HACK generator working.
1326 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1327 get the HACK generator working.
1328 (MACC) Rename to get the HACK generator working.
1329 (DMACC,MACCS,DMACCS): Add the 64.
1331 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1333 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1334 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1336 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1338 * mips/interp.c (DEBUG): Cleanups.
1340 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1342 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1343 (tx3904sio_tickle): fflush after a stdout character output.
1345 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1347 * interp.c (sim_close): Uninstall modules.
1349 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1351 * sim-main.h, interp.c (sim_monitor): Change to global
1354 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1356 * configure.in (vr4100): Only include vr4100 instructions in
1358 * configure: Re-generate.
1359 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1361 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1364 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1367 * configure.in (sim_default_gen, sim_use_gen): Replace with
1369 (--enable-sim-igen): Delete config option. Always using IGEN.
1370 * configure: Re-generate.
1372 * Makefile.in (gencode): Kill, kill, kill.
1375 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1377 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1378 bit mips16 igen simulator.
1379 * configure: Re-generate.
1381 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1382 as part of vr4100 ISA.
1383 * vr.igen: Mark all instructions as 64 bit only.
1385 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1387 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1390 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1392 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1393 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1394 * configure: Re-generate.
1396 * m16.igen (BREAK): Define breakpoint instruction.
1397 (JALX32): Mark instruction as mips16 and not r3900.
1398 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1400 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1402 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1404 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1405 insn as a debug breakpoint.
1407 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1409 (PENDING_SCHED): Clean up trace statement.
1410 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1411 (PENDING_FILL): Delay write by only one cycle.
1412 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1414 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1416 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1418 (pending_tick): Move incrementing of index to FOR statement.
1419 (pending_tick): Only update PENDING_OUT after a write has occured.
1421 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1423 * configure: Re-generate.
1425 * interp.c (sim_engine_run OLD): Delete explicit call to
1426 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1428 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1430 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1431 interrupt level number to match changed SignalExceptionInterrupt
1434 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1436 * interp.c: #include "itable.h" if WITH_IGEN.
1437 (get_insn_name): New function.
1438 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1439 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1441 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1443 * configure: Rebuilt to inhale new common/aclocal.m4.
1445 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1447 * dv-tx3904sio.c: Include sim-assert.h.
1449 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1451 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1452 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1453 Reorganize target-specific sim-hardware checks.
1454 * configure: rebuilt.
1455 * interp.c (sim_open): For tx39 target boards, set
1456 OPERATING_ENVIRONMENT, add tx3904sio devices.
1457 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1458 ROM executables. Install dv-sockser into sim-modules list.
1460 * dv-tx3904irc.c: Compiler warning clean-up.
1461 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1462 frequent hw-trace messages.
1464 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1466 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1468 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1470 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1472 * vr.igen: New file.
1473 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1474 * mips.igen: Define vr4100 model. Include vr.igen.
1475 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1477 * mips.igen (check_mf_hilo): Correct check.
1479 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1481 * sim-main.h (interrupt_event): Add prototype.
1483 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1484 register_ptr, register_value.
1485 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1487 * sim-main.h (tracefh): Make extern.
1489 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1491 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1492 Reduce unnecessarily high timer event frequency.
1493 * dv-tx3904cpu.c: Ditto for interrupt event.
1495 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1497 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1499 (interrupt_event): Made non-static.
1501 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1502 interchange of configuration values for external vs. internal
1505 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1507 * mips.igen (BREAK): Moved code to here for
1508 simulator-reserved break instructions.
1509 * gencode.c (build_instruction): Ditto.
1510 * interp.c (signal_exception): Code moved from here. Non-
1511 reserved instructions now use exception vector, rather
1513 * sim-main.h: Moved magic constants to here.
1515 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1517 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1518 register upon non-zero interrupt event level, clear upon zero
1520 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1521 by passing zero event value.
1522 (*_io_{read,write}_buffer): Endianness fixes.
1523 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1524 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1526 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1527 serial I/O and timer module at base address 0xFFFF0000.
1529 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1531 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1534 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1536 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1538 * configure: Update.
1540 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1542 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1543 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1544 * configure.in: Include tx3904tmr in hw_device list.
1545 * configure: Rebuilt.
1546 * interp.c (sim_open): Instantiate three timer instances.
1547 Fix address typo of tx3904irc instance.
1549 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1551 * interp.c (signal_exception): SystemCall exception now uses
1552 the exception vector.
1554 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1556 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1559 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1561 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1563 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1565 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1567 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1568 sim-main.h. Declare a struct hw_descriptor instead of struct
1569 hw_device_descriptor.
1571 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1573 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1574 right bits and then re-align left hand bytes to correct byte
1575 lanes. Fix incorrect computation in do_store_left when loading
1576 bytes from second word.
1578 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1580 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1581 * interp.c (sim_open): Only create a device tree when HW is
1584 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1585 * interp.c (signal_exception): Ditto.
1587 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1589 * gencode.c: Mark BEGEZALL as LIKELY.
1591 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1593 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1594 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1596 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1598 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1599 modules. Recognize TX39 target with "mips*tx39" pattern.
1600 * configure: Rebuilt.
1601 * sim-main.h (*): Added many macros defining bits in
1602 TX39 control registers.
1603 (SignalInterrupt): Send actual PC instead of NULL.
1604 (SignalNMIReset): New exception type.
1605 * interp.c (board): New variable for future use to identify
1606 a particular board being simulated.
1607 (mips_option_handler,mips_options): Added "--board" option.
1608 (interrupt_event): Send actual PC.
1609 (sim_open): Make memory layout conditional on board setting.
1610 (signal_exception): Initial implementation of hardware interrupt
1611 handling. Accept another break instruction variant for simulator
1613 (decode_coproc): Implement RFE instruction for TX39.
1614 (mips.igen): Decode RFE instruction as such.
1615 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1616 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1617 bbegin to implement memory map.
1618 * dv-tx3904cpu.c: New file.
1619 * dv-tx3904irc.c: New file.
1621 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1623 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1625 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1627 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1628 with calls to check_div_hilo.
1630 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1632 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1633 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1634 Add special r3900 version of do_mult_hilo.
1635 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1636 with calls to check_mult_hilo.
1637 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1638 with calls to check_div_hilo.
1640 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1642 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1643 Document a replacement.
1645 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1647 * interp.c (sim_monitor): Make mon_printf work.
1649 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1651 * sim-main.h (INSN_NAME): New arg `cpu'.
1653 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1655 * configure: Regenerated to track ../common/aclocal.m4 changes.
1657 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1659 * configure: Regenerated to track ../common/aclocal.m4 changes.
1662 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1664 * acconfig.h: New file.
1665 * configure.in: Reverted change of Apr 24; use sinclude again.
1667 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1669 * configure: Regenerated to track ../common/aclocal.m4 changes.
1672 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1674 * configure.in: Don't call sinclude.
1676 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1678 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1680 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1682 * mips.igen (ERET): Implement.
1684 * interp.c (decode_coproc): Return sign-extended EPC.
1686 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1688 * interp.c (signal_exception): Do not ignore Trap.
1689 (signal_exception): On TRAP, restart at exception address.
1690 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1691 (signal_exception): Update.
1692 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1693 so that TRAP instructions are caught.
1695 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1697 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1698 contains HI/LO access history.
1699 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1700 (HIACCESS, LOACCESS): Delete, replace with
1701 (HIHISTORY, LOHISTORY): New macros.
1702 (CHECKHILO): Delete all, moved to mips.igen
1704 * gencode.c (build_instruction): Do not generate checks for
1705 correct HI/LO register usage.
1707 * interp.c (old_engine_run): Delete checks for correct HI/LO
1710 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1711 check_mf_cycles): New functions.
1712 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1713 do_divu, domultx, do_mult, do_multu): Use.
1715 * tx.igen ("madd", "maddu"): Use.
1717 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1719 * mips.igen (DSRAV): Use function do_dsrav.
1720 (SRAV): Use new function do_srav.
1722 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1723 (B): Sign extend 11 bit immediate.
1724 (EXT-B*): Shift 16 bit immediate left by 1.
1725 (ADDIU*): Don't sign extend immediate value.
1727 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1729 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1731 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1734 * mips.igen (delayslot32, nullify_next_insn): New functions.
1735 (m16.igen): Always include.
1736 (do_*): Add more tracing.
1738 * m16.igen (delayslot16): Add NIA argument, could be called by a
1739 32 bit MIPS16 instruction.
1741 * interp.c (ifetch16): Move function from here.
1742 * sim-main.c (ifetch16): To here.
1744 * sim-main.c (ifetch16, ifetch32): Update to match current
1745 implementations of LH, LW.
1746 (signal_exception): Don't print out incorrect hex value of illegal
1749 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1751 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1754 * m16.igen: Implement MIPS16 instructions.
1756 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1757 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1758 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1759 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1760 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1761 bodies of corresponding code from 32 bit insn to these. Also used
1762 by MIPS16 versions of functions.
1764 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1765 (IMEM16): Drop NR argument from macro.
1767 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1769 * Makefile.in (SIM_OBJS): Add sim-main.o.
1771 * sim-main.h (address_translation, load_memory, store_memory,
1772 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1774 (pr_addr, pr_uword64): Declare.
1775 (sim-main.c): Include when H_REVEALS_MODULE_P.
1777 * interp.c (address_translation, load_memory, store_memory,
1778 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1780 * sim-main.c: To here. Fix compilation problems.
1782 * configure.in: Enable inlining.
1783 * configure: Re-config.
1785 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1787 * configure: Regenerated to track ../common/aclocal.m4 changes.
1789 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1791 * mips.igen: Include tx.igen.
1792 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1793 * tx.igen: New file, contains MADD and MADDU.
1795 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1796 the hardwired constant `7'.
1797 (store_memory): Ditto.
1798 (LOADDRMASK): Move definition to sim-main.h.
1800 mips.igen (MTC0): Enable for r3900.
1803 mips.igen (do_load_byte): Delete.
1804 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1805 do_store_right): New functions.
1806 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1808 configure.in: Let the tx39 use igen again.
1811 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1813 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1814 not an address sized quantity. Return zero for cache sizes.
1816 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1818 * mips.igen (r3900): r3900 does not support 64 bit integer
1821 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1823 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1825 * configure : Rebuild.
1827 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1829 * configure: Regenerated to track ../common/aclocal.m4 changes.
1831 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1833 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1835 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1837 * configure: Regenerated to track ../common/aclocal.m4 changes.
1838 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1840 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1842 * configure: Regenerated to track ../common/aclocal.m4 changes.
1844 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1846 * interp.c (Max, Min): Comment out functions. Not yet used.
1848 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1850 * configure: Regenerated to track ../common/aclocal.m4 changes.
1852 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1854 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1855 configurable settings for stand-alone simulator.
1857 * configure.in: Added X11 search, just in case.
1859 * configure: Regenerated.
1861 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1863 * interp.c (sim_write, sim_read, load_memory, store_memory):
1864 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1866 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868 * sim-main.h (GETFCC): Return an unsigned value.
1870 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1872 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1873 (DADD): Result destination is RD not RT.
1875 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877 * sim-main.h (HIACCESS, LOACCESS): Always define.
1879 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1881 * interp.c (sim_info): Delete.
1883 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1885 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1886 (mips_option_handler): New argument `cpu'.
1887 (sim_open): Update call to sim_add_option_table.
1889 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1891 * mips.igen (CxC1): Add tracing.
1893 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1895 * sim-main.h (Max, Min): Declare.
1897 * interp.c (Max, Min): New functions.
1899 * mips.igen (BC1): Add tracing.
1901 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1903 * interp.c Added memory map for stack in vr4100
1905 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1907 * interp.c (load_memory): Add missing "break"'s.
1909 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911 * interp.c (sim_store_register, sim_fetch_register): Pass in
1912 length parameter. Return -1.
1914 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1916 * interp.c: Added hardware init hook, fixed warnings.
1918 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1920 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1922 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1924 * interp.c (ifetch16): New function.
1926 * sim-main.h (IMEM32): Rename IMEM.
1927 (IMEM16_IMMED): Define.
1929 (DELAY_SLOT): Update.
1931 * m16run.c (sim_engine_run): New file.
1933 * m16.igen: All instructions except LB.
1934 (LB): Call do_load_byte.
1935 * mips.igen (do_load_byte): New function.
1936 (LB): Call do_load_byte.
1938 * mips.igen: Move spec for insn bit size and high bit from here.
1939 * Makefile.in (tmp-igen, tmp-m16): To here.
1941 * m16.dc: New file, decode mips16 instructions.
1943 * Makefile.in (SIM_NO_ALL): Define.
1944 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1946 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1948 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1949 point unit to 32 bit registers.
1950 * configure: Re-generate.
1952 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1954 * configure.in (sim_use_gen): Make IGEN the default simulator
1955 generator for generic 32 and 64 bit mips targets.
1956 * configure: Re-generate.
1958 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1960 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1963 * interp.c (sim_fetch_register, sim_store_register): Read/write
1964 FGR from correct location.
1965 (sim_open): Set size of FGR's according to
1966 WITH_TARGET_FLOATING_POINT_BITSIZE.
1968 * sim-main.h (FGR): Store floating point registers in a separate
1971 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1973 * configure: Regenerated to track ../common/aclocal.m4 changes.
1975 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1977 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1979 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1981 * interp.c (pending_tick): New function. Deliver pending writes.
1983 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1984 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1985 it can handle mixed sized quantites and single bits.
1987 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1989 * interp.c (oengine.h): Do not include when building with IGEN.
1990 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1991 (sim_info): Ditto for PROCESSOR_64BIT.
1992 (sim_monitor): Replace ut_reg with unsigned_word.
1993 (*): Ditto for t_reg.
1994 (LOADDRMASK): Define.
1995 (sim_open): Remove defunct check that host FP is IEEE compliant,
1996 using software to emulate floating point.
1997 (value_fpr, ...): Always compile, was conditional on HASFPU.
1999 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2001 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2004 * interp.c (SD, CPU): Define.
2005 (mips_option_handler): Set flags in each CPU.
2006 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2007 (sim_close): Do not clear STATE, deleted anyway.
2008 (sim_write, sim_read): Assume CPU zero's vm should be used for
2010 (sim_create_inferior): Set the PC for all processors.
2011 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2013 (mips16_entry): Pass correct nr of args to store_word, load_word.
2014 (ColdReset): Cold reset all cpu's.
2015 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2016 (sim_monitor, load_memory, store_memory, signal_exception): Use
2017 `CPU' instead of STATE_CPU.
2020 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2023 * sim-main.h (signal_exception): Add sim_cpu arg.
2024 (SignalException*): Pass both SD and CPU to signal_exception.
2025 * interp.c (signal_exception): Update.
2027 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2029 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2030 address_translation): Ditto
2031 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2033 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2035 * configure: Regenerated to track ../common/aclocal.m4 changes.
2037 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2039 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2041 * mips.igen (model): Map processor names onto BFD name.
2043 * sim-main.h (CPU_CIA): Delete.
2044 (SET_CIA, GET_CIA): Define
2046 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2048 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2051 * configure.in (default_endian): Configure a big-endian simulator
2053 * configure: Re-generate.
2055 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2057 * configure: Regenerated to track ../common/aclocal.m4 changes.
2059 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2061 * interp.c (sim_monitor): Handle Densan monitor outbyte
2062 and inbyte functions.
2064 1997-12-29 Felix Lee <flee@cygnus.com>
2066 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2068 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2070 * Makefile.in (tmp-igen): Arrange for $zero to always be
2071 reset to zero after every instruction.
2073 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2075 * configure: Regenerated to track ../common/aclocal.m4 changes.
2078 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2080 * mips.igen (MSUB): Fix to work like MADD.
2081 * gencode.c (MSUB): Similarly.
2083 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2085 * configure: Regenerated to track ../common/aclocal.m4 changes.
2087 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2089 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2091 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093 * sim-main.h (sim-fpu.h): Include.
2095 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2096 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2097 using host independant sim_fpu module.
2099 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101 * interp.c (signal_exception): Report internal errors with SIGABRT
2104 * sim-main.h (C0_CONFIG): New register.
2105 (signal.h): No longer include.
2107 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2109 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2111 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2113 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2115 * mips.igen: Tag vr5000 instructions.
2116 (ANDI): Was missing mipsIV model, fix assembler syntax.
2117 (do_c_cond_fmt): New function.
2118 (C.cond.fmt): Handle mips I-III which do not support CC field
2120 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2121 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2123 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2124 vr5000 which saves LO in a GPR separatly.
2126 * configure.in (enable-sim-igen): For vr5000, select vr5000
2127 specific instructions.
2128 * configure: Re-generate.
2130 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2134 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2135 fmt_uninterpreted_64 bit cases to switch. Convert to
2138 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2140 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2141 as specified in IV3.2 spec.
2142 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2144 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2146 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2147 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2148 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2149 PENDING_FILL versions of instructions. Simplify.
2151 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2153 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2155 (MTHI, MFHI): Disable code checking HI-LO.
2157 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2159 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2161 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2163 * gencode.c (build_mips16_operands): Replace IPC with cia.
2165 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2166 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2168 (UndefinedResult): Replace function with macro/function
2170 (sim_engine_run): Don't save PC in IPC.
2172 * sim-main.h (IPC): Delete.
2175 * interp.c (signal_exception, store_word, load_word,
2176 address_translation, load_memory, store_memory, cache_op,
2177 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2178 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2179 current instruction address - cia - argument.
2180 (sim_read, sim_write): Call address_translation directly.
2181 (sim_engine_run): Rename variable vaddr to cia.
2182 (signal_exception): Pass cia to sim_monitor
2184 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2185 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2186 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2188 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2189 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2192 * interp.c (signal_exception): Pass restart address to
2195 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2196 idecode.o): Add dependency.
2198 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2200 (DELAY_SLOT): Update NIA not PC with branch address.
2201 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2203 * mips.igen: Use CIA not PC in branch calculations.
2204 (illegal): Call SignalException.
2205 (BEQ, ADDIU): Fix assembler.
2207 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209 * m16.igen (JALX): Was missing.
2211 * configure.in (enable-sim-igen): New configuration option.
2212 * configure: Re-generate.
2214 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2216 * interp.c (load_memory, store_memory): Delete parameter RAW.
2217 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2218 bypassing {load,store}_memory.
2220 * sim-main.h (ByteSwapMem): Delete definition.
2222 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2224 * interp.c (sim_do_command, sim_commands): Delete mips specific
2225 commands. Handled by module sim-options.
2227 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2228 (WITH_MODULO_MEMORY): Define.
2230 * interp.c (sim_info): Delete code printing memory size.
2232 * interp.c (mips_size): Nee sim_size, delete function.
2234 (monitor, monitor_base, monitor_size): Delete global variables.
2235 (sim_open, sim_close): Delete code creating monitor and other
2236 memory regions. Use sim-memopts module, via sim_do_commandf, to
2237 manage memory regions.
2238 (load_memory, store_memory): Use sim-core for memory model.
2240 * interp.c (address_translation): Delete all memory map code
2241 except line forcing 32 bit addresses.
2243 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2245 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2248 * interp.c (logfh, logfile): Delete globals.
2249 (sim_open, sim_close): Delete code opening & closing log file.
2250 (mips_option_handler): Delete -l and -n options.
2251 (OPTION mips_options): Ditto.
2253 * interp.c (OPTION mips_options): Rename option trace to dinero.
2254 (mips_option_handler): Update.
2256 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2258 * interp.c (fetch_str): New function.
2259 (sim_monitor): Rewrite using sim_read & sim_write.
2260 (sim_open): Check magic number.
2261 (sim_open): Write monitor vectors into memory using sim_write.
2262 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2263 (sim_read, sim_write): Simplify - transfer data one byte at a
2265 (load_memory, store_memory): Clarify meaning of parameter RAW.
2267 * sim-main.h (isHOST): Defete definition.
2268 (isTARGET): Mark as depreciated.
2269 (address_translation): Delete parameter HOST.
2271 * interp.c (address_translation): Delete parameter HOST.
2273 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2278 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2280 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2282 * mips.igen: Add model filter field to records.
2284 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2288 interp.c (sim_engine_run): Do not compile function sim_engine_run
2289 when WITH_IGEN == 1.
2291 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2292 target architecture.
2294 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2295 igen. Replace with configuration variables sim_igen_flags /
2298 * m16.igen: New file. Copy mips16 insns here.
2299 * mips.igen: From here.
2301 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2303 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2305 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2307 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2309 * gencode.c (build_instruction): Follow sim_write's lead in using
2310 BigEndianMem instead of !ByteSwapMem.
2312 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2314 * configure.in (sim_gen): Dependent on target, select type of
2315 generator. Always select old style generator.
2317 configure: Re-generate.
2319 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2321 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2322 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2323 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2324 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2325 SIM_@sim_gen@_*, set by autoconf.
2327 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2329 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2331 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2332 CURRENT_FLOATING_POINT instead.
2334 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2335 (address_translation): Raise exception InstructionFetch when
2336 translation fails and isINSTRUCTION.
2338 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2339 sim_engine_run): Change type of of vaddr and paddr to
2341 (address_translation, prefetch, load_memory, store_memory,
2342 cache_op): Change type of vAddr and pAddr to address_word.
2344 * gencode.c (build_instruction): Change type of vaddr and paddr to
2347 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2349 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2350 macro to obtain result of ALU op.
2352 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354 * interp.c (sim_info): Call profile_print.
2356 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2358 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2360 * sim-main.h (WITH_PROFILE): Do not define, defined in
2361 common/sim-config.h. Use sim-profile module.
2362 (simPROFILE): Delete defintion.
2364 * interp.c (PROFILE): Delete definition.
2365 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2366 (sim_close): Delete code writing profile histogram.
2367 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2369 (sim_engine_run): Delete code profiling the PC.
2371 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2373 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2375 * interp.c (sim_monitor): Make register pointers of type
2378 * sim-main.h: Make registers of type unsigned_word not
2381 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2383 * interp.c (sync_operation): Rename from SyncOperation, make
2384 global, add SD argument.
2385 (prefetch): Rename from Prefetch, make global, add SD argument.
2386 (decode_coproc): Make global.
2388 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2390 * gencode.c (build_instruction): Generate DecodeCoproc not
2391 decode_coproc calls.
2393 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2394 (SizeFGR): Move to sim-main.h
2395 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2396 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2397 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2399 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2400 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2401 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2402 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2403 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2404 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2406 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2408 (sim-alu.h): Include.
2409 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2410 (sim_cia): Typedef to instruction_address.
2412 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2414 * Makefile.in (interp.o): Rename generated file engine.c to
2419 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2421 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2423 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2425 * gencode.c (build_instruction): For "FPSQRT", output correct
2426 number of arguments to Recip.
2428 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2430 * Makefile.in (interp.o): Depends on sim-main.h
2432 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2434 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2435 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2436 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2437 STATE, DSSTATE): Define
2438 (GPR, FGRIDX, ..): Define.
2440 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2441 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2442 (GPR, FGRIDX, ...): Delete macros.
2444 * interp.c: Update names to match defines from sim-main.h
2446 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2448 * interp.c (sim_monitor): Add SD argument.
2449 (sim_warning): Delete. Replace calls with calls to
2451 (sim_error): Delete. Replace calls with sim_io_error.
2452 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2453 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2454 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2456 (mips_size): Rename from sim_size. Add SD argument.
2458 * interp.c (simulator): Delete global variable.
2459 (callback): Delete global variable.
2460 (mips_option_handler, sim_open, sim_write, sim_read,
2461 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2462 sim_size,sim_monitor): Use sim_io_* not callback->*.
2463 (sim_open): ZALLOC simulator struct.
2464 (PROFILE): Do not define.
2466 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2468 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2469 support.h with corresponding code.
2471 * sim-main.h (word64, uword64), support.h: Move definition to
2473 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2476 * Makefile.in: Update dependencies
2477 * interp.c: Do not include.
2479 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2481 * interp.c (address_translation, load_memory, store_memory,
2482 cache_op): Rename to from AddressTranslation et.al., make global,
2485 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2488 * interp.c (SignalException): Rename to signal_exception, make
2491 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2493 * sim-main.h (SignalException, SignalExceptionInterrupt,
2494 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2495 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2496 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2499 * interp.c, support.h: Use.
2501 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2503 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2504 to value_fpr / store_fpr. Add SD argument.
2505 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2506 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2508 * sim-main.h (ValueFPR, StoreFPR): Define.
2510 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2512 * interp.c (sim_engine_run): Check consistency between configure
2513 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2516 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2517 (mips_fpu): Configure WITH_FLOATING_POINT.
2518 (mips_endian): Configure WITH_TARGET_ENDIAN.
2519 * configure: Update.
2521 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2523 * configure: Regenerated to track ../common/aclocal.m4 changes.
2525 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2527 * configure: Regenerated.
2529 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2531 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2533 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2535 * gencode.c (print_igen_insn_models): Assume certain architectures
2536 include all mips* instructions.
2537 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2540 * Makefile.in (tmp.igen): Add target. Generate igen input from
2543 * gencode.c (FEATURE_IGEN): Define.
2544 (main): Add --igen option. Generate output in igen format.
2545 (process_instructions): Format output according to igen option.
2546 (print_igen_insn_format): New function.
2547 (print_igen_insn_models): New function.
2548 (process_instructions): Only issue warnings and ignore
2549 instructions when no FEATURE_IGEN.
2551 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2553 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2556 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2558 * configure: Regenerated to track ../common/aclocal.m4 changes.
2560 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2563 SIM_RESERVED_BITS): Delete, moved to common.
2564 (SIM_EXTRA_CFLAGS): Update.
2566 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2568 * configure.in: Configure non-strict memory alignment.
2569 * configure: Regenerated to track ../common/aclocal.m4 changes.
2571 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2573 * configure: Regenerated to track ../common/aclocal.m4 changes.
2575 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2577 * gencode.c (SDBBP,DERET): Added (3900) insns.
2578 (RFE): Turn on for 3900.
2579 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2580 (dsstate): Made global.
2581 (SUBTARGET_R3900): Added.
2582 (CANCELDELAYSLOT): New.
2583 (SignalException): Ignore SystemCall rather than ignore and
2584 terminate. Add DebugBreakPoint handling.
2585 (decode_coproc): New insns RFE, DERET; and new registers Debug
2586 and DEPC protected by SUBTARGET_R3900.
2587 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2589 * Makefile.in,configure.in: Add mips subtarget option.
2590 * configure: Update.
2592 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2594 * gencode.c: Add r3900 (tx39).
2597 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2599 * gencode.c (build_instruction): Don't need to subtract 4 for
2602 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2604 * interp.c: Correct some HASFPU problems.
2606 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2608 * configure: Regenerated to track ../common/aclocal.m4 changes.
2610 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2612 * interp.c (mips_options): Fix samples option short form, should
2615 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2617 * interp.c (sim_info): Enable info code. Was just returning.
2619 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2621 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2624 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2626 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2628 (build_instruction): Ditto for LL.
2630 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2632 * configure: Regenerated to track ../common/aclocal.m4 changes.
2634 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2636 * configure: Regenerated to track ../common/aclocal.m4 changes.
2639 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2641 * interp.c (sim_open): Add call to sim_analyze_program, update
2644 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2646 * interp.c (sim_kill): Delete.
2647 (sim_create_inferior): Add ABFD argument. Set PC from same.
2648 (sim_load): Move code initializing trap handlers from here.
2649 (sim_open): To here.
2650 (sim_load): Delete, use sim-hload.c.
2652 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2654 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2656 * configure: Regenerated to track ../common/aclocal.m4 changes.
2659 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2661 * interp.c (sim_open): Add ABFD argument.
2662 (sim_load): Move call to sim_config from here.
2663 (sim_open): To here. Check return status.
2665 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2667 * gencode.c (build_instruction): Two arg MADD should
2668 not assign result to $0.
2670 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2672 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2673 * sim/mips/configure.in: Regenerate.
2675 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2677 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2678 signed8, unsigned8 et.al. types.
2680 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2681 hosts when selecting subreg.
2683 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2685 * interp.c (sim_engine_run): Reset the ZERO register to zero
2686 regardless of FEATURE_WARN_ZERO.
2687 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2689 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2691 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2692 (SignalException): For BreakPoints ignore any mode bits and just
2694 (SignalException): Always set the CAUSE register.
2696 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2698 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2699 exception has been taken.
2701 * interp.c: Implement the ERET and mt/f sr instructions.
2703 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2705 * interp.c (SignalException): Don't bother restarting an
2708 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2710 * interp.c (SignalException): Really take an interrupt.
2711 (interrupt_event): Only deliver interrupts when enabled.
2713 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2715 * interp.c (sim_info): Only print info when verbose.
2716 (sim_info) Use sim_io_printf for output.
2718 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2720 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2723 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725 * interp.c (sim_do_command): Check for common commands if a
2726 simulator specific command fails.
2728 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2730 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2731 and simBE when DEBUG is defined.
2733 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2735 * interp.c (interrupt_event): New function. Pass exception event
2736 onto exception handler.
2738 * configure.in: Check for stdlib.h.
2739 * configure: Regenerate.
2741 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2742 variable declaration.
2743 (build_instruction): Initialize memval1.
2744 (build_instruction): Add UNUSED attribute to byte, bigend,
2746 (build_operands): Ditto.
2748 * interp.c: Fix GCC warnings.
2749 (sim_get_quit_code): Delete.
2751 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2752 * Makefile.in: Ditto.
2753 * configure: Re-generate.
2755 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2757 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2759 * interp.c (mips_option_handler): New function parse argumes using
2761 (myname): Replace with STATE_MY_NAME.
2762 (sim_open): Delete check for host endianness - performed by
2764 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2765 (sim_open): Move much of the initialization from here.
2766 (sim_load): To here. After the image has been loaded and
2768 (sim_open): Move ColdReset from here.
2769 (sim_create_inferior): To here.
2770 (sim_open): Make FP check less dependant on host endianness.
2772 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2774 * interp.c (sim_set_callbacks): Delete.
2776 * interp.c (membank, membank_base, membank_size): Replace with
2777 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2778 (sim_open): Remove call to callback->init. gdb/run do this.
2782 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2784 * interp.c (big_endian_p): Delete, replaced by
2785 current_target_byte_order.
2787 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2789 * interp.c (host_read_long, host_read_word, host_swap_word,
2790 host_swap_long): Delete. Using common sim-endian.
2791 (sim_fetch_register, sim_store_register): Use H2T.
2792 (pipeline_ticks): Delete. Handled by sim-events.
2794 (sim_engine_run): Update.
2796 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2798 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2800 (SignalException): To here. Signal using sim_engine_halt.
2801 (sim_stop_reason): Delete, moved to common.
2803 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2805 * interp.c (sim_open): Add callback argument.
2806 (sim_set_callbacks): Delete SIM_DESC argument.
2809 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2811 * Makefile.in (SIM_OBJS): Add common modules.
2813 * interp.c (sim_set_callbacks): Also set SD callback.
2814 (set_endianness, xfer_*, swap_*): Delete.
2815 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2816 Change to functions using sim-endian macros.
2817 (control_c, sim_stop): Delete, use common version.
2818 (simulate): Convert into.
2819 (sim_engine_run): This function.
2820 (sim_resume): Delete.
2822 * interp.c (simulation): New variable - the simulator object.
2823 (sim_kind): Delete global - merged into simulation.
2824 (sim_load): Cleanup. Move PC assignment from here.
2825 (sim_create_inferior): To here.
2827 * sim-main.h: New file.
2828 * interp.c (sim-main.h): Include.
2830 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2832 * configure: Regenerated to track ../common/aclocal.m4 changes.
2834 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2836 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2838 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2840 * gencode.c (build_instruction): DIV instructions: check
2841 for division by zero and integer overflow before using
2842 host's division operation.
2844 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2846 * Makefile.in (SIM_OBJS): Add sim-load.o.
2847 * interp.c: #include bfd.h.
2848 (target_byte_order): Delete.
2849 (sim_kind, myname, big_endian_p): New static locals.
2850 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2851 after argument parsing. Recognize -E arg, set endianness accordingly.
2852 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2853 load file into simulator. Set PC from bfd.
2854 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2855 (set_endianness): Use big_endian_p instead of target_byte_order.
2857 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2859 * interp.c (sim_size): Delete prototype - conflicts with
2860 definition in remote-sim.h. Correct definition.
2862 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2864 * configure: Regenerated to track ../common/aclocal.m4 changes.
2867 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2869 * interp.c (sim_open): New arg `kind'.
2871 * configure: Regenerated to track ../common/aclocal.m4 changes.
2873 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2875 * configure: Regenerated to track ../common/aclocal.m4 changes.
2877 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2879 * interp.c (sim_open): Set optind to 0 before calling getopt.
2881 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2883 * configure: Regenerated to track ../common/aclocal.m4 changes.
2885 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2887 * interp.c : Replace uses of pr_addr with pr_uword64
2888 where the bit length is always 64 independent of SIM_ADDR.
2889 (pr_uword64) : added.
2891 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2893 * configure: Re-generate.
2895 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2897 * configure: Regenerate to track ../common/aclocal.m4 changes.
2899 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2901 * interp.c (sim_open): New SIM_DESC result. Argument is now
2903 (other sim_*): New SIM_DESC argument.
2905 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2907 * interp.c: Fix printing of addresses for non-64-bit targets.
2908 (pr_addr): Add function to print address based on size.
2910 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2912 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2914 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2916 * gencode.c (build_mips16_operands): Correct computation of base
2917 address for extended PC relative instruction.
2919 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2921 * interp.c (mips16_entry): Add support for floating point cases.
2922 (SignalException): Pass floating point cases to mips16_entry.
2923 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2925 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2927 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2928 and then set the state to fmt_uninterpreted.
2929 (COP_SW): Temporarily set the state to fmt_word while calling
2932 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2934 * gencode.c (build_instruction): The high order may be set in the
2935 comparison flags at any ISA level, not just ISA 4.
2937 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2939 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2940 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2941 * configure.in: sinclude ../common/aclocal.m4.
2942 * configure: Regenerated.
2944 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2946 * configure: Rebuild after change to aclocal.m4.
2948 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2950 * configure configure.in Makefile.in: Update to new configure
2951 scheme which is more compatible with WinGDB builds.
2952 * configure.in: Improve comment on how to run autoconf.
2953 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2954 * Makefile.in: Use autoconf substitution to install common
2957 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2959 * gencode.c (build_instruction): Use BigEndianCPU instead of
2962 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2964 * interp.c (sim_monitor): Make output to stdout visible in
2965 wingdb's I/O log window.
2967 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2969 * support.h: Undo previous change to SIGTRAP
2972 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2974 * interp.c (store_word, load_word): New static functions.
2975 (mips16_entry): New static function.
2976 (SignalException): Look for mips16 entry and exit instructions.
2977 (simulate): Use the correct index when setting fpr_state after
2978 doing a pending move.
2980 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2982 * interp.c: Fix byte-swapping code throughout to work on
2983 both little- and big-endian hosts.
2985 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2987 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2988 with gdb/config/i386/xm-windows.h.
2990 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2992 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2993 that messes up arithmetic shifts.
2995 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2997 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2998 SIGTRAP and SIGQUIT for _WIN32.
3000 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3002 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3003 force a 64 bit multiplication.
3004 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3005 destination register is 0, since that is the default mips16 nop
3008 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3010 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3011 (build_endian_shift): Don't check proc64.
3012 (build_instruction): Always set memval to uword64. Cast op2 to
3013 uword64 when shifting it left in memory instructions. Always use
3014 the same code for stores--don't special case proc64.
3016 * gencode.c (build_mips16_operands): Fix base PC value for PC
3018 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3020 * interp.c (simJALDELAYSLOT): Define.
3021 (JALDELAYSLOT): Define.
3022 (INDELAYSLOT, INJALDELAYSLOT): Define.
3023 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3025 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3027 * interp.c (sim_open): add flush_cache as a PMON routine
3028 (sim_monitor): handle flush_cache by ignoring it
3030 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3032 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3034 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3035 (BigEndianMem): Rename to ByteSwapMem and change sense.
3036 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3037 BigEndianMem references to !ByteSwapMem.
3038 (set_endianness): New function, with prototype.
3039 (sim_open): Call set_endianness.
3040 (sim_info): Use simBE instead of BigEndianMem.
3041 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3042 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3043 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3044 ifdefs, keeping the prototype declaration.
3045 (swap_word): Rewrite correctly.
3046 (ColdReset): Delete references to CONFIG. Delete endianness related
3047 code; moved to set_endianness.
3049 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3051 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3052 * interp.c (CHECKHILO): Define away.
3053 (simSIGINT): New macro.
3054 (membank_size): Increase from 1MB to 2MB.
3055 (control_c): New function.
3056 (sim_resume): Rename parameter signal to signal_number. Add local
3057 variable prev. Call signal before and after simulate.
3058 (sim_stop_reason): Add simSIGINT support.
3059 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3061 (sim_warning): Delete call to SignalException. Do call printf_filtered
3063 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3064 a call to sim_warning.
3066 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3068 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3069 16 bit instructions.
3071 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3073 Add support for mips16 (16 bit MIPS implementation):
3074 * gencode.c (inst_type): Add mips16 instruction encoding types.
3075 (GETDATASIZEINSN): Define.
3076 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3077 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3079 (MIPS16_DECODE): New table, for mips16 instructions.
3080 (bitmap_val): New static function.
3081 (struct mips16_op): Define.
3082 (mips16_op_table): New table, for mips16 operands.
3083 (build_mips16_operands): New static function.
3084 (process_instructions): If PC is odd, decode a mips16
3085 instruction. Break out instruction handling into new
3086 build_instruction function.
3087 (build_instruction): New static function, broken out of
3088 process_instructions. Check modifiers rather than flags for SHIFT
3089 bit count and m[ft]{hi,lo} direction.
3090 (usage): Pass program name to fprintf.
3091 (main): Remove unused variable this_option_optind. Change
3092 ``*loptarg++'' to ``loptarg++''.
3093 (my_strtoul): Parenthesize && within ||.
3094 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3095 (simulate): If PC is odd, fetch a 16 bit instruction, and
3096 increment PC by 2 rather than 4.
3097 * configure.in: Add case for mips16*-*-*.
3098 * configure: Rebuild.
3100 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3102 * interp.c: Allow -t to enable tracing in standalone simulator.
3103 Fix garbage output in trace file and error messages.
3105 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3107 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3108 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3109 * configure.in: Simplify using macros in ../common/aclocal.m4.
3110 * configure: Regenerated.
3111 * tconfig.in: New file.
3113 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3115 * interp.c: Fix bugs in 64-bit port.
3116 Use ansi function declarations for msvc compiler.
3117 Initialize and test file pointer in trace code.
3118 Prevent duplicate definition of LAST_EMED_REGNUM.
3120 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3122 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3124 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3126 * interp.c (SignalException): Check for explicit terminating
3128 * gencode.c: Pass instruction value through SignalException()
3129 calls for Trap, Breakpoint and Syscall.
3131 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3133 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3134 only used on those hosts that provide it.
3135 * configure.in: Add sqrt() to list of functions to be checked for.
3136 * config.in: Re-generated.
3137 * configure: Re-generated.
3139 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3141 * gencode.c (process_instructions): Call build_endian_shift when
3142 expanding STORE RIGHT, to fix swr.
3143 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3144 clear the high bits.
3145 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3146 Fix float to int conversions to produce signed values.
3148 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3150 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3151 (process_instructions): Correct handling of nor instruction.
3152 Correct shift count for 32 bit shift instructions. Correct sign
3153 extension for arithmetic shifts to not shift the number of bits in
3154 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3155 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3157 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3158 It's OK to have a mult follow a mult. What's not OK is to have a
3159 mult follow an mfhi.
3160 (Convert): Comment out incorrect rounding code.
3162 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3164 * interp.c (sim_monitor): Improved monitor printf
3165 simulation. Tidied up simulator warnings, and added "--log" option
3166 for directing warning message output.
3167 * gencode.c: Use sim_warning() rather than WARNING macro.
3169 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3171 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3172 getopt1.o, rather than on gencode.c. Link objects together.
3173 Don't link against -liberty.
3174 (gencode.o, getopt.o, getopt1.o): New targets.
3175 * gencode.c: Include <ctype.h> and "ansidecl.h".
3176 (AND): Undefine after including "ansidecl.h".
3177 (ULONG_MAX): Define if not defined.
3178 (OP_*): Don't define macros; now defined in opcode/mips.h.
3179 (main): Call my_strtoul rather than strtoul.
3180 (my_strtoul): New static function.
3182 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3184 * gencode.c (process_instructions): Generate word64 and uword64
3185 instead of `long long' and `unsigned long long' data types.
3186 * interp.c: #include sysdep.h to get signals, and define default
3188 * (Convert): Work around for Visual-C++ compiler bug with type
3190 * support.h: Make things compile under Visual-C++ by using
3191 __int64 instead of `long long'. Change many refs to long long
3192 into word64/uword64 typedefs.
3194 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3196 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3197 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3199 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3200 (AC_PROG_INSTALL): Added.
3201 (AC_PROG_CC): Moved to before configure.host call.
3202 * configure: Rebuilt.
3204 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3206 * configure.in: Define @SIMCONF@ depending on mips target.
3207 * configure: Rebuild.
3208 * Makefile.in (run): Add @SIMCONF@ to control simulator
3210 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3211 * interp.c: Remove some debugging, provide more detailed error
3212 messages, update memory accesses to use LOADDRMASK.
3214 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3216 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3217 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3219 * configure: Rebuild.
3220 * config.in: New file, generated by autoheader.
3221 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3222 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3223 HAVE_ANINT and HAVE_AINT, as appropriate.
3224 * Makefile.in (run): Use @LIBS@ rather than -lm.
3225 (interp.o): Depend upon config.h.
3226 (Makefile): Just rebuild Makefile.
3227 (clean): Remove stamp-h.
3228 (mostlyclean): Make the same as clean, not as distclean.
3229 (config.h, stamp-h): New targets.
3231 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3233 * interp.c (ColdReset): Fix boolean test. Make all simulator
3236 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3238 * interp.c (xfer_direct_word, xfer_direct_long,
3239 swap_direct_word, swap_direct_long, xfer_big_word,
3240 xfer_big_long, xfer_little_word, xfer_little_long,
3241 swap_word,swap_long): Added.
3242 * interp.c (ColdReset): Provide function indirection to
3243 host<->simulated_target transfer routines.
3244 * interp.c (sim_store_register, sim_fetch_register): Updated to
3245 make use of indirected transfer routines.
3247 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3249 * gencode.c (process_instructions): Ensure FP ABS instruction
3251 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3252 system call support.
3254 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3256 * interp.c (sim_do_command): Complain if callback structure not
3259 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3261 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3262 support for Sun hosts.
3263 * Makefile.in (gencode): Ensure the host compiler and libraries
3264 used for cross-hosted build.
3266 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3268 * interp.c, gencode.c: Some more (TODO) tidying.
3270 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3272 * gencode.c, interp.c: Replaced explicit long long references with
3273 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3274 * support.h (SET64LO, SET64HI): Macros added.
3276 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3278 * configure: Regenerate with autoconf 2.7.
3280 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3282 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3283 * support.h: Remove superfluous "1" from #if.
3284 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3286 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3288 * interp.c (StoreFPR): Control UndefinedResult() call on
3289 WARN_RESULT manifest.
3291 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3293 * gencode.c: Tidied instruction decoding, and added FP instruction
3296 * interp.c: Added dineroIII, and BSD profiling support. Also
3297 run-time FP handling.
3299 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3301 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3302 gencode.c, interp.c, support.h: created.