1 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
3 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
4 modules. Recognize TX39 target with "mips*tx39" pattern.
6 * sim-main.h (*): Added many macros defining bits in
7 TX39 control registers.
8 (SignalInterrupt): Send actual PC instead of NULL.
9 (SignalNMIReset): New exception type.
10 * interp.c (board): New variable for future use to identify
11 a particular board being simulated.
12 (mips_option_handler,mips_options): Added "--board" option.
13 (interrupt_event): Send actual PC.
14 (sim_open): Make memory layout conditional on board setting.
15 (signal_exception): Initial implementation of hardware interrupt
16 handling. Accept another break instruction variant for simulator
18 (decode_coproc): Implement RFE instruction for TX39.
19 (mips.igen): Decode RFE instruction as such.
21 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
22 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
23 bbegin to implement memory map.
24 * dv-tx3904cpu.c: New file.
25 * dv-tx3904irc.c: New file.
28 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
30 * mips.igen (check_mt_hilo): Create a separate r3900 version.
32 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
34 * r5900.igen: Replace the calls and the definition of the
35 function check_op_hilo_hi1lo1 with the pair
36 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
38 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
40 * tx.igen (madd,maddu): Replace calls to check_op_hilo
41 with calls to check_div_hilo.
43 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
45 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
46 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
47 Add special r3900 version of do_mult_hilo.
48 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
49 with calls to check_mult_hilo.
50 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
51 with calls to check_div_hilo.
53 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
55 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
56 Document a replacement.
58 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
60 * interp.c (sim_monitor): Make mon_printf work.
62 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
64 * sim-main.h (INSN_NAME): New arg `cpu'.
67 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
69 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
74 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
76 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
77 * r5900.igen (r59fp_overflow): Use.
79 * r5900.igen (r59fp_op3): Rename to
80 (r59fp_mula): This, delete opm argument.
81 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
82 (r59fp_mula): Overflowing product propogates through to result.
83 (r59fp_mula): ACC to the MAX propogates to result.
84 (r59fp_mula): Underflow during multiply only sets SU.
87 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
89 * configure: Regenerated to track ../common/aclocal.m4 changes.
91 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
93 * configure: Regenerated to track ../common/aclocal.m4 changes.
96 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
98 * acconfig.h: New file.
99 * configure.in: Reverted change of Apr 24; use sinclude again.
101 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
103 * configure: Regenerated to track ../common/aclocal.m4 changes.
106 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
108 * configure.in: Don't call sinclude.
110 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
112 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
114 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
116 * mips.igen (ERET): Implement.
118 * interp.c (decode_coproc): Return sign-extended EPC.
120 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
122 * interp.c (signal_exception): Do not ignore Trap.
123 (signal_exception): On TRAP, restart at exception address.
124 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
125 (signal_exception): Update.
126 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
127 so that TRAP instructions are caught.
129 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
131 * sim-main.h (struct hilo_access, struct hilo_history): Define,
132 contains HI/LO access history.
133 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
134 (HIACCESS, LOACCESS): Delete, replace with
135 (HIHISTORY, LOHISTORY): New macros.
136 (start-sanitize-r5900):
137 (struct sim_5900_cpu): Make hi1access, lo1access of type
139 (HI1ACCESS, LO1ACCESS): Delete, replace with
140 (HI1HISTORY, LO1HISTORY): New macros.
141 (end-sanitize-r5900):
142 (CHECKHILO): Delete all, moved to mips.igen
144 * gencode.c (build_instruction): Do not generate checks for
145 correct HI/LO register usage.
147 * interp.c (old_engine_run): Delete checks for correct HI/LO
150 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
151 check_mf_cycles): New functions.
152 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
153 do_divu, domultx, do_mult, do_multu): Use.
155 * tx.igen ("madd", "maddu"): Use.
156 (start-sanitize-r5900):
158 r5900.igen: Update all HI/LO checks.
159 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
160 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
161 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
162 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
163 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
165 (end-sanitize-r5900):
168 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
170 * interp.c (decode_coproc): Correct CMFC2/QMTC2
173 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
174 instead of a single 128-bit access.
178 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
180 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
181 * interp.c (cop_[ls]q): Fixes corresponding to above.
185 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
187 * interp.c (decode_coproc): Adapt COP2 micro interlock to
188 clarified specs. Reset "M" bit; exit also on "E" bit.
192 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
194 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
195 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
197 * r5900.igen (r59fp_unpack): New function.
198 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
199 RSQRT.S, SQRT.S): Use.
200 (r59fp_zero): New function.
201 (r59fp_overflow): Generate r5900 specific overflow value.
202 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
204 (CVT.S.W, CVT.W.S): Exchange implementations.
206 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
210 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
212 * configure.in (tx19, sim_use_gen): Switch to igen.
213 * configure: Re-build.
217 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
219 * interp.c (decode_coproc): Make COP2 branch code compile after
220 igen signature changes.
223 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
225 * mips.igen (DSRAV): Use function do_dsrav.
226 (SRAV): Use new function do_srav.
228 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
229 (B): Sign extend 11 bit immediate.
230 (EXT-B*): Shift 16 bit immediate left by 1.
231 (ADDIU*): Don't sign extend immediate value.
233 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
235 * m16run.c (sim_engine_run): Restore CIA after handling an event.
238 * mips.igen (mtc0): Valid tx19 instruction.
241 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
244 * mips.igen (delayslot32, nullify_next_insn): New functions.
245 (m16.igen): Always include.
246 (do_*): Add more tracing.
248 * m16.igen (delayslot16): Add NIA argument, could be called by a
249 32 bit MIPS16 instruction.
251 * interp.c (ifetch16): Move function from here.
252 * sim-main.c (ifetch16): To here.
254 * sim-main.c (ifetch16, ifetch32): Update to match current
255 implementations of LH, LW.
256 (signal_exception): Don't print out incorrect hex value of illegal
259 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
261 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
264 * m16.igen: Implement MIPS16 instructions.
266 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
267 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
268 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
269 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
270 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
271 bodies of corresponding code from 32 bit insn to these. Also used
272 by MIPS16 versions of functions.
274 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
275 (IMEM16): Drop NR argument from macro.
278 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
280 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
281 of VU lower instruction.
285 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
287 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
290 * sim-main.h: Removed attempt at allowing 128-bit access.
294 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
296 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
298 * interp.c (decode_coproc): Refer to VU CIA as a "special"
299 register, not as a "misc" register. Aha. Add activity
300 assertions after VCALLMS* instructions.
304 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
306 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
307 to upper code of generated VU instruction.
311 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
313 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
315 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
318 * r5900.igen (SQC2): Thinko.
322 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
324 * interp.c (*): Adapt code to merged VU device & state structs.
325 (decode_coproc): Execute COP2 each macroinstruction without
326 pipelining, by stepping VU to completion state. Adapted to
327 read_vu_*_reg style of register access.
329 * mips.igen ([SL]QC2): Removed these COP2 instructions.
331 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
333 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
336 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
338 * Makefile.in (SIM_OBJS): Add sim-main.o.
340 * sim-main.h (address_translation, load_memory, store_memory,
341 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
343 (pr_addr, pr_uword64): Declare.
344 (sim-main.c): Include when H_REVEALS_MODULE_P.
346 * interp.c (address_translation, load_memory, store_memory,
347 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
349 * sim-main.c: To here. Fix compilation problems.
351 * configure.in: Enable inlining.
352 * configure: Re-config.
354 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
356 * configure: Regenerated to track ../common/aclocal.m4 changes.
358 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
360 * mips.igen: Include tx.igen.
361 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
362 * tx.igen: New file, contains MADD and MADDU.
364 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
365 the hardwired constant `7'.
366 (store_memory): Ditto.
367 (LOADDRMASK): Move definition to sim-main.h.
369 mips.igen (MTC0): Enable for r3900.
372 mips.igen (do_load_byte): Delete.
373 (do_load, do_store, do_load_left, do_load_write, do_store_left,
374 do_store_right): New functions.
375 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
377 configure.in: Let the tx39 use igen again.
380 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
382 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
383 not an address sized quantity. Return zero for cache sizes.
385 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
387 * mips.igen (r3900): r3900 does not support 64 bit integer
391 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
393 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
397 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
399 * interp.c (decode_coproc): Continuing COP2 work.
400 (cop_[ls]q): Make sky-target-only.
402 * sim-main.h (COP_[LS]Q): Make sky-target-only.
404 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
406 * configure.in (mipstx39*-*-*): Use gencode simulator rather
408 * configure : Rebuild.
411 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
413 * interp.c (decode_coproc): Added a missing TARGET_SKY check
414 around COP2 implementation skeleton.
418 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
420 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
422 * interp.c (sim_{load,store}_register): Use new vu[01]_device
423 static to access VU registers.
424 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
425 decoding. Work in progress.
427 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
428 overlapping/redundant bit pattern.
429 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
432 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
435 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
436 access to coprocessor registers.
438 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
440 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
442 * configure: Regenerated to track ../common/aclocal.m4 changes.
444 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
446 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
448 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
450 * configure: Regenerated to track ../common/aclocal.m4 changes.
451 * config.in: Regenerated to track ../common/aclocal.m4 changes.
453 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
455 * configure: Regenerated to track ../common/aclocal.m4 changes.
457 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
459 * interp.c (Max, Min): Comment out functions. Not yet used.
461 start-sanitize-vr4320
462 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
464 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
467 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
469 * configure: Regenerated to track ../common/aclocal.m4 changes.
471 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
473 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
474 configurable settings for stand-alone simulator.
477 * configure.in: Added --with-sim-gpu2 option to specify path of
478 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
479 links/compiles stand-alone simulator with this library.
481 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
483 * configure.in: Added X11 search, just in case.
485 * configure: Regenerated.
487 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
489 * interp.c (sim_write, sim_read, load_memory, store_memory):
490 Replace sim_core_*_map with read_map, write_map, exec_map resp.
492 start-sanitize-vr4320
493 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
495 * vr4320.igen (clz,dclz) : Added.
496 (dmac): Replaced 99, with LO.
499 start-sanitize-vr5400
500 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
502 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
505 start-sanitize-vr4320
506 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
508 * vr4320.igen: New file.
509 * Makefile.in (vr4320.igen) : Added.
510 * configure.in (mips64vr4320-*-*): Added.
511 * configure : Rebuilt.
512 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
513 Add the vr4320 model entry and mark the vr4320 insn as necessary.
516 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
518 * sim-main.h (GETFCC): Return an unsigned value.
521 * r5900.igen: Use an unsigned array index variable `i'.
522 (QFSRV): Ditto for variable bytes.
525 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
527 * mips.igen (DIV): Fix check for -1 / MIN_INT.
528 (DADD): Result destination is RD not RT.
531 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
532 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
536 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
538 * sim-main.h (HIACCESS, LOACCESS): Always define.
540 * mdmx.igen (Maxi, Mini): Rename Max, Min.
542 * interp.c (sim_info): Delete.
544 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
546 * interp.c (DECLARE_OPTION_HANDLER): Use it.
547 (mips_option_handler): New argument `cpu'.
548 (sim_open): Update call to sim_add_option_table.
550 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
552 * mips.igen (CxC1): Add tracing.
555 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
557 * r5900.igen (StoreFP): Delete.
558 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
560 (rsqrt.s, sqrt.s): Implement.
561 (r59cond): New function.
562 (C.COND.S): Call r59cond in assembler line.
563 (cvt.w.s, cvt.s.w): Implement.
565 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
568 * sim-main.h: Define an enum of r5900 FCSR bit fields.
572 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
574 * r5900.igen: Add tracing to all p* instructions.
576 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
578 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
579 to get gdb talking to re-aranged sim_cpu register structure.
582 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
584 * sim-main.h (Max, Min): Declare.
586 * interp.c (Max, Min): New functions.
588 * mips.igen (BC1): Add tracing.
590 start-sanitize-vr5400
591 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
593 * mdmx.igen: Tag all functions as requiring either with mdmx or
598 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
600 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
602 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
604 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
606 * r5900.igen: Rewrite.
608 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
610 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
611 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
614 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
616 * interp.c Added memory map for stack in vr4100
618 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
620 * interp.c (load_memory): Add missing "break"'s.
622 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
624 * interp.c (sim_store_register, sim_fetch_register): Pass in
625 length parameter. Return -1.
627 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
629 * interp.c: Added hardware init hook, fixed warnings.
631 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
633 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
635 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
637 * interp.c (ifetch16): New function.
639 * sim-main.h (IMEM32): Rename IMEM.
640 (IMEM16_IMMED): Define.
642 (DELAY_SLOT): Update.
644 * m16run.c (sim_engine_run): New file.
646 * m16.igen: All instructions except LB.
647 (LB): Call do_load_byte.
648 * mips.igen (do_load_byte): New function.
649 (LB): Call do_load_byte.
651 * mips.igen: Move spec for insn bit size and high bit from here.
652 * Makefile.in (tmp-igen, tmp-m16): To here.
654 * m16.dc: New file, decode mips16 instructions.
656 * Makefile.in (SIM_NO_ALL): Define.
657 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
660 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
664 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
666 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
667 point unit to 32 bit registers.
668 * configure: Re-generate.
670 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
672 * configure.in (sim_use_gen): Make IGEN the default simulator
673 generator for generic 32 and 64 bit mips targets.
674 * configure: Re-generate.
676 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
678 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
681 * interp.c (sim_fetch_register, sim_store_register): Read/write
682 FGR from correct location.
683 (sim_open): Set size of FGR's according to
684 WITH_TARGET_FLOATING_POINT_BITSIZE.
686 * sim-main.h (FGR): Store floating point registers in a separate
689 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
691 * configure: Regenerated to track ../common/aclocal.m4 changes.
693 start-sanitize-vr5400
694 * mdmx.igen: Mark all instructions as 64bit/fp specific.
697 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
699 * interp.c (ColdReset): Call PENDING_INVALIDATE.
701 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
703 * interp.c (pending_tick): New function. Deliver pending writes.
705 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
706 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
707 it can handle mixed sized quantites and single bits.
709 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
711 * interp.c (oengine.h): Do not include when building with IGEN.
712 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
713 (sim_info): Ditto for PROCESSOR_64BIT.
714 (sim_monitor): Replace ut_reg with unsigned_word.
715 (*): Ditto for t_reg.
716 (LOADDRMASK): Define.
717 (sim_open): Remove defunct check that host FP is IEEE compliant,
718 using software to emulate floating point.
719 (value_fpr, ...): Always compile, was conditional on HASFPU.
721 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
723 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
726 * interp.c (SD, CPU): Define.
727 (mips_option_handler): Set flags in each CPU.
728 (interrupt_event): Assume CPU 0 is the one being iterrupted.
729 (sim_close): Do not clear STATE, deleted anyway.
730 (sim_write, sim_read): Assume CPU zero's vm should be used for
732 (sim_create_inferior): Set the PC for all processors.
733 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
735 (mips16_entry): Pass correct nr of args to store_word, load_word.
736 (ColdReset): Cold reset all cpu's.
737 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
738 (sim_monitor, load_memory, store_memory, signal_exception): Use
739 `CPU' instead of STATE_CPU.
742 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
745 * sim-main.h (signal_exception): Add sim_cpu arg.
746 (SignalException*): Pass both SD and CPU to signal_exception.
747 * interp.c (signal_exception): Update.
749 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
751 (sync_operation, prefetch, cache_op, store_memory, load_memory,
752 address_translation): Ditto
753 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
755 start-sanitize-vr5400
756 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
758 (ByteAlign): Use StoreFPR, pass args in correct order.
762 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
764 * configure.in (sim_igen_filter): For r5900, configure as SMP.
767 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
769 * configure: Regenerated to track ../common/aclocal.m4 changes.
771 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
774 * configure.in (sim_igen_filter): For r5900, use igen.
775 * configure: Re-generate.
778 * interp.c (sim_engine_run): Add `nr_cpus' argument.
780 * mips.igen (model): Map processor names onto BFD name.
782 * sim-main.h (CPU_CIA): Delete.
783 (SET_CIA, GET_CIA): Define
785 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
787 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
790 * configure.in (default_endian): Configure a big-endian simulator
792 * configure: Re-generate.
794 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
796 * configure: Regenerated to track ../common/aclocal.m4 changes.
798 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
800 * interp.c (sim_monitor): Handle Densan monitor outbyte
801 and inbyte functions.
803 1997-12-29 Felix Lee <flee@cygnus.com>
805 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
807 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
809 * Makefile.in (tmp-igen): Arrange for $zero to always be
810 reset to zero after every instruction.
812 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
814 * configure: Regenerated to track ../common/aclocal.m4 changes.
817 start-sanitize-vr5400
818 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
820 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
824 start-sanitize-vr5400
825 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
827 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
828 vr5400 with the vr5000 as the default.
831 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
833 * mips.igen (MSUB): Fix to work like MADD.
834 * gencode.c (MSUB): Similarly.
836 start-sanitize-vr5400
837 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
839 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
843 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
845 * configure: Regenerated to track ../common/aclocal.m4 changes.
847 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
849 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
851 start-sanitize-vr5400
852 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
853 (value_cc, store_cc): Implement.
855 * sim-main.h: Add 8*3*8 bit accumulator.
857 * vr5400.igen: Move mdmx instructins from here
858 * mdmx.igen: To here - new file. Add/fix missing instructions.
859 * mips.igen: Include mdmx.igen.
860 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
863 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
865 * sim-main.h (sim-fpu.h): Include.
867 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
868 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
869 using host independant sim_fpu module.
871 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
873 * interp.c (signal_exception): Report internal errors with SIGABRT
876 * sim-main.h (C0_CONFIG): New register.
877 (signal.h): No longer include.
879 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
881 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
883 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
885 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
887 * mips.igen: Tag vr5000 instructions.
888 (ANDI): Was missing mipsIV model, fix assembler syntax.
889 (do_c_cond_fmt): New function.
890 (C.cond.fmt): Handle mips I-III which do not support CC field
892 (bc1): Handle mips IV which do not have a delaed FCC separatly.
893 (SDR): Mask paddr when BigEndianMem, not the converse as specified
895 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
896 vr5000 which saves LO in a GPR separatly.
898 * configure.in (enable-sim-igen): For vr5000, select vr5000
899 specific instructions.
900 * configure: Re-generate.
902 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
904 * Makefile.in (SIM_OBJS): Add sim-fpu module.
906 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
907 fmt_uninterpreted_64 bit cases to switch. Convert to
910 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
912 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
913 as specified in IV3.2 spec.
914 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
916 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
918 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
919 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
920 (start-sanitize-r5900):
921 (LWXC1, SWXC1): Delete from r5900 instruction set.
922 (end-sanitize-r5900):
923 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
924 PENDING_FILL versions of instructions. Simplify.
926 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
928 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
930 (MTHI, MFHI): Disable code checking HI-LO.
932 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
934 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
936 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
938 * gencode.c (build_mips16_operands): Replace IPC with cia.
940 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
941 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
943 (UndefinedResult): Replace function with macro/function
945 (sim_engine_run): Don't save PC in IPC.
947 * sim-main.h (IPC): Delete.
949 start-sanitize-vr5400
950 * vr5400.igen (vr): Add missing cia argument to value_fpr.
951 (do_select): Rename function select.
954 * interp.c (signal_exception, store_word, load_word,
955 address_translation, load_memory, store_memory, cache_op,
956 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
957 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
958 current instruction address - cia - argument.
959 (sim_read, sim_write): Call address_translation directly.
960 (sim_engine_run): Rename variable vaddr to cia.
961 (signal_exception): Pass cia to sim_monitor
963 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
964 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
965 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
967 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
968 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
971 * interp.c (signal_exception): Pass restart address to
974 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
975 idecode.o): Add dependency.
977 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
979 (DELAY_SLOT): Update NIA not PC with branch address.
980 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
982 * mips.igen: Use CIA not PC in branch calculations.
983 (illegal): Call SignalException.
984 (BEQ, ADDIU): Fix assembler.
986 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
988 * m16.igen (JALX): Was missing.
990 * configure.in (enable-sim-igen): New configuration option.
991 * configure: Re-generate.
993 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
995 * interp.c (load_memory, store_memory): Delete parameter RAW.
996 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
997 bypassing {load,store}_memory.
999 * sim-main.h (ByteSwapMem): Delete definition.
1001 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1003 * interp.c (sim_do_command, sim_commands): Delete mips specific
1004 commands. Handled by module sim-options.
1006 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1007 (WITH_MODULO_MEMORY): Define.
1009 * interp.c (sim_info): Delete code printing memory size.
1011 * interp.c (mips_size): Nee sim_size, delete function.
1013 (monitor, monitor_base, monitor_size): Delete global variables.
1014 (sim_open, sim_close): Delete code creating monitor and other
1015 memory regions. Use sim-memopts module, via sim_do_commandf, to
1016 manage memory regions.
1017 (load_memory, store_memory): Use sim-core for memory model.
1019 * interp.c (address_translation): Delete all memory map code
1020 except line forcing 32 bit addresses.
1022 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1024 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1027 * interp.c (logfh, logfile): Delete globals.
1028 (sim_open, sim_close): Delete code opening & closing log file.
1029 (mips_option_handler): Delete -l and -n options.
1030 (OPTION mips_options): Ditto.
1032 * interp.c (OPTION mips_options): Rename option trace to dinero.
1033 (mips_option_handler): Update.
1035 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1037 * interp.c (fetch_str): New function.
1038 (sim_monitor): Rewrite using sim_read & sim_write.
1039 (sim_open): Check magic number.
1040 (sim_open): Write monitor vectors into memory using sim_write.
1041 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1042 (sim_read, sim_write): Simplify - transfer data one byte at a
1044 (load_memory, store_memory): Clarify meaning of parameter RAW.
1046 * sim-main.h (isHOST): Defete definition.
1047 (isTARGET): Mark as depreciated.
1048 (address_translation): Delete parameter HOST.
1050 * interp.c (address_translation): Delete parameter HOST.
1053 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1055 * gencode.c: Add tx49 configury and insns.
1056 * configure.in: Add tx49 configury.
1057 * configure: Update.
1060 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1064 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1065 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1067 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1069 * mips.igen: Add model filter field to records.
1071 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1073 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1075 interp.c (sim_engine_run): Do not compile function sim_engine_run
1076 when WITH_IGEN == 1.
1078 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1079 target architecture.
1081 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1082 igen. Replace with configuration variables sim_igen_flags /
1085 start-sanitize-r5900
1086 * r5900.igen: New file. Copy r5900 insns here.
1088 start-sanitize-vr5400
1089 * vr5400.igen: New file.
1091 * m16.igen: New file. Copy mips16 insns here.
1092 * mips.igen: From here.
1094 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1096 start-sanitize-vr5400
1097 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1099 * configure.in: Add mips64vr5400 target.
1100 * configure: Re-generate.
1103 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1105 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1107 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1109 * gencode.c (build_instruction): Follow sim_write's lead in using
1110 BigEndianMem instead of !ByteSwapMem.
1112 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1114 * configure.in (sim_gen): Dependent on target, select type of
1115 generator. Always select old style generator.
1117 configure: Re-generate.
1119 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1121 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1122 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1123 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1124 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1125 SIM_@sim_gen@_*, set by autoconf.
1127 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1129 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1131 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1132 CURRENT_FLOATING_POINT instead.
1134 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1135 (address_translation): Raise exception InstructionFetch when
1136 translation fails and isINSTRUCTION.
1138 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1139 sim_engine_run): Change type of of vaddr and paddr to
1141 (address_translation, prefetch, load_memory, store_memory,
1142 cache_op): Change type of vAddr and pAddr to address_word.
1144 * gencode.c (build_instruction): Change type of vaddr and paddr to
1147 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1149 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1150 macro to obtain result of ALU op.
1152 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1154 * interp.c (sim_info): Call profile_print.
1156 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1158 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1160 * sim-main.h (WITH_PROFILE): Do not define, defined in
1161 common/sim-config.h. Use sim-profile module.
1162 (simPROFILE): Delete defintion.
1164 * interp.c (PROFILE): Delete definition.
1165 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1166 (sim_close): Delete code writing profile histogram.
1167 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1169 (sim_engine_run): Delete code profiling the PC.
1171 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1173 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1175 * interp.c (sim_monitor): Make register pointers of type
1178 * sim-main.h: Make registers of type unsigned_word not
1181 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1183 start-sanitize-r5900
1184 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1185 ...): Move to sim-main.h
1188 * interp.c (sync_operation): Rename from SyncOperation, make
1189 global, add SD argument.
1190 (prefetch): Rename from Prefetch, make global, add SD argument.
1191 (decode_coproc): Make global.
1193 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1195 * gencode.c (build_instruction): Generate DecodeCoproc not
1196 decode_coproc calls.
1198 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1199 (SizeFGR): Move to sim-main.h
1200 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1201 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1202 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1204 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1205 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1206 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1207 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1208 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1209 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1211 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1213 (sim-alu.h): Include.
1214 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1215 (sim_cia): Typedef to instruction_address.
1217 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219 * Makefile.in (interp.o): Rename generated file engine.c to
1224 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1226 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1228 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1230 * gencode.c (build_instruction): For "FPSQRT", output correct
1231 number of arguments to Recip.
1233 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1235 * Makefile.in (interp.o): Depends on sim-main.h
1237 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1239 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1240 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1241 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1242 STATE, DSSTATE): Define
1243 (GPR, FGRIDX, ..): Define.
1245 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1246 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1247 (GPR, FGRIDX, ...): Delete macros.
1249 * interp.c: Update names to match defines from sim-main.h
1251 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1253 * interp.c (sim_monitor): Add SD argument.
1254 (sim_warning): Delete. Replace calls with calls to
1256 (sim_error): Delete. Replace calls with sim_io_error.
1257 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1258 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1259 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1261 (mips_size): Rename from sim_size. Add SD argument.
1263 * interp.c (simulator): Delete global variable.
1264 (callback): Delete global variable.
1265 (mips_option_handler, sim_open, sim_write, sim_read,
1266 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1267 sim_size,sim_monitor): Use sim_io_* not callback->*.
1268 (sim_open): ZALLOC simulator struct.
1269 (PROFILE): Do not define.
1271 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1273 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1274 support.h with corresponding code.
1276 * sim-main.h (word64, uword64), support.h: Move definition to
1278 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1281 * Makefile.in: Update dependencies
1282 * interp.c: Do not include.
1284 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1286 * interp.c (address_translation, load_memory, store_memory,
1287 cache_op): Rename to from AddressTranslation et.al., make global,
1290 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1293 * interp.c (SignalException): Rename to signal_exception, make
1296 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1298 * sim-main.h (SignalException, SignalExceptionInterrupt,
1299 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1300 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1301 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1304 * interp.c, support.h: Use.
1306 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1308 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1309 to value_fpr / store_fpr. Add SD argument.
1310 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1311 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1313 * sim-main.h (ValueFPR, StoreFPR): Define.
1315 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1317 * interp.c (sim_engine_run): Check consistency between configure
1318 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1321 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1322 (mips_fpu): Configure WITH_FLOATING_POINT.
1323 (mips_endian): Configure WITH_TARGET_ENDIAN.
1324 * configure: Update.
1326 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1328 * configure: Regenerated to track ../common/aclocal.m4 changes.
1330 start-sanitize-r5900
1331 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1333 * interp.c (MAX_REG): Allow up-to 128 registers.
1334 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1335 (REGISTER_SA): Ditto.
1336 (sim_open): Initialize register_widths for r5900 specific
1338 (sim_fetch_register, sim_store_register): Check for request of
1339 r5900 specific SA register. Check for request for hi 64 bits of
1340 r5900 specific registers.
1343 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1345 * configure: Regenerated.
1347 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1349 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1351 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1353 * gencode.c (print_igen_insn_models): Assume certain architectures
1354 include all mips* instructions.
1355 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1358 * Makefile.in (tmp.igen): Add target. Generate igen input from
1361 * gencode.c (FEATURE_IGEN): Define.
1362 (main): Add --igen option. Generate output in igen format.
1363 (process_instructions): Format output according to igen option.
1364 (print_igen_insn_format): New function.
1365 (print_igen_insn_models): New function.
1366 (process_instructions): Only issue warnings and ignore
1367 instructions when no FEATURE_IGEN.
1369 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1371 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1374 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1376 * configure: Regenerated to track ../common/aclocal.m4 changes.
1378 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1380 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1381 SIM_RESERVED_BITS): Delete, moved to common.
1382 (SIM_EXTRA_CFLAGS): Update.
1384 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1386 * configure.in: Configure non-strict memory alignment.
1387 * configure: Regenerated to track ../common/aclocal.m4 changes.
1389 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391 * configure: Regenerated to track ../common/aclocal.m4 changes.
1393 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1395 * gencode.c (SDBBP,DERET): Added (3900) insns.
1396 (RFE): Turn on for 3900.
1397 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1398 (dsstate): Made global.
1399 (SUBTARGET_R3900): Added.
1400 (CANCELDELAYSLOT): New.
1401 (SignalException): Ignore SystemCall rather than ignore and
1402 terminate. Add DebugBreakPoint handling.
1403 (decode_coproc): New insns RFE, DERET; and new registers Debug
1404 and DEPC protected by SUBTARGET_R3900.
1405 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1407 * Makefile.in,configure.in: Add mips subtarget option.
1408 * configure: Update.
1410 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1412 * gencode.c: Add r3900 (tx39).
1415 * gencode.c: Fix some configuration problems by improving
1416 the relationship between tx19 and tx39.
1419 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1421 * gencode.c (build_instruction): Don't need to subtract 4 for
1424 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1426 * interp.c: Correct some HASFPU problems.
1428 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1430 * configure: Regenerated to track ../common/aclocal.m4 changes.
1432 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1434 * interp.c (mips_options): Fix samples option short form, should
1437 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1439 * interp.c (sim_info): Enable info code. Was just returning.
1441 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1443 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1446 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1448 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1450 (build_instruction): Ditto for LL.
1453 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1455 * mips/configure.in, mips/gencode: Add tx19/r1900.
1458 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1460 * configure: Regenerated to track ../common/aclocal.m4 changes.
1462 start-sanitize-r5900
1463 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1466 for overflow due to ABS of MININT, set result to MAXINT.
1467 (build_instruction): For "psrlvw", signextend bit 31.
1470 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472 * configure: Regenerated to track ../common/aclocal.m4 changes.
1475 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477 * interp.c (sim_open): Add call to sim_analyze_program, update
1480 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482 * interp.c (sim_kill): Delete.
1483 (sim_create_inferior): Add ABFD argument. Set PC from same.
1484 (sim_load): Move code initializing trap handlers from here.
1485 (sim_open): To here.
1486 (sim_load): Delete, use sim-hload.c.
1488 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1490 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1492 * configure: Regenerated to track ../common/aclocal.m4 changes.
1495 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1497 * interp.c (sim_open): Add ABFD argument.
1498 (sim_load): Move call to sim_config from here.
1499 (sim_open): To here. Check return status.
1501 start-sanitize-r5900
1502 * gencode.c (build_instruction): Do not define x8000000000000000,
1503 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1506 start-sanitize-r5900
1507 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1509 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1510 "pdivuw" check for overflow due to signed divide by -1.
1513 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1515 * gencode.c (build_instruction): Two arg MADD should
1516 not assign result to $0.
1518 start-sanitize-r5900
1519 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1521 * gencode.c (build_instruction): For "ppac5" use unsigned
1522 arrithmetic so that the sign bit doesn't smear when right shifted.
1523 (build_instruction): For "pdiv" perform sign extension when
1524 storing results in HI and LO.
1525 (build_instructions): For "pdiv" and "pdivbw" check for
1527 (build_instruction): For "pmfhl.slw" update hi part of dest
1528 register as well as low part.
1529 (build_instruction): For "pmfhl" portably handle long long values.
1530 (build_instruction): For "pmfhl.sh" correctly negative values.
1531 Store half words 2 and three in the correct place.
1532 (build_instruction): For "psllvw", sign extend value after shift.
1535 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1537 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1538 * sim/mips/configure.in: Regenerate.
1540 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1542 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1543 signed8, unsigned8 et.al. types.
1545 start-sanitize-r5900
1546 * gencode.c (build_instruction): For PMULTU* do not sign extend
1547 registers. Make generated code easier to debug.
1550 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1551 hosts when selecting subreg.
1553 start-sanitize-r5900
1554 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1556 * gencode.c (type_for_data_len): For 32bit operations concerned
1557 with overflow, perform op using 64bits.
1558 (build_instruction): For PADD, always compute operation using type
1559 returned by type_for_data_len.
1560 (build_instruction): For PSUBU, when overflow, saturate to zero as
1564 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1566 start-sanitize-r5900
1567 * gencode.c (build_instruction): Handle "pext5" according to
1568 version 1.95 of the r5900 ISA.
1570 * gencode.c (build_instruction): Handle "ppac5" according to
1571 version 1.95 of the r5900 ISA.
1574 * interp.c (sim_engine_run): Reset the ZERO register to zero
1575 regardless of FEATURE_WARN_ZERO.
1576 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1578 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1580 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1581 (SignalException): For BreakPoints ignore any mode bits and just
1583 (SignalException): Always set the CAUSE register.
1585 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1587 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1588 exception has been taken.
1590 * interp.c: Implement the ERET and mt/f sr instructions.
1592 start-sanitize-r5900
1593 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595 * gencode.c (build_instruction): For paddu, extract unsigned
1598 * gencode.c (build_instruction): Saturate padds instead of padd
1602 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1604 * interp.c (SignalException): Don't bother restarting an
1607 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1609 * interp.c (SignalException): Really take an interrupt.
1610 (interrupt_event): Only deliver interrupts when enabled.
1612 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614 * interp.c (sim_info): Only print info when verbose.
1615 (sim_info) Use sim_io_printf for output.
1617 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1619 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1622 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1624 * interp.c (sim_do_command): Check for common commands if a
1625 simulator specific command fails.
1627 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1629 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1630 and simBE when DEBUG is defined.
1632 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1634 * interp.c (interrupt_event): New function. Pass exception event
1635 onto exception handler.
1637 * configure.in: Check for stdlib.h.
1638 * configure: Regenerate.
1640 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1641 variable declaration.
1642 (build_instruction): Initialize memval1.
1643 (build_instruction): Add UNUSED attribute to byte, bigend,
1645 (build_operands): Ditto.
1647 * interp.c: Fix GCC warnings.
1648 (sim_get_quit_code): Delete.
1650 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1651 * Makefile.in: Ditto.
1652 * configure: Re-generate.
1654 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1656 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658 * interp.c (mips_option_handler): New function parse argumes using
1660 (myname): Replace with STATE_MY_NAME.
1661 (sim_open): Delete check for host endianness - performed by
1663 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1664 (sim_open): Move much of the initialization from here.
1665 (sim_load): To here. After the image has been loaded and
1667 (sim_open): Move ColdReset from here.
1668 (sim_create_inferior): To here.
1669 (sim_open): Make FP check less dependant on host endianness.
1671 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1673 * interp.c (sim_set_callbacks): Delete.
1675 * interp.c (membank, membank_base, membank_size): Replace with
1676 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1677 (sim_open): Remove call to callback->init. gdb/run do this.
1681 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1683 * interp.c (big_endian_p): Delete, replaced by
1684 current_target_byte_order.
1686 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1688 * interp.c (host_read_long, host_read_word, host_swap_word,
1689 host_swap_long): Delete. Using common sim-endian.
1690 (sim_fetch_register, sim_store_register): Use H2T.
1691 (pipeline_ticks): Delete. Handled by sim-events.
1693 (sim_engine_run): Update.
1695 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1697 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1699 (SignalException): To here. Signal using sim_engine_halt.
1700 (sim_stop_reason): Delete, moved to common.
1702 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1704 * interp.c (sim_open): Add callback argument.
1705 (sim_set_callbacks): Delete SIM_DESC argument.
1708 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1710 * Makefile.in (SIM_OBJS): Add common modules.
1712 * interp.c (sim_set_callbacks): Also set SD callback.
1713 (set_endianness, xfer_*, swap_*): Delete.
1714 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1715 Change to functions using sim-endian macros.
1716 (control_c, sim_stop): Delete, use common version.
1717 (simulate): Convert into.
1718 (sim_engine_run): This function.
1719 (sim_resume): Delete.
1721 * interp.c (simulation): New variable - the simulator object.
1722 (sim_kind): Delete global - merged into simulation.
1723 (sim_load): Cleanup. Move PC assignment from here.
1724 (sim_create_inferior): To here.
1726 * sim-main.h: New file.
1727 * interp.c (sim-main.h): Include.
1729 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1731 * configure: Regenerated to track ../common/aclocal.m4 changes.
1733 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1735 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1737 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1739 * gencode.c (build_instruction): DIV instructions: check
1740 for division by zero and integer overflow before using
1741 host's division operation.
1743 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1745 * Makefile.in (SIM_OBJS): Add sim-load.o.
1746 * interp.c: #include bfd.h.
1747 (target_byte_order): Delete.
1748 (sim_kind, myname, big_endian_p): New static locals.
1749 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1750 after argument parsing. Recognize -E arg, set endianness accordingly.
1751 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1752 load file into simulator. Set PC from bfd.
1753 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1754 (set_endianness): Use big_endian_p instead of target_byte_order.
1756 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1758 * interp.c (sim_size): Delete prototype - conflicts with
1759 definition in remote-sim.h. Correct definition.
1761 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1763 * configure: Regenerated to track ../common/aclocal.m4 changes.
1766 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1768 * interp.c (sim_open): New arg `kind'.
1770 * configure: Regenerated to track ../common/aclocal.m4 changes.
1772 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1774 * configure: Regenerated to track ../common/aclocal.m4 changes.
1776 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1778 * interp.c (sim_open): Set optind to 0 before calling getopt.
1780 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1782 * configure: Regenerated to track ../common/aclocal.m4 changes.
1784 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1786 * interp.c : Replace uses of pr_addr with pr_uword64
1787 where the bit length is always 64 independent of SIM_ADDR.
1788 (pr_uword64) : added.
1790 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1792 * configure: Re-generate.
1794 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1796 * configure: Regenerate to track ../common/aclocal.m4 changes.
1798 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1800 * interp.c (sim_open): New SIM_DESC result. Argument is now
1802 (other sim_*): New SIM_DESC argument.
1804 start-sanitize-r5900
1805 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1807 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1808 Change values to avoid overloading DOUBLEWORD which is tested
1810 * gencode.c: reinstate "offending code".
1813 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1815 * interp.c: Fix printing of addresses for non-64-bit targets.
1816 (pr_addr): Add function to print address based on size.
1817 start-sanitize-r5900
1818 * gencode.c: #ifdef out offending code until a permanent fix
1819 can be added. Code is causing build errors for non-5900 mips targets.
1822 start-sanitize-r5900
1823 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1825 * gencode.c (process_instructions): Correct test for ISA dependent
1826 architecture bits in isa field of MIPS_DECODE.
1829 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1831 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1833 start-sanitize-r5900
1834 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1836 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1840 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1842 * gencode.c (build_mips16_operands): Correct computation of base
1843 address for extended PC relative instruction.
1845 start-sanitize-r5900
1846 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1848 * Makefile.in, configure, configure.in, gencode.c,
1849 interp.c, support.h: add r5900.
1852 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1854 * interp.c (mips16_entry): Add support for floating point cases.
1855 (SignalException): Pass floating point cases to mips16_entry.
1856 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1858 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1860 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1861 and then set the state to fmt_uninterpreted.
1862 (COP_SW): Temporarily set the state to fmt_word while calling
1865 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1867 * gencode.c (build_instruction): The high order may be set in the
1868 comparison flags at any ISA level, not just ISA 4.
1870 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1872 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1873 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1874 * configure.in: sinclude ../common/aclocal.m4.
1875 * configure: Regenerated.
1877 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1879 * configure: Rebuild after change to aclocal.m4.
1881 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1883 * configure configure.in Makefile.in: Update to new configure
1884 scheme which is more compatible with WinGDB builds.
1885 * configure.in: Improve comment on how to run autoconf.
1886 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1887 * Makefile.in: Use autoconf substitution to install common
1890 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1892 * gencode.c (build_instruction): Use BigEndianCPU instead of
1895 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1897 * interp.c (sim_monitor): Make output to stdout visible in
1898 wingdb's I/O log window.
1900 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1902 * support.h: Undo previous change to SIGTRAP
1905 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1907 * interp.c (store_word, load_word): New static functions.
1908 (mips16_entry): New static function.
1909 (SignalException): Look for mips16 entry and exit instructions.
1910 (simulate): Use the correct index when setting fpr_state after
1911 doing a pending move.
1913 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1915 * interp.c: Fix byte-swapping code throughout to work on
1916 both little- and big-endian hosts.
1918 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1920 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1921 with gdb/config/i386/xm-windows.h.
1923 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1925 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1926 that messes up arithmetic shifts.
1928 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1930 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1931 SIGTRAP and SIGQUIT for _WIN32.
1933 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1935 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1936 force a 64 bit multiplication.
1937 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1938 destination register is 0, since that is the default mips16 nop
1941 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1943 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1944 (build_endian_shift): Don't check proc64.
1945 (build_instruction): Always set memval to uword64. Cast op2 to
1946 uword64 when shifting it left in memory instructions. Always use
1947 the same code for stores--don't special case proc64.
1949 * gencode.c (build_mips16_operands): Fix base PC value for PC
1951 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1953 * interp.c (simJALDELAYSLOT): Define.
1954 (JALDELAYSLOT): Define.
1955 (INDELAYSLOT, INJALDELAYSLOT): Define.
1956 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1958 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1960 * interp.c (sim_open): add flush_cache as a PMON routine
1961 (sim_monitor): handle flush_cache by ignoring it
1963 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1965 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1967 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1968 (BigEndianMem): Rename to ByteSwapMem and change sense.
1969 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1970 BigEndianMem references to !ByteSwapMem.
1971 (set_endianness): New function, with prototype.
1972 (sim_open): Call set_endianness.
1973 (sim_info): Use simBE instead of BigEndianMem.
1974 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1975 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1976 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1977 ifdefs, keeping the prototype declaration.
1978 (swap_word): Rewrite correctly.
1979 (ColdReset): Delete references to CONFIG. Delete endianness related
1980 code; moved to set_endianness.
1982 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1984 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1985 * interp.c (CHECKHILO): Define away.
1986 (simSIGINT): New macro.
1987 (membank_size): Increase from 1MB to 2MB.
1988 (control_c): New function.
1989 (sim_resume): Rename parameter signal to signal_number. Add local
1990 variable prev. Call signal before and after simulate.
1991 (sim_stop_reason): Add simSIGINT support.
1992 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1994 (sim_warning): Delete call to SignalException. Do call printf_filtered
1996 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1997 a call to sim_warning.
1999 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2001 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2002 16 bit instructions.
2004 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2006 Add support for mips16 (16 bit MIPS implementation):
2007 * gencode.c (inst_type): Add mips16 instruction encoding types.
2008 (GETDATASIZEINSN): Define.
2009 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2010 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2012 (MIPS16_DECODE): New table, for mips16 instructions.
2013 (bitmap_val): New static function.
2014 (struct mips16_op): Define.
2015 (mips16_op_table): New table, for mips16 operands.
2016 (build_mips16_operands): New static function.
2017 (process_instructions): If PC is odd, decode a mips16
2018 instruction. Break out instruction handling into new
2019 build_instruction function.
2020 (build_instruction): New static function, broken out of
2021 process_instructions. Check modifiers rather than flags for SHIFT
2022 bit count and m[ft]{hi,lo} direction.
2023 (usage): Pass program name to fprintf.
2024 (main): Remove unused variable this_option_optind. Change
2025 ``*loptarg++'' to ``loptarg++''.
2026 (my_strtoul): Parenthesize && within ||.
2027 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2028 (simulate): If PC is odd, fetch a 16 bit instruction, and
2029 increment PC by 2 rather than 4.
2030 * configure.in: Add case for mips16*-*-*.
2031 * configure: Rebuild.
2033 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2035 * interp.c: Allow -t to enable tracing in standalone simulator.
2036 Fix garbage output in trace file and error messages.
2038 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2040 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2041 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2042 * configure.in: Simplify using macros in ../common/aclocal.m4.
2043 * configure: Regenerated.
2044 * tconfig.in: New file.
2046 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2048 * interp.c: Fix bugs in 64-bit port.
2049 Use ansi function declarations for msvc compiler.
2050 Initialize and test file pointer in trace code.
2051 Prevent duplicate definition of LAST_EMED_REGNUM.
2053 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2055 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2057 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2059 * interp.c (SignalException): Check for explicit terminating
2061 * gencode.c: Pass instruction value through SignalException()
2062 calls for Trap, Breakpoint and Syscall.
2064 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2066 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2067 only used on those hosts that provide it.
2068 * configure.in: Add sqrt() to list of functions to be checked for.
2069 * config.in: Re-generated.
2070 * configure: Re-generated.
2072 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2074 * gencode.c (process_instructions): Call build_endian_shift when
2075 expanding STORE RIGHT, to fix swr.
2076 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2077 clear the high bits.
2078 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2079 Fix float to int conversions to produce signed values.
2081 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2083 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2084 (process_instructions): Correct handling of nor instruction.
2085 Correct shift count for 32 bit shift instructions. Correct sign
2086 extension for arithmetic shifts to not shift the number of bits in
2087 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2088 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2090 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2091 It's OK to have a mult follow a mult. What's not OK is to have a
2092 mult follow an mfhi.
2093 (Convert): Comment out incorrect rounding code.
2095 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2097 * interp.c (sim_monitor): Improved monitor printf
2098 simulation. Tidied up simulator warnings, and added "--log" option
2099 for directing warning message output.
2100 * gencode.c: Use sim_warning() rather than WARNING macro.
2102 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2104 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2105 getopt1.o, rather than on gencode.c. Link objects together.
2106 Don't link against -liberty.
2107 (gencode.o, getopt.o, getopt1.o): New targets.
2108 * gencode.c: Include <ctype.h> and "ansidecl.h".
2109 (AND): Undefine after including "ansidecl.h".
2110 (ULONG_MAX): Define if not defined.
2111 (OP_*): Don't define macros; now defined in opcode/mips.h.
2112 (main): Call my_strtoul rather than strtoul.
2113 (my_strtoul): New static function.
2115 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2117 * gencode.c (process_instructions): Generate word64 and uword64
2118 instead of `long long' and `unsigned long long' data types.
2119 * interp.c: #include sysdep.h to get signals, and define default
2121 * (Convert): Work around for Visual-C++ compiler bug with type
2123 * support.h: Make things compile under Visual-C++ by using
2124 __int64 instead of `long long'. Change many refs to long long
2125 into word64/uword64 typedefs.
2127 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2129 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2130 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2132 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2133 (AC_PROG_INSTALL): Added.
2134 (AC_PROG_CC): Moved to before configure.host call.
2135 * configure: Rebuilt.
2137 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2139 * configure.in: Define @SIMCONF@ depending on mips target.
2140 * configure: Rebuild.
2141 * Makefile.in (run): Add @SIMCONF@ to control simulator
2143 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2144 * interp.c: Remove some debugging, provide more detailed error
2145 messages, update memory accesses to use LOADDRMASK.
2147 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2149 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2150 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2152 * configure: Rebuild.
2153 * config.in: New file, generated by autoheader.
2154 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2155 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2156 HAVE_ANINT and HAVE_AINT, as appropriate.
2157 * Makefile.in (run): Use @LIBS@ rather than -lm.
2158 (interp.o): Depend upon config.h.
2159 (Makefile): Just rebuild Makefile.
2160 (clean): Remove stamp-h.
2161 (mostlyclean): Make the same as clean, not as distclean.
2162 (config.h, stamp-h): New targets.
2164 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2166 * interp.c (ColdReset): Fix boolean test. Make all simulator
2169 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2171 * interp.c (xfer_direct_word, xfer_direct_long,
2172 swap_direct_word, swap_direct_long, xfer_big_word,
2173 xfer_big_long, xfer_little_word, xfer_little_long,
2174 swap_word,swap_long): Added.
2175 * interp.c (ColdReset): Provide function indirection to
2176 host<->simulated_target transfer routines.
2177 * interp.c (sim_store_register, sim_fetch_register): Updated to
2178 make use of indirected transfer routines.
2180 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2182 * gencode.c (process_instructions): Ensure FP ABS instruction
2184 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2185 system call support.
2187 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2189 * interp.c (sim_do_command): Complain if callback structure not
2192 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2194 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2195 support for Sun hosts.
2196 * Makefile.in (gencode): Ensure the host compiler and libraries
2197 used for cross-hosted build.
2199 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2201 * interp.c, gencode.c: Some more (TODO) tidying.
2203 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2205 * gencode.c, interp.c: Replaced explicit long long references with
2206 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2207 * support.h (SET64LO, SET64HI): Macros added.
2209 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2211 * configure: Regenerate with autoconf 2.7.
2213 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2215 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2216 * support.h: Remove superfluous "1" from #if.
2217 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2219 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2221 * interp.c (StoreFPR): Control UndefinedResult() call on
2222 WARN_RESULT manifest.
2224 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2226 * gencode.c: Tidied instruction decoding, and added FP instruction
2229 * interp.c: Added dineroIII, and BSD profiling support. Also
2230 run-time FP handling.
2232 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2234 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2235 gencode.c, interp.c, support.h: created.