1 2002-02-28 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (SDXC1): Fix instruction-printing string.
5 2002-02-28 Chris Demetriou <cgd@broadcom.com>
7 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
10 2002-02-27 Chris Demetriou <cgd@broadcom.com>
12 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
15 2002-02-27 Chris Demetriou <cgd@broadcom.com>
17 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
18 add a comma) so that it more closely match the MIPS ISA
19 documentation opcode partitioning.
20 (PREF): Put useful names on opcode fields, and include
21 instruction-printing string.
23 2002-02-27 Chris Demetriou <cgd@broadcom.com>
25 * mips.igen (check_u64): New function which in the future will
26 check whether 64-bit instructions are usable and signal an
27 exception if not. Currently a no-op.
28 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
29 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
30 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
31 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
33 * mips.igen (check_fpu): New function which in the future will
34 check whether FPU instructions are usable and signal an exception
35 if not. Currently a no-op.
36 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
37 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
38 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
39 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
40 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
41 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
42 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
43 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
45 2002-02-27 Chris Demetriou <cgd@broadcom.com>
47 * mips.igen (do_load_left, do_load_right): Move to be immediately
49 (do_store_left, do_store_right): Move to be immediately following
52 2002-02-27 Chris Demetriou <cgd@broadcom.com>
54 * mips.igen (mipsV): New model name. Also, add it to
55 all instructions and functions where it is appropriate.
57 2002-02-18 Chris Demetriou <cgd@broadcom.com>
59 * mips.igen: For all functions and instructions, list model
60 names that support that instruction one per line.
62 2002-02-11 Chris Demetriou <cgd@broadcom.com>
64 * mips.igen: Add some additional comments about supported
65 models, and about which instructions go where.
66 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
67 order as is used in the rest of the file.
69 2002-02-11 Chris Demetriou <cgd@broadcom.com>
71 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
72 indicating that ALU32_END or ALU64_END are there to check
74 (DADD): Likewise, but also remove previous comment about
77 2002-02-10 Chris Demetriou <cgd@broadcom.com>
79 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
80 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
81 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
82 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
83 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
84 fields (i.e., add and move commas) so that they more closely
85 match the MIPS ISA documentation opcode partitioning.
87 2002-02-10 Chris Demetriou <cgd@broadcom.com>
89 * mips.igen (ADDI): Print immediate value.
91 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
92 (SLL): Print "nop" specially, and don't run the code
93 that does the shift for the "nop" case.
95 2001-11-17 Fred Fish <fnf@redhat.com>
97 * sim-main.h (float_operation): Move enum declaration outside
98 of _sim_cpu struct declaration.
100 2001-04-12 Jim Blandy <jimb@redhat.com>
102 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
103 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
105 * sim-main.h (COCIDX): Remove definition; this isn't supported by
106 PENDING_FILL, and you can get the intended effect gracefully by
107 calling PENDING_SCHED directly.
109 2001-02-23 Ben Elliston <bje@redhat.com>
111 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
112 already defined elsewhere.
114 2001-02-19 Ben Elliston <bje@redhat.com>
116 * sim-main.h (sim_monitor): Return an int.
117 * interp.c (sim_monitor): Add return values.
118 (signal_exception): Handle error conditions from sim_monitor.
120 2001-02-08 Ben Elliston <bje@redhat.com>
122 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
123 (store_memory): Likewise, pass cia to sim_core_write*.
125 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
127 On advice from Chris G. Demetriou <cgd@sibyte.com>:
128 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
130 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
132 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
133 * Makefile.in: Don't delete *.igen when cleaning directory.
135 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
137 * m16.igen (break): Call SignalException not sim_engine_halt.
139 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
142 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
144 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
146 * mips.igen (MxC1, DMxC1): Fix printf formatting.
148 2000-05-24 Michael Hayes <mhayes@cygnus.com>
150 * mips.igen (do_dmultx): Fix typo.
152 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
154 * configure: Regenerated to track ../common/aclocal.m4 changes.
156 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
158 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
160 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
162 * sim-main.h (GPR_CLEAR): Define macro.
164 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
166 * interp.c (decode_coproc): Output long using %lx and not %s.
168 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
170 * interp.c (sim_open): Sort & extend dummy memory regions for
171 --board=jmr3904 for eCos.
173 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
175 * configure: Regenerated.
177 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
179 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
180 calls, conditional on the simulator being in verbose mode.
182 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
184 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
185 cache don't get ReservedInstruction traps.
187 1999-11-29 Mark Salter <msalter@cygnus.com>
189 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
190 to clear status bits in sdisr register. This is how the hardware works.
192 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
193 being used by cygmon.
195 1999-11-11 Andrew Haley <aph@cygnus.com>
197 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
200 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
202 * mips.igen (MULT): Correct previous mis-applied patch.
204 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
206 * mips.igen (delayslot32): Handle sequence like
207 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
208 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
209 (MULT): Actually pass the third register...
211 1999-09-03 Mark Salter <msalter@cygnus.com>
213 * interp.c (sim_open): Added more memory aliases for additional
214 hardware being touched by cygmon on jmr3904 board.
216 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
218 * configure: Regenerated to track ../common/aclocal.m4 changes.
220 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
222 * interp.c (sim_store_register): Handle case where client - GDB -
223 specifies that a 4 byte register is 8 bytes in size.
224 (sim_fetch_register): Ditto.
226 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
228 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
229 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
230 (idt_monitor_base): Base address for IDT monitor traps.
231 (pmon_monitor_base): Ditto for PMON.
232 (lsipmon_monitor_base): Ditto for LSI PMON.
233 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
234 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
235 (sim_firmware_command): New function.
236 (mips_option_handler): Call it for OPTION_FIRMWARE.
237 (sim_open): Allocate memory for idt_monitor region. If "--board"
238 option was given, add no monitor by default. Add BREAK hooks only if
239 monitors are also there.
241 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
243 * interp.c (sim_monitor): Flush output before reading input.
245 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
247 * tconfig.in (SIM_HANDLES_LMA): Always define.
249 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
251 From Mark Salter <msalter@cygnus.com>:
252 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
253 (sim_open): Add setup for BSP board.
255 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
257 * mips.igen (MULT, MULTU): Add syntax for two operand version.
258 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
259 them as unimplemented.
261 1999-05-08 Felix Lee <flee@cygnus.com>
263 * configure: Regenerated to track ../common/aclocal.m4 changes.
265 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
267 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
269 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
271 * configure.in: Any mips64vr5*-*-* target should have
272 -DTARGET_ENABLE_FR=1.
273 (default_endian): Any mips64vr*el-*-* target should default to
275 * configure: Re-generate.
277 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
279 * mips.igen (ldl): Extend from _16_, not 32.
281 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
283 * interp.c (sim_store_register): Force registers written to by GDB
284 into an un-interpreted state.
286 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
288 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
289 CPU, start periodic background I/O polls.
290 (tx3904sio_poll): New function: periodic I/O poller.
292 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
294 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
296 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
298 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
301 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
303 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
304 (load_word): Call SIM_CORE_SIGNAL hook on error.
305 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
306 starting. For exception dispatching, pass PC instead of NULL_CIA.
307 (decode_coproc): Use COP0_BADVADDR to store faulting address.
308 * sim-main.h (COP0_BADVADDR): Define.
309 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
310 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
311 (_sim_cpu): Add exc_* fields to store register value snapshots.
312 * mips.igen (*): Replace memory-related SignalException* calls
313 with references to SIM_CORE_SIGNAL hook.
315 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
317 * sim-main.c (*): Minor warning cleanups.
319 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
321 * m16.igen (DADDIU5): Correct type-o.
323 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
325 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
328 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
330 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
332 (interp.o): Add dependency on itable.h
333 (oengine.c, gencode): Delete remaining references.
334 (BUILT_SRC_FROM_GEN): Clean up.
336 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
339 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
340 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
342 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
343 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
344 Drop the "64" qualifier to get the HACK generator working.
345 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
346 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
347 qualifier to get the hack generator working.
348 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
350 (DSLLV): Use do_dsllv.
353 (DSRLV): Use do_dsrlv.
354 (BC1): Move *vr4100 to get the HACK generator working.
355 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
356 get the HACK generator working.
357 (MACC) Rename to get the HACK generator working.
358 (DMACC,MACCS,DMACCS): Add the 64.
360 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
362 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
363 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
365 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
367 * mips/interp.c (DEBUG): Cleanups.
369 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
371 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
372 (tx3904sio_tickle): fflush after a stdout character output.
374 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
376 * interp.c (sim_close): Uninstall modules.
378 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
380 * sim-main.h, interp.c (sim_monitor): Change to global
383 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
385 * configure.in (vr4100): Only include vr4100 instructions in
387 * configure: Re-generate.
388 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
390 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
392 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
393 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
396 * configure.in (sim_default_gen, sim_use_gen): Replace with
398 (--enable-sim-igen): Delete config option. Always using IGEN.
399 * configure: Re-generate.
401 * Makefile.in (gencode): Kill, kill, kill.
404 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
406 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
407 bit mips16 igen simulator.
408 * configure: Re-generate.
410 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
411 as part of vr4100 ISA.
412 * vr.igen: Mark all instructions as 64 bit only.
414 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
416 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
419 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
421 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
422 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
423 * configure: Re-generate.
425 * m16.igen (BREAK): Define breakpoint instruction.
426 (JALX32): Mark instruction as mips16 and not r3900.
427 * mips.igen (C.cond.fmt): Fix typo in instruction format.
429 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
431 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
433 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
434 insn as a debug breakpoint.
436 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
438 (PENDING_SCHED): Clean up trace statement.
439 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
440 (PENDING_FILL): Delay write by only one cycle.
441 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
443 * sim-main.c (pending_tick): Clean up trace statements. Add trace
445 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
447 (pending_tick): Move incrementing of index to FOR statement.
448 (pending_tick): Only update PENDING_OUT after a write has occured.
450 * configure.in: Add explicit mips-lsi-* target. Use gencode to
452 * configure: Re-generate.
454 * interp.c (sim_engine_run OLD): Delete explicit call to
455 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
457 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
459 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
460 interrupt level number to match changed SignalExceptionInterrupt
463 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
465 * interp.c: #include "itable.h" if WITH_IGEN.
466 (get_insn_name): New function.
467 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
468 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
470 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
472 * configure: Rebuilt to inhale new common/aclocal.m4.
474 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
476 * dv-tx3904sio.c: Include sim-assert.h.
478 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
480 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
481 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
482 Reorganize target-specific sim-hardware checks.
483 * configure: rebuilt.
484 * interp.c (sim_open): For tx39 target boards, set
485 OPERATING_ENVIRONMENT, add tx3904sio devices.
486 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
487 ROM executables. Install dv-sockser into sim-modules list.
489 * dv-tx3904irc.c: Compiler warning clean-up.
490 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
491 frequent hw-trace messages.
493 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
495 * vr.igen (MulAcc): Identify as a vr4100 specific function.
497 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
499 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
502 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
503 * mips.igen: Define vr4100 model. Include vr.igen.
504 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
506 * mips.igen (check_mf_hilo): Correct check.
508 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
510 * sim-main.h (interrupt_event): Add prototype.
512 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
513 register_ptr, register_value.
514 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
516 * sim-main.h (tracefh): Make extern.
518 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
520 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
521 Reduce unnecessarily high timer event frequency.
522 * dv-tx3904cpu.c: Ditto for interrupt event.
524 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
526 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
528 (interrupt_event): Made non-static.
530 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
531 interchange of configuration values for external vs. internal
534 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
536 * mips.igen (BREAK): Moved code to here for
537 simulator-reserved break instructions.
538 * gencode.c (build_instruction): Ditto.
539 * interp.c (signal_exception): Code moved from here. Non-
540 reserved instructions now use exception vector, rather
542 * sim-main.h: Moved magic constants to here.
544 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
546 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
547 register upon non-zero interrupt event level, clear upon zero
549 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
550 by passing zero event value.
551 (*_io_{read,write}_buffer): Endianness fixes.
552 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
553 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
555 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
556 serial I/O and timer module at base address 0xFFFF0000.
558 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
560 * mips.igen (SWC1) : Correct the handling of ReverseEndian
563 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
565 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
569 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
571 * dv-tx3904tmr.c: New file - implements tx3904 timer.
572 * dv-tx3904{irc,cpu}.c: Mild reformatting.
573 * configure.in: Include tx3904tmr in hw_device list.
574 * configure: Rebuilt.
575 * interp.c (sim_open): Instantiate three timer instances.
576 Fix address typo of tx3904irc instance.
578 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
580 * interp.c (signal_exception): SystemCall exception now uses
581 the exception vector.
583 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
585 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
588 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
590 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
592 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
594 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
596 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
597 sim-main.h. Declare a struct hw_descriptor instead of struct
598 hw_device_descriptor.
600 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
602 * mips.igen (do_store_left, do_load_left): Compute nr of left and
603 right bits and then re-align left hand bytes to correct byte
604 lanes. Fix incorrect computation in do_store_left when loading
605 bytes from second word.
607 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
609 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
610 * interp.c (sim_open): Only create a device tree when HW is
613 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
614 * interp.c (signal_exception): Ditto.
616 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
618 * gencode.c: Mark BEGEZALL as LIKELY.
620 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
622 * sim-main.h (ALU32_END): Sign extend 32 bit results.
623 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
625 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
627 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
628 modules. Recognize TX39 target with "mips*tx39" pattern.
629 * configure: Rebuilt.
630 * sim-main.h (*): Added many macros defining bits in
631 TX39 control registers.
632 (SignalInterrupt): Send actual PC instead of NULL.
633 (SignalNMIReset): New exception type.
634 * interp.c (board): New variable for future use to identify
635 a particular board being simulated.
636 (mips_option_handler,mips_options): Added "--board" option.
637 (interrupt_event): Send actual PC.
638 (sim_open): Make memory layout conditional on board setting.
639 (signal_exception): Initial implementation of hardware interrupt
640 handling. Accept another break instruction variant for simulator
642 (decode_coproc): Implement RFE instruction for TX39.
643 (mips.igen): Decode RFE instruction as such.
644 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
645 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
646 bbegin to implement memory map.
647 * dv-tx3904cpu.c: New file.
648 * dv-tx3904irc.c: New file.
650 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
652 * mips.igen (check_mt_hilo): Create a separate r3900 version.
654 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
656 * tx.igen (madd,maddu): Replace calls to check_op_hilo
657 with calls to check_div_hilo.
659 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
661 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
662 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
663 Add special r3900 version of do_mult_hilo.
664 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
665 with calls to check_mult_hilo.
666 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
667 with calls to check_div_hilo.
669 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
671 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
672 Document a replacement.
674 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
676 * interp.c (sim_monitor): Make mon_printf work.
678 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
680 * sim-main.h (INSN_NAME): New arg `cpu'.
682 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
684 * configure: Regenerated to track ../common/aclocal.m4 changes.
686 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
688 * configure: Regenerated to track ../common/aclocal.m4 changes.
691 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
693 * acconfig.h: New file.
694 * configure.in: Reverted change of Apr 24; use sinclude again.
696 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
698 * configure: Regenerated to track ../common/aclocal.m4 changes.
701 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
703 * configure.in: Don't call sinclude.
705 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
707 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
709 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
711 * mips.igen (ERET): Implement.
713 * interp.c (decode_coproc): Return sign-extended EPC.
715 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
717 * interp.c (signal_exception): Do not ignore Trap.
718 (signal_exception): On TRAP, restart at exception address.
719 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
720 (signal_exception): Update.
721 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
722 so that TRAP instructions are caught.
724 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
726 * sim-main.h (struct hilo_access, struct hilo_history): Define,
727 contains HI/LO access history.
728 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
729 (HIACCESS, LOACCESS): Delete, replace with
730 (HIHISTORY, LOHISTORY): New macros.
731 (CHECKHILO): Delete all, moved to mips.igen
733 * gencode.c (build_instruction): Do not generate checks for
734 correct HI/LO register usage.
736 * interp.c (old_engine_run): Delete checks for correct HI/LO
739 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
740 check_mf_cycles): New functions.
741 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
742 do_divu, domultx, do_mult, do_multu): Use.
744 * tx.igen ("madd", "maddu"): Use.
746 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
748 * mips.igen (DSRAV): Use function do_dsrav.
749 (SRAV): Use new function do_srav.
751 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
752 (B): Sign extend 11 bit immediate.
753 (EXT-B*): Shift 16 bit immediate left by 1.
754 (ADDIU*): Don't sign extend immediate value.
756 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
758 * m16run.c (sim_engine_run): Restore CIA after handling an event.
760 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
763 * mips.igen (delayslot32, nullify_next_insn): New functions.
764 (m16.igen): Always include.
765 (do_*): Add more tracing.
767 * m16.igen (delayslot16): Add NIA argument, could be called by a
768 32 bit MIPS16 instruction.
770 * interp.c (ifetch16): Move function from here.
771 * sim-main.c (ifetch16): To here.
773 * sim-main.c (ifetch16, ifetch32): Update to match current
774 implementations of LH, LW.
775 (signal_exception): Don't print out incorrect hex value of illegal
778 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
780 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
783 * m16.igen: Implement MIPS16 instructions.
785 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
786 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
787 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
788 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
789 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
790 bodies of corresponding code from 32 bit insn to these. Also used
791 by MIPS16 versions of functions.
793 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
794 (IMEM16): Drop NR argument from macro.
796 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
798 * Makefile.in (SIM_OBJS): Add sim-main.o.
800 * sim-main.h (address_translation, load_memory, store_memory,
801 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
803 (pr_addr, pr_uword64): Declare.
804 (sim-main.c): Include when H_REVEALS_MODULE_P.
806 * interp.c (address_translation, load_memory, store_memory,
807 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
809 * sim-main.c: To here. Fix compilation problems.
811 * configure.in: Enable inlining.
812 * configure: Re-config.
814 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
816 * configure: Regenerated to track ../common/aclocal.m4 changes.
818 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
820 * mips.igen: Include tx.igen.
821 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
822 * tx.igen: New file, contains MADD and MADDU.
824 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
825 the hardwired constant `7'.
826 (store_memory): Ditto.
827 (LOADDRMASK): Move definition to sim-main.h.
829 mips.igen (MTC0): Enable for r3900.
832 mips.igen (do_load_byte): Delete.
833 (do_load, do_store, do_load_left, do_load_write, do_store_left,
834 do_store_right): New functions.
835 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
837 configure.in: Let the tx39 use igen again.
840 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
842 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
843 not an address sized quantity. Return zero for cache sizes.
845 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
847 * mips.igen (r3900): r3900 does not support 64 bit integer
850 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
852 * configure.in (mipstx39*-*-*): Use gencode simulator rather
854 * configure : Rebuild.
856 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
858 * configure: Regenerated to track ../common/aclocal.m4 changes.
860 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
862 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
864 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
866 * configure: Regenerated to track ../common/aclocal.m4 changes.
867 * config.in: Regenerated to track ../common/aclocal.m4 changes.
869 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
871 * configure: Regenerated to track ../common/aclocal.m4 changes.
873 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
875 * interp.c (Max, Min): Comment out functions. Not yet used.
877 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
879 * configure: Regenerated to track ../common/aclocal.m4 changes.
881 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
883 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
884 configurable settings for stand-alone simulator.
886 * configure.in: Added X11 search, just in case.
888 * configure: Regenerated.
890 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
892 * interp.c (sim_write, sim_read, load_memory, store_memory):
893 Replace sim_core_*_map with read_map, write_map, exec_map resp.
895 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
897 * sim-main.h (GETFCC): Return an unsigned value.
899 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
901 * mips.igen (DIV): Fix check for -1 / MIN_INT.
902 (DADD): Result destination is RD not RT.
904 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
906 * sim-main.h (HIACCESS, LOACCESS): Always define.
908 * mdmx.igen (Maxi, Mini): Rename Max, Min.
910 * interp.c (sim_info): Delete.
912 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
914 * interp.c (DECLARE_OPTION_HANDLER): Use it.
915 (mips_option_handler): New argument `cpu'.
916 (sim_open): Update call to sim_add_option_table.
918 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
920 * mips.igen (CxC1): Add tracing.
922 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
924 * sim-main.h (Max, Min): Declare.
926 * interp.c (Max, Min): New functions.
928 * mips.igen (BC1): Add tracing.
930 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
932 * interp.c Added memory map for stack in vr4100
934 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
936 * interp.c (load_memory): Add missing "break"'s.
938 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
940 * interp.c (sim_store_register, sim_fetch_register): Pass in
941 length parameter. Return -1.
943 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
945 * interp.c: Added hardware init hook, fixed warnings.
947 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
949 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
951 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
953 * interp.c (ifetch16): New function.
955 * sim-main.h (IMEM32): Rename IMEM.
956 (IMEM16_IMMED): Define.
958 (DELAY_SLOT): Update.
960 * m16run.c (sim_engine_run): New file.
962 * m16.igen: All instructions except LB.
963 (LB): Call do_load_byte.
964 * mips.igen (do_load_byte): New function.
965 (LB): Call do_load_byte.
967 * mips.igen: Move spec for insn bit size and high bit from here.
968 * Makefile.in (tmp-igen, tmp-m16): To here.
970 * m16.dc: New file, decode mips16 instructions.
972 * Makefile.in (SIM_NO_ALL): Define.
973 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
975 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
977 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
978 point unit to 32 bit registers.
979 * configure: Re-generate.
981 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
983 * configure.in (sim_use_gen): Make IGEN the default simulator
984 generator for generic 32 and 64 bit mips targets.
985 * configure: Re-generate.
987 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
989 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
992 * interp.c (sim_fetch_register, sim_store_register): Read/write
993 FGR from correct location.
994 (sim_open): Set size of FGR's according to
995 WITH_TARGET_FLOATING_POINT_BITSIZE.
997 * sim-main.h (FGR): Store floating point registers in a separate
1000 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1002 * configure: Regenerated to track ../common/aclocal.m4 changes.
1004 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1006 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1008 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1010 * interp.c (pending_tick): New function. Deliver pending writes.
1012 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1013 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1014 it can handle mixed sized quantites and single bits.
1016 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1018 * interp.c (oengine.h): Do not include when building with IGEN.
1019 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1020 (sim_info): Ditto for PROCESSOR_64BIT.
1021 (sim_monitor): Replace ut_reg with unsigned_word.
1022 (*): Ditto for t_reg.
1023 (LOADDRMASK): Define.
1024 (sim_open): Remove defunct check that host FP is IEEE compliant,
1025 using software to emulate floating point.
1026 (value_fpr, ...): Always compile, was conditional on HASFPU.
1028 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1030 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1033 * interp.c (SD, CPU): Define.
1034 (mips_option_handler): Set flags in each CPU.
1035 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1036 (sim_close): Do not clear STATE, deleted anyway.
1037 (sim_write, sim_read): Assume CPU zero's vm should be used for
1039 (sim_create_inferior): Set the PC for all processors.
1040 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1042 (mips16_entry): Pass correct nr of args to store_word, load_word.
1043 (ColdReset): Cold reset all cpu's.
1044 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1045 (sim_monitor, load_memory, store_memory, signal_exception): Use
1046 `CPU' instead of STATE_CPU.
1049 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1052 * sim-main.h (signal_exception): Add sim_cpu arg.
1053 (SignalException*): Pass both SD and CPU to signal_exception.
1054 * interp.c (signal_exception): Update.
1056 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1058 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1059 address_translation): Ditto
1060 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1062 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064 * configure: Regenerated to track ../common/aclocal.m4 changes.
1066 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1068 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1070 * mips.igen (model): Map processor names onto BFD name.
1072 * sim-main.h (CPU_CIA): Delete.
1073 (SET_CIA, GET_CIA): Define
1075 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1077 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1080 * configure.in (default_endian): Configure a big-endian simulator
1082 * configure: Re-generate.
1084 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1086 * configure: Regenerated to track ../common/aclocal.m4 changes.
1088 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1090 * interp.c (sim_monitor): Handle Densan monitor outbyte
1091 and inbyte functions.
1093 1997-12-29 Felix Lee <flee@cygnus.com>
1095 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1097 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1099 * Makefile.in (tmp-igen): Arrange for $zero to always be
1100 reset to zero after every instruction.
1102 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1104 * configure: Regenerated to track ../common/aclocal.m4 changes.
1107 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1109 * mips.igen (MSUB): Fix to work like MADD.
1110 * gencode.c (MSUB): Similarly.
1112 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1114 * configure: Regenerated to track ../common/aclocal.m4 changes.
1116 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1118 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1120 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1122 * sim-main.h (sim-fpu.h): Include.
1124 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1125 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1126 using host independant sim_fpu module.
1128 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1130 * interp.c (signal_exception): Report internal errors with SIGABRT
1133 * sim-main.h (C0_CONFIG): New register.
1134 (signal.h): No longer include.
1136 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1138 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1140 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1142 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1144 * mips.igen: Tag vr5000 instructions.
1145 (ANDI): Was missing mipsIV model, fix assembler syntax.
1146 (do_c_cond_fmt): New function.
1147 (C.cond.fmt): Handle mips I-III which do not support CC field
1149 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1150 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1152 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1153 vr5000 which saves LO in a GPR separatly.
1155 * configure.in (enable-sim-igen): For vr5000, select vr5000
1156 specific instructions.
1157 * configure: Re-generate.
1159 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1161 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1163 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1164 fmt_uninterpreted_64 bit cases to switch. Convert to
1167 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1169 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1170 as specified in IV3.2 spec.
1171 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1173 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1175 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1176 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1177 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1178 PENDING_FILL versions of instructions. Simplify.
1180 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1182 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1184 (MTHI, MFHI): Disable code checking HI-LO.
1186 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1188 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1190 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1192 * gencode.c (build_mips16_operands): Replace IPC with cia.
1194 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1195 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1197 (UndefinedResult): Replace function with macro/function
1199 (sim_engine_run): Don't save PC in IPC.
1201 * sim-main.h (IPC): Delete.
1204 * interp.c (signal_exception, store_word, load_word,
1205 address_translation, load_memory, store_memory, cache_op,
1206 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1207 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1208 current instruction address - cia - argument.
1209 (sim_read, sim_write): Call address_translation directly.
1210 (sim_engine_run): Rename variable vaddr to cia.
1211 (signal_exception): Pass cia to sim_monitor
1213 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1214 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1215 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1217 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1218 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1221 * interp.c (signal_exception): Pass restart address to
1224 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1225 idecode.o): Add dependency.
1227 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1229 (DELAY_SLOT): Update NIA not PC with branch address.
1230 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1232 * mips.igen: Use CIA not PC in branch calculations.
1233 (illegal): Call SignalException.
1234 (BEQ, ADDIU): Fix assembler.
1236 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1238 * m16.igen (JALX): Was missing.
1240 * configure.in (enable-sim-igen): New configuration option.
1241 * configure: Re-generate.
1243 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1245 * interp.c (load_memory, store_memory): Delete parameter RAW.
1246 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1247 bypassing {load,store}_memory.
1249 * sim-main.h (ByteSwapMem): Delete definition.
1251 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1253 * interp.c (sim_do_command, sim_commands): Delete mips specific
1254 commands. Handled by module sim-options.
1256 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1257 (WITH_MODULO_MEMORY): Define.
1259 * interp.c (sim_info): Delete code printing memory size.
1261 * interp.c (mips_size): Nee sim_size, delete function.
1263 (monitor, monitor_base, monitor_size): Delete global variables.
1264 (sim_open, sim_close): Delete code creating monitor and other
1265 memory regions. Use sim-memopts module, via sim_do_commandf, to
1266 manage memory regions.
1267 (load_memory, store_memory): Use sim-core for memory model.
1269 * interp.c (address_translation): Delete all memory map code
1270 except line forcing 32 bit addresses.
1272 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1274 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1277 * interp.c (logfh, logfile): Delete globals.
1278 (sim_open, sim_close): Delete code opening & closing log file.
1279 (mips_option_handler): Delete -l and -n options.
1280 (OPTION mips_options): Ditto.
1282 * interp.c (OPTION mips_options): Rename option trace to dinero.
1283 (mips_option_handler): Update.
1285 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1287 * interp.c (fetch_str): New function.
1288 (sim_monitor): Rewrite using sim_read & sim_write.
1289 (sim_open): Check magic number.
1290 (sim_open): Write monitor vectors into memory using sim_write.
1291 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1292 (sim_read, sim_write): Simplify - transfer data one byte at a
1294 (load_memory, store_memory): Clarify meaning of parameter RAW.
1296 * sim-main.h (isHOST): Defete definition.
1297 (isTARGET): Mark as depreciated.
1298 (address_translation): Delete parameter HOST.
1300 * interp.c (address_translation): Delete parameter HOST.
1302 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1306 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1307 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1309 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1311 * mips.igen: Add model filter field to records.
1313 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1317 interp.c (sim_engine_run): Do not compile function sim_engine_run
1318 when WITH_IGEN == 1.
1320 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1321 target architecture.
1323 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1324 igen. Replace with configuration variables sim_igen_flags /
1327 * m16.igen: New file. Copy mips16 insns here.
1328 * mips.igen: From here.
1330 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1332 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1334 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1336 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1338 * gencode.c (build_instruction): Follow sim_write's lead in using
1339 BigEndianMem instead of !ByteSwapMem.
1341 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1343 * configure.in (sim_gen): Dependent on target, select type of
1344 generator. Always select old style generator.
1346 configure: Re-generate.
1348 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1350 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1351 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1352 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1353 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1354 SIM_@sim_gen@_*, set by autoconf.
1356 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1358 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1360 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1361 CURRENT_FLOATING_POINT instead.
1363 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1364 (address_translation): Raise exception InstructionFetch when
1365 translation fails and isINSTRUCTION.
1367 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1368 sim_engine_run): Change type of of vaddr and paddr to
1370 (address_translation, prefetch, load_memory, store_memory,
1371 cache_op): Change type of vAddr and pAddr to address_word.
1373 * gencode.c (build_instruction): Change type of vaddr and paddr to
1376 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1378 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1379 macro to obtain result of ALU op.
1381 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1383 * interp.c (sim_info): Call profile_print.
1385 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1387 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1389 * sim-main.h (WITH_PROFILE): Do not define, defined in
1390 common/sim-config.h. Use sim-profile module.
1391 (simPROFILE): Delete defintion.
1393 * interp.c (PROFILE): Delete definition.
1394 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1395 (sim_close): Delete code writing profile histogram.
1396 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1398 (sim_engine_run): Delete code profiling the PC.
1400 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1404 * interp.c (sim_monitor): Make register pointers of type
1407 * sim-main.h: Make registers of type unsigned_word not
1410 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1412 * interp.c (sync_operation): Rename from SyncOperation, make
1413 global, add SD argument.
1414 (prefetch): Rename from Prefetch, make global, add SD argument.
1415 (decode_coproc): Make global.
1417 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1419 * gencode.c (build_instruction): Generate DecodeCoproc not
1420 decode_coproc calls.
1422 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1423 (SizeFGR): Move to sim-main.h
1424 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1425 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1426 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1428 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1429 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1430 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1431 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1432 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1433 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1435 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1437 (sim-alu.h): Include.
1438 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1439 (sim_cia): Typedef to instruction_address.
1441 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1443 * Makefile.in (interp.o): Rename generated file engine.c to
1448 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1450 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1452 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1454 * gencode.c (build_instruction): For "FPSQRT", output correct
1455 number of arguments to Recip.
1457 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1459 * Makefile.in (interp.o): Depends on sim-main.h
1461 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1463 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1464 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1465 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1466 STATE, DSSTATE): Define
1467 (GPR, FGRIDX, ..): Define.
1469 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1470 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1471 (GPR, FGRIDX, ...): Delete macros.
1473 * interp.c: Update names to match defines from sim-main.h
1475 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477 * interp.c (sim_monitor): Add SD argument.
1478 (sim_warning): Delete. Replace calls with calls to
1480 (sim_error): Delete. Replace calls with sim_io_error.
1481 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1482 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1483 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1485 (mips_size): Rename from sim_size. Add SD argument.
1487 * interp.c (simulator): Delete global variable.
1488 (callback): Delete global variable.
1489 (mips_option_handler, sim_open, sim_write, sim_read,
1490 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1491 sim_size,sim_monitor): Use sim_io_* not callback->*.
1492 (sim_open): ZALLOC simulator struct.
1493 (PROFILE): Do not define.
1495 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1497 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1498 support.h with corresponding code.
1500 * sim-main.h (word64, uword64), support.h: Move definition to
1502 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1505 * Makefile.in: Update dependencies
1506 * interp.c: Do not include.
1508 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * interp.c (address_translation, load_memory, store_memory,
1511 cache_op): Rename to from AddressTranslation et.al., make global,
1514 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1517 * interp.c (SignalException): Rename to signal_exception, make
1520 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1522 * sim-main.h (SignalException, SignalExceptionInterrupt,
1523 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1524 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1525 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1528 * interp.c, support.h: Use.
1530 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1532 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1533 to value_fpr / store_fpr. Add SD argument.
1534 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1535 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1537 * sim-main.h (ValueFPR, StoreFPR): Define.
1539 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1541 * interp.c (sim_engine_run): Check consistency between configure
1542 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1545 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1546 (mips_fpu): Configure WITH_FLOATING_POINT.
1547 (mips_endian): Configure WITH_TARGET_ENDIAN.
1548 * configure: Update.
1550 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1552 * configure: Regenerated to track ../common/aclocal.m4 changes.
1554 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1556 * configure: Regenerated.
1558 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1560 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1562 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1564 * gencode.c (print_igen_insn_models): Assume certain architectures
1565 include all mips* instructions.
1566 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1569 * Makefile.in (tmp.igen): Add target. Generate igen input from
1572 * gencode.c (FEATURE_IGEN): Define.
1573 (main): Add --igen option. Generate output in igen format.
1574 (process_instructions): Format output according to igen option.
1575 (print_igen_insn_format): New function.
1576 (print_igen_insn_models): New function.
1577 (process_instructions): Only issue warnings and ignore
1578 instructions when no FEATURE_IGEN.
1580 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1582 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1585 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1587 * configure: Regenerated to track ../common/aclocal.m4 changes.
1589 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1592 SIM_RESERVED_BITS): Delete, moved to common.
1593 (SIM_EXTRA_CFLAGS): Update.
1595 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597 * configure.in: Configure non-strict memory alignment.
1598 * configure: Regenerated to track ../common/aclocal.m4 changes.
1600 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1602 * configure: Regenerated to track ../common/aclocal.m4 changes.
1604 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1606 * gencode.c (SDBBP,DERET): Added (3900) insns.
1607 (RFE): Turn on for 3900.
1608 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1609 (dsstate): Made global.
1610 (SUBTARGET_R3900): Added.
1611 (CANCELDELAYSLOT): New.
1612 (SignalException): Ignore SystemCall rather than ignore and
1613 terminate. Add DebugBreakPoint handling.
1614 (decode_coproc): New insns RFE, DERET; and new registers Debug
1615 and DEPC protected by SUBTARGET_R3900.
1616 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1618 * Makefile.in,configure.in: Add mips subtarget option.
1619 * configure: Update.
1621 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1623 * gencode.c: Add r3900 (tx39).
1626 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1628 * gencode.c (build_instruction): Don't need to subtract 4 for
1631 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1633 * interp.c: Correct some HASFPU problems.
1635 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637 * configure: Regenerated to track ../common/aclocal.m4 changes.
1639 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * interp.c (mips_options): Fix samples option short form, should
1644 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1646 * interp.c (sim_info): Enable info code. Was just returning.
1648 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1653 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1655 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1657 (build_instruction): Ditto for LL.
1659 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1661 * configure: Regenerated to track ../common/aclocal.m4 changes.
1663 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1665 * configure: Regenerated to track ../common/aclocal.m4 changes.
1668 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670 * interp.c (sim_open): Add call to sim_analyze_program, update
1673 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675 * interp.c (sim_kill): Delete.
1676 (sim_create_inferior): Add ABFD argument. Set PC from same.
1677 (sim_load): Move code initializing trap handlers from here.
1678 (sim_open): To here.
1679 (sim_load): Delete, use sim-hload.c.
1681 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1683 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1685 * configure: Regenerated to track ../common/aclocal.m4 changes.
1688 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1690 * interp.c (sim_open): Add ABFD argument.
1691 (sim_load): Move call to sim_config from here.
1692 (sim_open): To here. Check return status.
1694 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1696 * gencode.c (build_instruction): Two arg MADD should
1697 not assign result to $0.
1699 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1701 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1702 * sim/mips/configure.in: Regenerate.
1704 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1706 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1707 signed8, unsigned8 et.al. types.
1709 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1710 hosts when selecting subreg.
1712 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1714 * interp.c (sim_engine_run): Reset the ZERO register to zero
1715 regardless of FEATURE_WARN_ZERO.
1716 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1718 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1721 (SignalException): For BreakPoints ignore any mode bits and just
1723 (SignalException): Always set the CAUSE register.
1725 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1728 exception has been taken.
1730 * interp.c: Implement the ERET and mt/f sr instructions.
1732 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1734 * interp.c (SignalException): Don't bother restarting an
1737 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1739 * interp.c (SignalException): Really take an interrupt.
1740 (interrupt_event): Only deliver interrupts when enabled.
1742 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1744 * interp.c (sim_info): Only print info when verbose.
1745 (sim_info) Use sim_io_printf for output.
1747 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1749 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1752 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1754 * interp.c (sim_do_command): Check for common commands if a
1755 simulator specific command fails.
1757 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1759 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1760 and simBE when DEBUG is defined.
1762 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1764 * interp.c (interrupt_event): New function. Pass exception event
1765 onto exception handler.
1767 * configure.in: Check for stdlib.h.
1768 * configure: Regenerate.
1770 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1771 variable declaration.
1772 (build_instruction): Initialize memval1.
1773 (build_instruction): Add UNUSED attribute to byte, bigend,
1775 (build_operands): Ditto.
1777 * interp.c: Fix GCC warnings.
1778 (sim_get_quit_code): Delete.
1780 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1781 * Makefile.in: Ditto.
1782 * configure: Re-generate.
1784 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1786 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1788 * interp.c (mips_option_handler): New function parse argumes using
1790 (myname): Replace with STATE_MY_NAME.
1791 (sim_open): Delete check for host endianness - performed by
1793 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1794 (sim_open): Move much of the initialization from here.
1795 (sim_load): To here. After the image has been loaded and
1797 (sim_open): Move ColdReset from here.
1798 (sim_create_inferior): To here.
1799 (sim_open): Make FP check less dependant on host endianness.
1801 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1803 * interp.c (sim_set_callbacks): Delete.
1805 * interp.c (membank, membank_base, membank_size): Replace with
1806 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1807 (sim_open): Remove call to callback->init. gdb/run do this.
1811 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1813 * interp.c (big_endian_p): Delete, replaced by
1814 current_target_byte_order.
1816 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818 * interp.c (host_read_long, host_read_word, host_swap_word,
1819 host_swap_long): Delete. Using common sim-endian.
1820 (sim_fetch_register, sim_store_register): Use H2T.
1821 (pipeline_ticks): Delete. Handled by sim-events.
1823 (sim_engine_run): Update.
1825 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1827 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1829 (SignalException): To here. Signal using sim_engine_halt.
1830 (sim_stop_reason): Delete, moved to common.
1832 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1834 * interp.c (sim_open): Add callback argument.
1835 (sim_set_callbacks): Delete SIM_DESC argument.
1838 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840 * Makefile.in (SIM_OBJS): Add common modules.
1842 * interp.c (sim_set_callbacks): Also set SD callback.
1843 (set_endianness, xfer_*, swap_*): Delete.
1844 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1845 Change to functions using sim-endian macros.
1846 (control_c, sim_stop): Delete, use common version.
1847 (simulate): Convert into.
1848 (sim_engine_run): This function.
1849 (sim_resume): Delete.
1851 * interp.c (simulation): New variable - the simulator object.
1852 (sim_kind): Delete global - merged into simulation.
1853 (sim_load): Cleanup. Move PC assignment from here.
1854 (sim_create_inferior): To here.
1856 * sim-main.h: New file.
1857 * interp.c (sim-main.h): Include.
1859 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1861 * configure: Regenerated to track ../common/aclocal.m4 changes.
1863 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1865 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1867 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1869 * gencode.c (build_instruction): DIV instructions: check
1870 for division by zero and integer overflow before using
1871 host's division operation.
1873 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1875 * Makefile.in (SIM_OBJS): Add sim-load.o.
1876 * interp.c: #include bfd.h.
1877 (target_byte_order): Delete.
1878 (sim_kind, myname, big_endian_p): New static locals.
1879 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1880 after argument parsing. Recognize -E arg, set endianness accordingly.
1881 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1882 load file into simulator. Set PC from bfd.
1883 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1884 (set_endianness): Use big_endian_p instead of target_byte_order.
1886 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1888 * interp.c (sim_size): Delete prototype - conflicts with
1889 definition in remote-sim.h. Correct definition.
1891 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1893 * configure: Regenerated to track ../common/aclocal.m4 changes.
1896 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1898 * interp.c (sim_open): New arg `kind'.
1900 * configure: Regenerated to track ../common/aclocal.m4 changes.
1902 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1904 * configure: Regenerated to track ../common/aclocal.m4 changes.
1906 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1908 * interp.c (sim_open): Set optind to 0 before calling getopt.
1910 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1912 * configure: Regenerated to track ../common/aclocal.m4 changes.
1914 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1916 * interp.c : Replace uses of pr_addr with pr_uword64
1917 where the bit length is always 64 independent of SIM_ADDR.
1918 (pr_uword64) : added.
1920 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1922 * configure: Re-generate.
1924 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1926 * configure: Regenerate to track ../common/aclocal.m4 changes.
1928 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1930 * interp.c (sim_open): New SIM_DESC result. Argument is now
1932 (other sim_*): New SIM_DESC argument.
1934 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1936 * interp.c: Fix printing of addresses for non-64-bit targets.
1937 (pr_addr): Add function to print address based on size.
1939 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1941 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1943 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1945 * gencode.c (build_mips16_operands): Correct computation of base
1946 address for extended PC relative instruction.
1948 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1950 * interp.c (mips16_entry): Add support for floating point cases.
1951 (SignalException): Pass floating point cases to mips16_entry.
1952 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1954 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1956 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1957 and then set the state to fmt_uninterpreted.
1958 (COP_SW): Temporarily set the state to fmt_word while calling
1961 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1963 * gencode.c (build_instruction): The high order may be set in the
1964 comparison flags at any ISA level, not just ISA 4.
1966 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1968 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1969 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1970 * configure.in: sinclude ../common/aclocal.m4.
1971 * configure: Regenerated.
1973 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1975 * configure: Rebuild after change to aclocal.m4.
1977 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1979 * configure configure.in Makefile.in: Update to new configure
1980 scheme which is more compatible with WinGDB builds.
1981 * configure.in: Improve comment on how to run autoconf.
1982 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1983 * Makefile.in: Use autoconf substitution to install common
1986 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1988 * gencode.c (build_instruction): Use BigEndianCPU instead of
1991 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1993 * interp.c (sim_monitor): Make output to stdout visible in
1994 wingdb's I/O log window.
1996 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1998 * support.h: Undo previous change to SIGTRAP
2001 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2003 * interp.c (store_word, load_word): New static functions.
2004 (mips16_entry): New static function.
2005 (SignalException): Look for mips16 entry and exit instructions.
2006 (simulate): Use the correct index when setting fpr_state after
2007 doing a pending move.
2009 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2011 * interp.c: Fix byte-swapping code throughout to work on
2012 both little- and big-endian hosts.
2014 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2016 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2017 with gdb/config/i386/xm-windows.h.
2019 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2021 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2022 that messes up arithmetic shifts.
2024 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2026 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2027 SIGTRAP and SIGQUIT for _WIN32.
2029 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2031 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2032 force a 64 bit multiplication.
2033 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2034 destination register is 0, since that is the default mips16 nop
2037 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2039 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2040 (build_endian_shift): Don't check proc64.
2041 (build_instruction): Always set memval to uword64. Cast op2 to
2042 uword64 when shifting it left in memory instructions. Always use
2043 the same code for stores--don't special case proc64.
2045 * gencode.c (build_mips16_operands): Fix base PC value for PC
2047 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2049 * interp.c (simJALDELAYSLOT): Define.
2050 (JALDELAYSLOT): Define.
2051 (INDELAYSLOT, INJALDELAYSLOT): Define.
2052 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2054 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2056 * interp.c (sim_open): add flush_cache as a PMON routine
2057 (sim_monitor): handle flush_cache by ignoring it
2059 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2061 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2063 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2064 (BigEndianMem): Rename to ByteSwapMem and change sense.
2065 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2066 BigEndianMem references to !ByteSwapMem.
2067 (set_endianness): New function, with prototype.
2068 (sim_open): Call set_endianness.
2069 (sim_info): Use simBE instead of BigEndianMem.
2070 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2071 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2072 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2073 ifdefs, keeping the prototype declaration.
2074 (swap_word): Rewrite correctly.
2075 (ColdReset): Delete references to CONFIG. Delete endianness related
2076 code; moved to set_endianness.
2078 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2080 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2081 * interp.c (CHECKHILO): Define away.
2082 (simSIGINT): New macro.
2083 (membank_size): Increase from 1MB to 2MB.
2084 (control_c): New function.
2085 (sim_resume): Rename parameter signal to signal_number. Add local
2086 variable prev. Call signal before and after simulate.
2087 (sim_stop_reason): Add simSIGINT support.
2088 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2090 (sim_warning): Delete call to SignalException. Do call printf_filtered
2092 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2093 a call to sim_warning.
2095 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2097 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2098 16 bit instructions.
2100 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2102 Add support for mips16 (16 bit MIPS implementation):
2103 * gencode.c (inst_type): Add mips16 instruction encoding types.
2104 (GETDATASIZEINSN): Define.
2105 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2106 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2108 (MIPS16_DECODE): New table, for mips16 instructions.
2109 (bitmap_val): New static function.
2110 (struct mips16_op): Define.
2111 (mips16_op_table): New table, for mips16 operands.
2112 (build_mips16_operands): New static function.
2113 (process_instructions): If PC is odd, decode a mips16
2114 instruction. Break out instruction handling into new
2115 build_instruction function.
2116 (build_instruction): New static function, broken out of
2117 process_instructions. Check modifiers rather than flags for SHIFT
2118 bit count and m[ft]{hi,lo} direction.
2119 (usage): Pass program name to fprintf.
2120 (main): Remove unused variable this_option_optind. Change
2121 ``*loptarg++'' to ``loptarg++''.
2122 (my_strtoul): Parenthesize && within ||.
2123 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2124 (simulate): If PC is odd, fetch a 16 bit instruction, and
2125 increment PC by 2 rather than 4.
2126 * configure.in: Add case for mips16*-*-*.
2127 * configure: Rebuild.
2129 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2131 * interp.c: Allow -t to enable tracing in standalone simulator.
2132 Fix garbage output in trace file and error messages.
2134 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2136 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2137 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2138 * configure.in: Simplify using macros in ../common/aclocal.m4.
2139 * configure: Regenerated.
2140 * tconfig.in: New file.
2142 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2144 * interp.c: Fix bugs in 64-bit port.
2145 Use ansi function declarations for msvc compiler.
2146 Initialize and test file pointer in trace code.
2147 Prevent duplicate definition of LAST_EMED_REGNUM.
2149 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2151 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2153 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2155 * interp.c (SignalException): Check for explicit terminating
2157 * gencode.c: Pass instruction value through SignalException()
2158 calls for Trap, Breakpoint and Syscall.
2160 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2162 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2163 only used on those hosts that provide it.
2164 * configure.in: Add sqrt() to list of functions to be checked for.
2165 * config.in: Re-generated.
2166 * configure: Re-generated.
2168 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2170 * gencode.c (process_instructions): Call build_endian_shift when
2171 expanding STORE RIGHT, to fix swr.
2172 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2173 clear the high bits.
2174 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2175 Fix float to int conversions to produce signed values.
2177 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2179 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2180 (process_instructions): Correct handling of nor instruction.
2181 Correct shift count for 32 bit shift instructions. Correct sign
2182 extension for arithmetic shifts to not shift the number of bits in
2183 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2184 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2186 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2187 It's OK to have a mult follow a mult. What's not OK is to have a
2188 mult follow an mfhi.
2189 (Convert): Comment out incorrect rounding code.
2191 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2193 * interp.c (sim_monitor): Improved monitor printf
2194 simulation. Tidied up simulator warnings, and added "--log" option
2195 for directing warning message output.
2196 * gencode.c: Use sim_warning() rather than WARNING macro.
2198 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2200 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2201 getopt1.o, rather than on gencode.c. Link objects together.
2202 Don't link against -liberty.
2203 (gencode.o, getopt.o, getopt1.o): New targets.
2204 * gencode.c: Include <ctype.h> and "ansidecl.h".
2205 (AND): Undefine after including "ansidecl.h".
2206 (ULONG_MAX): Define if not defined.
2207 (OP_*): Don't define macros; now defined in opcode/mips.h.
2208 (main): Call my_strtoul rather than strtoul.
2209 (my_strtoul): New static function.
2211 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2213 * gencode.c (process_instructions): Generate word64 and uword64
2214 instead of `long long' and `unsigned long long' data types.
2215 * interp.c: #include sysdep.h to get signals, and define default
2217 * (Convert): Work around for Visual-C++ compiler bug with type
2219 * support.h: Make things compile under Visual-C++ by using
2220 __int64 instead of `long long'. Change many refs to long long
2221 into word64/uword64 typedefs.
2223 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2225 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2226 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2228 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2229 (AC_PROG_INSTALL): Added.
2230 (AC_PROG_CC): Moved to before configure.host call.
2231 * configure: Rebuilt.
2233 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2235 * configure.in: Define @SIMCONF@ depending on mips target.
2236 * configure: Rebuild.
2237 * Makefile.in (run): Add @SIMCONF@ to control simulator
2239 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2240 * interp.c: Remove some debugging, provide more detailed error
2241 messages, update memory accesses to use LOADDRMASK.
2243 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2245 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2246 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2248 * configure: Rebuild.
2249 * config.in: New file, generated by autoheader.
2250 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2251 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2252 HAVE_ANINT and HAVE_AINT, as appropriate.
2253 * Makefile.in (run): Use @LIBS@ rather than -lm.
2254 (interp.o): Depend upon config.h.
2255 (Makefile): Just rebuild Makefile.
2256 (clean): Remove stamp-h.
2257 (mostlyclean): Make the same as clean, not as distclean.
2258 (config.h, stamp-h): New targets.
2260 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2262 * interp.c (ColdReset): Fix boolean test. Make all simulator
2265 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2267 * interp.c (xfer_direct_word, xfer_direct_long,
2268 swap_direct_word, swap_direct_long, xfer_big_word,
2269 xfer_big_long, xfer_little_word, xfer_little_long,
2270 swap_word,swap_long): Added.
2271 * interp.c (ColdReset): Provide function indirection to
2272 host<->simulated_target transfer routines.
2273 * interp.c (sim_store_register, sim_fetch_register): Updated to
2274 make use of indirected transfer routines.
2276 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2278 * gencode.c (process_instructions): Ensure FP ABS instruction
2280 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2281 system call support.
2283 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2285 * interp.c (sim_do_command): Complain if callback structure not
2288 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2290 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2291 support for Sun hosts.
2292 * Makefile.in (gencode): Ensure the host compiler and libraries
2293 used for cross-hosted build.
2295 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2297 * interp.c, gencode.c: Some more (TODO) tidying.
2299 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2301 * gencode.c, interp.c: Replaced explicit long long references with
2302 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2303 * support.h (SET64LO, SET64HI): Macros added.
2305 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2307 * configure: Regenerate with autoconf 2.7.
2309 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2311 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2312 * support.h: Remove superfluous "1" from #if.
2313 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2315 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2317 * interp.c (StoreFPR): Control UndefinedResult() call on
2318 WARN_RESULT manifest.
2320 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2322 * gencode.c: Tidied instruction decoding, and added FP instruction
2325 * interp.c: Added dineroIII, and BSD profiling support. Also
2326 run-time FP handling.
2328 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2330 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2331 gencode.c, interp.c, support.h: created.
projects / deliverable / binutils-gdb.git / blob