1 2015-11-17 Mike Frysinger <vapier@gentoo.org>
3 * sim-main.h (WITH_MODULO_MEMORY): Delete.
5 2015-11-15 Mike Frysinger <vapier@gentoo.org>
7 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
9 2015-11-14 Mike Frysinger <vapier@gentoo.org>
11 * interp.c (sim_close): Rename to ...
12 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
14 * sim-main.h (mips_sim_close): Declare.
15 (SIM_CLOSE_HOOK): Define.
17 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
18 Ali Lown <ali.lown@imgtec.com>
20 * Makefile.in (tmp-micromips): New rule.
21 (tmp-mach-multi): Add support for micromips.
22 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
23 that works for both mips64 and micromips64.
24 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
26 Add build support for micromips.
27 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
28 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
29 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
30 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
31 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
32 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
33 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
34 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
35 Refactored instruction code to use these functions.
36 * dsp2.igen: Refactored instruction code to use the new functions.
37 * interp.c (decode_coproc): Refactored to work with any instruction
39 (isa_mode): New variable
40 (RSVD_INSTRUCTION): Changed to 0x00000039.
41 * m16.igen (BREAK16): Refactored instruction to use do_break16.
42 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
43 * micromips.dc: New file.
44 * micromips.igen: New file.
45 * micromips16.dc: New file.
46 * micromipsdsp.igen: New file.
47 * micromipsrun.c: New file.
48 * mips.igen (do_swc1): Changed to work with any instruction encoding.
49 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
50 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
51 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
52 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
53 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
54 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
55 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
56 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
57 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
58 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
59 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
60 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
61 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
62 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
63 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
64 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
65 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
66 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
68 Refactored instruction code to use these functions.
69 (RSVD): Changed to use new reserved instruction.
70 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
71 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
72 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
73 do_store_double): Added micromips32 and micromips64 models.
74 Added include for micromips.igen and micromipsdsp.igen
75 Add micromips32 and micromips64 models.
76 (DecodeCoproc): Updated to use new macro definition.
77 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
78 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
79 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
80 Refactored instruction code to use these functions.
81 * sim-main.h (CP0_operation): New enum.
82 (DecodeCoproc): Updated macro.
83 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
84 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
85 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
86 ISA_MODE_MICROMIPS): New defines.
87 (sim_state): Add isa_mode field.
89 2015-06-23 Mike Frysinger <vapier@gentoo.org>
91 * configure: Regenerate.
93 2015-06-12 Mike Frysinger <vapier@gentoo.org>
95 * configure.ac: Change configure.in to configure.ac.
96 * configure: Regenerate.
98 2015-06-12 Mike Frysinger <vapier@gentoo.org>
100 * configure: Regenerate.
102 2015-06-12 Mike Frysinger <vapier@gentoo.org>
104 * interp.c [TRACE]: Delete.
105 (TRACE): Change to WITH_TRACE_ANY_P.
106 [!WITH_TRACE_ANY_P] (open_trace): Define.
107 (mips_option_handler, open_trace, sim_close, dotrace):
108 Change defined(TRACE) to WITH_TRACE_ANY_P.
109 (sim_open): Delete TRACE ifdef check.
110 * sim-main.c (load_memory): Delete TRACE ifdef check.
111 (store_memory): Likewise.
112 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
113 [!WITH_TRACE_ANY_P] (dotrace): Define.
115 2015-04-18 Mike Frysinger <vapier@gentoo.org>
117 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
120 2015-04-18 Mike Frysinger <vapier@gentoo.org>
122 * sim-main.h (SIM_CPU): Delete.
124 2015-04-18 Mike Frysinger <vapier@gentoo.org>
126 * sim-main.h (sim_cia): Delete.
128 2015-04-17 Mike Frysinger <vapier@gentoo.org>
130 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
132 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
133 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
134 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
135 CIA_SET to CPU_PC_SET.
136 * sim-main.h (CIA_GET, CIA_SET): Delete.
138 2015-04-15 Mike Frysinger <vapier@gentoo.org>
140 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
141 * sim-main.h (STATE_CPU): Delete.
143 2015-04-13 Mike Frysinger <vapier@gentoo.org>
145 * configure: Regenerate.
147 2015-04-13 Mike Frysinger <vapier@gentoo.org>
149 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
150 * interp.c (mips_pc_get, mips_pc_set): New functions.
151 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
152 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
153 (sim_pc_get): Delete.
154 * sim-main.h (SIM_CPU): Define.
155 (struct sim_state): Change cpu to an array of pointers.
158 2015-04-13 Mike Frysinger <vapier@gentoo.org>
160 * interp.c (mips_option_handler, open_trace, sim_close,
161 sim_write, sim_read, sim_store_register, sim_fetch_register,
162 sim_create_inferior, pr_addr, pr_uword64): Convert old style
164 (sim_open): Convert old style prototype. Change casts with
165 sim_write to unsigned char *.
166 (fetch_str): Change null to unsigned char, and change cast to
168 (sim_monitor): Change c & ch to unsigned char. Change cast to
171 2015-04-12 Mike Frysinger <vapier@gentoo.org>
173 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
175 2015-04-06 Mike Frysinger <vapier@gentoo.org>
177 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
179 2015-04-01 Mike Frysinger <vapier@gentoo.org>
181 * tconfig.h (SIM_HAVE_PROFILE): Delete.
183 2015-03-31 Mike Frysinger <vapier@gentoo.org>
185 * config.in, configure: Regenerate.
187 2015-03-24 Mike Frysinger <vapier@gentoo.org>
189 * interp.c (sim_pc_get): New function.
191 2015-03-24 Mike Frysinger <vapier@gentoo.org>
193 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
194 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
196 2015-03-24 Mike Frysinger <vapier@gentoo.org>
198 * configure: Regenerate.
200 2015-03-23 Mike Frysinger <vapier@gentoo.org>
202 * configure: Regenerate.
204 2015-03-23 Mike Frysinger <vapier@gentoo.org>
206 * configure: Regenerate.
207 * configure.ac (mips_extra_objs): Delete.
208 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
209 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
211 2015-03-23 Mike Frysinger <vapier@gentoo.org>
213 * configure: Regenerate.
214 * configure.ac: Delete sim_hw checks for dv-sockser.
216 2015-03-16 Mike Frysinger <vapier@gentoo.org>
218 * config.in, configure: Regenerate.
219 * tconfig.in: Rename file ...
220 * tconfig.h: ... here.
222 2015-03-15 Mike Frysinger <vapier@gentoo.org>
224 * tconfig.in: Delete includes.
225 [HAVE_DV_SOCKSER]: Delete.
227 2015-03-14 Mike Frysinger <vapier@gentoo.org>
229 * Makefile.in (SIM_RUN_OBJS): Delete.
231 2015-03-14 Mike Frysinger <vapier@gentoo.org>
233 * configure.ac (AC_CHECK_HEADERS): Delete.
234 * aclocal.m4, configure: Regenerate.
236 2014-08-19 Alan Modra <amodra@gmail.com>
238 * configure: Regenerate.
240 2014-08-15 Roland McGrath <mcgrathr@google.com>
242 * configure: Regenerate.
243 * config.in: Regenerate.
245 2014-03-04 Mike Frysinger <vapier@gentoo.org>
247 * configure: Regenerate.
249 2013-09-23 Alan Modra <amodra@gmail.com>
251 * configure: Regenerate.
253 2013-06-03 Mike Frysinger <vapier@gentoo.org>
255 * aclocal.m4, configure: Regenerate.
257 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
259 * configure: Rebuild.
261 2013-03-26 Mike Frysinger <vapier@gentoo.org>
263 * configure: Regenerate.
265 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
267 * configure.ac: Address use of dv-sockser.o.
268 * tconfig.in: Conditionalize use of dv_sockser_install.
269 * configure: Regenerated.
270 * config.in: Regenerated.
272 2012-10-04 Chao-ying Fu <fu@mips.com>
273 Steve Ellcey <sellcey@mips.com>
275 * mips/mips3264r2.igen (rdhwr): New.
277 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
279 * configure.ac: Always link against dv-sockser.o.
280 * configure: Regenerate.
282 2012-06-15 Joel Brobecker <brobecker@adacore.com>
284 * config.in, configure: Regenerate.
286 2012-05-18 Nick Clifton <nickc@redhat.com>
289 * interp.c: Include config.h before system header files.
291 2012-03-24 Mike Frysinger <vapier@gentoo.org>
293 * aclocal.m4, config.in, configure: Regenerate.
295 2011-12-03 Mike Frysinger <vapier@gentoo.org>
297 * aclocal.m4: New file.
298 * configure: Regenerate.
300 2011-10-19 Mike Frysinger <vapier@gentoo.org>
302 * configure: Regenerate after common/acinclude.m4 update.
304 2011-10-17 Mike Frysinger <vapier@gentoo.org>
306 * configure.ac: Change include to common/acinclude.m4.
308 2011-10-17 Mike Frysinger <vapier@gentoo.org>
310 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
311 call. Replace common.m4 include with SIM_AC_COMMON.
312 * configure: Regenerate.
314 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
316 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
318 (tmp-mach-multi): Exit early when igen fails.
320 2011-07-05 Mike Frysinger <vapier@gentoo.org>
322 * interp.c (sim_do_command): Delete.
324 2011-02-14 Mike Frysinger <vapier@gentoo.org>
326 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
327 (tx3904sio_fifo_reset): Likewise.
328 * interp.c (sim_monitor): Likewise.
330 2010-04-14 Mike Frysinger <vapier@gentoo.org>
332 * interp.c (sim_write): Add const to buffer arg.
334 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
336 * interp.c: Don't include sysdep.h
338 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
340 * configure: Regenerate.
342 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
344 * config.in: Regenerate.
345 * configure: Likewise.
347 * configure: Regenerate.
349 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
351 * configure: Regenerate to track ../common/common.m4 changes.
354 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
355 Daniel Jacobowitz <dan@codesourcery.com>
356 Joseph Myers <joseph@codesourcery.com>
358 * configure: Regenerate.
360 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
362 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
363 that unconditionally allows fmt_ps.
364 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
365 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
366 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
367 filter from 64,f to 32,f.
368 (PREFX): Change filter from 64 to 32.
369 (LDXC1, LUXC1): Provide separate mips32r2 implementations
370 that use do_load_double instead of do_load. Make both LUXC1
371 versions unpredictable if SizeFGR () != 64.
372 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
373 instead of do_store. Remove unused variable. Make both SUXC1
374 versions unpredictable if SizeFGR () != 64.
376 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
378 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
379 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
380 shifts for that case.
382 2007-09-04 Nick Clifton <nickc@redhat.com>
384 * interp.c (options enum): Add OPTION_INFO_MEMORY.
385 (display_mem_info): New static variable.
386 (mips_option_handler): Handle OPTION_INFO_MEMORY.
387 (mips_options): Add info-memory and memory-info.
388 (sim_open): After processing the command line and board
389 specification, check display_mem_info. If it is set then
390 call the real handler for the --memory-info command line
393 2007-08-24 Joel Brobecker <brobecker@adacore.com>
395 * configure.ac: Change license of multi-run.c to GPL version 3.
396 * configure: Regenerate.
398 2007-06-28 Richard Sandiford <richard@codesourcery.com>
400 * configure.ac, configure: Revert last patch.
402 2007-06-26 Richard Sandiford <richard@codesourcery.com>
404 * configure.ac (sim_mipsisa3264_configs): New variable.
405 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
406 every configuration support all four targets, using the triplet to
407 determine the default.
408 * configure: Regenerate.
410 2007-06-25 Richard Sandiford <richard@codesourcery.com>
412 * Makefile.in (m16run.o): New rule.
414 2007-05-15 Thiemo Seufer <ths@mips.com>
416 * mips3264r2.igen (DSHD): Fix compile warning.
418 2007-05-14 Thiemo Seufer <ths@mips.com>
420 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
421 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
422 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
423 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
426 2007-03-01 Thiemo Seufer <ths@mips.com>
428 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
431 2007-02-20 Thiemo Seufer <ths@mips.com>
433 * dsp.igen: Update copyright notice.
434 * dsp2.igen: Fix copyright notice.
436 2007-02-20 Thiemo Seufer <ths@mips.com>
437 Chao-Ying Fu <fu@mips.com>
439 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
440 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
441 Add dsp2 to sim_igen_machine.
442 * configure: Regenerate.
443 * dsp.igen (do_ph_op): Add MUL support when op = 2.
444 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
445 (mulq_rs.ph): Use do_ph_mulq.
446 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
447 * mips.igen: Add dsp2 model and include dsp2.igen.
448 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
449 for *mips32r2, *mips64r2, *dsp.
450 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
451 for *mips32r2, *mips64r2, *dsp2.
452 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
454 2007-02-19 Thiemo Seufer <ths@mips.com>
455 Nigel Stephens <nigel@mips.com>
457 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
458 jumps with hazard barrier.
460 2007-02-19 Thiemo Seufer <ths@mips.com>
461 Nigel Stephens <nigel@mips.com>
463 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
464 after each call to sim_io_write.
466 2007-02-19 Thiemo Seufer <ths@mips.com>
467 Nigel Stephens <nigel@mips.com>
469 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
470 supported by this simulator.
471 (decode_coproc): Recognise additional CP0 Config registers
474 2007-02-19 Thiemo Seufer <ths@mips.com>
475 Nigel Stephens <nigel@mips.com>
476 David Ung <davidu@mips.com>
478 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
479 uninterpreted formats. If fmt is one of the uninterpreted types
480 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
481 fmt_word, and fmt_uninterpreted_64 like fmt_long.
482 (store_fpr): When writing an invalid odd register, set the
483 matching even register to fmt_unknown, not the following register.
484 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
485 the the memory window at offset 0 set by --memory-size command
487 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
489 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
491 (sim_monitor): When returning the memory size to the MIPS
492 application, use the value in STATE_MEM_SIZE, not an arbitrary
494 (cop_lw): Don' mess around with FPR_STATE, just pass
495 fmt_uninterpreted_32 to StoreFPR.
497 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
499 * mips.igen (not_word_value): Single version for mips32, mips64
502 2007-02-19 Thiemo Seufer <ths@mips.com>
503 Nigel Stephens <nigel@mips.com>
505 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
508 2007-02-17 Thiemo Seufer <ths@mips.com>
510 * configure.ac (mips*-sde-elf*): Move in front of generic machine
512 * configure: Regenerate.
514 2007-02-17 Thiemo Seufer <ths@mips.com>
516 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
517 Add mdmx to sim_igen_machine.
518 (mipsisa64*-*-*): Likewise. Remove dsp.
519 (mipsisa32*-*-*): Remove dsp.
520 * configure: Regenerate.
522 2007-02-13 Thiemo Seufer <ths@mips.com>
524 * configure.ac: Add mips*-sde-elf* target.
525 * configure: Regenerate.
527 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
529 * acconfig.h: Remove.
530 * config.in, configure: Regenerate.
532 2006-11-07 Thiemo Seufer <ths@mips.com>
534 * dsp.igen (do_w_op): Fix compiler warning.
536 2006-08-29 Thiemo Seufer <ths@mips.com>
537 David Ung <davidu@mips.com>
539 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
541 * configure: Regenerate.
542 * mips.igen (model): Add smartmips.
543 (MADDU): Increment ACX if carry.
544 (do_mult): Clear ACX.
545 (ROR,RORV): Add smartmips.
546 (include): Include smartmips.igen.
547 * sim-main.h (ACX): Set to REGISTERS[89].
548 * smartmips.igen: New file.
550 2006-08-29 Thiemo Seufer <ths@mips.com>
551 David Ung <davidu@mips.com>
553 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
554 mips3264r2.igen. Add missing dependency rules.
555 * m16e.igen: Support for mips16e save/restore instructions.
557 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
559 * configure: Regenerated.
561 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
563 * configure: Regenerated.
565 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
567 * configure: Regenerated.
569 2006-05-15 Chao-ying Fu <fu@mips.com>
571 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
573 2006-04-18 Nick Clifton <nickc@redhat.com>
575 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
578 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
580 * configure: Regenerate.
582 2005-12-14 Chao-ying Fu <fu@mips.com>
584 * Makefile.in (SIM_OBJS): Add dsp.o.
585 (dsp.o): New dependency.
586 (IGEN_INCLUDE): Add dsp.igen.
587 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
588 mipsisa64*-*-*): Add dsp to sim_igen_machine.
589 * configure: Regenerate.
590 * mips.igen: Add dsp model and include dsp.igen.
591 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
592 because these instructions are extended in DSP ASE.
593 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
594 adding 6 DSP accumulator registers and 1 DSP control register.
595 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
596 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
597 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
598 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
599 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
600 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
601 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
602 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
603 DSPCR_CCOND_SMASK): New define.
604 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
605 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
607 2005-07-08 Ian Lance Taylor <ian@airs.com>
609 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
611 2005-06-16 David Ung <davidu@mips.com>
612 Nigel Stephens <nigel@mips.com>
614 * mips.igen: New mips16e model and include m16e.igen.
615 (check_u64): Add mips16e tag.
616 * m16e.igen: New file for MIPS16e instructions.
617 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
618 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
620 * configure: Regenerate.
622 2005-05-26 David Ung <davidu@mips.com>
624 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
625 tags to all instructions which are applicable to the new ISAs.
626 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
628 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
630 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
632 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
633 * configure: Regenerate.
635 2005-03-23 Mark Kettenis <kettenis@gnu.org>
637 * configure: Regenerate.
639 2005-01-14 Andrew Cagney <cagney@gnu.org>
641 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
642 explicit call to AC_CONFIG_HEADER.
643 * configure: Regenerate.
645 2005-01-12 Andrew Cagney <cagney@gnu.org>
647 * configure.ac: Update to use ../common/common.m4.
648 * configure: Re-generate.
650 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
652 * configure: Regenerated to track ../common/aclocal.m4 changes.
654 2005-01-07 Andrew Cagney <cagney@gnu.org>
656 * configure.ac: Rename configure.in, require autoconf 2.59.
657 * configure: Re-generate.
659 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
661 * configure: Regenerate for ../common/aclocal.m4 update.
663 2004-09-24 Monika Chaddha <monika@acmet.com>
665 Committed by Andrew Cagney.
666 * m16.igen (CMP, CMPI): Fix assembler.
668 2004-08-18 Chris Demetriou <cgd@broadcom.com>
670 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
671 * configure: Regenerate.
673 2004-06-25 Chris Demetriou <cgd@broadcom.com>
675 * configure.in (sim_m16_machine): Include mipsIII.
676 * configure: Regenerate.
678 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
680 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
682 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
684 2004-04-10 Chris Demetriou <cgd@broadcom.com>
686 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
688 2004-04-09 Chris Demetriou <cgd@broadcom.com>
690 * mips.igen (check_fmt): Remove.
691 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
692 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
693 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
694 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
695 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
696 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
697 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
698 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
699 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
700 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
702 2004-04-09 Chris Demetriou <cgd@broadcom.com>
704 * sb1.igen (check_sbx): New function.
705 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
707 2004-03-29 Chris Demetriou <cgd@broadcom.com>
708 Richard Sandiford <rsandifo@redhat.com>
710 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
711 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
712 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
713 separate implementations for mipsIV and mipsV. Use new macros to
714 determine whether the restrictions apply.
716 2004-01-19 Chris Demetriou <cgd@broadcom.com>
718 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
719 (check_mult_hilo): Improve comments.
720 (check_div_hilo): Likewise. Also, fork off a new version
721 to handle mips32/mips64 (since there are no hazards to check
724 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
726 * mips.igen (do_dmultx): Fix check for negative operands.
728 2003-05-16 Ian Lance Taylor <ian@airs.com>
730 * Makefile.in (SHELL): Make sure this is defined.
731 (various): Use $(SHELL) whenever we invoke move-if-change.
733 2003-05-03 Chris Demetriou <cgd@broadcom.com>
735 * cp1.c: Tweak attribution slightly.
738 * mdmx.igen: Likewise.
739 * mips3d.igen: Likewise.
740 * sb1.igen: Likewise.
742 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
744 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
747 2003-02-27 Andrew Cagney <cagney@redhat.com>
749 * interp.c (sim_open): Rename _bfd to bfd.
750 (sim_create_inferior): Ditto.
752 2003-01-14 Chris Demetriou <cgd@broadcom.com>
754 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
756 2003-01-14 Chris Demetriou <cgd@broadcom.com>
758 * mips.igen (EI, DI): Remove.
760 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
762 * Makefile.in (tmp-run-multi): Fix mips16 filter.
764 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
765 Andrew Cagney <ac131313@redhat.com>
766 Gavin Romig-Koch <gavin@redhat.com>
767 Graydon Hoare <graydon@redhat.com>
768 Aldy Hernandez <aldyh@redhat.com>
769 Dave Brolley <brolley@redhat.com>
770 Chris Demetriou <cgd@broadcom.com>
772 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
773 (sim_mach_default): New variable.
774 (mips64vr-*-*, mips64vrel-*-*): New configurations.
775 Add a new simulator generator, MULTI.
776 * configure: Regenerate.
777 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
778 (multi-run.o): New dependency.
779 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
780 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
781 (tmp-multi): Combine them.
782 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
783 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
784 (distclean-extra): New rule.
785 * sim-main.h: Include bfd.h.
786 (MIPS_MACH): New macro.
787 * mips.igen (vr4120, vr5400, vr5500): New models.
788 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
789 * vr.igen: Replace with new version.
791 2003-01-04 Chris Demetriou <cgd@broadcom.com>
793 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
794 * configure: Regenerate.
796 2002-12-31 Chris Demetriou <cgd@broadcom.com>
798 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
799 * mips.igen: Remove all invocations of check_branch_bug and
802 2002-12-16 Chris Demetriou <cgd@broadcom.com>
804 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
806 2002-07-30 Chris Demetriou <cgd@broadcom.com>
808 * mips.igen (do_load_double, do_store_double): New functions.
809 (LDC1, SDC1): Rename to...
810 (LDC1b, SDC1b): respectively.
811 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
813 2002-07-29 Michael Snyder <msnyder@redhat.com>
815 * cp1.c (fp_recip2): Modify initialization expression so that
816 GCC will recognize it as constant.
818 2002-06-18 Chris Demetriou <cgd@broadcom.com>
820 * mdmx.c (SD_): Delete.
821 (Unpredictable): Re-define, for now, to directly invoke
822 unpredictable_action().
823 (mdmx_acc_op): Fix error in .ob immediate handling.
825 2002-06-18 Andrew Cagney <cagney@redhat.com>
827 * interp.c (sim_firmware_command): Initialize `address'.
829 2002-06-16 Andrew Cagney <ac131313@redhat.com>
831 * configure: Regenerated to track ../common/aclocal.m4 changes.
833 2002-06-14 Chris Demetriou <cgd@broadcom.com>
834 Ed Satterthwaite <ehs@broadcom.com>
836 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
837 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
838 * mips.igen: Include mips3d.igen.
839 (mips3d): New model name for MIPS-3D ASE instructions.
840 (CVT.W.fmt): Don't use this instruction for word (source) format
842 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
843 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
844 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
845 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
846 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
847 (RSquareRoot1, RSquareRoot2): New macros.
848 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
849 (fp_rsqrt2): New functions.
850 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
851 * configure: Regenerate.
853 2002-06-13 Chris Demetriou <cgd@broadcom.com>
854 Ed Satterthwaite <ehs@broadcom.com>
856 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
857 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
858 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
859 (convert): Note that this function is not used for paired-single
861 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
862 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
863 (check_fmt_p): Enable paired-single support.
864 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
865 (PUU.PS): New instructions.
866 (CVT.S.fmt): Don't use this instruction for paired-single format
868 * sim-main.h (FP_formats): New value 'fmt_ps.'
869 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
870 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
872 2002-06-12 Chris Demetriou <cgd@broadcom.com>
874 * mips.igen: Fix formatting of function calls in
877 2002-06-12 Chris Demetriou <cgd@broadcom.com>
879 * mips.igen (MOVN, MOVZ): Trace result.
880 (TNEI): Print "tnei" as the opcode name in traces.
881 (CEIL.W): Add disassembly string for traces.
882 (RSQRT.fmt): Make location of disassembly string consistent
883 with other instructions.
885 2002-06-12 Chris Demetriou <cgd@broadcom.com>
887 * mips.igen (X): Delete unused function.
889 2002-06-08 Andrew Cagney <cagney@redhat.com>
891 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
893 2002-06-07 Chris Demetriou <cgd@broadcom.com>
894 Ed Satterthwaite <ehs@broadcom.com>
896 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
897 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
898 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
899 (fp_nmsub): New prototypes.
900 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
901 (NegMultiplySub): New defines.
902 * mips.igen (RSQRT.fmt): Use RSquareRoot().
903 (MADD.D, MADD.S): Replace with...
904 (MADD.fmt): New instruction.
905 (MSUB.D, MSUB.S): Replace with...
906 (MSUB.fmt): New instruction.
907 (NMADD.D, NMADD.S): Replace with...
908 (NMADD.fmt): New instruction.
909 (NMSUB.D, MSUB.S): Replace with...
910 (NMSUB.fmt): New instruction.
912 2002-06-07 Chris Demetriou <cgd@broadcom.com>
913 Ed Satterthwaite <ehs@broadcom.com>
915 * cp1.c: Fix more comment spelling and formatting.
916 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
917 (denorm_mode): New function.
918 (fpu_unary, fpu_binary): Round results after operation, collect
919 status from rounding operations, and update the FCSR.
920 (convert): Collect status from integer conversions and rounding
921 operations, and update the FCSR. Adjust NaN values that result
922 from conversions. Convert to use sim_io_eprintf rather than
923 fprintf, and remove some debugging code.
924 * cp1.h (fenr_FS): New define.
926 2002-06-07 Chris Demetriou <cgd@broadcom.com>
928 * cp1.c (convert): Remove unusable debugging code, and move MIPS
929 rounding mode to sim FP rounding mode flag conversion code into...
930 (rounding_mode): New function.
932 2002-06-07 Chris Demetriou <cgd@broadcom.com>
934 * cp1.c: Clean up formatting of a few comments.
935 (value_fpr): Reformat switch statement.
937 2002-06-06 Chris Demetriou <cgd@broadcom.com>
938 Ed Satterthwaite <ehs@broadcom.com>
941 * sim-main.h: Include cp1.h.
942 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
943 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
944 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
945 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
946 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
947 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
948 * cp1.c: Don't include sim-fpu.h; already included by
949 sim-main.h. Clean up formatting of some comments.
950 (NaN, Equal, Less): Remove.
951 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
952 (fp_cmp): New functions.
953 * mips.igen (do_c_cond_fmt): Remove.
954 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
955 Compare. Add result tracing.
956 (CxC1): Remove, replace with...
957 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
958 (DMxC1): Remove, replace with...
959 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
960 (MxC1): Remove, replace with...
961 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
963 2002-06-04 Chris Demetriou <cgd@broadcom.com>
965 * sim-main.h (FGRIDX): Remove, replace all uses with...
966 (FGR_BASE): New macro.
967 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
968 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
969 (NR_FGR, FGR): Likewise.
970 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
971 * mips.igen: Likewise.
973 2002-06-04 Chris Demetriou <cgd@broadcom.com>
975 * cp1.c: Add an FSF Copyright notice to this file.
977 2002-06-04 Chris Demetriou <cgd@broadcom.com>
978 Ed Satterthwaite <ehs@broadcom.com>
980 * cp1.c (Infinity): Remove.
981 * sim-main.h (Infinity): Likewise.
983 * cp1.c (fp_unary, fp_binary): New functions.
984 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
985 (fp_sqrt): New functions, implemented in terms of the above.
986 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
987 (Recip, SquareRoot): Remove (replaced by functions above).
988 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
989 (fp_recip, fp_sqrt): New prototypes.
990 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
991 (Recip, SquareRoot): Replace prototypes with #defines which
992 invoke the functions above.
994 2002-06-03 Chris Demetriou <cgd@broadcom.com>
996 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
997 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
998 file, remove PARAMS from prototypes.
999 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1000 simulator state arguments.
1001 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1002 pass simulator state arguments.
1003 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1004 (store_fpr, convert): Remove 'sd' argument.
1005 (value_fpr): Likewise. Convert to use 'SD' instead.
1007 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1009 * cp1.c (Min, Max): Remove #if 0'd functions.
1010 * sim-main.h (Min, Max): Remove.
1012 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1014 * cp1.c: fix formatting of switch case and default labels.
1015 * interp.c: Likewise.
1016 * sim-main.c: Likewise.
1018 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1020 * cp1.c: Clean up comments which describe FP formats.
1021 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1023 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1024 Ed Satterthwaite <ehs@broadcom.com>
1026 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1027 Broadcom SiByte SB-1 processor configurations.
1028 * configure: Regenerate.
1029 * sb1.igen: New file.
1030 * mips.igen: Include sb1.igen.
1032 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1033 * mdmx.igen: Add "sb1" model to all appropriate functions and
1035 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1036 (ob_func, ob_acc): Reference the above.
1037 (qh_acc): Adjust to keep the same size as ob_acc.
1038 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1039 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1041 2002-06-03 Chris Demetriou <cgd@broadcom.com>
1043 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1045 2002-06-02 Chris Demetriou <cgd@broadcom.com>
1046 Ed Satterthwaite <ehs@broadcom.com>
1048 * mips.igen (mdmx): New (pseudo-)model.
1049 * mdmx.c, mdmx.igen: New files.
1050 * Makefile.in (SIM_OBJS): Add mdmx.o.
1051 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1053 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1054 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1055 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1056 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1057 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1058 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1059 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1060 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1061 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1062 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1063 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1064 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1065 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1066 (qh_fmtsel): New macros.
1067 (_sim_cpu): New member "acc".
1068 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1069 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1071 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1073 * interp.c: Use 'deprecated' rather than 'depreciated.'
1074 * sim-main.h: Likewise.
1076 2002-05-01 Chris Demetriou <cgd@broadcom.com>
1078 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1079 which wouldn't compile anyway.
1080 * sim-main.h (unpredictable_action): New function prototype.
1081 (Unpredictable): Define to call igen function unpredictable().
1082 (NotWordValue): New macro to call igen function not_word_value().
1083 (UndefinedResult): Remove.
1084 * interp.c (undefined_result): Remove.
1085 (unpredictable_action): New function.
1086 * mips.igen (not_word_value, unpredictable): New functions.
1087 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1088 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1089 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1090 NotWordValue() to check for unpredictable inputs, then
1091 Unpredictable() to handle them.
1093 2002-02-24 Chris Demetriou <cgd@broadcom.com>
1095 * mips.igen: Fix formatting of calls to Unpredictable().
1097 2002-04-20 Andrew Cagney <ac131313@redhat.com>
1099 * interp.c (sim_open): Revert previous change.
1101 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
1103 * interp.c (sim_open): Disable chunk of code that wrote code in
1104 vector table entries.
1106 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1108 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1109 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1112 2002-03-19 Chris Demetriou <cgd@broadcom.com>
1114 * cp1.c: Fix many formatting issues.
1116 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1118 * cp1.c (fpu_format_name): New function to replace...
1119 (DOFMT): This. Delete, and update all callers.
1120 (fpu_rounding_mode_name): New function to replace...
1121 (RMMODE): This. Delete, and update all callers.
1123 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1125 * interp.c: Move FPU support routines from here to...
1126 * cp1.c: Here. New file.
1127 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1128 (cp1.o): New target.
1130 2002-03-12 Chris Demetriou <cgd@broadcom.com>
1132 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1133 * mips.igen (mips32, mips64): New models, add to all instructions
1134 and functions as appropriate.
1135 (loadstore_ea, check_u64): New variant for model mips64.
1136 (check_fmt_p): New variant for models mipsV and mips64, remove
1137 mipsV model marking fro other variant.
1140 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1141 for mips32 and mips64.
1142 (DCLO, DCLZ): New instructions for mips64.
1144 2002-03-07 Chris Demetriou <cgd@broadcom.com>
1146 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1147 immediate or code as a hex value with the "%#lx" format.
1148 (ANDI): Likewise, and fix printed instruction name.
1150 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1152 * sim-main.h (UndefinedResult, Unpredictable): New macros
1153 which currently do nothing.
1155 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1157 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1158 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1159 (status_CU3): New definitions.
1161 * sim-main.h (ExceptionCause): Add new values for MIPS32
1162 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1163 for DebugBreakPoint and NMIReset to note their status in
1165 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1166 (SignalExceptionCacheErr): New exception macros.
1168 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1170 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1171 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1173 (SignalExceptionCoProcessorUnusable): Take as argument the
1174 unusable coprocessor number.
1176 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1178 * mips.igen: Fix formatting of all SignalException calls.
1180 2002-03-05 Chris Demetriou <cgd@broadcom.com>
1182 * sim-main.h (SIGNEXTEND): Remove.
1184 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1186 * mips.igen: Remove gencode comment from top of file, fix
1187 spelling in another comment.
1189 2002-03-04 Chris Demetriou <cgd@broadcom.com>
1191 * mips.igen (check_fmt, check_fmt_p): New functions to check
1192 whether specific floating point formats are usable.
1193 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1194 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1195 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1196 Use the new functions.
1197 (do_c_cond_fmt): Remove format checks...
1198 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1200 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1202 * mips.igen: Fix formatting of check_fpu calls.
1204 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1206 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1208 2002-03-03 Chris Demetriou <cgd@broadcom.com>
1210 * mips.igen: Remove whitespace at end of lines.
1212 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1214 * mips.igen (loadstore_ea): New function to do effective
1215 address calculations.
1216 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1217 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1218 CACHE): Use loadstore_ea to do effective address computations.
1220 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1222 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1223 * mips.igen (LL, CxC1, MxC1): Likewise.
1225 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1227 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1228 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1229 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1230 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1231 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1232 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1233 Don't split opcode fields by hand, use the opcode field values
1236 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1238 * mips.igen (do_divu): Fix spacing.
1240 * mips.igen (do_dsllv): Move to be right before DSLLV,
1241 to match the rest of the do_<shift> functions.
1243 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1245 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1246 DSRL32, do_dsrlv): Trace inputs and results.
1248 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1250 * mips.igen (CACHE): Provide instruction-printing string.
1252 * interp.c (signal_exception): Comment tokens after #endif.
1254 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1256 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1257 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1258 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1259 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1260 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1261 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1262 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1263 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1265 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1267 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1268 instruction-printing string.
1269 (LWU): Use '64' as the filter flag.
1271 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1273 * mips.igen (SDXC1): Fix instruction-printing string.
1275 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1277 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1278 filter flags "32,f".
1280 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1282 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1285 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1287 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1288 add a comma) so that it more closely match the MIPS ISA
1289 documentation opcode partitioning.
1290 (PREF): Put useful names on opcode fields, and include
1291 instruction-printing string.
1293 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1295 * mips.igen (check_u64): New function which in the future will
1296 check whether 64-bit instructions are usable and signal an
1297 exception if not. Currently a no-op.
1298 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1299 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1300 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1301 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1303 * mips.igen (check_fpu): New function which in the future will
1304 check whether FPU instructions are usable and signal an exception
1305 if not. Currently a no-op.
1306 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1307 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1308 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1309 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1310 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1311 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1312 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1313 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1315 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1317 * mips.igen (do_load_left, do_load_right): Move to be immediately
1319 (do_store_left, do_store_right): Move to be immediately following
1322 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1324 * mips.igen (mipsV): New model name. Also, add it to
1325 all instructions and functions where it is appropriate.
1327 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1329 * mips.igen: For all functions and instructions, list model
1330 names that support that instruction one per line.
1332 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1334 * mips.igen: Add some additional comments about supported
1335 models, and about which instructions go where.
1336 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1337 order as is used in the rest of the file.
1339 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1341 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1342 indicating that ALU32_END or ALU64_END are there to check
1344 (DADD): Likewise, but also remove previous comment about
1347 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1349 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1350 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1351 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1352 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1353 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1354 fields (i.e., add and move commas) so that they more closely
1355 match the MIPS ISA documentation opcode partitioning.
1357 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1359 * mips.igen (ADDI): Print immediate value.
1360 (BREAK): Print code.
1361 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1362 (SLL): Print "nop" specially, and don't run the code
1363 that does the shift for the "nop" case.
1365 2001-11-17 Fred Fish <fnf@redhat.com>
1367 * sim-main.h (float_operation): Move enum declaration outside
1368 of _sim_cpu struct declaration.
1370 2001-04-12 Jim Blandy <jimb@redhat.com>
1372 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1373 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1375 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1376 PENDING_FILL, and you can get the intended effect gracefully by
1377 calling PENDING_SCHED directly.
1379 2001-02-23 Ben Elliston <bje@redhat.com>
1381 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1382 already defined elsewhere.
1384 2001-02-19 Ben Elliston <bje@redhat.com>
1386 * sim-main.h (sim_monitor): Return an int.
1387 * interp.c (sim_monitor): Add return values.
1388 (signal_exception): Handle error conditions from sim_monitor.
1390 2001-02-08 Ben Elliston <bje@redhat.com>
1392 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1393 (store_memory): Likewise, pass cia to sim_core_write*.
1395 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1397 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1398 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1400 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1402 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1403 * Makefile.in: Don't delete *.igen when cleaning directory.
1405 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1407 * m16.igen (break): Call SignalException not sim_engine_halt.
1409 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1411 From Jason Eckhardt:
1412 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1414 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1416 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1418 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1420 * mips.igen (do_dmultx): Fix typo.
1422 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1424 * configure: Regenerated to track ../common/aclocal.m4 changes.
1426 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1428 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1430 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1432 * sim-main.h (GPR_CLEAR): Define macro.
1434 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1436 * interp.c (decode_coproc): Output long using %lx and not %s.
1438 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1440 * interp.c (sim_open): Sort & extend dummy memory regions for
1441 --board=jmr3904 for eCos.
1443 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1445 * configure: Regenerated.
1447 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1449 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1450 calls, conditional on the simulator being in verbose mode.
1452 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1454 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1455 cache don't get ReservedInstruction traps.
1457 1999-11-29 Mark Salter <msalter@cygnus.com>
1459 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1460 to clear status bits in sdisr register. This is how the hardware works.
1462 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1463 being used by cygmon.
1465 1999-11-11 Andrew Haley <aph@cygnus.com>
1467 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1470 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1472 * mips.igen (MULT): Correct previous mis-applied patch.
1474 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1476 * mips.igen (delayslot32): Handle sequence like
1477 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1478 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1479 (MULT): Actually pass the third register...
1481 1999-09-03 Mark Salter <msalter@cygnus.com>
1483 * interp.c (sim_open): Added more memory aliases for additional
1484 hardware being touched by cygmon on jmr3904 board.
1486 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1488 * configure: Regenerated to track ../common/aclocal.m4 changes.
1490 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1492 * interp.c (sim_store_register): Handle case where client - GDB -
1493 specifies that a 4 byte register is 8 bytes in size.
1494 (sim_fetch_register): Ditto.
1496 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1498 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1499 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1500 (idt_monitor_base): Base address for IDT monitor traps.
1501 (pmon_monitor_base): Ditto for PMON.
1502 (lsipmon_monitor_base): Ditto for LSI PMON.
1503 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1504 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1505 (sim_firmware_command): New function.
1506 (mips_option_handler): Call it for OPTION_FIRMWARE.
1507 (sim_open): Allocate memory for idt_monitor region. If "--board"
1508 option was given, add no monitor by default. Add BREAK hooks only if
1509 monitors are also there.
1511 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1513 * interp.c (sim_monitor): Flush output before reading input.
1515 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1517 * tconfig.in (SIM_HANDLES_LMA): Always define.
1519 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1521 From Mark Salter <msalter@cygnus.com>:
1522 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1523 (sim_open): Add setup for BSP board.
1525 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1527 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1528 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1529 them as unimplemented.
1531 1999-05-08 Felix Lee <flee@cygnus.com>
1533 * configure: Regenerated to track ../common/aclocal.m4 changes.
1535 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1537 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1539 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1541 * configure.in: Any mips64vr5*-*-* target should have
1542 -DTARGET_ENABLE_FR=1.
1543 (default_endian): Any mips64vr*el-*-* target should default to
1545 * configure: Re-generate.
1547 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1549 * mips.igen (ldl): Extend from _16_, not 32.
1551 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1553 * interp.c (sim_store_register): Force registers written to by GDB
1554 into an un-interpreted state.
1556 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1558 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1559 CPU, start periodic background I/O polls.
1560 (tx3904sio_poll): New function: periodic I/O poller.
1562 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1564 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1566 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1568 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1571 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1573 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1574 (load_word): Call SIM_CORE_SIGNAL hook on error.
1575 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1576 starting. For exception dispatching, pass PC instead of NULL_CIA.
1577 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1578 * sim-main.h (COP0_BADVADDR): Define.
1579 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1580 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1581 (_sim_cpu): Add exc_* fields to store register value snapshots.
1582 * mips.igen (*): Replace memory-related SignalException* calls
1583 with references to SIM_CORE_SIGNAL hook.
1585 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1587 * sim-main.c (*): Minor warning cleanups.
1589 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1591 * m16.igen (DADDIU5): Correct type-o.
1593 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1595 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1598 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1600 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1602 (interp.o): Add dependency on itable.h
1603 (oengine.c, gencode): Delete remaining references.
1604 (BUILT_SRC_FROM_GEN): Clean up.
1606 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1609 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1610 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1611 tmp-run-hack) : New.
1612 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1613 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1614 Drop the "64" qualifier to get the HACK generator working.
1615 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1616 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1617 qualifier to get the hack generator working.
1618 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1619 (DSLL): Use do_dsll.
1620 (DSLLV): Use do_dsllv.
1621 (DSRA): Use do_dsra.
1622 (DSRL): Use do_dsrl.
1623 (DSRLV): Use do_dsrlv.
1624 (BC1): Move *vr4100 to get the HACK generator working.
1625 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1626 get the HACK generator working.
1627 (MACC) Rename to get the HACK generator working.
1628 (DMACC,MACCS,DMACCS): Add the 64.
1630 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1632 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1633 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1635 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1637 * mips/interp.c (DEBUG): Cleanups.
1639 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1641 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1642 (tx3904sio_tickle): fflush after a stdout character output.
1644 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1646 * interp.c (sim_close): Uninstall modules.
1648 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1650 * sim-main.h, interp.c (sim_monitor): Change to global
1653 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1655 * configure.in (vr4100): Only include vr4100 instructions in
1657 * configure: Re-generate.
1658 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1660 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1662 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1663 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1666 * configure.in (sim_default_gen, sim_use_gen): Replace with
1668 (--enable-sim-igen): Delete config option. Always using IGEN.
1669 * configure: Re-generate.
1671 * Makefile.in (gencode): Kill, kill, kill.
1674 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1676 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1677 bit mips16 igen simulator.
1678 * configure: Re-generate.
1680 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1681 as part of vr4100 ISA.
1682 * vr.igen: Mark all instructions as 64 bit only.
1684 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1686 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1689 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1691 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1692 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1693 * configure: Re-generate.
1695 * m16.igen (BREAK): Define breakpoint instruction.
1696 (JALX32): Mark instruction as mips16 and not r3900.
1697 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1699 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1701 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1703 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1704 insn as a debug breakpoint.
1706 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1708 (PENDING_SCHED): Clean up trace statement.
1709 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1710 (PENDING_FILL): Delay write by only one cycle.
1711 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1713 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1715 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1717 (pending_tick): Move incrementing of index to FOR statement.
1718 (pending_tick): Only update PENDING_OUT after a write has occured.
1720 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1722 * configure: Re-generate.
1724 * interp.c (sim_engine_run OLD): Delete explicit call to
1725 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1727 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1729 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1730 interrupt level number to match changed SignalExceptionInterrupt
1733 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1735 * interp.c: #include "itable.h" if WITH_IGEN.
1736 (get_insn_name): New function.
1737 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1738 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1740 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1742 * configure: Rebuilt to inhale new common/aclocal.m4.
1744 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1746 * dv-tx3904sio.c: Include sim-assert.h.
1748 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1750 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1751 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1752 Reorganize target-specific sim-hardware checks.
1753 * configure: rebuilt.
1754 * interp.c (sim_open): For tx39 target boards, set
1755 OPERATING_ENVIRONMENT, add tx3904sio devices.
1756 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1757 ROM executables. Install dv-sockser into sim-modules list.
1759 * dv-tx3904irc.c: Compiler warning clean-up.
1760 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1761 frequent hw-trace messages.
1763 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1765 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1767 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1769 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1771 * vr.igen: New file.
1772 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1773 * mips.igen: Define vr4100 model. Include vr.igen.
1774 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1776 * mips.igen (check_mf_hilo): Correct check.
1778 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1780 * sim-main.h (interrupt_event): Add prototype.
1782 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1783 register_ptr, register_value.
1784 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1786 * sim-main.h (tracefh): Make extern.
1788 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1790 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1791 Reduce unnecessarily high timer event frequency.
1792 * dv-tx3904cpu.c: Ditto for interrupt event.
1794 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1796 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1798 (interrupt_event): Made non-static.
1800 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1801 interchange of configuration values for external vs. internal
1804 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1806 * mips.igen (BREAK): Moved code to here for
1807 simulator-reserved break instructions.
1808 * gencode.c (build_instruction): Ditto.
1809 * interp.c (signal_exception): Code moved from here. Non-
1810 reserved instructions now use exception vector, rather
1812 * sim-main.h: Moved magic constants to here.
1814 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1816 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1817 register upon non-zero interrupt event level, clear upon zero
1819 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1820 by passing zero event value.
1821 (*_io_{read,write}_buffer): Endianness fixes.
1822 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1823 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1825 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1826 serial I/O and timer module at base address 0xFFFF0000.
1828 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1830 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1833 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1835 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1837 * configure: Update.
1839 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1841 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1842 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1843 * configure.in: Include tx3904tmr in hw_device list.
1844 * configure: Rebuilt.
1845 * interp.c (sim_open): Instantiate three timer instances.
1846 Fix address typo of tx3904irc instance.
1848 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1850 * interp.c (signal_exception): SystemCall exception now uses
1851 the exception vector.
1853 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1855 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1858 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1860 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1862 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1864 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1866 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1867 sim-main.h. Declare a struct hw_descriptor instead of struct
1868 hw_device_descriptor.
1870 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1872 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1873 right bits and then re-align left hand bytes to correct byte
1874 lanes. Fix incorrect computation in do_store_left when loading
1875 bytes from second word.
1877 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1879 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1880 * interp.c (sim_open): Only create a device tree when HW is
1883 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1884 * interp.c (signal_exception): Ditto.
1886 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1888 * gencode.c: Mark BEGEZALL as LIKELY.
1890 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1892 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1893 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1895 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1897 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1898 modules. Recognize TX39 target with "mips*tx39" pattern.
1899 * configure: Rebuilt.
1900 * sim-main.h (*): Added many macros defining bits in
1901 TX39 control registers.
1902 (SignalInterrupt): Send actual PC instead of NULL.
1903 (SignalNMIReset): New exception type.
1904 * interp.c (board): New variable for future use to identify
1905 a particular board being simulated.
1906 (mips_option_handler,mips_options): Added "--board" option.
1907 (interrupt_event): Send actual PC.
1908 (sim_open): Make memory layout conditional on board setting.
1909 (signal_exception): Initial implementation of hardware interrupt
1910 handling. Accept another break instruction variant for simulator
1912 (decode_coproc): Implement RFE instruction for TX39.
1913 (mips.igen): Decode RFE instruction as such.
1914 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1915 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1916 bbegin to implement memory map.
1917 * dv-tx3904cpu.c: New file.
1918 * dv-tx3904irc.c: New file.
1920 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1922 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1924 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1926 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1927 with calls to check_div_hilo.
1929 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1931 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1932 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1933 Add special r3900 version of do_mult_hilo.
1934 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1935 with calls to check_mult_hilo.
1936 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1937 with calls to check_div_hilo.
1939 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1941 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1942 Document a replacement.
1944 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1946 * interp.c (sim_monitor): Make mon_printf work.
1948 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1950 * sim-main.h (INSN_NAME): New arg `cpu'.
1952 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1954 * configure: Regenerated to track ../common/aclocal.m4 changes.
1956 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1958 * configure: Regenerated to track ../common/aclocal.m4 changes.
1961 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1963 * acconfig.h: New file.
1964 * configure.in: Reverted change of Apr 24; use sinclude again.
1966 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1968 * configure: Regenerated to track ../common/aclocal.m4 changes.
1971 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1973 * configure.in: Don't call sinclude.
1975 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1977 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1979 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1981 * mips.igen (ERET): Implement.
1983 * interp.c (decode_coproc): Return sign-extended EPC.
1985 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1987 * interp.c (signal_exception): Do not ignore Trap.
1988 (signal_exception): On TRAP, restart at exception address.
1989 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1990 (signal_exception): Update.
1991 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1992 so that TRAP instructions are caught.
1994 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1996 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1997 contains HI/LO access history.
1998 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1999 (HIACCESS, LOACCESS): Delete, replace with
2000 (HIHISTORY, LOHISTORY): New macros.
2001 (CHECKHILO): Delete all, moved to mips.igen
2003 * gencode.c (build_instruction): Do not generate checks for
2004 correct HI/LO register usage.
2006 * interp.c (old_engine_run): Delete checks for correct HI/LO
2009 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2010 check_mf_cycles): New functions.
2011 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2012 do_divu, domultx, do_mult, do_multu): Use.
2014 * tx.igen ("madd", "maddu"): Use.
2016 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2018 * mips.igen (DSRAV): Use function do_dsrav.
2019 (SRAV): Use new function do_srav.
2021 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2022 (B): Sign extend 11 bit immediate.
2023 (EXT-B*): Shift 16 bit immediate left by 1.
2024 (ADDIU*): Don't sign extend immediate value.
2026 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2028 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2030 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2033 * mips.igen (delayslot32, nullify_next_insn): New functions.
2034 (m16.igen): Always include.
2035 (do_*): Add more tracing.
2037 * m16.igen (delayslot16): Add NIA argument, could be called by a
2038 32 bit MIPS16 instruction.
2040 * interp.c (ifetch16): Move function from here.
2041 * sim-main.c (ifetch16): To here.
2043 * sim-main.c (ifetch16, ifetch32): Update to match current
2044 implementations of LH, LW.
2045 (signal_exception): Don't print out incorrect hex value of illegal
2048 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2050 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2053 * m16.igen: Implement MIPS16 instructions.
2055 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2056 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2057 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2058 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2059 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2060 bodies of corresponding code from 32 bit insn to these. Also used
2061 by MIPS16 versions of functions.
2063 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2064 (IMEM16): Drop NR argument from macro.
2066 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2068 * Makefile.in (SIM_OBJS): Add sim-main.o.
2070 * sim-main.h (address_translation, load_memory, store_memory,
2071 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2073 (pr_addr, pr_uword64): Declare.
2074 (sim-main.c): Include when H_REVEALS_MODULE_P.
2076 * interp.c (address_translation, load_memory, store_memory,
2077 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2079 * sim-main.c: To here. Fix compilation problems.
2081 * configure.in: Enable inlining.
2082 * configure: Re-config.
2084 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2086 * configure: Regenerated to track ../common/aclocal.m4 changes.
2088 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2090 * mips.igen: Include tx.igen.
2091 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2092 * tx.igen: New file, contains MADD and MADDU.
2094 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2095 the hardwired constant `7'.
2096 (store_memory): Ditto.
2097 (LOADDRMASK): Move definition to sim-main.h.
2099 mips.igen (MTC0): Enable for r3900.
2102 mips.igen (do_load_byte): Delete.
2103 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2104 do_store_right): New functions.
2105 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2107 configure.in: Let the tx39 use igen again.
2110 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2112 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2113 not an address sized quantity. Return zero for cache sizes.
2115 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2117 * mips.igen (r3900): r3900 does not support 64 bit integer
2120 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2122 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2124 * configure : Rebuild.
2126 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2128 * configure: Regenerated to track ../common/aclocal.m4 changes.
2130 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2132 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2134 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2136 * configure: Regenerated to track ../common/aclocal.m4 changes.
2137 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2139 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2141 * configure: Regenerated to track ../common/aclocal.m4 changes.
2143 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2145 * interp.c (Max, Min): Comment out functions. Not yet used.
2147 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2149 * configure: Regenerated to track ../common/aclocal.m4 changes.
2151 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2153 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2154 configurable settings for stand-alone simulator.
2156 * configure.in: Added X11 search, just in case.
2158 * configure: Regenerated.
2160 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162 * interp.c (sim_write, sim_read, load_memory, store_memory):
2163 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2165 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2167 * sim-main.h (GETFCC): Return an unsigned value.
2169 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2171 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2172 (DADD): Result destination is RD not RT.
2174 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2176 * sim-main.h (HIACCESS, LOACCESS): Always define.
2178 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2180 * interp.c (sim_info): Delete.
2182 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2184 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2185 (mips_option_handler): New argument `cpu'.
2186 (sim_open): Update call to sim_add_option_table.
2188 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2190 * mips.igen (CxC1): Add tracing.
2192 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2194 * sim-main.h (Max, Min): Declare.
2196 * interp.c (Max, Min): New functions.
2198 * mips.igen (BC1): Add tracing.
2200 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
2202 * interp.c Added memory map for stack in vr4100
2204 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2206 * interp.c (load_memory): Add missing "break"'s.
2208 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2210 * interp.c (sim_store_register, sim_fetch_register): Pass in
2211 length parameter. Return -1.
2213 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2215 * interp.c: Added hardware init hook, fixed warnings.
2217 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2219 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2221 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2223 * interp.c (ifetch16): New function.
2225 * sim-main.h (IMEM32): Rename IMEM.
2226 (IMEM16_IMMED): Define.
2228 (DELAY_SLOT): Update.
2230 * m16run.c (sim_engine_run): New file.
2232 * m16.igen: All instructions except LB.
2233 (LB): Call do_load_byte.
2234 * mips.igen (do_load_byte): New function.
2235 (LB): Call do_load_byte.
2237 * mips.igen: Move spec for insn bit size and high bit from here.
2238 * Makefile.in (tmp-igen, tmp-m16): To here.
2240 * m16.dc: New file, decode mips16 instructions.
2242 * Makefile.in (SIM_NO_ALL): Define.
2243 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2245 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2247 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2248 point unit to 32 bit registers.
2249 * configure: Re-generate.
2251 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2253 * configure.in (sim_use_gen): Make IGEN the default simulator
2254 generator for generic 32 and 64 bit mips targets.
2255 * configure: Re-generate.
2257 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2262 * interp.c (sim_fetch_register, sim_store_register): Read/write
2263 FGR from correct location.
2264 (sim_open): Set size of FGR's according to
2265 WITH_TARGET_FLOATING_POINT_BITSIZE.
2267 * sim-main.h (FGR): Store floating point registers in a separate
2270 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272 * configure: Regenerated to track ../common/aclocal.m4 changes.
2274 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2276 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2278 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2280 * interp.c (pending_tick): New function. Deliver pending writes.
2282 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2283 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2284 it can handle mixed sized quantites and single bits.
2286 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2288 * interp.c (oengine.h): Do not include when building with IGEN.
2289 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2290 (sim_info): Ditto for PROCESSOR_64BIT.
2291 (sim_monitor): Replace ut_reg with unsigned_word.
2292 (*): Ditto for t_reg.
2293 (LOADDRMASK): Define.
2294 (sim_open): Remove defunct check that host FP is IEEE compliant,
2295 using software to emulate floating point.
2296 (value_fpr, ...): Always compile, was conditional on HASFPU.
2298 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2300 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2303 * interp.c (SD, CPU): Define.
2304 (mips_option_handler): Set flags in each CPU.
2305 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2306 (sim_close): Do not clear STATE, deleted anyway.
2307 (sim_write, sim_read): Assume CPU zero's vm should be used for
2309 (sim_create_inferior): Set the PC for all processors.
2310 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2312 (mips16_entry): Pass correct nr of args to store_word, load_word.
2313 (ColdReset): Cold reset all cpu's.
2314 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2315 (sim_monitor, load_memory, store_memory, signal_exception): Use
2316 `CPU' instead of STATE_CPU.
2319 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2322 * sim-main.h (signal_exception): Add sim_cpu arg.
2323 (SignalException*): Pass both SD and CPU to signal_exception.
2324 * interp.c (signal_exception): Update.
2326 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2328 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2329 address_translation): Ditto
2330 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2332 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2334 * configure: Regenerated to track ../common/aclocal.m4 changes.
2336 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2338 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2340 * mips.igen (model): Map processor names onto BFD name.
2342 * sim-main.h (CPU_CIA): Delete.
2343 (SET_CIA, GET_CIA): Define
2345 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2347 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2350 * configure.in (default_endian): Configure a big-endian simulator
2352 * configure: Re-generate.
2354 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2356 * configure: Regenerated to track ../common/aclocal.m4 changes.
2358 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2360 * interp.c (sim_monitor): Handle Densan monitor outbyte
2361 and inbyte functions.
2363 1997-12-29 Felix Lee <flee@cygnus.com>
2365 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2367 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2369 * Makefile.in (tmp-igen): Arrange for $zero to always be
2370 reset to zero after every instruction.
2372 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2374 * configure: Regenerated to track ../common/aclocal.m4 changes.
2377 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2379 * mips.igen (MSUB): Fix to work like MADD.
2380 * gencode.c (MSUB): Similarly.
2382 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2384 * configure: Regenerated to track ../common/aclocal.m4 changes.
2386 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2388 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2390 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2392 * sim-main.h (sim-fpu.h): Include.
2394 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2395 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2396 using host independant sim_fpu module.
2398 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2400 * interp.c (signal_exception): Report internal errors with SIGABRT
2403 * sim-main.h (C0_CONFIG): New register.
2404 (signal.h): No longer include.
2406 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2408 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2410 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2412 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2414 * mips.igen: Tag vr5000 instructions.
2415 (ANDI): Was missing mipsIV model, fix assembler syntax.
2416 (do_c_cond_fmt): New function.
2417 (C.cond.fmt): Handle mips I-III which do not support CC field
2419 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2420 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2422 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2423 vr5000 which saves LO in a GPR separatly.
2425 * configure.in (enable-sim-igen): For vr5000, select vr5000
2426 specific instructions.
2427 * configure: Re-generate.
2429 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2431 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2433 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2434 fmt_uninterpreted_64 bit cases to switch. Convert to
2437 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2439 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2440 as specified in IV3.2 spec.
2441 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2443 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2445 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2446 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2447 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2448 PENDING_FILL versions of instructions. Simplify.
2450 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2452 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2454 (MTHI, MFHI): Disable code checking HI-LO.
2456 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2458 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2460 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2462 * gencode.c (build_mips16_operands): Replace IPC with cia.
2464 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2465 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2467 (UndefinedResult): Replace function with macro/function
2469 (sim_engine_run): Don't save PC in IPC.
2471 * sim-main.h (IPC): Delete.
2474 * interp.c (signal_exception, store_word, load_word,
2475 address_translation, load_memory, store_memory, cache_op,
2476 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2477 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2478 current instruction address - cia - argument.
2479 (sim_read, sim_write): Call address_translation directly.
2480 (sim_engine_run): Rename variable vaddr to cia.
2481 (signal_exception): Pass cia to sim_monitor
2483 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2484 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2485 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2487 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2488 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2491 * interp.c (signal_exception): Pass restart address to
2494 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2495 idecode.o): Add dependency.
2497 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2499 (DELAY_SLOT): Update NIA not PC with branch address.
2500 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2502 * mips.igen: Use CIA not PC in branch calculations.
2503 (illegal): Call SignalException.
2504 (BEQ, ADDIU): Fix assembler.
2506 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2508 * m16.igen (JALX): Was missing.
2510 * configure.in (enable-sim-igen): New configuration option.
2511 * configure: Re-generate.
2513 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2515 * interp.c (load_memory, store_memory): Delete parameter RAW.
2516 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2517 bypassing {load,store}_memory.
2519 * sim-main.h (ByteSwapMem): Delete definition.
2521 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2523 * interp.c (sim_do_command, sim_commands): Delete mips specific
2524 commands. Handled by module sim-options.
2526 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2527 (WITH_MODULO_MEMORY): Define.
2529 * interp.c (sim_info): Delete code printing memory size.
2531 * interp.c (mips_size): Nee sim_size, delete function.
2533 (monitor, monitor_base, monitor_size): Delete global variables.
2534 (sim_open, sim_close): Delete code creating monitor and other
2535 memory regions. Use sim-memopts module, via sim_do_commandf, to
2536 manage memory regions.
2537 (load_memory, store_memory): Use sim-core for memory model.
2539 * interp.c (address_translation): Delete all memory map code
2540 except line forcing 32 bit addresses.
2542 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2544 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2547 * interp.c (logfh, logfile): Delete globals.
2548 (sim_open, sim_close): Delete code opening & closing log file.
2549 (mips_option_handler): Delete -l and -n options.
2550 (OPTION mips_options): Ditto.
2552 * interp.c (OPTION mips_options): Rename option trace to dinero.
2553 (mips_option_handler): Update.
2555 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2557 * interp.c (fetch_str): New function.
2558 (sim_monitor): Rewrite using sim_read & sim_write.
2559 (sim_open): Check magic number.
2560 (sim_open): Write monitor vectors into memory using sim_write.
2561 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2562 (sim_read, sim_write): Simplify - transfer data one byte at a
2564 (load_memory, store_memory): Clarify meaning of parameter RAW.
2566 * sim-main.h (isHOST): Defete definition.
2567 (isTARGET): Mark as depreciated.
2568 (address_translation): Delete parameter HOST.
2570 * interp.c (address_translation): Delete parameter HOST.
2572 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2577 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2579 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2581 * mips.igen: Add model filter field to records.
2583 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2585 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2587 interp.c (sim_engine_run): Do not compile function sim_engine_run
2588 when WITH_IGEN == 1.
2590 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2591 target architecture.
2593 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2594 igen. Replace with configuration variables sim_igen_flags /
2597 * m16.igen: New file. Copy mips16 insns here.
2598 * mips.igen: From here.
2600 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2602 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2604 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2606 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2608 * gencode.c (build_instruction): Follow sim_write's lead in using
2609 BigEndianMem instead of !ByteSwapMem.
2611 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2613 * configure.in (sim_gen): Dependent on target, select type of
2614 generator. Always select old style generator.
2616 configure: Re-generate.
2618 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2620 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2621 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2622 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2623 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2624 SIM_@sim_gen@_*, set by autoconf.
2626 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2628 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2630 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2631 CURRENT_FLOATING_POINT instead.
2633 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2634 (address_translation): Raise exception InstructionFetch when
2635 translation fails and isINSTRUCTION.
2637 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2638 sim_engine_run): Change type of of vaddr and paddr to
2640 (address_translation, prefetch, load_memory, store_memory,
2641 cache_op): Change type of vAddr and pAddr to address_word.
2643 * gencode.c (build_instruction): Change type of vaddr and paddr to
2646 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2648 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2649 macro to obtain result of ALU op.
2651 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2653 * interp.c (sim_info): Call profile_print.
2655 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2657 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2659 * sim-main.h (WITH_PROFILE): Do not define, defined in
2660 common/sim-config.h. Use sim-profile module.
2661 (simPROFILE): Delete defintion.
2663 * interp.c (PROFILE): Delete definition.
2664 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2665 (sim_close): Delete code writing profile histogram.
2666 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2668 (sim_engine_run): Delete code profiling the PC.
2670 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2672 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2674 * interp.c (sim_monitor): Make register pointers of type
2677 * sim-main.h: Make registers of type unsigned_word not
2680 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2682 * interp.c (sync_operation): Rename from SyncOperation, make
2683 global, add SD argument.
2684 (prefetch): Rename from Prefetch, make global, add SD argument.
2685 (decode_coproc): Make global.
2687 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2689 * gencode.c (build_instruction): Generate DecodeCoproc not
2690 decode_coproc calls.
2692 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2693 (SizeFGR): Move to sim-main.h
2694 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2695 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2696 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2698 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2699 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2700 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2701 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2702 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2703 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2705 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2707 (sim-alu.h): Include.
2708 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2709 (sim_cia): Typedef to instruction_address.
2711 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2713 * Makefile.in (interp.o): Rename generated file engine.c to
2718 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2720 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2722 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2724 * gencode.c (build_instruction): For "FPSQRT", output correct
2725 number of arguments to Recip.
2727 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729 * Makefile.in (interp.o): Depends on sim-main.h
2731 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2733 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2734 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2735 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2736 STATE, DSSTATE): Define
2737 (GPR, FGRIDX, ..): Define.
2739 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2740 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2741 (GPR, FGRIDX, ...): Delete macros.
2743 * interp.c: Update names to match defines from sim-main.h
2745 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2747 * interp.c (sim_monitor): Add SD argument.
2748 (sim_warning): Delete. Replace calls with calls to
2750 (sim_error): Delete. Replace calls with sim_io_error.
2751 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2752 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2753 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2755 (mips_size): Rename from sim_size. Add SD argument.
2757 * interp.c (simulator): Delete global variable.
2758 (callback): Delete global variable.
2759 (mips_option_handler, sim_open, sim_write, sim_read,
2760 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2761 sim_size,sim_monitor): Use sim_io_* not callback->*.
2762 (sim_open): ZALLOC simulator struct.
2763 (PROFILE): Do not define.
2765 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2767 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2768 support.h with corresponding code.
2770 * sim-main.h (word64, uword64), support.h: Move definition to
2772 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2775 * Makefile.in: Update dependencies
2776 * interp.c: Do not include.
2778 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2780 * interp.c (address_translation, load_memory, store_memory,
2781 cache_op): Rename to from AddressTranslation et.al., make global,
2784 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2787 * interp.c (SignalException): Rename to signal_exception, make
2790 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2792 * sim-main.h (SignalException, SignalExceptionInterrupt,
2793 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2794 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2795 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2798 * interp.c, support.h: Use.
2800 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2802 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2803 to value_fpr / store_fpr. Add SD argument.
2804 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2805 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2807 * sim-main.h (ValueFPR, StoreFPR): Define.
2809 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2811 * interp.c (sim_engine_run): Check consistency between configure
2812 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2815 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2816 (mips_fpu): Configure WITH_FLOATING_POINT.
2817 (mips_endian): Configure WITH_TARGET_ENDIAN.
2818 * configure: Update.
2820 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2822 * configure: Regenerated to track ../common/aclocal.m4 changes.
2824 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2826 * configure: Regenerated.
2828 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2830 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2832 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834 * gencode.c (print_igen_insn_models): Assume certain architectures
2835 include all mips* instructions.
2836 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2839 * Makefile.in (tmp.igen): Add target. Generate igen input from
2842 * gencode.c (FEATURE_IGEN): Define.
2843 (main): Add --igen option. Generate output in igen format.
2844 (process_instructions): Format output according to igen option.
2845 (print_igen_insn_format): New function.
2846 (print_igen_insn_models): New function.
2847 (process_instructions): Only issue warnings and ignore
2848 instructions when no FEATURE_IGEN.
2850 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2852 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2855 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2857 * configure: Regenerated to track ../common/aclocal.m4 changes.
2859 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2861 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2862 SIM_RESERVED_BITS): Delete, moved to common.
2863 (SIM_EXTRA_CFLAGS): Update.
2865 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2867 * configure.in: Configure non-strict memory alignment.
2868 * configure: Regenerated to track ../common/aclocal.m4 changes.
2870 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2872 * configure: Regenerated to track ../common/aclocal.m4 changes.
2874 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2876 * gencode.c (SDBBP,DERET): Added (3900) insns.
2877 (RFE): Turn on for 3900.
2878 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2879 (dsstate): Made global.
2880 (SUBTARGET_R3900): Added.
2881 (CANCELDELAYSLOT): New.
2882 (SignalException): Ignore SystemCall rather than ignore and
2883 terminate. Add DebugBreakPoint handling.
2884 (decode_coproc): New insns RFE, DERET; and new registers Debug
2885 and DEPC protected by SUBTARGET_R3900.
2886 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2888 * Makefile.in,configure.in: Add mips subtarget option.
2889 * configure: Update.
2891 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2893 * gencode.c: Add r3900 (tx39).
2896 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2898 * gencode.c (build_instruction): Don't need to subtract 4 for
2901 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2903 * interp.c: Correct some HASFPU problems.
2905 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2907 * configure: Regenerated to track ../common/aclocal.m4 changes.
2909 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2911 * interp.c (mips_options): Fix samples option short form, should
2914 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916 * interp.c (sim_info): Enable info code. Was just returning.
2918 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2920 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2923 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2925 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2927 (build_instruction): Ditto for LL.
2929 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2931 * configure: Regenerated to track ../common/aclocal.m4 changes.
2933 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2935 * configure: Regenerated to track ../common/aclocal.m4 changes.
2938 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2940 * interp.c (sim_open): Add call to sim_analyze_program, update
2943 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2945 * interp.c (sim_kill): Delete.
2946 (sim_create_inferior): Add ABFD argument. Set PC from same.
2947 (sim_load): Move code initializing trap handlers from here.
2948 (sim_open): To here.
2949 (sim_load): Delete, use sim-hload.c.
2951 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2953 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2955 * configure: Regenerated to track ../common/aclocal.m4 changes.
2958 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2960 * interp.c (sim_open): Add ABFD argument.
2961 (sim_load): Move call to sim_config from here.
2962 (sim_open): To here. Check return status.
2964 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2966 * gencode.c (build_instruction): Two arg MADD should
2967 not assign result to $0.
2969 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2971 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2972 * sim/mips/configure.in: Regenerate.
2974 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2976 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2977 signed8, unsigned8 et.al. types.
2979 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2980 hosts when selecting subreg.
2982 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2984 * interp.c (sim_engine_run): Reset the ZERO register to zero
2985 regardless of FEATURE_WARN_ZERO.
2986 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2988 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2990 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2991 (SignalException): For BreakPoints ignore any mode bits and just
2993 (SignalException): Always set the CAUSE register.
2995 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2997 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2998 exception has been taken.
3000 * interp.c: Implement the ERET and mt/f sr instructions.
3002 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3004 * interp.c (SignalException): Don't bother restarting an
3007 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3009 * interp.c (SignalException): Really take an interrupt.
3010 (interrupt_event): Only deliver interrupts when enabled.
3012 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3014 * interp.c (sim_info): Only print info when verbose.
3015 (sim_info) Use sim_io_printf for output.
3017 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3019 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3022 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3024 * interp.c (sim_do_command): Check for common commands if a
3025 simulator specific command fails.
3027 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3029 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3030 and simBE when DEBUG is defined.
3032 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3034 * interp.c (interrupt_event): New function. Pass exception event
3035 onto exception handler.
3037 * configure.in: Check for stdlib.h.
3038 * configure: Regenerate.
3040 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3041 variable declaration.
3042 (build_instruction): Initialize memval1.
3043 (build_instruction): Add UNUSED attribute to byte, bigend,
3045 (build_operands): Ditto.
3047 * interp.c: Fix GCC warnings.
3048 (sim_get_quit_code): Delete.
3050 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3051 * Makefile.in: Ditto.
3052 * configure: Re-generate.
3054 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3056 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3058 * interp.c (mips_option_handler): New function parse argumes using
3060 (myname): Replace with STATE_MY_NAME.
3061 (sim_open): Delete check for host endianness - performed by
3063 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3064 (sim_open): Move much of the initialization from here.
3065 (sim_load): To here. After the image has been loaded and
3067 (sim_open): Move ColdReset from here.
3068 (sim_create_inferior): To here.
3069 (sim_open): Make FP check less dependant on host endianness.
3071 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3073 * interp.c (sim_set_callbacks): Delete.
3075 * interp.c (membank, membank_base, membank_size): Replace with
3076 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3077 (sim_open): Remove call to callback->init. gdb/run do this.
3081 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3083 * interp.c (big_endian_p): Delete, replaced by
3084 current_target_byte_order.
3086 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3088 * interp.c (host_read_long, host_read_word, host_swap_word,
3089 host_swap_long): Delete. Using common sim-endian.
3090 (sim_fetch_register, sim_store_register): Use H2T.
3091 (pipeline_ticks): Delete. Handled by sim-events.
3093 (sim_engine_run): Update.
3095 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3097 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3099 (SignalException): To here. Signal using sim_engine_halt.
3100 (sim_stop_reason): Delete, moved to common.
3102 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3104 * interp.c (sim_open): Add callback argument.
3105 (sim_set_callbacks): Delete SIM_DESC argument.
3108 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3110 * Makefile.in (SIM_OBJS): Add common modules.
3112 * interp.c (sim_set_callbacks): Also set SD callback.
3113 (set_endianness, xfer_*, swap_*): Delete.
3114 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3115 Change to functions using sim-endian macros.
3116 (control_c, sim_stop): Delete, use common version.
3117 (simulate): Convert into.
3118 (sim_engine_run): This function.
3119 (sim_resume): Delete.
3121 * interp.c (simulation): New variable - the simulator object.
3122 (sim_kind): Delete global - merged into simulation.
3123 (sim_load): Cleanup. Move PC assignment from here.
3124 (sim_create_inferior): To here.
3126 * sim-main.h: New file.
3127 * interp.c (sim-main.h): Include.
3129 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3131 * configure: Regenerated to track ../common/aclocal.m4 changes.
3133 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3135 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3137 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3139 * gencode.c (build_instruction): DIV instructions: check
3140 for division by zero and integer overflow before using
3141 host's division operation.
3143 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3145 * Makefile.in (SIM_OBJS): Add sim-load.o.
3146 * interp.c: #include bfd.h.
3147 (target_byte_order): Delete.
3148 (sim_kind, myname, big_endian_p): New static locals.
3149 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3150 after argument parsing. Recognize -E arg, set endianness accordingly.
3151 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3152 load file into simulator. Set PC from bfd.
3153 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3154 (set_endianness): Use big_endian_p instead of target_byte_order.
3156 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3158 * interp.c (sim_size): Delete prototype - conflicts with
3159 definition in remote-sim.h. Correct definition.
3161 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3163 * configure: Regenerated to track ../common/aclocal.m4 changes.
3166 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3168 * interp.c (sim_open): New arg `kind'.
3170 * configure: Regenerated to track ../common/aclocal.m4 changes.
3172 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3174 * configure: Regenerated to track ../common/aclocal.m4 changes.
3176 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3178 * interp.c (sim_open): Set optind to 0 before calling getopt.
3180 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3182 * configure: Regenerated to track ../common/aclocal.m4 changes.
3184 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3186 * interp.c : Replace uses of pr_addr with pr_uword64
3187 where the bit length is always 64 independent of SIM_ADDR.
3188 (pr_uword64) : added.
3190 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3192 * configure: Re-generate.
3194 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3196 * configure: Regenerate to track ../common/aclocal.m4 changes.
3198 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3200 * interp.c (sim_open): New SIM_DESC result. Argument is now
3202 (other sim_*): New SIM_DESC argument.
3204 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3206 * interp.c: Fix printing of addresses for non-64-bit targets.
3207 (pr_addr): Add function to print address based on size.
3209 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3211 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3213 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3215 * gencode.c (build_mips16_operands): Correct computation of base
3216 address for extended PC relative instruction.
3218 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3220 * interp.c (mips16_entry): Add support for floating point cases.
3221 (SignalException): Pass floating point cases to mips16_entry.
3222 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3224 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3226 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3227 and then set the state to fmt_uninterpreted.
3228 (COP_SW): Temporarily set the state to fmt_word while calling
3231 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3233 * gencode.c (build_instruction): The high order may be set in the
3234 comparison flags at any ISA level, not just ISA 4.
3236 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3238 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3239 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3240 * configure.in: sinclude ../common/aclocal.m4.
3241 * configure: Regenerated.
3243 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3245 * configure: Rebuild after change to aclocal.m4.
3247 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3249 * configure configure.in Makefile.in: Update to new configure
3250 scheme which is more compatible with WinGDB builds.
3251 * configure.in: Improve comment on how to run autoconf.
3252 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3253 * Makefile.in: Use autoconf substitution to install common
3256 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3258 * gencode.c (build_instruction): Use BigEndianCPU instead of
3261 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3263 * interp.c (sim_monitor): Make output to stdout visible in
3264 wingdb's I/O log window.
3266 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3268 * support.h: Undo previous change to SIGTRAP
3271 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3273 * interp.c (store_word, load_word): New static functions.
3274 (mips16_entry): New static function.
3275 (SignalException): Look for mips16 entry and exit instructions.
3276 (simulate): Use the correct index when setting fpr_state after
3277 doing a pending move.
3279 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3281 * interp.c: Fix byte-swapping code throughout to work on
3282 both little- and big-endian hosts.
3284 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3286 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3287 with gdb/config/i386/xm-windows.h.
3289 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3291 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3292 that messes up arithmetic shifts.
3294 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3296 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3297 SIGTRAP and SIGQUIT for _WIN32.
3299 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3301 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3302 force a 64 bit multiplication.
3303 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3304 destination register is 0, since that is the default mips16 nop
3307 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3309 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3310 (build_endian_shift): Don't check proc64.
3311 (build_instruction): Always set memval to uword64. Cast op2 to
3312 uword64 when shifting it left in memory instructions. Always use
3313 the same code for stores--don't special case proc64.
3315 * gencode.c (build_mips16_operands): Fix base PC value for PC
3317 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3319 * interp.c (simJALDELAYSLOT): Define.
3320 (JALDELAYSLOT): Define.
3321 (INDELAYSLOT, INJALDELAYSLOT): Define.
3322 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3324 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3326 * interp.c (sim_open): add flush_cache as a PMON routine
3327 (sim_monitor): handle flush_cache by ignoring it
3329 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3331 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3333 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3334 (BigEndianMem): Rename to ByteSwapMem and change sense.
3335 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3336 BigEndianMem references to !ByteSwapMem.
3337 (set_endianness): New function, with prototype.
3338 (sim_open): Call set_endianness.
3339 (sim_info): Use simBE instead of BigEndianMem.
3340 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3341 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3342 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3343 ifdefs, keeping the prototype declaration.
3344 (swap_word): Rewrite correctly.
3345 (ColdReset): Delete references to CONFIG. Delete endianness related
3346 code; moved to set_endianness.
3348 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3350 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3351 * interp.c (CHECKHILO): Define away.
3352 (simSIGINT): New macro.
3353 (membank_size): Increase from 1MB to 2MB.
3354 (control_c): New function.
3355 (sim_resume): Rename parameter signal to signal_number. Add local
3356 variable prev. Call signal before and after simulate.
3357 (sim_stop_reason): Add simSIGINT support.
3358 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3360 (sim_warning): Delete call to SignalException. Do call printf_filtered
3362 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3363 a call to sim_warning.
3365 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3367 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3368 16 bit instructions.
3370 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3372 Add support for mips16 (16 bit MIPS implementation):
3373 * gencode.c (inst_type): Add mips16 instruction encoding types.
3374 (GETDATASIZEINSN): Define.
3375 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3376 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3378 (MIPS16_DECODE): New table, for mips16 instructions.
3379 (bitmap_val): New static function.
3380 (struct mips16_op): Define.
3381 (mips16_op_table): New table, for mips16 operands.
3382 (build_mips16_operands): New static function.
3383 (process_instructions): If PC is odd, decode a mips16
3384 instruction. Break out instruction handling into new
3385 build_instruction function.
3386 (build_instruction): New static function, broken out of
3387 process_instructions. Check modifiers rather than flags for SHIFT
3388 bit count and m[ft]{hi,lo} direction.
3389 (usage): Pass program name to fprintf.
3390 (main): Remove unused variable this_option_optind. Change
3391 ``*loptarg++'' to ``loptarg++''.
3392 (my_strtoul): Parenthesize && within ||.
3393 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3394 (simulate): If PC is odd, fetch a 16 bit instruction, and
3395 increment PC by 2 rather than 4.
3396 * configure.in: Add case for mips16*-*-*.
3397 * configure: Rebuild.
3399 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3401 * interp.c: Allow -t to enable tracing in standalone simulator.
3402 Fix garbage output in trace file and error messages.
3404 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3406 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3407 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3408 * configure.in: Simplify using macros in ../common/aclocal.m4.
3409 * configure: Regenerated.
3410 * tconfig.in: New file.
3412 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3414 * interp.c: Fix bugs in 64-bit port.
3415 Use ansi function declarations for msvc compiler.
3416 Initialize and test file pointer in trace code.
3417 Prevent duplicate definition of LAST_EMED_REGNUM.
3419 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3421 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3423 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3425 * interp.c (SignalException): Check for explicit terminating
3427 * gencode.c: Pass instruction value through SignalException()
3428 calls for Trap, Breakpoint and Syscall.
3430 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3432 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3433 only used on those hosts that provide it.
3434 * configure.in: Add sqrt() to list of functions to be checked for.
3435 * config.in: Re-generated.
3436 * configure: Re-generated.
3438 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3440 * gencode.c (process_instructions): Call build_endian_shift when
3441 expanding STORE RIGHT, to fix swr.
3442 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3443 clear the high bits.
3444 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3445 Fix float to int conversions to produce signed values.
3447 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3449 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3450 (process_instructions): Correct handling of nor instruction.
3451 Correct shift count for 32 bit shift instructions. Correct sign
3452 extension for arithmetic shifts to not shift the number of bits in
3453 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3454 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3456 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3457 It's OK to have a mult follow a mult. What's not OK is to have a
3458 mult follow an mfhi.
3459 (Convert): Comment out incorrect rounding code.
3461 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3463 * interp.c (sim_monitor): Improved monitor printf
3464 simulation. Tidied up simulator warnings, and added "--log" option
3465 for directing warning message output.
3466 * gencode.c: Use sim_warning() rather than WARNING macro.
3468 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3470 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3471 getopt1.o, rather than on gencode.c. Link objects together.
3472 Don't link against -liberty.
3473 (gencode.o, getopt.o, getopt1.o): New targets.
3474 * gencode.c: Include <ctype.h> and "ansidecl.h".
3475 (AND): Undefine after including "ansidecl.h".
3476 (ULONG_MAX): Define if not defined.
3477 (OP_*): Don't define macros; now defined in opcode/mips.h.
3478 (main): Call my_strtoul rather than strtoul.
3479 (my_strtoul): New static function.
3481 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3483 * gencode.c (process_instructions): Generate word64 and uword64
3484 instead of `long long' and `unsigned long long' data types.
3485 * interp.c: #include sysdep.h to get signals, and define default
3487 * (Convert): Work around for Visual-C++ compiler bug with type
3489 * support.h: Make things compile under Visual-C++ by using
3490 __int64 instead of `long long'. Change many refs to long long
3491 into word64/uword64 typedefs.
3493 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3495 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3496 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3498 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3499 (AC_PROG_INSTALL): Added.
3500 (AC_PROG_CC): Moved to before configure.host call.
3501 * configure: Rebuilt.
3503 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3505 * configure.in: Define @SIMCONF@ depending on mips target.
3506 * configure: Rebuild.
3507 * Makefile.in (run): Add @SIMCONF@ to control simulator
3509 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3510 * interp.c: Remove some debugging, provide more detailed error
3511 messages, update memory accesses to use LOADDRMASK.
3513 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3515 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3516 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3518 * configure: Rebuild.
3519 * config.in: New file, generated by autoheader.
3520 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3521 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3522 HAVE_ANINT and HAVE_AINT, as appropriate.
3523 * Makefile.in (run): Use @LIBS@ rather than -lm.
3524 (interp.o): Depend upon config.h.
3525 (Makefile): Just rebuild Makefile.
3526 (clean): Remove stamp-h.
3527 (mostlyclean): Make the same as clean, not as distclean.
3528 (config.h, stamp-h): New targets.
3530 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3532 * interp.c (ColdReset): Fix boolean test. Make all simulator
3535 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3537 * interp.c (xfer_direct_word, xfer_direct_long,
3538 swap_direct_word, swap_direct_long, xfer_big_word,
3539 xfer_big_long, xfer_little_word, xfer_little_long,
3540 swap_word,swap_long): Added.
3541 * interp.c (ColdReset): Provide function indirection to
3542 host<->simulated_target transfer routines.
3543 * interp.c (sim_store_register, sim_fetch_register): Updated to
3544 make use of indirected transfer routines.
3546 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3548 * gencode.c (process_instructions): Ensure FP ABS instruction
3550 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3551 system call support.
3553 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3555 * interp.c (sim_do_command): Complain if callback structure not
3558 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3560 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3561 support for Sun hosts.
3562 * Makefile.in (gencode): Ensure the host compiler and libraries
3563 used for cross-hosted build.
3565 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3567 * interp.c, gencode.c: Some more (TODO) tidying.
3569 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3571 * gencode.c, interp.c: Replaced explicit long long references with
3572 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3573 * support.h (SET64LO, SET64HI): Macros added.
3575 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3577 * configure: Regenerate with autoconf 2.7.
3579 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3581 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3582 * support.h: Remove superfluous "1" from #if.
3583 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3585 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3587 * interp.c (StoreFPR): Control UndefinedResult() call on
3588 WARN_RESULT manifest.
3590 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3592 * gencode.c: Tidied instruction decoding, and added FP instruction
3595 * interp.c: Added dineroIII, and BSD profiling support. Also
3596 run-time FP handling.
3598 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3600 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3601 gencode.c, interp.c, support.h: created.