2 /* MIPS Simulator FPU (CoProcessor 1) support.
3 Copyright (C) 2002-2021 Free Software Foundation, Inc.
4 Originally created by Cygnus Solutions. Extensive modifications,
5 including paired-single operation support and MIPS-3D support
6 contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
9 This file is part of GDB, the GNU debugger.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* XXX: The following notice should be removed as soon as is practical: */
25 /* Floating Point Support for gdb MIPS simulators
27 This file is part of the MIPS sim
29 THIS SOFTWARE IS NOT COPYRIGHTED
32 Cygnus offers the following for use in the public domain. Cygnus
33 makes no warranty with regard to the software or it's performance
34 and the user accepts the software "AS IS" with all faults.
36 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
37 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
38 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
40 (Originally, this code was in interp.c)
43 /* This must come before any other includes. */
50 /* Within cp1.c we refer to sim_cpu directly. */
52 #define SD CPU_STATE(cpu)
54 /*-- FPU support routines ---------------------------------------------------*/
56 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
57 formats conform to ANSI/IEEE Std 754-1985.
59 SINGLE precision floating:
60 seeeeeeeefffffffffffffffffffffff
65 SINGLE precision fixed:
66 siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
70 DOUBLE precision floating:
71 seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
76 DOUBLE precision fixed:
77 siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
81 PAIRED SINGLE precision floating:
82 seeeeeeeefffffffffffffffffffffffseeeeeeeefffffffffffffffffffffff
87 Note: upper = [63..32], lower = [31..0]
90 /* Extract packed single values: */
91 #define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF)
92 #define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF)
93 #define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \
94 | (unsigned64)((l) & 0xFFFFFFFF))
96 /* Explicit QNaN values. */
97 #define FPQNaN_SINGLE (0x7FBFFFFF)
98 #define FPQNaN_WORD (0x7FFFFFFF)
99 #define FPQNaN_DOUBLE (UNSIGNED64 (0x7FF7FFFFFFFFFFFF))
100 #define FPQNaN_LONG (UNSIGNED64 (0x7FFFFFFFFFFFFFFF))
101 #define FPQNaN_PS (FP_PS_cat (FPQNaN_SINGLE, FPQNaN_SINGLE))
103 static const char *fpu_format_name (FP_formats fmt
);
105 static const char *fpu_rounding_mode_name (int rm
);
109 value_fpr (sim_cpu
*cpu
,
117 /* Treat unused register values, as fixed-point 64bit values. */
118 if (fmt
== fmt_unknown
)
121 /* If request to read data as "unknown", then use the current
123 fmt
= FPR_STATE
[fpr
];
129 /* For values not yet accessed, set to the desired format. */
130 if (fmt
< fmt_uninterpreted
)
132 if (FPR_STATE
[fpr
] == fmt_uninterpreted
)
134 FPR_STATE
[fpr
] = fmt
;
136 printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr
,
137 fpu_format_name (fmt
));
140 else if (fmt
!= FPR_STATE
[fpr
])
142 sim_io_eprintf (SD
, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
143 fpr
, fpu_format_name (FPR_STATE
[fpr
]),
144 fpu_format_name (fmt
), pr_addr (cia
));
145 FPR_STATE
[fpr
] = fmt_unknown
;
149 if (FPR_STATE
[fpr
] == fmt_unknown
)
151 /* Set QNaN value: */
154 case fmt_single
: value
= FPQNaN_SINGLE
; break;
155 case fmt_double
: value
= FPQNaN_DOUBLE
; break;
156 case fmt_word
: value
= FPQNaN_WORD
; break;
157 case fmt_long
: value
= FPQNaN_LONG
; break;
158 case fmt_ps
: value
= FPQNaN_PS
; break;
159 default: err
= -1; break;
162 else if (SizeFGR () == 64)
166 case fmt_uninterpreted_32
:
169 value
= (FGR
[fpr
] & 0xFFFFFFFF);
172 case fmt_uninterpreted_64
:
173 case fmt_uninterpreted
:
189 case fmt_uninterpreted_32
:
192 value
= (FGR
[fpr
] & 0xFFFFFFFF);
195 case fmt_uninterpreted_64
:
196 case fmt_uninterpreted
:
201 /* Even register numbers only. */
203 printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
204 fpr
+ 1, pr_uword64 ((uword64
) FGR
[fpr
+1]),
205 fpr
, pr_uword64 ((uword64
) FGR
[fpr
]));
207 value
= ((((uword64
) FGR
[fpr
+1]) << 32)
208 | (FGR
[fpr
] & 0xFFFFFFFF));
212 SignalException (ReservedInstruction
, 0);
217 SignalException (ReservedInstruction
, 0);
227 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()");
230 printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n",
231 fpr
, fpu_format_name (fmt
), pr_uword64 (value
), pr_addr (cia
),
239 store_fpr (sim_cpu
*cpu
,
248 printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n",
249 fpr
, fpu_format_name (fmt
), pr_uword64 (value
), pr_addr (cia
),
253 if (SizeFGR () == 64)
257 case fmt_uninterpreted_32
:
258 fmt
= fmt_uninterpreted
;
261 if (STATE_VERBOSE_P (SD
))
263 "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
265 FGR
[fpr
] = (((uword64
) 0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
266 FPR_STATE
[fpr
] = fmt
;
269 case fmt_uninterpreted_64
:
270 fmt
= fmt_uninterpreted
;
271 case fmt_uninterpreted
:
276 FPR_STATE
[fpr
] = fmt
;
280 FPR_STATE
[fpr
] = fmt_unknown
;
289 case fmt_uninterpreted_32
:
290 fmt
= fmt_uninterpreted
;
293 FGR
[fpr
] = (value
& 0xFFFFFFFF);
294 FPR_STATE
[fpr
] = fmt
;
297 case fmt_uninterpreted_64
:
298 fmt
= fmt_uninterpreted
;
299 case fmt_uninterpreted
:
304 /* Even register numbers only. */
305 FGR
[fpr
+1] = (value
>> 32);
306 FGR
[fpr
] = (value
& 0xFFFFFFFF);
307 FPR_STATE
[fpr
+ 1] = fmt
;
308 FPR_STATE
[fpr
] = fmt
;
312 FPR_STATE
[fpr
] = fmt_unknown
;
313 FPR_STATE
[fpr
^ 1] = fmt_unknown
;
314 SignalException (ReservedInstruction
, 0);
319 FPR_STATE
[fpr
] = fmt_unknown
;
320 SignalException (ReservedInstruction
, 0);
324 FPR_STATE
[fpr
] = fmt_unknown
;
331 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
334 printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",
335 fpr
, pr_uword64 (FGR
[fpr
]), fpu_format_name (fmt
));
342 /* CP1 control/status register access functions. */
345 test_fcsr (sim_cpu
*cpu
,
350 cause
= (FCSR
& fcsr_CAUSE_mask
) >> fcsr_CAUSE_shift
;
351 if ((cause
& ((FCSR
& fcsr_ENABLES_mask
) >> fcsr_ENABLES_shift
)) != 0
352 || (cause
& (1 << UO
)))
354 SignalExceptionFPE();
359 value_fcr(sim_cpu
*cpu
,
363 unsigned32 value
= 0;
367 case 0: /* FP Implementation and Revision Register. */
370 case 25: /* FP Condition Codes Register (derived from FCSR). */
371 value
= (FCR31
& fcsr_FCC_mask
) >> fcsr_FCC_shift
;
372 value
= (value
& 0x1) | (value
>> 1); /* Close FCC gap. */
374 case 26: /* FP Exceptions Register (derived from FCSR). */
375 value
= FCR31
& (fcsr_CAUSE_mask
| fcsr_FLAGS_mask
);
377 case 28: /* FP Enables Register (derived from FCSR). */
378 value
= FCR31
& (fcsr_ENABLES_mask
| fcsr_RM_mask
);
379 if ((FCR31
& fcsr_FS
) != 0)
382 case 31: /* FP Control/Status Register (FCSR). */
383 value
= FCR31
& ~fcsr_ZERO_mask
;
387 return (EXTEND32 (value
));
391 store_fcr(sim_cpu
*cpu
,
401 case 25: /* FP Condition Codes Register (stored into FCSR). */
402 v
= (v
<< 1) | (v
& 0x1); /* Adjust for FCC gap. */
403 FCR31
&= ~fcsr_FCC_mask
;
404 FCR31
|= ((v
<< fcsr_FCC_shift
) & fcsr_FCC_mask
);
406 case 26: /* FP Exceptions Register (stored into FCSR). */
407 FCR31
&= ~(fcsr_CAUSE_mask
| fcsr_FLAGS_mask
);
408 FCR31
|= (v
& (fcsr_CAUSE_mask
| fcsr_FLAGS_mask
));
411 case 28: /* FP Enables Register (stored into FCSR). */
412 if ((v
& fenr_FS
) != 0)
416 FCR31
&= (fcsr_FCC_mask
| fcsr_CAUSE_mask
| fcsr_FLAGS_mask
);
417 FCR31
|= (v
& (fcsr_FS
| fcsr_ENABLES_mask
| fcsr_RM_mask
));
420 case 31: /* FP Control/Status Register (FCSR). */
421 FCR31
= v
& ~fcsr_ZERO_mask
;
428 update_fcsr (sim_cpu
*cpu
,
430 sim_fpu_status status
)
432 FCSR
&= ~fcsr_CAUSE_mask
;
436 unsigned int cause
= 0;
438 /* map between sim_fpu codes and MIPS FCSR */
439 if (status
& (sim_fpu_status_invalid_snan
440 | sim_fpu_status_invalid_isi
441 | sim_fpu_status_invalid_idi
442 | sim_fpu_status_invalid_zdz
443 | sim_fpu_status_invalid_imz
444 | sim_fpu_status_invalid_cmp
445 | sim_fpu_status_invalid_sqrt
446 | sim_fpu_status_invalid_cvi
))
448 if (status
& sim_fpu_status_invalid_div0
)
450 if (status
& sim_fpu_status_overflow
)
452 if (status
& sim_fpu_status_underflow
)
454 if (status
& sim_fpu_status_inexact
)
457 /* Implicit clearing of other bits by unimplemented done by callers. */
458 if (status
& sim_fpu_status_unimplemented
)
462 FCSR
|= (cause
<< fcsr_CAUSE_shift
);
463 test_fcsr (cpu
, cia
);
464 FCSR
|= ((cause
& ~(1 << UO
)) << fcsr_FLAGS_shift
);
470 rounding_mode(int rm
)
477 /* Round result to nearest representable value. When two
478 representable values are equally near, round to the value
479 that has a least significant bit of zero (i.e. is even). */
480 round
= sim_fpu_round_near
;
483 /* Round result to the value closest to, and not greater in
484 magnitude than, the result. */
485 round
= sim_fpu_round_zero
;
488 /* Round result to the value closest to, and not less than,
490 round
= sim_fpu_round_up
;
493 /* Round result to the value closest to, and not greater than,
495 round
= sim_fpu_round_down
;
499 fprintf (stderr
, "Bad switch\n");
505 /* When the FS bit is set, MIPS processors return zero for
506 denormalized results and optionally replace denormalized inputs
507 with zero. When FS is clear, some implementation trap on input
508 and/or output, while other perform the operation in hardware. */
509 static sim_fpu_denorm
510 denorm_mode(sim_cpu
*cpu
)
512 sim_fpu_denorm denorm
;
514 /* XXX: FIXME: Eventually should be CPU model dependent. */
516 denorm
= sim_fpu_denorm_zero
;
523 /* Comparison operations. */
525 static sim_fpu_status
526 fp_test(unsigned64 op1
,
535 sim_fpu_status status
= 0;
536 int less
, equal
, unordered
;
538 /* The format type has already been checked: */
543 sim_fpu_32to (&wop1
, op1
);
544 sim_fpu_32to (&wop2
, op2
);
549 sim_fpu_64to (&wop1
, op1
);
550 sim_fpu_64to (&wop2
, op2
);
554 fprintf (stderr
, "Bad switch\n");
558 if (sim_fpu_is_nan (&wop1
) || sim_fpu_is_nan (&wop2
))
560 if ((cond
& (1 << 3)) ||
561 sim_fpu_is_snan (&wop1
) || sim_fpu_is_snan (&wop2
))
562 status
= sim_fpu_status_invalid_snan
;
571 status
|= sim_fpu_abs (&wop1
, &wop1
);
572 status
|= sim_fpu_abs (&wop2
, &wop2
);
574 equal
= sim_fpu_is_eq (&wop1
, &wop2
);
575 less
= !equal
&& sim_fpu_is_lt (&wop1
, &wop2
);
578 *condition
= (((cond
& (1 << 2)) && less
)
579 || ((cond
& (1 << 1)) && equal
)
580 || ((cond
& (1 << 0)) && unordered
));
594 sim_fpu_status status
= 0;
596 /* The format type should already have been checked. The FCSR is
597 updated before the condition codes so that any exceptions will
598 be signalled before the condition codes are changed. */
605 status
= fp_test(op1
, op2
, fmt
, abs
, cond
, &result
);
606 update_fcsr (cpu
, cia
, status
);
612 int result0
, result1
;
613 status
= fp_test(FP_PS_lower (op1
), FP_PS_lower (op2
), fmt_single
,
614 abs
, cond
, &result0
);
615 status
|= fp_test(FP_PS_upper (op1
), FP_PS_upper (op2
), fmt_single
,
616 abs
, cond
, &result1
);
617 update_fcsr (cpu
, cia
, status
);
618 SETFCC (cc
, result0
);
619 SETFCC (cc
+1, result1
);
623 sim_io_eprintf (SD
, "Bad switch\n");
629 /* Basic arithmetic operations. */
632 fp_unary(sim_cpu
*cpu
,
634 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*),
640 sim_fpu_round round
= rounding_mode (GETRM());
641 sim_fpu_denorm denorm
= denorm_mode (cpu
);
642 sim_fpu_status status
= 0;
643 unsigned64 result
= 0;
645 /* The format type has already been checked: */
651 sim_fpu_32to (&wop
, op
);
652 status
|= (*sim_fpu_op
) (&ans
, &wop
);
653 status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
654 sim_fpu_to32 (&res
, &ans
);
661 sim_fpu_64to (&wop
, op
);
662 status
|= (*sim_fpu_op
) (&ans
, &wop
);
663 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
664 sim_fpu_to64 (&res
, &ans
);
670 int status_u
= 0, status_l
= 0;
671 unsigned32 res_u
, res_l
;
672 sim_fpu_32to (&wop
, FP_PS_upper(op
));
673 status_u
|= (*sim_fpu_op
) (&ans
, &wop
);
674 sim_fpu_to32 (&res_u
, &ans
);
675 sim_fpu_32to (&wop
, FP_PS_lower(op
));
676 status_l
|= (*sim_fpu_op
) (&ans
, &wop
);
677 sim_fpu_to32 (&res_l
, &ans
);
678 result
= FP_PS_cat(res_u
, res_l
);
679 status
= status_u
| status_l
;
683 sim_io_eprintf (SD
, "Bad switch\n");
687 update_fcsr (cpu
, cia
, status
);
692 fp_binary(sim_cpu
*cpu
,
694 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
702 sim_fpu_round round
= rounding_mode (GETRM());
703 sim_fpu_denorm denorm
= denorm_mode (cpu
);
704 sim_fpu_status status
= 0;
705 unsigned64 result
= 0;
707 /* The format type has already been checked: */
713 sim_fpu_32to (&wop1
, op1
);
714 sim_fpu_32to (&wop2
, op2
);
715 status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
716 status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
717 sim_fpu_to32 (&res
, &ans
);
724 sim_fpu_64to (&wop1
, op1
);
725 sim_fpu_64to (&wop2
, op2
);
726 status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
727 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
728 sim_fpu_to64 (&res
, &ans
);
734 int status_u
= 0, status_l
= 0;
735 unsigned32 res_u
, res_l
;
736 sim_fpu_32to (&wop1
, FP_PS_upper(op1
));
737 sim_fpu_32to (&wop2
, FP_PS_upper(op2
));
738 status_u
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
739 sim_fpu_to32 (&res_u
, &ans
);
740 sim_fpu_32to (&wop1
, FP_PS_lower(op1
));
741 sim_fpu_32to (&wop2
, FP_PS_lower(op2
));
742 status_l
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
743 sim_fpu_to32 (&res_l
, &ans
);
744 result
= FP_PS_cat(res_u
, res_l
);
745 status
= status_u
| status_l
;
749 sim_io_eprintf (SD
, "Bad switch\n");
753 update_fcsr (cpu
, cia
, status
);
757 /* Common MAC code for single operands (.s or .d), defers setting FCSR. */
758 static sim_fpu_status
759 inner_mac(int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
767 sim_fpu_denorm denorm
,
773 sim_fpu_status status
= 0;
774 sim_fpu_status op_status
;
782 sim_fpu_32to (&wop1
, op1
);
783 sim_fpu_32to (&wop2
, op2
);
784 status
|= sim_fpu_mul (&ans
, &wop1
, &wop2
);
785 if (scale
!= 0 && sim_fpu_is_number (&ans
)) /* number or denorm */
786 ans
.normal_exp
+= scale
;
787 status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
790 sim_fpu_32to (&wop2
, op3
);
791 op_status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
792 op_status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
797 op_status
= sim_fpu_neg (&ans
, &wop1
);
798 op_status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
801 sim_fpu_to32 (&res
, &ans
);
808 sim_fpu_64to (&wop1
, op1
);
809 sim_fpu_64to (&wop2
, op2
);
810 status
|= sim_fpu_mul (&ans
, &wop1
, &wop2
);
811 if (scale
!= 0 && sim_fpu_is_number (&ans
)) /* number or denorm */
812 ans
.normal_exp
+= scale
;
813 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
816 sim_fpu_64to (&wop2
, op3
);
817 op_status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
818 op_status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
823 op_status
= sim_fpu_neg (&ans
, &wop1
);
824 op_status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
827 sim_fpu_to64 (&res
, &ans
);
832 fprintf (stderr
, "Bad switch\n");
839 /* Common implementation of madd, nmadd, msub, nmsub that does
840 intermediate rounding per spec. Also used for recip2 and rsqrt2,
841 which are transformed into equivalent nmsub operations. The scale
842 argument is an adjustment to the exponent of the intermediate
843 product op1*op2. It is currently non-zero for rsqrt2 (-1), which
844 requires an effective division by 2. */
848 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
856 sim_fpu_round round
= rounding_mode (GETRM());
857 sim_fpu_denorm denorm
= denorm_mode (cpu
);
858 sim_fpu_status status
= 0;
859 unsigned64 result
= 0;
861 /* The format type has already been checked: */
866 status
= inner_mac(sim_fpu_op
, op1
, op2
, op3
, scale
,
867 negate
, fmt
, round
, denorm
, &result
);
871 int status_u
, status_l
;
872 unsigned64 result_u
, result_l
;
873 status_u
= inner_mac(sim_fpu_op
, FP_PS_upper(op1
), FP_PS_upper(op2
),
874 FP_PS_upper(op3
), scale
, negate
, fmt_single
,
875 round
, denorm
, &result_u
);
876 status_l
= inner_mac(sim_fpu_op
, FP_PS_lower(op1
), FP_PS_lower(op2
),
877 FP_PS_lower(op3
), scale
, negate
, fmt_single
,
878 round
, denorm
, &result_l
);
879 result
= FP_PS_cat(result_u
, result_l
);
880 status
= status_u
| status_l
;
884 sim_io_eprintf (SD
, "Bad switch\n");
888 update_fcsr (cpu
, cia
, status
);
892 /* Common rsqrt code for single operands (.s or .d), intermediate rounding. */
893 static sim_fpu_status
894 inner_rsqrt(unsigned64 op1
,
897 sim_fpu_denorm denorm
,
902 sim_fpu_status status
= 0;
903 sim_fpu_status op_status
;
911 sim_fpu_32to (&wop1
, op1
);
912 status
|= sim_fpu_sqrt (&ans
, &wop1
);
913 status
|= sim_fpu_round_32 (&ans
, status
, round
);
915 op_status
= sim_fpu_inv (&ans
, &wop1
);
916 op_status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
917 sim_fpu_to32 (&res
, &ans
);
925 sim_fpu_64to (&wop1
, op1
);
926 status
|= sim_fpu_sqrt (&ans
, &wop1
);
927 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
929 op_status
= sim_fpu_inv (&ans
, &wop1
);
930 op_status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
931 sim_fpu_to64 (&res
, &ans
);
937 fprintf (stderr
, "Bad switch\n");
945 fp_inv_sqrt(sim_cpu
*cpu
,
950 sim_fpu_round round
= rounding_mode (GETRM());
951 sim_fpu_round denorm
= denorm_mode (cpu
);
952 sim_fpu_status status
= 0;
953 unsigned64 result
= 0;
955 /* The format type has already been checked: */
960 status
= inner_rsqrt (op1
, fmt
, round
, denorm
, &result
);
964 int status_u
, status_l
;
965 unsigned64 result_u
, result_l
;
966 status_u
= inner_rsqrt (FP_PS_upper(op1
), fmt_single
, round
, denorm
,
968 status_l
= inner_rsqrt (FP_PS_lower(op1
), fmt_single
, round
, denorm
,
970 result
= FP_PS_cat(result_u
, result_l
);
971 status
= status_u
| status_l
;
975 sim_io_eprintf (SD
, "Bad switch\n");
979 update_fcsr (cpu
, cia
, status
);
990 return fp_unary(cpu
, cia
, &sim_fpu_abs
, op
, fmt
);
999 return fp_unary(cpu
, cia
, &sim_fpu_neg
, op
, fmt
);
1003 fp_add(sim_cpu
*cpu
,
1009 return fp_binary(cpu
, cia
, &sim_fpu_add
, op1
, op2
, fmt
);
1013 fp_sub(sim_cpu
*cpu
,
1019 return fp_binary(cpu
, cia
, &sim_fpu_sub
, op1
, op2
, fmt
);
1023 fp_mul(sim_cpu
*cpu
,
1029 return fp_binary(cpu
, cia
, &sim_fpu_mul
, op1
, op2
, fmt
);
1033 fp_div(sim_cpu
*cpu
,
1039 return fp_binary(cpu
, cia
, &sim_fpu_div
, op1
, op2
, fmt
);
1043 fp_recip(sim_cpu
*cpu
,
1048 return fp_unary(cpu
, cia
, &sim_fpu_inv
, op
, fmt
);
1052 fp_sqrt(sim_cpu
*cpu
,
1057 return fp_unary(cpu
, cia
, &sim_fpu_sqrt
, op
, fmt
);
1061 fp_rsqrt(sim_cpu
*cpu
,
1066 return fp_inv_sqrt(cpu
, cia
, op
, fmt
);
1070 fp_madd(sim_cpu
*cpu
,
1077 return fp_mac(cpu
, cia
, &sim_fpu_add
, op1
, op2
, op3
, 0, 0, fmt
);
1081 fp_msub(sim_cpu
*cpu
,
1088 return fp_mac(cpu
, cia
, &sim_fpu_sub
, op1
, op2
, op3
, 0, 0, fmt
);
1092 fp_nmadd(sim_cpu
*cpu
,
1099 return fp_mac(cpu
, cia
, &sim_fpu_add
, op1
, op2
, op3
, 0, 1, fmt
);
1103 fp_nmsub(sim_cpu
*cpu
,
1110 return fp_mac(cpu
, cia
, &sim_fpu_sub
, op1
, op2
, op3
, 0, 1, fmt
);
1114 /* MIPS-3D ASE operations. */
1116 /* Variant of fp_binary for *r.ps MIPS-3D operations. */
1118 fp_binary_r(sim_cpu
*cpu
,
1120 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
1127 sim_fpu_round round
= rounding_mode (GETRM ());
1128 sim_fpu_denorm denorm
= denorm_mode (cpu
);
1129 sim_fpu_status status_u
, status_l
;
1131 unsigned32 res_u
, res_l
;
1133 /* The format must be fmt_ps. */
1135 sim_fpu_32to (&wop1
, FP_PS_upper (op1
));
1136 sim_fpu_32to (&wop2
, FP_PS_lower (op1
));
1137 status_u
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
1138 status_u
|= sim_fpu_round_32 (&ans
, round
, denorm
);
1139 sim_fpu_to32 (&res_u
, &ans
);
1141 sim_fpu_32to (&wop1
, FP_PS_upper (op2
));
1142 sim_fpu_32to (&wop2
, FP_PS_lower (op2
));
1143 status_l
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
1144 status_l
|= sim_fpu_round_32 (&ans
, round
, denorm
);
1145 sim_fpu_to32 (&res_l
, &ans
);
1146 result
= FP_PS_cat (res_u
, res_l
);
1148 update_fcsr (cpu
, cia
, status_u
| status_l
);
1153 fp_add_r(sim_cpu
*cpu
,
1159 return fp_binary_r (cpu
, cia
, &sim_fpu_add
, op1
, op2
);
1163 fp_mul_r(sim_cpu
*cpu
,
1169 return fp_binary_r (cpu
, cia
, &sim_fpu_mul
, op1
, op2
);
1172 #define NR_FRAC_GUARD (60)
1173 #define IMPLICIT_1 LSBIT64 (NR_FRAC_GUARD)
1176 fpu_inv1(sim_fpu
*f
, const sim_fpu
*l
)
1178 static const sim_fpu sim_fpu_one
= {
1179 sim_fpu_class_number
, 0, IMPLICIT_1
, 0
1184 if (sim_fpu_is_zero (l
))
1188 return sim_fpu_status_invalid_div0
;
1190 if (sim_fpu_is_infinity (l
))
1196 status
|= sim_fpu_div (f
, &sim_fpu_one
, l
);
1201 fpu_inv1_32(sim_fpu
*f
, const sim_fpu
*l
)
1203 if (sim_fpu_is_zero (l
))
1207 return sim_fpu_status_invalid_div0
;
1209 return fpu_inv1 (f
, l
);
1213 fpu_inv1_64(sim_fpu
*f
, const sim_fpu
*l
)
1215 if (sim_fpu_is_zero (l
))
1219 return sim_fpu_status_invalid_div0
;
1221 return fpu_inv1 (f
, l
);
1225 fp_recip1(sim_cpu
*cpu
,
1234 return fp_unary (cpu
, cia
, &fpu_inv1_32
, op
, fmt
);
1236 return fp_unary (cpu
, cia
, &fpu_inv1_64
, op
, fmt
);
1242 fp_recip2(sim_cpu
*cpu
,
1248 static const unsigned64 one_single
= UNSIGNED64 (0x3F800000);
1249 static const unsigned64 one_double
= UNSIGNED64 (0x3FF0000000000000);
1250 static const unsigned64 one_ps
= (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000));
1253 /* Implemented as nmsub fd, 1, fs, ft. */
1256 case fmt_single
: one
= one_single
; break;
1257 case fmt_double
: one
= one_double
; break;
1258 case fmt_ps
: one
= one_ps
; break;
1259 default: one
= 0; abort ();
1261 return fp_mac (cpu
, cia
, &sim_fpu_sub
, op1
, op2
, one
, 0, 1, fmt
);
1265 fpu_inv_sqrt1(sim_fpu
*f
, const sim_fpu
*l
)
1267 static const sim_fpu sim_fpu_one
= {
1268 sim_fpu_class_number
, 0, IMPLICIT_1
, 0
1273 if (sim_fpu_is_zero (l
))
1277 return sim_fpu_status_invalid_div0
;
1279 if (sim_fpu_is_infinity (l
))
1283 f
->class = sim_fpu_class_zero
;
1289 status
= sim_fpu_status_invalid_sqrt
;
1293 status
|= sim_fpu_sqrt (&t
, l
);
1294 status
|= sim_fpu_div (f
, &sim_fpu_one
, &t
);
1299 fpu_inv_sqrt1_32(sim_fpu
*f
, const sim_fpu
*l
)
1301 if (sim_fpu_is_zero (l
))
1305 return sim_fpu_status_invalid_div0
;
1307 return fpu_inv_sqrt1 (f
, l
);
1311 fpu_inv_sqrt1_64(sim_fpu
*f
, const sim_fpu
*l
)
1313 if (sim_fpu_is_zero (l
))
1317 return sim_fpu_status_invalid_div0
;
1319 return fpu_inv_sqrt1 (f
, l
);
1323 fp_rsqrt1(sim_cpu
*cpu
,
1332 return fp_unary (cpu
, cia
, &fpu_inv_sqrt1_32
, op
, fmt
);
1334 return fp_unary (cpu
, cia
, &fpu_inv_sqrt1_64
, op
, fmt
);
1340 fp_rsqrt2(sim_cpu
*cpu
,
1346 static const unsigned64 half_single
= UNSIGNED64 (0x3F000000);
1347 static const unsigned64 half_double
= UNSIGNED64 (0x3FE0000000000000);
1348 static const unsigned64 half_ps
= (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000));
1351 /* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is
1352 done by scaling the exponent during multiply. */
1355 case fmt_single
: half
= half_single
; break;
1356 case fmt_double
: half
= half_double
; break;
1357 case fmt_ps
: half
= half_ps
; break;
1358 default: half
= 0; abort ();
1360 return fp_mac (cpu
, cia
, &sim_fpu_sub
, op1
, op2
, half
, -1, 1, fmt
);
1364 /* Conversion operations. */
1367 convert (sim_cpu
*cpu
,
1375 sim_fpu_round round
= rounding_mode (rm
);
1376 sim_fpu_denorm denorm
= denorm_mode (cpu
);
1377 unsigned32 result32
;
1378 unsigned64 result64
;
1379 sim_fpu_status status
= 0;
1381 /* Convert the input to sim_fpu internal format */
1385 sim_fpu_64to (&wop
, op
);
1388 sim_fpu_32to (&wop
, op
);
1391 status
= sim_fpu_i32to (&wop
, op
, round
);
1394 status
= sim_fpu_i64to (&wop
, op
, round
);
1397 sim_io_eprintf (SD
, "Bad switch\n");
1401 /* Convert sim_fpu format into the output */
1402 /* The value WOP is converted to the destination format, rounding
1403 using mode RM. When the destination is a fixed-point format, then
1404 a source value of Infinity, NaN or one which would round to an
1405 integer outside the fixed point range then an IEEE Invalid Operation
1406 condition is raised. Not used if destination format is PS. */
1410 status
|= sim_fpu_round_32 (&wop
, round
, denorm
);
1411 /* For a NaN, normalize mantissa bits (cvt.s.d can't preserve them) */
1412 if (sim_fpu_is_qnan (&wop
))
1414 sim_fpu_to32 (&result32
, &wop
);
1415 result64
= result32
;
1418 status
|= sim_fpu_round_64 (&wop
, round
, denorm
);
1419 /* For a NaN, normalize mantissa bits (make cvt.d.s consistent) */
1420 if (sim_fpu_is_qnan (&wop
))
1422 sim_fpu_to64 (&result64
, &wop
);
1425 status
|= sim_fpu_to32i (&result32
, &wop
, round
);
1426 result64
= result32
;
1429 status
|= sim_fpu_to64i (&result64
, &wop
, round
);
1433 sim_io_eprintf (SD
, "Bad switch\n");
1437 update_fcsr (cpu
, cia
, status
);
1442 ps_lower(sim_cpu
*cpu
,
1446 return FP_PS_lower (op
);
1450 ps_upper(sim_cpu
*cpu
,
1454 return FP_PS_upper(op
);
1458 pack_ps(sim_cpu
*cpu
,
1464 unsigned64 result
= 0;
1466 /* The registers must specify FPRs valid for operands of type
1467 "fmt". If they are not valid, the result is undefined. */
1469 /* The format type should already have been checked: */
1475 unsigned32 res_u
, res_l
;
1476 sim_fpu_32to (&wop
, op1
);
1477 sim_fpu_to32 (&res_u
, &wop
);
1478 sim_fpu_32to (&wop
, op2
);
1479 sim_fpu_to32 (&res_l
, &wop
);
1480 result
= FP_PS_cat(res_u
, res_l
);
1484 sim_io_eprintf (SD
, "Bad switch\n");
1492 convert_ps (sim_cpu
*cpu
,
1499 sim_fpu wop_u
, wop_l
;
1500 sim_fpu_round round
= rounding_mode (rm
);
1501 sim_fpu_denorm denorm
= denorm_mode (cpu
);
1502 unsigned32 res_u
, res_l
;
1504 sim_fpu_status status_u
= 0, status_l
= 0;
1506 /* As convert, but used only for paired values (formats PS, PW) */
1508 /* Convert the input to sim_fpu internal format */
1511 case fmt_word
: /* fmt_pw */
1512 sim_fpu_i32to (&wop_u
, (op
>> 32) & (unsigned)0xFFFFFFFF, round
);
1513 sim_fpu_i32to (&wop_l
, op
& (unsigned)0xFFFFFFFF, round
);
1516 sim_fpu_32to (&wop_u
, FP_PS_upper(op
));
1517 sim_fpu_32to (&wop_l
, FP_PS_lower(op
));
1520 sim_io_eprintf (SD
, "Bad switch\n");
1524 /* Convert sim_fpu format into the output */
1527 case fmt_word
: /* fmt_pw */
1528 status_u
|= sim_fpu_to32i (&res_u
, &wop_u
, round
);
1529 status_l
|= sim_fpu_to32i (&res_l
, &wop_l
, round
);
1530 result
= (((unsigned64
)res_u
) << 32) | (unsigned64
)res_l
;
1533 status_u
|= sim_fpu_round_32 (&wop_u
, 0, round
);
1534 status_l
|= sim_fpu_round_32 (&wop_l
, 0, round
);
1535 sim_fpu_to32 (&res_u
, &wop_u
);
1536 sim_fpu_to32 (&res_l
, &wop_l
);
1537 result
= FP_PS_cat(res_u
, res_l
);
1541 sim_io_eprintf (SD
, "Bad switch\n");
1545 update_fcsr (cpu
, cia
, status_u
| status_l
);
1550 fpu_format_name (FP_formats fmt
)
1566 case fmt_uninterpreted
:
1567 return "<uninterpreted>";
1568 case fmt_uninterpreted_32
:
1569 return "<uninterpreted_32>";
1570 case fmt_uninterpreted_64
:
1571 return "<uninterpreted_64>";
1573 return "<format error>";
1579 fpu_rounding_mode_name (int rm
)
1592 return "<rounding mode error>";