2 /* MIPS Simulator FPU (CoProcessor 1) support.
3 Copyright (C) 2002-2021 Free Software Foundation, Inc.
4 Originally created by Cygnus Solutions. Extensive modifications,
5 including paired-single operation support and MIPS-3D support
6 contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
9 This file is part of GDB, the GNU debugger.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* XXX: The following notice should be removed as soon as is practical: */
25 /* Floating Point Support for gdb MIPS simulators
27 This file is part of the MIPS sim
29 THIS SOFTWARE IS NOT COPYRIGHTED
32 Cygnus offers the following for use in the public domain. Cygnus
33 makes no warranty with regard to the software or it's performance
34 and the user accepts the software "AS IS" with all faults.
36 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
37 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
38 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
40 (Originally, this code was in interp.c)
47 /* Within cp1.c we refer to sim_cpu directly. */
49 #define SD CPU_STATE(cpu)
51 /*-- FPU support routines ---------------------------------------------------*/
53 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
54 formats conform to ANSI/IEEE Std 754-1985.
56 SINGLE precision floating:
57 seeeeeeeefffffffffffffffffffffff
62 SINGLE precision fixed:
63 siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
67 DOUBLE precision floating:
68 seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
73 DOUBLE precision fixed:
74 siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
78 PAIRED SINGLE precision floating:
79 seeeeeeeefffffffffffffffffffffffseeeeeeeefffffffffffffffffffffff
84 Note: upper = [63..32], lower = [31..0]
87 /* Extract packed single values: */
88 #define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF)
89 #define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF)
90 #define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \
91 | (unsigned64)((l) & 0xFFFFFFFF))
93 /* Explicit QNaN values. */
94 #define FPQNaN_SINGLE (0x7FBFFFFF)
95 #define FPQNaN_WORD (0x7FFFFFFF)
96 #define FPQNaN_DOUBLE (UNSIGNED64 (0x7FF7FFFFFFFFFFFF))
97 #define FPQNaN_LONG (UNSIGNED64 (0x7FFFFFFFFFFFFFFF))
98 #define FPQNaN_PS (FP_PS_cat (FPQNaN_SINGLE, FPQNaN_SINGLE))
100 static const char *fpu_format_name (FP_formats fmt
);
102 static const char *fpu_rounding_mode_name (int rm
);
106 value_fpr (sim_cpu
*cpu
,
114 /* Treat unused register values, as fixed-point 64bit values. */
115 if (fmt
== fmt_unknown
)
118 /* If request to read data as "unknown", then use the current
120 fmt
= FPR_STATE
[fpr
];
126 /* For values not yet accessed, set to the desired format. */
127 if (fmt
< fmt_uninterpreted
)
129 if (FPR_STATE
[fpr
] == fmt_uninterpreted
)
131 FPR_STATE
[fpr
] = fmt
;
133 printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr
,
134 fpu_format_name (fmt
));
137 else if (fmt
!= FPR_STATE
[fpr
])
139 sim_io_eprintf (SD
, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
140 fpr
, fpu_format_name (FPR_STATE
[fpr
]),
141 fpu_format_name (fmt
), pr_addr (cia
));
142 FPR_STATE
[fpr
] = fmt_unknown
;
146 if (FPR_STATE
[fpr
] == fmt_unknown
)
148 /* Set QNaN value: */
151 case fmt_single
: value
= FPQNaN_SINGLE
; break;
152 case fmt_double
: value
= FPQNaN_DOUBLE
; break;
153 case fmt_word
: value
= FPQNaN_WORD
; break;
154 case fmt_long
: value
= FPQNaN_LONG
; break;
155 case fmt_ps
: value
= FPQNaN_PS
; break;
156 default: err
= -1; break;
159 else if (SizeFGR () == 64)
163 case fmt_uninterpreted_32
:
166 value
= (FGR
[fpr
] & 0xFFFFFFFF);
169 case fmt_uninterpreted_64
:
170 case fmt_uninterpreted
:
186 case fmt_uninterpreted_32
:
189 value
= (FGR
[fpr
] & 0xFFFFFFFF);
192 case fmt_uninterpreted_64
:
193 case fmt_uninterpreted
:
198 /* Even register numbers only. */
200 printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
201 fpr
+ 1, pr_uword64 ((uword64
) FGR
[fpr
+1]),
202 fpr
, pr_uword64 ((uword64
) FGR
[fpr
]));
204 value
= ((((uword64
) FGR
[fpr
+1]) << 32)
205 | (FGR
[fpr
] & 0xFFFFFFFF));
209 SignalException (ReservedInstruction
, 0);
214 SignalException (ReservedInstruction
, 0);
224 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()");
227 printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n",
228 fpr
, fpu_format_name (fmt
), pr_uword64 (value
), pr_addr (cia
),
236 store_fpr (sim_cpu
*cpu
,
245 printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n",
246 fpr
, fpu_format_name (fmt
), pr_uword64 (value
), pr_addr (cia
),
250 if (SizeFGR () == 64)
254 case fmt_uninterpreted_32
:
255 fmt
= fmt_uninterpreted
;
258 if (STATE_VERBOSE_P (SD
))
260 "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
262 FGR
[fpr
] = (((uword64
) 0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
263 FPR_STATE
[fpr
] = fmt
;
266 case fmt_uninterpreted_64
:
267 fmt
= fmt_uninterpreted
;
268 case fmt_uninterpreted
:
273 FPR_STATE
[fpr
] = fmt
;
277 FPR_STATE
[fpr
] = fmt_unknown
;
286 case fmt_uninterpreted_32
:
287 fmt
= fmt_uninterpreted
;
290 FGR
[fpr
] = (value
& 0xFFFFFFFF);
291 FPR_STATE
[fpr
] = fmt
;
294 case fmt_uninterpreted_64
:
295 fmt
= fmt_uninterpreted
;
296 case fmt_uninterpreted
:
301 /* Even register numbers only. */
302 FGR
[fpr
+1] = (value
>> 32);
303 FGR
[fpr
] = (value
& 0xFFFFFFFF);
304 FPR_STATE
[fpr
+ 1] = fmt
;
305 FPR_STATE
[fpr
] = fmt
;
309 FPR_STATE
[fpr
] = fmt_unknown
;
310 FPR_STATE
[fpr
^ 1] = fmt_unknown
;
311 SignalException (ReservedInstruction
, 0);
316 FPR_STATE
[fpr
] = fmt_unknown
;
317 SignalException (ReservedInstruction
, 0);
321 FPR_STATE
[fpr
] = fmt_unknown
;
328 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
331 printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",
332 fpr
, pr_uword64 (FGR
[fpr
]), fpu_format_name (fmt
));
339 /* CP1 control/status register access functions. */
342 test_fcsr (sim_cpu
*cpu
,
347 cause
= (FCSR
& fcsr_CAUSE_mask
) >> fcsr_CAUSE_shift
;
348 if ((cause
& ((FCSR
& fcsr_ENABLES_mask
) >> fcsr_ENABLES_shift
)) != 0
349 || (cause
& (1 << UO
)))
351 SignalExceptionFPE();
356 value_fcr(sim_cpu
*cpu
,
360 unsigned32 value
= 0;
364 case 0: /* FP Implementation and Revision Register. */
367 case 25: /* FP Condition Codes Register (derived from FCSR). */
368 value
= (FCR31
& fcsr_FCC_mask
) >> fcsr_FCC_shift
;
369 value
= (value
& 0x1) | (value
>> 1); /* Close FCC gap. */
371 case 26: /* FP Exceptions Register (derived from FCSR). */
372 value
= FCR31
& (fcsr_CAUSE_mask
| fcsr_FLAGS_mask
);
374 case 28: /* FP Enables Register (derived from FCSR). */
375 value
= FCR31
& (fcsr_ENABLES_mask
| fcsr_RM_mask
);
376 if ((FCR31
& fcsr_FS
) != 0)
379 case 31: /* FP Control/Status Register (FCSR). */
380 value
= FCR31
& ~fcsr_ZERO_mask
;
384 return (EXTEND32 (value
));
388 store_fcr(sim_cpu
*cpu
,
398 case 25: /* FP Condition Codes Register (stored into FCSR). */
399 v
= (v
<< 1) | (v
& 0x1); /* Adjust for FCC gap. */
400 FCR31
&= ~fcsr_FCC_mask
;
401 FCR31
|= ((v
<< fcsr_FCC_shift
) & fcsr_FCC_mask
);
403 case 26: /* FP Exceptions Register (stored into FCSR). */
404 FCR31
&= ~(fcsr_CAUSE_mask
| fcsr_FLAGS_mask
);
405 FCR31
|= (v
& (fcsr_CAUSE_mask
| fcsr_FLAGS_mask
));
408 case 28: /* FP Enables Register (stored into FCSR). */
409 if ((v
& fenr_FS
) != 0)
413 FCR31
&= (fcsr_FCC_mask
| fcsr_CAUSE_mask
| fcsr_FLAGS_mask
);
414 FCR31
|= (v
& (fcsr_FS
| fcsr_ENABLES_mask
| fcsr_RM_mask
));
417 case 31: /* FP Control/Status Register (FCSR). */
418 FCR31
= v
& ~fcsr_ZERO_mask
;
425 update_fcsr (sim_cpu
*cpu
,
427 sim_fpu_status status
)
429 FCSR
&= ~fcsr_CAUSE_mask
;
433 unsigned int cause
= 0;
435 /* map between sim_fpu codes and MIPS FCSR */
436 if (status
& (sim_fpu_status_invalid_snan
437 | sim_fpu_status_invalid_isi
438 | sim_fpu_status_invalid_idi
439 | sim_fpu_status_invalid_zdz
440 | sim_fpu_status_invalid_imz
441 | sim_fpu_status_invalid_cmp
442 | sim_fpu_status_invalid_sqrt
443 | sim_fpu_status_invalid_cvi
))
445 if (status
& sim_fpu_status_invalid_div0
)
447 if (status
& sim_fpu_status_overflow
)
449 if (status
& sim_fpu_status_underflow
)
451 if (status
& sim_fpu_status_inexact
)
454 /* Implicit clearing of other bits by unimplemented done by callers. */
455 if (status
& sim_fpu_status_unimplemented
)
459 FCSR
|= (cause
<< fcsr_CAUSE_shift
);
460 test_fcsr (cpu
, cia
);
461 FCSR
|= ((cause
& ~(1 << UO
)) << fcsr_FLAGS_shift
);
467 rounding_mode(int rm
)
474 /* Round result to nearest representable value. When two
475 representable values are equally near, round to the value
476 that has a least significant bit of zero (i.e. is even). */
477 round
= sim_fpu_round_near
;
480 /* Round result to the value closest to, and not greater in
481 magnitude than, the result. */
482 round
= sim_fpu_round_zero
;
485 /* Round result to the value closest to, and not less than,
487 round
= sim_fpu_round_up
;
490 /* Round result to the value closest to, and not greater than,
492 round
= sim_fpu_round_down
;
496 fprintf (stderr
, "Bad switch\n");
502 /* When the FS bit is set, MIPS processors return zero for
503 denormalized results and optionally replace denormalized inputs
504 with zero. When FS is clear, some implementation trap on input
505 and/or output, while other perform the operation in hardware. */
506 static sim_fpu_denorm
507 denorm_mode(sim_cpu
*cpu
)
509 sim_fpu_denorm denorm
;
511 /* XXX: FIXME: Eventually should be CPU model dependent. */
513 denorm
= sim_fpu_denorm_zero
;
520 /* Comparison operations. */
522 static sim_fpu_status
523 fp_test(unsigned64 op1
,
532 sim_fpu_status status
= 0;
533 int less
, equal
, unordered
;
535 /* The format type has already been checked: */
540 sim_fpu_32to (&wop1
, op1
);
541 sim_fpu_32to (&wop2
, op2
);
546 sim_fpu_64to (&wop1
, op1
);
547 sim_fpu_64to (&wop2
, op2
);
551 fprintf (stderr
, "Bad switch\n");
555 if (sim_fpu_is_nan (&wop1
) || sim_fpu_is_nan (&wop2
))
557 if ((cond
& (1 << 3)) ||
558 sim_fpu_is_snan (&wop1
) || sim_fpu_is_snan (&wop2
))
559 status
= sim_fpu_status_invalid_snan
;
568 status
|= sim_fpu_abs (&wop1
, &wop1
);
569 status
|= sim_fpu_abs (&wop2
, &wop2
);
571 equal
= sim_fpu_is_eq (&wop1
, &wop2
);
572 less
= !equal
&& sim_fpu_is_lt (&wop1
, &wop2
);
575 *condition
= (((cond
& (1 << 2)) && less
)
576 || ((cond
& (1 << 1)) && equal
)
577 || ((cond
& (1 << 0)) && unordered
));
591 sim_fpu_status status
= 0;
593 /* The format type should already have been checked. The FCSR is
594 updated before the condition codes so that any exceptions will
595 be signalled before the condition codes are changed. */
602 status
= fp_test(op1
, op2
, fmt
, abs
, cond
, &result
);
603 update_fcsr (cpu
, cia
, status
);
609 int result0
, result1
;
610 status
= fp_test(FP_PS_lower (op1
), FP_PS_lower (op2
), fmt_single
,
611 abs
, cond
, &result0
);
612 status
|= fp_test(FP_PS_upper (op1
), FP_PS_upper (op2
), fmt_single
,
613 abs
, cond
, &result1
);
614 update_fcsr (cpu
, cia
, status
);
615 SETFCC (cc
, result0
);
616 SETFCC (cc
+1, result1
);
620 sim_io_eprintf (SD
, "Bad switch\n");
626 /* Basic arithmetic operations. */
629 fp_unary(sim_cpu
*cpu
,
631 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*),
637 sim_fpu_round round
= rounding_mode (GETRM());
638 sim_fpu_denorm denorm
= denorm_mode (cpu
);
639 sim_fpu_status status
= 0;
640 unsigned64 result
= 0;
642 /* The format type has already been checked: */
648 sim_fpu_32to (&wop
, op
);
649 status
|= (*sim_fpu_op
) (&ans
, &wop
);
650 status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
651 sim_fpu_to32 (&res
, &ans
);
658 sim_fpu_64to (&wop
, op
);
659 status
|= (*sim_fpu_op
) (&ans
, &wop
);
660 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
661 sim_fpu_to64 (&res
, &ans
);
667 int status_u
= 0, status_l
= 0;
668 unsigned32 res_u
, res_l
;
669 sim_fpu_32to (&wop
, FP_PS_upper(op
));
670 status_u
|= (*sim_fpu_op
) (&ans
, &wop
);
671 sim_fpu_to32 (&res_u
, &ans
);
672 sim_fpu_32to (&wop
, FP_PS_lower(op
));
673 status_l
|= (*sim_fpu_op
) (&ans
, &wop
);
674 sim_fpu_to32 (&res_l
, &ans
);
675 result
= FP_PS_cat(res_u
, res_l
);
676 status
= status_u
| status_l
;
680 sim_io_eprintf (SD
, "Bad switch\n");
684 update_fcsr (cpu
, cia
, status
);
689 fp_binary(sim_cpu
*cpu
,
691 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
699 sim_fpu_round round
= rounding_mode (GETRM());
700 sim_fpu_denorm denorm
= denorm_mode (cpu
);
701 sim_fpu_status status
= 0;
702 unsigned64 result
= 0;
704 /* The format type has already been checked: */
710 sim_fpu_32to (&wop1
, op1
);
711 sim_fpu_32to (&wop2
, op2
);
712 status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
713 status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
714 sim_fpu_to32 (&res
, &ans
);
721 sim_fpu_64to (&wop1
, op1
);
722 sim_fpu_64to (&wop2
, op2
);
723 status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
724 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
725 sim_fpu_to64 (&res
, &ans
);
731 int status_u
= 0, status_l
= 0;
732 unsigned32 res_u
, res_l
;
733 sim_fpu_32to (&wop1
, FP_PS_upper(op1
));
734 sim_fpu_32to (&wop2
, FP_PS_upper(op2
));
735 status_u
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
736 sim_fpu_to32 (&res_u
, &ans
);
737 sim_fpu_32to (&wop1
, FP_PS_lower(op1
));
738 sim_fpu_32to (&wop2
, FP_PS_lower(op2
));
739 status_l
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
740 sim_fpu_to32 (&res_l
, &ans
);
741 result
= FP_PS_cat(res_u
, res_l
);
742 status
= status_u
| status_l
;
746 sim_io_eprintf (SD
, "Bad switch\n");
750 update_fcsr (cpu
, cia
, status
);
754 /* Common MAC code for single operands (.s or .d), defers setting FCSR. */
755 static sim_fpu_status
756 inner_mac(int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
764 sim_fpu_denorm denorm
,
770 sim_fpu_status status
= 0;
771 sim_fpu_status op_status
;
779 sim_fpu_32to (&wop1
, op1
);
780 sim_fpu_32to (&wop2
, op2
);
781 status
|= sim_fpu_mul (&ans
, &wop1
, &wop2
);
782 if (scale
!= 0 && sim_fpu_is_number (&ans
)) /* number or denorm */
783 ans
.normal_exp
+= scale
;
784 status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
787 sim_fpu_32to (&wop2
, op3
);
788 op_status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
789 op_status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
794 op_status
= sim_fpu_neg (&ans
, &wop1
);
795 op_status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
798 sim_fpu_to32 (&res
, &ans
);
805 sim_fpu_64to (&wop1
, op1
);
806 sim_fpu_64to (&wop2
, op2
);
807 status
|= sim_fpu_mul (&ans
, &wop1
, &wop2
);
808 if (scale
!= 0 && sim_fpu_is_number (&ans
)) /* number or denorm */
809 ans
.normal_exp
+= scale
;
810 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
813 sim_fpu_64to (&wop2
, op3
);
814 op_status
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
815 op_status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
820 op_status
= sim_fpu_neg (&ans
, &wop1
);
821 op_status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
824 sim_fpu_to64 (&res
, &ans
);
829 fprintf (stderr
, "Bad switch\n");
836 /* Common implementation of madd, nmadd, msub, nmsub that does
837 intermediate rounding per spec. Also used for recip2 and rsqrt2,
838 which are transformed into equivalent nmsub operations. The scale
839 argument is an adjustment to the exponent of the intermediate
840 product op1*op2. It is currently non-zero for rsqrt2 (-1), which
841 requires an effective division by 2. */
845 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
853 sim_fpu_round round
= rounding_mode (GETRM());
854 sim_fpu_denorm denorm
= denorm_mode (cpu
);
855 sim_fpu_status status
= 0;
856 unsigned64 result
= 0;
858 /* The format type has already been checked: */
863 status
= inner_mac(sim_fpu_op
, op1
, op2
, op3
, scale
,
864 negate
, fmt
, round
, denorm
, &result
);
868 int status_u
, status_l
;
869 unsigned64 result_u
, result_l
;
870 status_u
= inner_mac(sim_fpu_op
, FP_PS_upper(op1
), FP_PS_upper(op2
),
871 FP_PS_upper(op3
), scale
, negate
, fmt_single
,
872 round
, denorm
, &result_u
);
873 status_l
= inner_mac(sim_fpu_op
, FP_PS_lower(op1
), FP_PS_lower(op2
),
874 FP_PS_lower(op3
), scale
, negate
, fmt_single
,
875 round
, denorm
, &result_l
);
876 result
= FP_PS_cat(result_u
, result_l
);
877 status
= status_u
| status_l
;
881 sim_io_eprintf (SD
, "Bad switch\n");
885 update_fcsr (cpu
, cia
, status
);
889 /* Common rsqrt code for single operands (.s or .d), intermediate rounding. */
890 static sim_fpu_status
891 inner_rsqrt(unsigned64 op1
,
894 sim_fpu_denorm denorm
,
899 sim_fpu_status status
= 0;
900 sim_fpu_status op_status
;
908 sim_fpu_32to (&wop1
, op1
);
909 status
|= sim_fpu_sqrt (&ans
, &wop1
);
910 status
|= sim_fpu_round_32 (&ans
, status
, round
);
912 op_status
= sim_fpu_inv (&ans
, &wop1
);
913 op_status
|= sim_fpu_round_32 (&ans
, round
, denorm
);
914 sim_fpu_to32 (&res
, &ans
);
922 sim_fpu_64to (&wop1
, op1
);
923 status
|= sim_fpu_sqrt (&ans
, &wop1
);
924 status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
926 op_status
= sim_fpu_inv (&ans
, &wop1
);
927 op_status
|= sim_fpu_round_64 (&ans
, round
, denorm
);
928 sim_fpu_to64 (&res
, &ans
);
934 fprintf (stderr
, "Bad switch\n");
942 fp_inv_sqrt(sim_cpu
*cpu
,
947 sim_fpu_round round
= rounding_mode (GETRM());
948 sim_fpu_round denorm
= denorm_mode (cpu
);
949 sim_fpu_status status
= 0;
950 unsigned64 result
= 0;
952 /* The format type has already been checked: */
957 status
= inner_rsqrt (op1
, fmt
, round
, denorm
, &result
);
961 int status_u
, status_l
;
962 unsigned64 result_u
, result_l
;
963 status_u
= inner_rsqrt (FP_PS_upper(op1
), fmt_single
, round
, denorm
,
965 status_l
= inner_rsqrt (FP_PS_lower(op1
), fmt_single
, round
, denorm
,
967 result
= FP_PS_cat(result_u
, result_l
);
968 status
= status_u
| status_l
;
972 sim_io_eprintf (SD
, "Bad switch\n");
976 update_fcsr (cpu
, cia
, status
);
987 return fp_unary(cpu
, cia
, &sim_fpu_abs
, op
, fmt
);
996 return fp_unary(cpu
, cia
, &sim_fpu_neg
, op
, fmt
);
1000 fp_add(sim_cpu
*cpu
,
1006 return fp_binary(cpu
, cia
, &sim_fpu_add
, op1
, op2
, fmt
);
1010 fp_sub(sim_cpu
*cpu
,
1016 return fp_binary(cpu
, cia
, &sim_fpu_sub
, op1
, op2
, fmt
);
1020 fp_mul(sim_cpu
*cpu
,
1026 return fp_binary(cpu
, cia
, &sim_fpu_mul
, op1
, op2
, fmt
);
1030 fp_div(sim_cpu
*cpu
,
1036 return fp_binary(cpu
, cia
, &sim_fpu_div
, op1
, op2
, fmt
);
1040 fp_recip(sim_cpu
*cpu
,
1045 return fp_unary(cpu
, cia
, &sim_fpu_inv
, op
, fmt
);
1049 fp_sqrt(sim_cpu
*cpu
,
1054 return fp_unary(cpu
, cia
, &sim_fpu_sqrt
, op
, fmt
);
1058 fp_rsqrt(sim_cpu
*cpu
,
1063 return fp_inv_sqrt(cpu
, cia
, op
, fmt
);
1067 fp_madd(sim_cpu
*cpu
,
1074 return fp_mac(cpu
, cia
, &sim_fpu_add
, op1
, op2
, op3
, 0, 0, fmt
);
1078 fp_msub(sim_cpu
*cpu
,
1085 return fp_mac(cpu
, cia
, &sim_fpu_sub
, op1
, op2
, op3
, 0, 0, fmt
);
1089 fp_nmadd(sim_cpu
*cpu
,
1096 return fp_mac(cpu
, cia
, &sim_fpu_add
, op1
, op2
, op3
, 0, 1, fmt
);
1100 fp_nmsub(sim_cpu
*cpu
,
1107 return fp_mac(cpu
, cia
, &sim_fpu_sub
, op1
, op2
, op3
, 0, 1, fmt
);
1111 /* MIPS-3D ASE operations. */
1113 /* Variant of fp_binary for *r.ps MIPS-3D operations. */
1115 fp_binary_r(sim_cpu
*cpu
,
1117 int (*sim_fpu_op
)(sim_fpu
*, const sim_fpu
*, const sim_fpu
*),
1124 sim_fpu_round round
= rounding_mode (GETRM ());
1125 sim_fpu_denorm denorm
= denorm_mode (cpu
);
1126 sim_fpu_status status_u
, status_l
;
1128 unsigned32 res_u
, res_l
;
1130 /* The format must be fmt_ps. */
1132 sim_fpu_32to (&wop1
, FP_PS_upper (op1
));
1133 sim_fpu_32to (&wop2
, FP_PS_lower (op1
));
1134 status_u
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
1135 status_u
|= sim_fpu_round_32 (&ans
, round
, denorm
);
1136 sim_fpu_to32 (&res_u
, &ans
);
1138 sim_fpu_32to (&wop1
, FP_PS_upper (op2
));
1139 sim_fpu_32to (&wop2
, FP_PS_lower (op2
));
1140 status_l
|= (*sim_fpu_op
) (&ans
, &wop1
, &wop2
);
1141 status_l
|= sim_fpu_round_32 (&ans
, round
, denorm
);
1142 sim_fpu_to32 (&res_l
, &ans
);
1143 result
= FP_PS_cat (res_u
, res_l
);
1145 update_fcsr (cpu
, cia
, status_u
| status_l
);
1150 fp_add_r(sim_cpu
*cpu
,
1156 return fp_binary_r (cpu
, cia
, &sim_fpu_add
, op1
, op2
);
1160 fp_mul_r(sim_cpu
*cpu
,
1166 return fp_binary_r (cpu
, cia
, &sim_fpu_mul
, op1
, op2
);
1169 #define NR_FRAC_GUARD (60)
1170 #define IMPLICIT_1 LSBIT64 (NR_FRAC_GUARD)
1173 fpu_inv1(sim_fpu
*f
, const sim_fpu
*l
)
1175 static const sim_fpu sim_fpu_one
= {
1176 sim_fpu_class_number
, 0, IMPLICIT_1
, 0
1181 if (sim_fpu_is_zero (l
))
1185 return sim_fpu_status_invalid_div0
;
1187 if (sim_fpu_is_infinity (l
))
1193 status
|= sim_fpu_div (f
, &sim_fpu_one
, l
);
1198 fpu_inv1_32(sim_fpu
*f
, const sim_fpu
*l
)
1200 if (sim_fpu_is_zero (l
))
1204 return sim_fpu_status_invalid_div0
;
1206 return fpu_inv1 (f
, l
);
1210 fpu_inv1_64(sim_fpu
*f
, const sim_fpu
*l
)
1212 if (sim_fpu_is_zero (l
))
1216 return sim_fpu_status_invalid_div0
;
1218 return fpu_inv1 (f
, l
);
1222 fp_recip1(sim_cpu
*cpu
,
1231 return fp_unary (cpu
, cia
, &fpu_inv1_32
, op
, fmt
);
1233 return fp_unary (cpu
, cia
, &fpu_inv1_64
, op
, fmt
);
1239 fp_recip2(sim_cpu
*cpu
,
1245 static const unsigned64 one_single
= UNSIGNED64 (0x3F800000);
1246 static const unsigned64 one_double
= UNSIGNED64 (0x3FF0000000000000);
1247 static const unsigned64 one_ps
= (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000));
1250 /* Implemented as nmsub fd, 1, fs, ft. */
1253 case fmt_single
: one
= one_single
; break;
1254 case fmt_double
: one
= one_double
; break;
1255 case fmt_ps
: one
= one_ps
; break;
1256 default: one
= 0; abort ();
1258 return fp_mac (cpu
, cia
, &sim_fpu_sub
, op1
, op2
, one
, 0, 1, fmt
);
1262 fpu_inv_sqrt1(sim_fpu
*f
, const sim_fpu
*l
)
1264 static const sim_fpu sim_fpu_one
= {
1265 sim_fpu_class_number
, 0, IMPLICIT_1
, 0
1270 if (sim_fpu_is_zero (l
))
1274 return sim_fpu_status_invalid_div0
;
1276 if (sim_fpu_is_infinity (l
))
1280 f
->class = sim_fpu_class_zero
;
1286 status
= sim_fpu_status_invalid_sqrt
;
1290 status
|= sim_fpu_sqrt (&t
, l
);
1291 status
|= sim_fpu_div (f
, &sim_fpu_one
, &t
);
1296 fpu_inv_sqrt1_32(sim_fpu
*f
, const sim_fpu
*l
)
1298 if (sim_fpu_is_zero (l
))
1302 return sim_fpu_status_invalid_div0
;
1304 return fpu_inv_sqrt1 (f
, l
);
1308 fpu_inv_sqrt1_64(sim_fpu
*f
, const sim_fpu
*l
)
1310 if (sim_fpu_is_zero (l
))
1314 return sim_fpu_status_invalid_div0
;
1316 return fpu_inv_sqrt1 (f
, l
);
1320 fp_rsqrt1(sim_cpu
*cpu
,
1329 return fp_unary (cpu
, cia
, &fpu_inv_sqrt1_32
, op
, fmt
);
1331 return fp_unary (cpu
, cia
, &fpu_inv_sqrt1_64
, op
, fmt
);
1337 fp_rsqrt2(sim_cpu
*cpu
,
1343 static const unsigned64 half_single
= UNSIGNED64 (0x3F000000);
1344 static const unsigned64 half_double
= UNSIGNED64 (0x3FE0000000000000);
1345 static const unsigned64 half_ps
= (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000));
1348 /* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is
1349 done by scaling the exponent during multiply. */
1352 case fmt_single
: half
= half_single
; break;
1353 case fmt_double
: half
= half_double
; break;
1354 case fmt_ps
: half
= half_ps
; break;
1355 default: half
= 0; abort ();
1357 return fp_mac (cpu
, cia
, &sim_fpu_sub
, op1
, op2
, half
, -1, 1, fmt
);
1361 /* Conversion operations. */
1364 convert (sim_cpu
*cpu
,
1372 sim_fpu_round round
= rounding_mode (rm
);
1373 sim_fpu_denorm denorm
= denorm_mode (cpu
);
1374 unsigned32 result32
;
1375 unsigned64 result64
;
1376 sim_fpu_status status
= 0;
1378 /* Convert the input to sim_fpu internal format */
1382 sim_fpu_64to (&wop
, op
);
1385 sim_fpu_32to (&wop
, op
);
1388 status
= sim_fpu_i32to (&wop
, op
, round
);
1391 status
= sim_fpu_i64to (&wop
, op
, round
);
1394 sim_io_eprintf (SD
, "Bad switch\n");
1398 /* Convert sim_fpu format into the output */
1399 /* The value WOP is converted to the destination format, rounding
1400 using mode RM. When the destination is a fixed-point format, then
1401 a source value of Infinity, NaN or one which would round to an
1402 integer outside the fixed point range then an IEEE Invalid Operation
1403 condition is raised. Not used if destination format is PS. */
1407 status
|= sim_fpu_round_32 (&wop
, round
, denorm
);
1408 /* For a NaN, normalize mantissa bits (cvt.s.d can't preserve them) */
1409 if (sim_fpu_is_qnan (&wop
))
1411 sim_fpu_to32 (&result32
, &wop
);
1412 result64
= result32
;
1415 status
|= sim_fpu_round_64 (&wop
, round
, denorm
);
1416 /* For a NaN, normalize mantissa bits (make cvt.d.s consistent) */
1417 if (sim_fpu_is_qnan (&wop
))
1419 sim_fpu_to64 (&result64
, &wop
);
1422 status
|= sim_fpu_to32i (&result32
, &wop
, round
);
1423 result64
= result32
;
1426 status
|= sim_fpu_to64i (&result64
, &wop
, round
);
1430 sim_io_eprintf (SD
, "Bad switch\n");
1434 update_fcsr (cpu
, cia
, status
);
1439 ps_lower(sim_cpu
*cpu
,
1443 return FP_PS_lower (op
);
1447 ps_upper(sim_cpu
*cpu
,
1451 return FP_PS_upper(op
);
1455 pack_ps(sim_cpu
*cpu
,
1461 unsigned64 result
= 0;
1463 /* The registers must specify FPRs valid for operands of type
1464 "fmt". If they are not valid, the result is undefined. */
1466 /* The format type should already have been checked: */
1472 unsigned32 res_u
, res_l
;
1473 sim_fpu_32to (&wop
, op1
);
1474 sim_fpu_to32 (&res_u
, &wop
);
1475 sim_fpu_32to (&wop
, op2
);
1476 sim_fpu_to32 (&res_l
, &wop
);
1477 result
= FP_PS_cat(res_u
, res_l
);
1481 sim_io_eprintf (SD
, "Bad switch\n");
1489 convert_ps (sim_cpu
*cpu
,
1496 sim_fpu wop_u
, wop_l
;
1497 sim_fpu_round round
= rounding_mode (rm
);
1498 sim_fpu_denorm denorm
= denorm_mode (cpu
);
1499 unsigned32 res_u
, res_l
;
1501 sim_fpu_status status_u
= 0, status_l
= 0;
1503 /* As convert, but used only for paired values (formats PS, PW) */
1505 /* Convert the input to sim_fpu internal format */
1508 case fmt_word
: /* fmt_pw */
1509 sim_fpu_i32to (&wop_u
, (op
>> 32) & (unsigned)0xFFFFFFFF, round
);
1510 sim_fpu_i32to (&wop_l
, op
& (unsigned)0xFFFFFFFF, round
);
1513 sim_fpu_32to (&wop_u
, FP_PS_upper(op
));
1514 sim_fpu_32to (&wop_l
, FP_PS_lower(op
));
1517 sim_io_eprintf (SD
, "Bad switch\n");
1521 /* Convert sim_fpu format into the output */
1524 case fmt_word
: /* fmt_pw */
1525 status_u
|= sim_fpu_to32i (&res_u
, &wop_u
, round
);
1526 status_l
|= sim_fpu_to32i (&res_l
, &wop_l
, round
);
1527 result
= (((unsigned64
)res_u
) << 32) | (unsigned64
)res_l
;
1530 status_u
|= sim_fpu_round_32 (&wop_u
, 0, round
);
1531 status_l
|= sim_fpu_round_32 (&wop_l
, 0, round
);
1532 sim_fpu_to32 (&res_u
, &wop_u
);
1533 sim_fpu_to32 (&res_l
, &wop_l
);
1534 result
= FP_PS_cat(res_u
, res_l
);
1538 sim_io_eprintf (SD
, "Bad switch\n");
1542 update_fcsr (cpu
, cia
, status_u
| status_l
);
1547 fpu_format_name (FP_formats fmt
)
1563 case fmt_uninterpreted
:
1564 return "<uninterpreted>";
1565 case fmt_uninterpreted_32
:
1566 return "<uninterpreted_32>";
1567 case fmt_uninterpreted_64
:
1568 return "<uninterpreted_64>";
1570 return "<format error>";
1576 fpu_rounding_mode_name (int rm
)
1589 return "<rounding mode error>";