1 /* This file is part of the program GDB, the GNU debugger.
3 Copyright (C) 1998 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 tx3904cpu - tx3904 cpu virtual device
35 Implements the external tx3904 functionality. This includes the
36 delivery of of interrupts generated from other devices and the
37 handling of device specific registers.
55 Deliver a non-maskable interrupt to the processor.
60 Deliver a maskable interrupt of given level, corresponding to
61 IP[5:0], to processor.
68 When delivering an interrupt, this code assumes that there is only
69 one processor (number 0).
71 This code does not attempt to be efficient at handling pending
72 interrupts. It simply schedules the interrupt delivery handler
73 every instruction cycle until all pending interrupts go away. An
74 alternative implementation might modify instructions that change
75 the PSW and have them check to see if the change makes an interrupt
83 /* Pending interrupts for delivery by event handler */
84 int pending_reset
, pending_nmi
, pending_level
;
98 static const struct hw_port_descriptor tx3904cpu_ports
[] = {
100 /* interrupt inputs */
101 { "reset", RESET_PORT
, 0, input_port
, },
102 { "nmi", NMI_PORT
, 0, input_port
, },
103 { "level", LEVEL_PORT
, 0, input_port
, },
109 /* Finish off the partially created hw device. Attach our local
110 callbacks. Wire up our port names etc */
112 static hw_port_event_method tx3904cpu_port_event
;
117 tx3904cpu_finish (struct hw
*me
)
119 struct tx3904cpu
*controller
;
121 controller
= HW_ZALLOC (me
, struct tx3904cpu
);
122 set_hw_data (me
, controller
);
123 set_hw_ports (me
, tx3904cpu_ports
);
124 set_hw_port_event (me
, tx3904cpu_port_event
);
126 /* Initialize the pending interrupt flags */
127 controller
->pending_level
= 0;
128 controller
->pending_reset
= 0;
129 controller
->pending_nmi
= 0;
134 /* An event arrives on an interrupt port */
137 deliver_tx3904cpu_interrupt (struct hw
*me
,
140 struct tx3904cpu
*controller
= hw_data (me
);
141 SIM_DESC sd
= hw_system (me
);
142 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* NB: fix CPU 0. */
143 address_word cia
= CIA_GET (cpu
);
146 #define SD current_state
148 if (controller
->pending_reset
)
150 controller
->pending_reset
= 0;
151 HW_TRACE ((me
, "reset pc=0x%08lx", (long) CIA_GET (cpu
)));
152 SignalExceptionNMIReset();
154 else if (controller
->pending_nmi
)
156 controller
->pending_nmi
= 0;
157 HW_TRACE ((me
, "nmi pc=0x%08lx", (long) CIA_GET (cpu
)));
158 SignalExceptionNMIReset();
160 else if (controller
->pending_level
)
162 HW_TRACE ((me
, "interrupt level=%d pc=0x%08lx sr=0x%08lx",
163 controller
->pending_level
,
164 (long) CIA_GET (cpu
), (long) SR
));
166 /* Clear CAUSE register. It may stay this way if the interrupt
167 was cleared with a negative pending_level. */
168 CAUSE
&= ~ (cause_IP_mask
<< cause_IP_shift
);
170 if(controller
->pending_level
> 0) /* interrupt set */
172 /* set hardware-interrupt subfields of CAUSE register */
173 CAUSE
|= (controller
->pending_level
& cause_IP_mask
) << cause_IP_shift
;
175 /* check for enabled / unmasked interrupts */
176 if((SR
& status_IEc
) &&
177 (controller
->pending_level
& ((SR
>> status_IM_shift
) & status_IM_mask
)))
179 controller
->pending_level
= 0;
180 SignalExceptionInterrupt();
184 /* reschedule soon */
185 hw_event_queue_schedule (me
, 1, deliver_tx3904cpu_interrupt
, NULL
);
187 } /* interrupt set */
190 #undef SD current_state
195 tx3904cpu_port_event (struct hw
*me
,
201 struct tx3904cpu
*controller
= hw_data (me
);
206 controller
->pending_reset
= 1;
207 HW_TRACE ((me
, "port-in reset"));
211 controller
->pending_nmi
= 1;
212 HW_TRACE ((me
, "port-in nmi"));
216 /* level == 0 means that the interrupt was cleared */
218 controller
->pending_level
= -1; /* signal end of interrupt */
220 controller
->pending_level
= level
;
221 HW_TRACE ((me
, "port-in level=%d", level
));
225 hw_abort (me
, "bad switch");
229 /* Schedule an event to be delivered immediately after current
231 hw_event_queue_schedule (me
, 0, deliver_tx3904cpu_interrupt
, NULL
);
235 const struct hw_descriptor dv_tx3904cpu_descriptor
[] = {
236 { "tx3904cpu", tx3904cpu_finish
, },