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3 Copyright (C) 1998-2013 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
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7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
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11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
29 tx3904irc - tx3904 interrupt controller
35 Implements the tx3904 interrupt controller described in the tx3904
36 user guide. It does not include the interrupt detection circuit
37 that preprocesses the eight external interrupts, so assumes that
38 each event on an input interrupt port signals a new interrupt.
39 That is, it implements edge- rather than level-triggered
42 This implementation does not support multiple concurrent
51 Base of IRC control register bank. <length> must equal 0x20.
52 Registers offsets: 0: ISR: interrupt status register
53 4: IMR: interrupt mask register
54 16: ILR0: interrupt level register 3..0
55 20: ILR1: interrupt level register 7..4
56 24: ILR2: interrupt level register 11..8
57 28: ILR3: interrupt level register 15..12
66 Interrupt priority port. An event is generated when an interrupt
67 of a sufficient priority is passed through the IRC. The value
68 associated with the event is the interrupt level (16-31), as given
69 for bits IP[5:0] in the book TMPR3904F Rev. 2.0, pg. 11-3. Note
70 that even though INT[0] is tied externally to IP[5], we simulate
71 it as passing through the controller.
73 An output level of zero signals the clearing of a level interrupt.
78 External interrupts. Level = 0 -> level interrupt cleared.
83 DMA internal interrupts, correspond to DMA channels 0-3. Level = 0 -> level interrupt cleared.
88 SIO internal interrupts. Level = 0 -> level interrupt cleared.
93 Timer internal interrupts. Level = 0 -> level interrupt cleared.
101 /* register numbers; each is one word long */
117 /* inputs, ordered to correspond to interrupt sources 0..15 */
118 INT1_PORT
= 0, INT2_PORT
, INT3_PORT
, INT4_PORT
, INT5_PORT
, INT6_PORT
, INT7_PORT
,
119 DMAC3_PORT
, DMAC2_PORT
, DMAC1_PORT
, DMAC0_PORT
, SIO0_PORT
, SIO1_PORT
,
120 TMR0_PORT
, TMR1_PORT
, TMR2_PORT
,
122 /* special INT[0] port */
133 static const struct hw_port_descriptor tx3904irc_ports
[] = {
135 /* interrupt output */
137 { "ip", IP_PORT
, 0, output_port
, },
139 /* interrupt inputs (as names) */
140 /* in increasing order of level number */
142 { "int1", INT1_PORT
, 0, input_port
, },
143 { "int2", INT2_PORT
, 0, input_port
, },
144 { "int3", INT3_PORT
, 0, input_port
, },
145 { "int4", INT4_PORT
, 0, input_port
, },
146 { "int5", INT5_PORT
, 0, input_port
, },
147 { "int6", INT6_PORT
, 0, input_port
, },
148 { "int7", INT7_PORT
, 0, input_port
, },
150 { "dmac3", DMAC3_PORT
, 0, input_port
, },
151 { "dmac2", DMAC2_PORT
, 0, input_port
, },
152 { "dmac1", DMAC1_PORT
, 0, input_port
, },
153 { "dmac0", DMAC0_PORT
, 0, input_port
, },
155 { "sio0", SIO0_PORT
, 0, input_port
, },
156 { "sio1", SIO1_PORT
, 0, input_port
, },
158 { "tmr0", TMR0_PORT
, 0, input_port
, },
159 { "tmr1", TMR1_PORT
, 0, input_port
, },
160 { "tmr2", TMR2_PORT
, 0, input_port
, },
162 { "reset", RESET_PORT
, 0, input_port
, },
163 { "int0", INT0_PORT
, 0, input_port
, },
169 #define NR_SOURCES (TMR3_PORT - INT1_PORT + 1) /* 16: number of interrupt sources */
172 /* The interrupt controller register internal state. Note that we
173 store state using the control register images, in host endian
177 address_word base_address
; /* control register base */
179 #define ISR_SET(c,s) ((c)->isr &= ~ (1 << (s)))
181 #define IMR_GET(c) ((c)->imr)
183 #define ILR_GET(c,s) LSEXTRACTED32((c)->ilr[(s)/4], (s) % 4 * 8 + 2, (s) % 4 * 8)
188 /* Finish off the partially created hw device. Attach our local
189 callbacks. Wire up our port names etc */
191 static hw_io_read_buffer_method tx3904irc_io_read_buffer
;
192 static hw_io_write_buffer_method tx3904irc_io_write_buffer
;
193 static hw_port_event_method tx3904irc_port_event
;
196 attach_tx3904irc_regs (struct hw
*me
,
197 struct tx3904irc
*controller
)
199 unsigned_word attach_address
;
201 unsigned attach_size
;
202 reg_property_spec reg
;
204 if (hw_find_property (me
, "reg") == NULL
)
205 hw_abort (me
, "Missing \"reg\" property");
207 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
208 hw_abort (me
, "\"reg\" property must contain one addr/size entry");
210 hw_unit_address_to_attach_address (hw_parent (me
),
215 hw_unit_size_to_attach_size (hw_parent (me
),
219 hw_attach_address (hw_parent (me
), 0,
220 attach_space
, attach_address
, attach_size
,
223 controller
->base_address
= attach_address
;
228 tx3904irc_finish (struct hw
*me
)
230 struct tx3904irc
*controller
;
232 controller
= HW_ZALLOC (me
, struct tx3904irc
);
233 set_hw_data (me
, controller
);
234 set_hw_io_read_buffer (me
, tx3904irc_io_read_buffer
);
235 set_hw_io_write_buffer (me
, tx3904irc_io_write_buffer
);
236 set_hw_ports (me
, tx3904irc_ports
);
237 set_hw_port_event (me
, tx3904irc_port_event
);
239 /* Attach ourself to our parent bus */
240 attach_tx3904irc_regs (me
, controller
);
242 /* Initialize to reset state */
243 controller
->isr
= 0x0000ffff;
248 controller
->ilr
[3] = 0;
253 /* An event arrives on an interrupt port */
256 tx3904irc_port_event (struct hw
*me
,
258 struct hw
*source_dev
,
262 struct tx3904irc
*controller
= hw_data (me
);
264 /* handle deactivated interrupt */
267 HW_TRACE ((me
, "interrupt cleared on port %d", my_port
));
268 hw_port_event(me
, IP_PORT
, 0);
276 int ip_number
= 32; /* compute IP[5:0] */
277 HW_TRACE ((me
, "port-event INT[0]"));
278 hw_port_event(me
, IP_PORT
, ip_number
);
282 case INT1_PORT
: case INT2_PORT
: case INT3_PORT
: case INT4_PORT
:
283 case INT5_PORT
: case INT6_PORT
: case INT7_PORT
: case DMAC3_PORT
:
284 case DMAC2_PORT
: case DMAC1_PORT
: case DMAC0_PORT
: case SIO0_PORT
:
285 case SIO1_PORT
: case TMR0_PORT
: case TMR1_PORT
: case TMR2_PORT
:
287 int source
= my_port
- INT1_PORT
;
289 HW_TRACE ((me
, "interrupt asserted on port %d", source
));
290 ISR_SET(controller
, source
);
291 if(ILR_GET(controller
, source
) > IMR_GET(controller
))
293 int ip_number
= 16 + source
; /* compute IP[4:0] */
294 HW_TRACE ((me
, "interrupt level %d", ILR_GET(controller
,source
)));
295 hw_port_event(me
, IP_PORT
, ip_number
);
302 HW_TRACE ((me
, "reset"));
303 controller
->isr
= 0x0000ffff;
308 controller
->ilr
[3] = 0;
313 hw_abort (me
, "Event on output port %d", my_port
);
317 hw_abort (me
, "Event on unknown port %d", my_port
);
323 /* generic read/write */
326 tx3904irc_io_read_buffer (struct hw
*me
,
332 struct tx3904irc
*controller
= hw_data (me
);
335 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
336 for (byte
= 0; byte
< nr_bytes
; byte
++)
338 address_word address
= base
+ byte
;
339 int reg_number
= (address
- controller
->base_address
) / 4;
340 int reg_offset
= (address
- controller
->base_address
) % 4;
341 unsigned_4 register_value
; /* in target byte order */
343 /* fill in entire register_value word */
346 case ISR_REG
: register_value
= controller
->isr
; break;
347 case IMR_REG
: register_value
= controller
->imr
; break;
348 case ILR0_REG
: register_value
= controller
->ilr
[0]; break;
349 case ILR1_REG
: register_value
= controller
->ilr
[1]; break;
350 case ILR2_REG
: register_value
= controller
->ilr
[2]; break;
351 case ILR3_REG
: register_value
= controller
->ilr
[3]; break;
352 default: register_value
= 0;
355 /* write requested byte out */
356 register_value
= H2T_4(register_value
);
357 memcpy ((char*) dest
+ byte
, ((char*)& register_value
)+reg_offset
, 1);
366 tx3904irc_io_write_buffer (struct hw
*me
,
372 struct tx3904irc
*controller
= hw_data (me
);
375 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
376 for (byte
= 0; byte
< nr_bytes
; byte
++)
378 address_word address
= base
+ byte
;
379 int reg_number
= (address
- controller
->base_address
) / 4;
380 int reg_offset
= (address
- controller
->base_address
) % 4;
381 unsigned_4
* register_ptr
;
382 unsigned_4 register_value
;
384 /* fill in entire register_value word */
387 case ISR_REG
: register_ptr
= & controller
->isr
; break;
388 case IMR_REG
: register_ptr
= & controller
->imr
; break;
389 case ILR0_REG
: register_ptr
= & controller
->ilr
[0]; break;
390 case ILR1_REG
: register_ptr
= & controller
->ilr
[1]; break;
391 case ILR2_REG
: register_ptr
= & controller
->ilr
[2]; break;
392 case ILR3_REG
: register_ptr
= & controller
->ilr
[3]; break;
393 default: register_ptr
= & register_value
; /* used as a dummy */
396 /* HW_TRACE ((me, "reg %d pre: %08lx", reg_number, (long) *register_ptr)); */
398 /* overwrite requested byte */
399 register_value
= H2T_4(* register_ptr
);
400 memcpy (((char*)®ister_value
)+reg_offset
, (const char*)source
+ byte
, 1);
401 * register_ptr
= T2H_4(register_value
);
403 /* HW_TRACE ((me, "post: %08lx", (long) *register_ptr)); */
409 const struct hw_descriptor dv_tx3904irc_descriptor
[] = {
410 { "tx3904irc", tx3904irc_finish
, },