1 /* This file is part of the program GDB, the GNU debugger.
3 Copyright (C) 1998 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 tx3904irc - tx3904 interrupt controller
36 Implements the tx3904 interrupt controller described in the tx3904
37 user guide. It does not include the interrupt detection circuit
38 that preprocesses the eight external interrupts, so assumes that
39 each event on an input interrupt port signals a new interrupt.
40 That is, it implements edge- rather than level-triggered
49 Base of IRC control register bank. <length> must equal 0x20.
50 Registers offsets: 0: ISR: interrupt status register
51 4: IMR: interrupt mask register
52 16: ILR0: interrupt level register 3..0
53 20: ILR1: interrupt level register 7..4
54 24: ILR2: interrupt level register 11..8
55 28: ILR3: interrupt level register 15..12
64 Interrupt priority port. An event is generated when an interrupt
65 of a sufficient priority is passed through the IRC. The value
66 associated with the event is the interrupt level (16-31), as given
67 for bits IP[5:0] in the book TMPR3904F Rev. 2.0, pg. 11-3. Note
68 that even though INT[0] is tied externally to IP[5], we simulate
69 it as passing through the controller.
79 DMA internal interrupts, correspond to DMA channels 0-3.
84 SIO internal interrupts.
89 Timer internal interrupts.
97 /* register numbers; each is one word long */
113 /* inputs, ordered to correspond to interrupt sources 0..15 */
114 INT1_PORT
= 0, INT2_PORT
, INT3_PORT
, INT4_PORT
, INT5_PORT
, INT6_PORT
, INT7_PORT
,
115 DMAC3_PORT
, DMAC2_PORT
, DMAC1_PORT
, DMAC0_PORT
, SIO0_PORT
, SIO1_PORT
,
116 TMR0_PORT
, TMR1_PORT
, TMR2_PORT
,
118 /* special INT[0] port */
129 static const struct hw_port_descriptor tx3904irc_ports
[] = {
131 /* interrupt output */
133 { "ip", IP_PORT
, 0, output_port
, },
135 /* interrupt inputs (as names) */
136 /* in increasing order of level number */
138 { "int1", INT1_PORT
, 0, input_port
, },
139 { "int2", INT2_PORT
, 0, input_port
, },
140 { "int3", INT3_PORT
, 0, input_port
, },
141 { "int4", INT4_PORT
, 0, input_port
, },
142 { "int5", INT5_PORT
, 0, input_port
, },
143 { "int6", INT6_PORT
, 0, input_port
, },
144 { "int7", INT7_PORT
, 0, input_port
, },
146 { "dmac3", DMAC3_PORT
, 0, input_port
, },
147 { "dmac2", DMAC2_PORT
, 0, input_port
, },
148 { "dmac1", DMAC1_PORT
, 0, input_port
, },
149 { "dmac0", DMAC0_PORT
, 0, input_port
, },
151 { "sio0", SIO0_PORT
, 0, input_port
, },
152 { "sio1", SIO1_PORT
, 0, input_port
, },
154 { "tmr0", TMR0_PORT
, 0, input_port
, },
155 { "tmr1", TMR1_PORT
, 0, input_port
, },
156 { "tmr2", TMR2_PORT
, 0, input_port
, },
158 { "reset", RESET_PORT
, 0, input_port
, },
159 { "int0", INT0_PORT
, 0, input_port
, },
165 #define NR_SOURCES (TMR3_PORT - INT1_PORT + 1) /* 16: number of interrupt sources */
168 /* The interrupt controller register internal state. Note that we
169 store state using the control register images, in host endian
173 address_word base_address
; /* control register base */
175 #define ISR_SET(c,s) ((c)->isr &= ~ (1 << (s)))
177 #define IMR_GET(c) ((c)->imr)
179 #define ILR_GET(c,s) LSEXTRACTED32((c)->ilr[(s)/4], (s) % 4 * 8 + 2, (s) % 4 * 8)
184 /* Finish off the partially created hw device. Attach our local
185 callbacks. Wire up our port names etc */
187 static hw_io_read_buffer_method tx3904irc_io_read_buffer
;
188 static hw_io_write_buffer_method tx3904irc_io_write_buffer
;
189 static hw_port_event_method tx3904irc_port_event
;
192 attach_tx3904irc_regs (struct hw
*me
,
193 struct tx3904irc
*controller
)
195 unsigned_word attach_address
;
197 unsigned attach_size
;
198 reg_property_spec reg
;
200 if (hw_find_property (me
, "reg") == NULL
)
201 hw_abort (me
, "Missing \"reg\" property");
203 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
204 hw_abort (me
, "\"reg\" property must contain one addr/size entry");
206 hw_unit_address_to_attach_address (hw_parent (me
),
211 hw_unit_size_to_attach_size (hw_parent (me
),
215 hw_attach_address (hw_parent (me
), 0,
216 attach_space
, attach_address
, attach_size
,
219 controller
->base_address
= attach_address
;
224 tx3904irc_finish (struct hw
*me
)
226 struct tx3904irc
*controller
;
228 controller
= HW_ZALLOC (me
, struct tx3904irc
);
229 set_hw_data (me
, controller
);
230 set_hw_io_read_buffer (me
, tx3904irc_io_read_buffer
);
231 set_hw_io_write_buffer (me
, tx3904irc_io_write_buffer
);
232 set_hw_ports (me
, tx3904irc_ports
);
233 set_hw_port_event (me
, tx3904irc_port_event
);
235 /* Attach ourself to our parent bus */
236 attach_tx3904irc_regs (me
, controller
);
238 /* Initialize to reset state */
239 controller
->isr
= 0x0000ffff;
244 controller
->ilr
[3] = 0;
249 /* An event arrives on an interrupt port */
252 tx3904irc_port_event (struct hw
*me
,
258 struct tx3904irc
*controller
= hw_data (me
);
260 /* Ignore level - use only edge-triggered interrupts */
266 int ip_number
= 32; /* compute IP[5:0] */
267 HW_TRACE ((me
, "port-event INT[0]"));
268 hw_port_event(me
, IP_PORT
, ip_number
);
272 case INT1_PORT
: case INT2_PORT
: case INT3_PORT
: case INT4_PORT
:
273 case INT5_PORT
: case INT6_PORT
: case INT7_PORT
: case DMAC3_PORT
:
274 case DMAC2_PORT
: case DMAC1_PORT
: case DMAC0_PORT
: case SIO0_PORT
:
275 case SIO1_PORT
: case TMR0_PORT
: case TMR1_PORT
: case TMR2_PORT
:
277 int source
= my_port
- INT1_PORT
;
279 HW_TRACE ((me
, "port-event interrupt source %d", source
));
280 ISR_SET(controller
, source
);
281 if(ILR_GET(controller
, source
) > IMR_GET(controller
))
283 int ip_number
= 16 + source
; /* compute IP[4:0] */
284 HW_TRACE ((me
, "interrupt level %ld", ILR_GET(controller
,source
)));
285 hw_port_event(me
, IP_PORT
, ip_number
);
292 HW_TRACE ((me
, "reset"));
293 controller
->isr
= 0x0000ffff;
298 controller
->ilr
[3] = 0;
303 hw_abort (me
, "Event on output port %d", my_port
);
307 hw_abort (me
, "Event on unknown port %d", my_port
);
313 /* generic read/write */
316 tx3904irc_io_read_buffer (struct hw
*me
,
322 struct tx3904irc
*controller
= hw_data (me
);
325 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
326 for (byte
= 0; byte
< nr_bytes
; byte
++)
328 address_word address
= base
+ byte
;
329 int reg_number
= (address
- controller
->base_address
) / 4;
330 int reg_offset
= (address
- controller
->base_address
) % 4;
331 unsigned_4 register_value
; /* in target byte order */
333 /* fill in entire register_value word */
336 case ISR_REG
: register_value
= controller
->isr
; break;
337 case IMR_REG
: register_value
= controller
->imr
; break;
338 case ILR0_REG
: register_value
= controller
->ilr
[0]; break;
339 case ILR1_REG
: register_value
= controller
->ilr
[1]; break;
340 case ILR2_REG
: register_value
= controller
->ilr
[2]; break;
341 case ILR3_REG
: register_value
= controller
->ilr
[3]; break;
342 default: register_value
= 0;
345 /* write requested byte out */
346 memcpy ((char*) dest
+ byte
, ((char*)& register_value
)+reg_offset
, 1);
355 tx3904irc_io_write_buffer (struct hw
*me
,
361 struct tx3904irc
*controller
= hw_data (me
);
364 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
365 for (byte
= 0; byte
< nr_bytes
; byte
++)
367 address_word address
= base
+ byte
;
368 int reg_number
= (address
- controller
->base_address
) / 4;
369 int reg_offset
= (address
- controller
->base_address
) % 4;
370 unsigned_4
* register_ptr
;
371 unsigned_4 register_value
;
373 /* fill in entire register_value word */
376 case ISR_REG
: register_ptr
= & controller
->isr
; break;
377 case IMR_REG
: register_ptr
= & controller
->imr
; break;
378 case ILR0_REG
: register_ptr
= & controller
->ilr
[0]; break;
379 case ILR1_REG
: register_ptr
= & controller
->ilr
[1]; break;
380 case ILR2_REG
: register_ptr
= & controller
->ilr
[2]; break;
381 case ILR3_REG
: register_ptr
= & controller
->ilr
[3]; break;
382 default: register_ptr
= & register_value
; /* used as a dummy */
385 HW_TRACE ((me
, "reg %d pre: %08lx", reg_number
, (long) *register_ptr
));
387 /* overwrite requested byte */
388 memcpy (((char*)register_ptr
)+reg_offset
, (char*)source
+ byte
, 1);
390 HW_TRACE ((me
, "post: %08lx", (long) *register_ptr
));
396 const struct hw_descriptor dv_tx3904irc_descriptor
[] = {
397 { "tx3904irc", tx3904irc_finish
, },