1 /* This file is part of the program GDB, the GNU debugger.
3 Copyright (C) 1998 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 tx3904irc - tx3904 interrupt controller
36 Implements the tx3904 interrupt controller described in the tx3904
37 user guide. It does not include the interrupt detection circuit
38 that preprocesses the eight external interrupts.
46 Base of IRC control register bank. <length> must equal 0x20.
47 Registers offsets: 0: ISR: interrupt status register
48 4: IMR: interrupt mask register
49 16: ILR0: interrupt level register 3..0
50 20: ILR1: interrupt level register 7..4
51 24: ILR2: interrupt level register 11..8
52 28: ILR3: interrupt level register 15..12
61 Interrupt priority port. An event is generated when an interrupt
62 of a sufficient priority is passed through the IRC. The value
63 associated with the event is the interrupt level (16-31), as given
64 for bits IP[5:0] in the book TMPR3904F Rev. 2.0, pg. 11-3. Note
65 that even though INT[0] is tied externally to IP[5], we simulate
66 it as passing through the controller.
76 DMA internal interrupts, correspond to DMA channels 0-3.
81 SIO internal interrupts.
86 Timer internal interrupts.
95 /* inputs, ordered to correspond to interrupt sources 0..15 */
96 INT1_PORT
= 0, INT2_PORT
, INT3_PORT
, INT4_PORT
, INT5_PORT
, INT6_PORT
, INT7_PORT
,
97 DMAC3_PORT
, DMAC2_PORT
, DMAC1_PORT
, DMAC0_PORT
, SIO0_PORT
, SIO1_PORT
,
98 TMR0_PORT
, TMR1_PORT
, TMR2_PORT
,
100 /* special INT[0] port */
111 /* register numbers; each is one word long */
123 static const struct hw_port_descriptor tx3904irc_ports
[] = {
125 /* interrupt output */
127 { "ip", IP_PORT
, 0, output_port
, },
129 /* interrupt inputs (as names) */
130 /* in increasing order of level number */
132 { "int1", INT1_PORT
, 0, input_port
, },
133 { "int2", INT2_PORT
, 0, input_port
, },
134 { "int3", INT3_PORT
, 0, input_port
, },
135 { "int4", INT4_PORT
, 0, input_port
, },
136 { "int5", INT5_PORT
, 0, input_port
, },
137 { "int6", INT6_PORT
, 0, input_port
, },
138 { "int7", INT7_PORT
, 0, input_port
, },
140 { "dmac3", DMAC3_PORT
, 0, input_port
, },
141 { "dmac2", DMAC2_PORT
, 0, input_port
, },
142 { "dmac1", DMAC1_PORT
, 0, input_port
, },
143 { "dmac0", DMAC0_PORT
, 0, input_port
, },
145 { "sio0", SIO0_PORT
, 0, input_port
, },
146 { "sio1", SIO1_PORT
, 0, input_port
, },
148 { "tmr0", TMR0_PORT
, 0, input_port
, },
149 { "tmr1", TMR1_PORT
, 0, input_port
, },
150 { "tmr2", TMR2_PORT
, 0, input_port
, },
152 { "reset", RESET_PORT
, 0, input_port
, },
153 { "int0", INT0_PORT
, 0, input_port
, },
159 #define NR_SOURCES (TMR3_PORT - INT1_PORT + 1) /* 16: number of interrupt sources */
162 /* The interrupt controller register internal state. Note that we
163 store state using the control register images, in host endian
167 address_word base_address
; /* control register base */
169 #define ISR_SET(c,s) ((c)->isr &= ~ (1 << (s)))
171 #define IMR_GET(c) ((c)->imr)
173 #define ILR_GET(c,s) LSEXTRACTED32((c)->ilr[(s)/4], (s) % 4 * 8 + 2, (s) % 4 * 8)
178 /* Finish off the partially created hw device. Attach our local
179 callbacks. Wire up our port names etc */
181 static hw_io_read_buffer_callback tx3904irc_io_read_buffer
;
182 static hw_io_write_buffer_callback tx3904irc_io_write_buffer
;
183 static hw_port_event_callback tx3904irc_port_event
;
186 attach_tx3904irc_regs (struct hw
*me
,
187 struct tx3904irc
*controller
)
189 unsigned_word attach_address
;
191 unsigned attach_size
;
192 reg_property_spec reg
;
194 if (hw_find_property (me
, "reg") == NULL
)
195 hw_abort (me
, "Missing \"reg\" property");
197 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
198 hw_abort (me
, "\"reg\" property must contain one addr/size entry");
200 hw_unit_address_to_attach_address (hw_parent (me
),
205 hw_unit_size_to_attach_size (hw_parent (me
),
209 hw_attach_address (hw_parent (me
), 0,
210 attach_space
, attach_address
, attach_size
,
213 controller
->base_address
= attach_address
;
218 tx3904irc_finish (struct hw
*me
)
220 struct tx3904irc
*controller
;
222 controller
= HW_ZALLOC (me
, struct tx3904irc
);
223 set_hw_data (me
, controller
);
224 set_hw_io_read_buffer (me
, tx3904irc_io_read_buffer
);
225 set_hw_io_write_buffer (me
, tx3904irc_io_write_buffer
);
226 set_hw_ports (me
, tx3904irc_ports
);
227 set_hw_port_event (me
, tx3904irc_port_event
);
229 /* Attach ourself to our parent bus */
230 attach_tx3904irc_regs (me
, controller
);
232 /* Initialize to reset state */
233 controller
->isr
= 0x0000ffff;
238 controller
->ilr
[3] = 0;
243 /* An event arrives on an interrupt port */
246 tx3904irc_port_event (struct hw
*me
,
252 struct tx3904irc
*controller
= hw_data (me
);
258 int ip_number
= 32; /* compute IP[5:0] */
259 HW_TRACE ((me
, "port-event INT[0]"));
260 hw_port_event(me
, IP_PORT
, ip_number
);
264 case INT1_PORT
: case INT2_PORT
: case INT3_PORT
: case INT4_PORT
:
265 case INT5_PORT
: case INT6_PORT
: case INT7_PORT
: case DMAC3_PORT
:
266 case DMAC2_PORT
: case DMAC1_PORT
: case DMAC0_PORT
: case SIO0_PORT
:
267 case SIO1_PORT
: case TMR0_PORT
: case TMR1_PORT
: case TMR2_PORT
:
269 int source
= my_port
- INT1_PORT
;
271 HW_TRACE ((me
, "port-event interrupt source %d", source
));
272 ISR_SET(controller
, source
);
273 if(ILR_GET(controller
, source
) > IMR_GET(controller
))
275 int ip_number
= 16 + source
; /* compute IP[4:0] */
276 HW_TRACE ((me
, "interrupt level %ld", ILR_GET(controller
,source
)));
277 hw_port_event(me
, IP_PORT
, ip_number
);
284 HW_TRACE ((me
, "reset"));
285 controller
->isr
= 0x0000ffff;
290 controller
->ilr
[3] = 0;
295 hw_abort (me
, "Event on output port %d", my_port
);
299 hw_abort (me
, "Event on unknown port %d", my_port
);
305 /* generic read/write */
308 tx3904irc_io_read_buffer (struct hw
*me
,
314 struct tx3904irc
*controller
= hw_data (me
);
317 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
318 for (byte
= 0; byte
< nr_bytes
; byte
++)
320 address_word address
= base
+ byte
;
321 int reg_number
= (address
- controller
->base_address
) / 4;
322 int reg_offset
= (address
- controller
->base_address
) % 4;
323 unsigned_4 register_value
; /* in target byte order */
325 /* fill in entire register_value word */
328 case ISR_REG
: register_value
= controller
->isr
; break;
329 case IMR_REG
: register_value
= controller
->imr
; break;
330 case ILR0_REG
: register_value
= controller
->ilr
[0]; break;
331 case ILR1_REG
: register_value
= controller
->ilr
[1]; break;
332 case ILR2_REG
: register_value
= controller
->ilr
[2]; break;
333 case ILR3_REG
: register_value
= controller
->ilr
[3]; break;
334 default: register_value
= 0;
337 /* write requested byte out */
338 memcpy ((char*) dest
+ byte
, ((char*)& register_value
)+reg_offset
, 1);
347 tx3904irc_io_write_buffer (struct hw
*me
,
353 struct tx3904irc
*controller
= hw_data (me
);
356 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
357 for (byte
= 0; byte
< nr_bytes
; byte
++)
359 address_word address
= base
+ byte
;
360 int reg_number
= (address
- controller
->base_address
) / 4;
361 int reg_offset
= (address
- controller
->base_address
) % 4;
362 unsigned_4
* register_ptr
;
363 unsigned_4 register_value
;
365 /* fill in entire register_value word */
368 case ISR_REG
: register_ptr
= & controller
->isr
; break;
369 case IMR_REG
: register_ptr
= & controller
->imr
; break;
370 case ILR0_REG
: register_ptr
= & controller
->ilr
[0]; break;
371 case ILR1_REG
: register_ptr
= & controller
->ilr
[1]; break;
372 case ILR2_REG
: register_ptr
= & controller
->ilr
[2]; break;
373 case ILR3_REG
: register_ptr
= & controller
->ilr
[3]; break;
374 default: register_ptr
= & register_value
; /* used as a dummy */
377 HW_TRACE ((me
, "reg %d pre: %08lx", reg_number
, (long) *register_ptr
));
379 /* overwrite requested byte */
380 memcpy (((char*)register_ptr
)+reg_offset
, (char*)source
+ byte
, 1);
382 HW_TRACE ((me
, "post: %08lx", (long) *register_ptr
));
388 const struct hw_device_descriptor dv_tx3904irc_descriptor
[] = {
389 { "tx3904irc", tx3904irc_finish
, },