projects / deliverable / binutils-gdb.git / blob
? search:


104e0d88fc677c1b5be3723d44a2fbad1b306050
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Date$
18
19 NOTEs:
20
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
24 code on the hardware.
25
26 */
27
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
32 #define TRACE (1)
33 #endif
34
35 #include "bfd.h"
36 #include "sim-main.h"
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
40 #include "sim-hw.h"
41
42 /* start-sanitize-sky */
43 #ifdef TARGET_SKY
44 #include "sky-vu.h"
45 #include "sky-vpe.h"
46 #include "sky-libvpe.h"
47 #include "sky-pke.h"
48 #include "sky-gpuif.h"
49 #include "idecode.h"
50 #include "support.h"
51 #undef SD
52 #endif
53 /* end-sanitize-sky */
54
55 #include "config.h"
56
57 #include <stdio.h>
58 #include <stdarg.h>
59 #include <ansidecl.h>
60 #include <ctype.h>
61 #include <limits.h>
62 #include <math.h>
63 #ifdef HAVE_STDLIB_H
64 #include <stdlib.h>
65 #endif
66 #ifdef HAVE_STRING_H
67 #include <string.h>
68 #else
69 #ifdef HAVE_STRINGS_H
70 #include <strings.h>
71 #endif
72 #endif
73
74 #include "getopt.h"
75 #include "libiberty.h"
76 #include "bfd.h"
77 #include "callback.h" /* GDB simulator callback interface */
78 #include "remote-sim.h" /* GDB simulator interface */
79
80 #include "sysdep.h"
81
82 #ifndef PARAMS
83 #define PARAMS(x)
84 #endif
85
86 char* pr_addr PARAMS ((SIM_ADDR addr));
87 char* pr_uword64 PARAMS ((uword64 addr));
88
89
90 /* Get the simulator engine description, without including the code: */
91 #if !(WITH_IGEN)
92 #define SIM_MANIFESTS
93 #include "oengine.c"
94 #undef SIM_MANIFESTS
95 #endif
96
97 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
98 #define CPU cpu
99 #define SD sd
100
101
102 /* The following reserved instruction value is used when a simulator
103 trap is required. NOTE: Care must be taken, since this value may be
104 used in later revisions of the MIPS ISA. */
105
106 #define RSVD_INSTRUCTION (0x00000005)
107 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
108
109 #define RSVD_INSTRUCTION_ARG_SHIFT 6
110 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
111
112
113 /* Bits in the Debug register */
114 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
115 #define Debug_DM 0x40000000 /* Debug Mode */
116 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
117
118 /*---------------------------------------------------------------------------*/
119 /*-- GDB simulator interface ------------------------------------------------*/
120 /*---------------------------------------------------------------------------*/
121
122 static void ColdReset PARAMS((SIM_DESC sd));
123
124 /*---------------------------------------------------------------------------*/
125
126
127
128 #define DELAYSLOT() {\
129 if (STATE & simDELAYSLOT)\
130 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
131 STATE |= simDELAYSLOT;\
132 }
133
134 #define JALDELAYSLOT() {\
135 DELAYSLOT ();\
136 STATE |= simJALDELAYSLOT;\
137 }
138
139 #define NULLIFY() {\
140 STATE &= ~simDELAYSLOT;\
141 STATE |= simSKIPNEXT;\
142 }
143
144 #define CANCELDELAYSLOT() {\
145 DSSTATE = 0;\
146 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
147 }
148
149 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
150 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
151
152 #define K0BASE (0x80000000)
153 #define K0SIZE (0x20000000)
154 #define K1BASE (0xA0000000)
155 #define K1SIZE (0x20000000)
156 #define MONITOR_BASE (0xBFC00000)
157 #define MONITOR_SIZE (1 << 11)
158 #define MEM_SIZE (2 << 20)
159
160 /* start-sanitize-sky */
161 #ifdef TARGET_SKY
162 #undef MEM_SIZE
163 #define MEM_SIZE (16 << 20) /* 16 MB */
164 #endif
165 /* end-sanitize-sky */
166
167 #if defined(TRACE)
168 static char *tracefile = "trace.din"; /* default filename for trace log */
169 FILE *tracefh = NULL;
170 static void open_trace PARAMS((SIM_DESC sd));
171 #endif /* TRACE */
172
173 /* simulation target board. NULL=canonical */
174 static char* board = NULL;
175
176
177 static DECLARE_OPTION_HANDLER (mips_option_handler);
178
179 enum {
180 OPTION_DINERO_TRACE = OPTION_START,
181 OPTION_DINERO_FILE
182 /* start-sanitize-sky */
183 #ifdef TARGET_SKY
184 #ifdef SKY_FUNIT
185 ,OPTION_FLOAT_TYPE
186 #endif
187 ,OPTION_GS_ENABLE
188 ,OPTION_GS_REFRESH1
189 ,OPTION_GS_REFRESH2
190 #endif
191 /* end-sanitize-sky */
192 ,OPTION_BOARD
193 };
194
195
196 static SIM_RC
197 mips_option_handler (sd, cpu, opt, arg, is_command)
198 SIM_DESC sd;
199 sim_cpu *cpu;
200 int opt;
201 char *arg;
202 int is_command;
203 {
204 int cpu_nr;
205 switch (opt)
206 {
207 case OPTION_DINERO_TRACE: /* ??? */
208 #if defined(TRACE)
209 /* Eventually the simTRACE flag could be treated as a toggle, to
210 allow external control of the program points being traced
211 (i.e. only from main onwards, excluding the run-time setup,
212 etc.). */
213 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
214 {
215 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
216 if (arg == NULL)
217 STATE |= simTRACE;
218 else if (strcmp (arg, "yes") == 0)
219 STATE |= simTRACE;
220 else if (strcmp (arg, "no") == 0)
221 STATE &= ~simTRACE;
222 else if (strcmp (arg, "on") == 0)
223 STATE |= simTRACE;
224 else if (strcmp (arg, "off") == 0)
225 STATE &= ~simTRACE;
226 else
227 {
228 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
229 return SIM_RC_FAIL;
230 }
231 }
232 return SIM_RC_OK;
233 #else /* !TRACE */
234 fprintf(stderr,"\
235 Simulator constructed without dinero tracing support (for performance).\n\
236 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
237 return SIM_RC_FAIL;
238 #endif /* !TRACE */
239
240 case OPTION_DINERO_FILE:
241 #if defined(TRACE)
242 if (optarg != NULL) {
243 char *tmp;
244 tmp = (char *)malloc(strlen(optarg) + 1);
245 if (tmp == NULL)
246 {
247 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
248 return SIM_RC_FAIL;
249 }
250 else {
251 strcpy(tmp,optarg);
252 tracefile = tmp;
253 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
254 }
255 }
256 #endif /* TRACE */
257 return SIM_RC_OK;
258
259 /* start-sanitize-sky */
260 #ifdef TARGET_SKY
261 #ifdef SKY_FUNIT
262 case OPTION_FLOAT_TYPE:
263 /* Use host (fast) or target (accurate) floating point implementation. */
264 if (arg && strcmp (arg, "fast") == 0)
265 STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_ACCURATE;
266 else if (arg && strcmp (arg, "accurate") == 0)
267 STATE_FP_TYPE_OPT (sd) |= STATE_FP_TYPE_OPT_ACCURATE;
268 else
269 {
270 fprintf (stderr, "Unrecognized float-type option `%s'\n", arg);
271 return SIM_RC_FAIL;
272 }
273 /*printf ("float-type=0x%08x\n", STATE_FP_TYPE_OPT (sd));*/
274 return SIM_RC_OK;
275 #endif
276
277 case OPTION_GS_ENABLE:
278 /* Enable GS libraries. */
279 if ( arg && strcmp (arg, "on") == 0 )
280 gif_options (&GIF_full,GIF_OPT_GS_ENABLE,1,0,0);
281 else if ( arg && strcmp (arg, "off") == 0 )
282 gif_options (&GIF_full,GIF_OPT_GS_ENABLE,0,0,0);
283 else
284 {
285 fprintf (stderr, "Unrecognized enable-gs option `%s'\n", arg);
286 return SIM_RC_FAIL;
287 }
288 return SIM_RC_OK;
289
290 case OPTION_GS_REFRESH1:
291 case OPTION_GS_REFRESH2:
292 {
293 /* The GS has defineable register and register values. */
294 unsigned_4 address[2];
295 long long value[2];
296 char c[3];
297
298 if ( arg && strlen (arg) == 59 && arg[10] == '=' &&
299 arg[29] == ':' && arg[40] == '=' &&
300 ( sscanf (arg,"%lx%c%Lx%c%lx%c%Lx", &address[0],&c[0],&value[0],
301 &c[1],&address[1],&c[2],&value[1]) == 7 ))
302 {
303 gif_options (&GIF_full, ( opt == OPTION_GS_REFRESH1 ) ?
304 GIF_OPT_GS_REFRESH1:GIF_OPT_GS_REFRESH2,
305 0,&address[0],&value[0]);
306 }
307 else
308 {
309 fprintf (stderr, "Unrecognized gs-refresh option `%s'\n", arg);
310 return SIM_RC_FAIL;
311 }
312 }
313 return SIM_RC_OK;
314
315 #endif
316 /* end-sanitize-sky */
317
318 case OPTION_BOARD:
319 {
320 if (arg)
321 {
322 board = zalloc(strlen(arg) + 1);
323 strcpy(board, arg);
324 }
325 return SIM_RC_OK;
326 }
327 }
328
329 return SIM_RC_OK;
330 }
331
332
333 static const OPTION mips_options[] =
334 {
335 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
336 '\0', "on|off", "Enable dinero tracing",
337 mips_option_handler },
338 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
339 '\0', "FILE", "Write dinero trace to FILE",
340 mips_option_handler },
341 /* start-sanitize-sky */
342 #ifdef TARGET_SKY
343 #ifdef SKY_FUNIT
344 { {"float-type", required_argument, NULL, OPTION_FLOAT_TYPE},
345 '\0', "fast|accurate", "Use fast (host) or accurate (target) floating point",
346 mips_option_handler },
347 #endif
348 { {"enable-gs", required_argument, NULL, OPTION_GS_ENABLE},
349 '\0', "on|off", "Enable GS library routines",
350 mips_option_handler },
351 { {"gs-refresh1", required_argument, NULL, OPTION_GS_REFRESH1},
352 '\0', "0xaddress0=0xvalue0:0xaddress1=0xvalue1", "GS refresh buffer 1 addresses and values",
353 mips_option_handler },
354 { {"gs-refresh2", required_argument, NULL, OPTION_GS_REFRESH2},
355 '\0', "0xaddress0=0xvalue0:0xaddress1=0xvalue1", "GS refresh buffer 2 addresses and values",
356 mips_option_handler },
357 #endif
358 /* end-sanitize-sky */
359
360 { {"board", required_argument, NULL, OPTION_BOARD},
361 '\0', "none" /* rely on compile-time string concatenation for other options */
362
363 /* start-sanitize-tx3904 */
364 #define BOARD_JMR3904 "jmr3904"
365 "|" BOARD_JMR3904
366 #define BOARD_JMR3904_PAL "jmr3904pal"
367 "|" BOARD_JMR3904_PAL
368 #define BOARD_JMR3904_DEBUG "jmr3904debug"
369 "|" BOARD_JMR3904_DEBUG
370 /* end-sanitize-tx3904 */
371
372 , "Customize simulation for a particular board.", mips_option_handler },
373
374 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
375 };
376
377
378 int interrupt_pending;
379
380 static void
381 interrupt_event (SIM_DESC sd, void *data)
382 {
383 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
384 address_word cia = CIA_GET (cpu);
385 if (SR & status_IE)
386 {
387 interrupt_pending = 0;
388 SignalExceptionInterrupt ();
389 }
390 else if (!interrupt_pending)
391 sim_events_schedule (sd, 1, interrupt_event, data);
392 }
393
394
395 /*---------------------------------------------------------------------------*/
396 /*-- Device registration hook -----------------------------------------------*/
397 /*---------------------------------------------------------------------------*/
398 static void device_init(SIM_DESC sd) {
399 #ifdef DEVICE_INIT
400 extern void register_devices(SIM_DESC);
401 register_devices(sd);
402 #endif
403 }
404
405 /*---------------------------------------------------------------------------*/
406 /*-- GDB simulator interface ------------------------------------------------*/
407 /*---------------------------------------------------------------------------*/
408
409 SIM_DESC
410 sim_open (kind, cb, abfd, argv)
411 SIM_OPEN_KIND kind;
412 host_callback *cb;
413 struct _bfd *abfd;
414 char **argv;
415 {
416 SIM_DESC sd = sim_state_alloc (kind, cb);
417 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
418
419 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
420 /* start-sanitize-sky */
421
422 #if defined(TARGET_SKY) && defined(SKY_FUNIT)
423 /* Set "--float-type fast" as the default. */
424 STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_ACCURATE;
425 #endif
426 /* end-sanitize-sky */
427
428 /* FIXME: watchpoints code shouldn't need this */
429 STATE_WATCHPOINTS (sd)->pc = &(PC);
430 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
431 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
432
433 STATE = 0;
434
435 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
436 return 0;
437 sim_add_option_table (sd, NULL, mips_options);
438
439 /* getopt will print the error message so we just have to exit if this fails.
440 FIXME: Hmmm... in the case of gdb we need getopt to call
441 print_filtered. */
442 if (sim_parse_args (sd, argv) != SIM_RC_OK)
443 {
444 /* Uninstall the modules to avoid memory leaks,
445 file descriptor leaks, etc. */
446 sim_module_uninstall (sd);
447 return 0;
448 }
449
450 /* handle board-specific memory maps */
451 if (board == NULL)
452 {
453 /* Allocate core managed memory */
454
455 /* start-sanitize-sky */
456 #ifndef TARGET_SKY
457 /* end-sanitize-sky */
458 /* the monitor */
459 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
460 /* For compatibility with the old code - under this (at level one)
461 are the kernel spaces K0 & K1. Both of these map to a single
462 smaller sub region */
463 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
464 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
465 K1BASE, K0SIZE,
466 MEM_SIZE, /* actual size */
467 K0BASE);
468 /* start-sanitize-sky */
469 #else
470 /* the monitor */
471 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE - K1BASE, MONITOR_SIZE);
472 sim_do_command (sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
473 /* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
474 address_translation() */
475 sim_do_commandf (sd, "memory size 0x%lx", MEM_SIZE);
476 #endif
477 /* end-sanitize-sky */
478
479 device_init(sd);
480 }
481
482 /* start-sanitize-tx3904 */
483 #if (WITH_HW)
484 if (board != NULL
485 && (strcmp(board, BOARD_JMR3904) == 0 ||
486 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
487 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
488 {
489 /* match VIRTUAL memory layout of JMR-TX3904 board */
490
491 /* --- memory --- */
492
493 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
494 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
495 0x9FC00000,
496 4 * 1024 * 1024, /* 4 MB */
497 0xBFC00000);
498
499 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
500 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
501 0x80000000,
502 4 * 1024 * 1024, /* 4 MB */
503 0xA0000000);
504
505 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
506 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
507 0x88000000,
508 32 * 1024 * 1024, /* 32 MB */
509 0xA8000000);
510
511 /* --- simulated devices --- */
512 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
513 sim_hw_parse (sd, "/tx3904cpu");
514 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
515 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
516 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
517
518 /* -- device connections --- */
519 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
520 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
521 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
522 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
523
524 /* add PAL timer & I/O module */
525 if(! strcmp(board, BOARD_JMR3904_PAL))
526 {
527 /* the device */
528 sim_hw_parse (sd, "/pal@0xffff0000");
529 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
530
531 /* wire up interrupt ports to irc */
532 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
533 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
534 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
535 }
536
537 if(! strcmp(board, BOARD_JMR3904_DEBUG))
538 {
539 /* -- DEBUG: glue interrupt generators --- */
540 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
541 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
542 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
543 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
544 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
545 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
546 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
547 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
548 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
549 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
550 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
551 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
552 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
553 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
554 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
555 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
556 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
557 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
558 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
559 }
560
561 device_init(sd);
562 }
563 #endif
564 /* end-sanitize-tx3904 */
565
566
567 /* check for/establish the a reference program image */
568 if (sim_analyze_program (sd,
569 (STATE_PROG_ARGV (sd) != NULL
570 ? *STATE_PROG_ARGV (sd)
571 : NULL),
572 abfd) != SIM_RC_OK)
573 {
574 sim_module_uninstall (sd);
575 return 0;
576 }
577
578 /* Configure/verify the target byte order and other runtime
579 configuration options */
580 if (sim_config (sd) != SIM_RC_OK)
581 {
582 sim_module_uninstall (sd);
583 return 0;
584 }
585
586 if (sim_post_argv_init (sd) != SIM_RC_OK)
587 {
588 /* Uninstall the modules to avoid memory leaks,
589 file descriptor leaks, etc. */
590 sim_module_uninstall (sd);
591 return 0;
592 }
593
594 /* verify assumptions the simulator made about the host type system.
595 This macro does not return if there is a problem */
596 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
597 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
598
599 /* This is NASTY, in that we are assuming the size of specific
600 registers: */
601 {
602 int rn;
603 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
604 {
605 if (rn < 32)
606 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
607 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
608 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
609 else if ((rn >= 33) && (rn <= 37))
610 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
611 else if ((rn == SRIDX)
612 || (rn == FCR0IDX)
613 || (rn == FCR31IDX)
614 || ((rn >= 72) && (rn <= 89)))
615 cpu->register_widths[rn] = 32;
616 else
617 cpu->register_widths[rn] = 0;
618 }
619 /* start-sanitize-r5900 */
620
621 /* set the 5900 "upper" registers to 64 bits */
622 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
623 cpu->register_widths[rn] = 64;
624 /* end-sanitize-r5900 */
625
626 /* start-sanitize-sky */
627 #ifdef TARGET_SKY
628 /* Now the VU registers */
629 for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
630 cpu->register_widths[rn + NUM_R5900_REGS] = 16;
631 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
632 }
633
634 for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
635 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
636 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
637 }
638
639 /* Finally the VIF registers */
640 for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
641 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
642
643 cpu->cur_device = 0;
644 #endif
645 /* end-sanitize-sky */
646 }
647
648 #if defined(TRACE)
649 if (STATE & simTRACE)
650 open_trace(sd);
651 #endif /* TRACE */
652
653 /* Write an abort sequence into the TRAP (common) exception vector
654 addresses. This is to catch code executing a TRAP (et.al.)
655 instruction without installing a trap handler. */
656 {
657 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
658 HALT_INSTRUCTION /* BREAK */ };
659 H2T (halt[0]);
660 H2T (halt[1]);
661 sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
662 sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
663 }
664
665
666 /* Write the monitor trap address handlers into the monitor (eeprom)
667 address space. This can only be done once the target endianness
668 has been determined. */
669 {
670 unsigned loop;
671 /* Entry into the IDT monitor is via fixed address vectors, and
672 not using machine instructions. To avoid clashing with use of
673 the MIPS TRAP system, we place our own (simulator specific)
674 "undefined" instructions into the relevant vector slots. */
675 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
676 {
677 address_word vaddr = (MONITOR_BASE + loop);
678 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
679 H2T (insn);
680 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
681 }
682 /* The PMON monitor uses the same address space, but rather than
683 branching into it the address of a routine is loaded. We can
684 cheat for the moment, and direct the PMON routine to IDT style
685 instructions within the monitor space. This relies on the IDT
686 monitor not using the locations from 0xBFC00500 onwards as its
687 entry points.*/
688 for (loop = 0; (loop < 24); loop++)
689 {
690 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
691 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
692 switch (loop)
693 {
694 case 0: /* read */
695 value = 7;
696 break;
697 case 1: /* write */
698 value = 8;
699 break;
700 case 2: /* open */
701 value = 6;
702 break;
703 case 3: /* close */
704 value = 10;
705 break;
706 case 5: /* printf */
707 value = ((0x500 - 16) / 8); /* not an IDT reason code */
708 break;
709 case 8: /* cliexit */
710 value = 17;
711 break;
712 case 11: /* flush_cache */
713 value = 28;
714 break;
715 }
716 /* FIXME - should monitor_base be SIM_ADDR?? */
717 value = ((unsigned int)MONITOR_BASE + (value * 8));
718 H2T (value);
719 sim_write (sd, vaddr, (char *)&value, sizeof (value));
720
721 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
722 vaddr -= 0x300;
723 sim_write (sd, vaddr, (char *)&value, sizeof (value));
724 }
725 }
726
727 return sd;
728 }
729
730 #if defined(TRACE)
731 static void
732 open_trace(sd)
733 SIM_DESC sd;
734 {
735 tracefh = fopen(tracefile,"wb+");
736 if (tracefh == NULL)
737 {
738 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
739 tracefh = stderr;
740 }
741 }
742 #endif /* TRACE */
743
744 void
745 sim_close (sd, quitting)
746 SIM_DESC sd;
747 int quitting;
748 {
749 #ifdef DEBUG
750 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
751 #endif
752
753 /* "quitting" is non-zero if we cannot hang on errors */
754
755 /* Ensure that any resources allocated through the callback
756 mechanism are released: */
757 sim_io_shutdown (sd);
758
759 #if defined(TRACE)
760 if (tracefh != NULL && tracefh != stderr)
761 fclose(tracefh);
762 tracefh = NULL;
763 #endif /* TRACE */
764
765 /* FIXME - free SD */
766
767 return;
768 }
769
770
771 int
772 sim_write (sd,addr,buffer,size)
773 SIM_DESC sd;
774 SIM_ADDR addr;
775 unsigned char *buffer;
776 int size;
777 {
778 int index;
779 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
780
781 /* Return the number of bytes written, or zero if error. */
782 #ifdef DEBUG
783 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
784 #endif
785
786 /* We use raw read and write routines, since we do not want to count
787 the GDB memory accesses in our statistics gathering. */
788
789 for (index = 0; index < size; index++)
790 {
791 address_word vaddr = (address_word)addr + index;
792 address_word paddr;
793 int cca;
794 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
795 break;
796 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
797 break;
798 }
799
800 return(index);
801 }
802
803 int
804 sim_read (sd,addr,buffer,size)
805 SIM_DESC sd;
806 SIM_ADDR addr;
807 unsigned char *buffer;
808 int size;
809 {
810 int index;
811 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
812
813 /* Return the number of bytes read, or zero if error. */
814 #ifdef DEBUG
815 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
816 #endif /* DEBUG */
817
818 for (index = 0; (index < size); index++)
819 {
820 address_word vaddr = (address_word)addr + index;
821 address_word paddr;
822 int cca;
823 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
824 break;
825 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
826 break;
827 }
828
829 return(index);
830 }
831
832 int
833 sim_store_register (sd,rn,memory,length)
834 SIM_DESC sd;
835 int rn;
836 unsigned char *memory;
837 int length;
838 {
839 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
840 /* NOTE: gdb (the client) stores registers in target byte order
841 while the simulator uses host byte order */
842 #ifdef DEBUG
843 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
844 #endif /* DEBUG */
845
846 /* Unfortunately this suffers from the same problem as the register
847 numbering one. We need to know what the width of each logical
848 register number is for the architecture being simulated. */
849
850 if (cpu->register_widths[rn] == 0)
851 {
852 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
853 return 0;
854 }
855
856 /* start-sanitize-r5900 */
857 if (rn >= 90 && rn < 90 + 32)
858 {
859 GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
860 return 8;
861 }
862 switch (rn)
863 {
864 case REGISTER_SA:
865 SA = T2H_8(*(unsigned64*)memory);
866 return 8;
867 case 122: /* FIXME */
868 LO1 = T2H_8(*(unsigned64*)memory);
869 return 8;
870 case 123: /* FIXME */
871 HI1 = T2H_8(*(unsigned64*)memory);
872 return 8;
873 }
874 /* end-sanitize-r5900 */
875
876 /* start-sanitize-sky */
877 #ifdef TARGET_SKY
878 if (rn >= NUM_R5900_REGS)
879 {
880 rn = rn - NUM_R5900_REGS;
881
882 if( rn < NUM_VU_REGS )
883 {
884 if (rn < NUM_VU_INTEGER_REGS)
885 return write_vu_int_reg (&(vu0_device.regs), rn, memory);
886 else if (rn >= FIRST_VEC_REG)
887 {
888 rn -= FIRST_VEC_REG;
889 return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
890 memory);
891 }
892 else switch (rn - NUM_VU_INTEGER_REGS)
893 {
894 case 0:
895 return write_vu_special_reg (&vu0_device, VU_REG_CIA,
896 memory);
897 case 1:
898 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
899 memory);
900 case 2: /* VU0 has no P register */
901 return 4;
902 case 3:
903 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
904 memory);
905 case 4:
906 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
907 memory);
908 default:
909 return write_vu_acc_reg (&(vu0_device.regs),
910 rn - (NUM_VU_INTEGER_REGS + 5),
911 memory);
912 }
913 }
914
915 rn = rn - NUM_VU_REGS;
916
917 if (rn < NUM_VU_REGS)
918 {
919 if (rn < NUM_VU_INTEGER_REGS)
920 return write_vu_int_reg (&(vu1_device.regs), rn, memory);
921 else if (rn >= FIRST_VEC_REG)
922 {
923 rn -= FIRST_VEC_REG;
924 return write_vu_vec_reg (&(vu1_device.regs),
925 rn >> 2, rn & 3, memory);
926 }
927 else switch (rn - NUM_VU_INTEGER_REGS)
928 {
929 case 0:
930 return write_vu_special_reg (&vu1_device, VU_REG_CIA,
931 memory);
932 case 1:
933 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
934 memory);
935 case 2:
936 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
937 memory);
938 case 3:
939 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
940 memory);
941 case 4:
942 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
943 memory);
944 default:
945 return write_vu_acc_reg (&(vu1_device.regs),
946 rn - (NUM_VU_INTEGER_REGS + 5),
947 memory);
948 }
949 }
950
951 rn -= NUM_VU_REGS; /* VIF0 registers are next */
952
953 if (rn < NUM_VIF_REGS)
954 {
955 if (rn < NUM_VIF_REGS-1)
956 return write_pke_reg (&pke0_device, rn, memory);
957 else
958 {
959 sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
960 return 0;
961 }
962 }
963
964 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
965
966 if (rn < NUM_VIF_REGS)
967 {
968 if (rn < NUM_VIF_REGS-1)
969 return write_pke_reg (&pke1_device, rn, memory);
970 else
971 {
972 sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
973 return 0;
974 }
975 }
976
977 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
978 return 0;
979 }
980 #endif
981 /* end-sanitize-sky */
982
983 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
984 {
985 if (cpu->register_widths[rn] == 32)
986 {
987 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
988 return 4;
989 }
990 else
991 {
992 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
993 return 8;
994 }
995 }
996
997 if (cpu->register_widths[rn] == 32)
998 {
999 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
1000 return 4;
1001 }
1002 else
1003 {
1004 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
1005 return 8;
1006 }
1007
1008 return 0;
1009 }
1010
1011 int
1012 sim_fetch_register (sd,rn,memory,length)
1013 SIM_DESC sd;
1014 int rn;
1015 unsigned char *memory;
1016 int length;
1017 {
1018 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
1019 /* NOTE: gdb (the client) stores registers in target byte order
1020 while the simulator uses host byte order */
1021 #ifdef DEBUG
1022 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
1023 #endif /* DEBUG */
1024
1025 if (cpu->register_widths[rn] == 0)
1026 {
1027 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
1028 return 0;
1029 }
1030
1031 /* start-sanitize-r5900 */
1032 if (rn >= 90 && rn < 90 + 32)
1033 {
1034 *((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
1035 return 8;
1036 }
1037 switch (rn)
1038 {
1039 case REGISTER_SA:
1040 *((unsigned64*)memory) = H2T_8(SA);
1041 return 8;
1042 case 122: /* FIXME */
1043 *((unsigned64*)memory) = H2T_8(LO1);
1044 return 8;
1045 case 123: /* FIXME */
1046 *((unsigned64*)memory) = H2T_8(HI1);
1047 return 8;
1048 }
1049 /* end-sanitize-r5900 */
1050
1051 /* start-sanitize-sky */
1052 #ifdef TARGET_SKY
1053 if (rn >= NUM_R5900_REGS)
1054 {
1055 rn = rn - NUM_R5900_REGS;
1056
1057 if (rn < NUM_VU_REGS)
1058 {
1059 if (rn < NUM_VU_INTEGER_REGS)
1060 return read_vu_int_reg (&(vu0_device.regs), rn, memory);
1061 else if (rn >= FIRST_VEC_REG)
1062 {
1063 rn -= FIRST_VEC_REG;
1064 return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
1065 memory);
1066 }
1067 else switch (rn - NUM_VU_INTEGER_REGS)
1068 {
1069 case 0:
1070 return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
1071 case 1:
1072 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
1073 memory);
1074 case 2: /* VU0 has no P register */
1075 *((int *) memory) = 0;
1076 return 4;
1077 case 3:
1078 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
1079 memory);
1080 case 4:
1081 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
1082 memory);
1083 default:
1084 return read_vu_acc_reg (&(vu0_device.regs),
1085 rn - (NUM_VU_INTEGER_REGS + 5),
1086 memory);
1087 }
1088 }
1089
1090 rn -= NUM_VU_REGS; /* VU1 registers are next */
1091
1092 if (rn < NUM_VU_REGS)
1093 {
1094 if (rn < NUM_VU_INTEGER_REGS)
1095 return read_vu_int_reg (&(vu1_device.regs), rn, memory);
1096 else if (rn >= FIRST_VEC_REG)
1097 {
1098 rn -= FIRST_VEC_REG;
1099 return read_vu_vec_reg (&(vu1_device.regs),
1100 rn >> 2, rn & 3, memory);
1101 }
1102 else switch (rn - NUM_VU_INTEGER_REGS)
1103 {
1104 case 0:
1105 return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
1106 case 1:
1107 return read_vu_misc_reg (&(vu1_device.regs),
1108 VU_REG_MR, memory);
1109 case 2:
1110 return read_vu_misc_reg (&(vu1_device.regs),
1111 VU_REG_MP, memory);
1112 case 3:
1113 return read_vu_misc_reg (&(vu1_device.regs),
1114 VU_REG_MI, memory);
1115 case 4:
1116 return read_vu_misc_reg (&(vu1_device.regs),
1117 VU_REG_MQ, memory);
1118 default:
1119 return read_vu_acc_reg (&(vu1_device.regs),
1120 rn - (NUM_VU_INTEGER_REGS + 5),
1121 memory);
1122 }
1123 }
1124
1125 rn -= NUM_VU_REGS; /* VIF0 registers are next */
1126
1127 if (rn < NUM_VIF_REGS)
1128 {
1129 if (rn < NUM_VIF_REGS-1)
1130 return read_pke_reg (&pke0_device, rn, memory);
1131 else
1132 return read_pke_pc (&pke0_device, memory);
1133 }
1134
1135 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
1136
1137 if (rn < NUM_VIF_REGS)
1138 {
1139 if (rn < NUM_VIF_REGS-1)
1140 return read_pke_reg (&pke1_device, rn, memory);
1141 else
1142 return read_pke_pc (&pke1_device, memory);
1143 }
1144
1145 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
1146 }
1147 #endif
1148 /* end-sanitize-sky */
1149
1150 /* Any floating point register */
1151 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
1152 {
1153 if (cpu->register_widths[rn] == 32)
1154 {
1155 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
1156 return 4;
1157 }
1158 else
1159 {
1160 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
1161 return 8;
1162 }
1163 }
1164
1165 if (cpu->register_widths[rn] == 32)
1166 {
1167 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1168 return 4;
1169 }
1170 else
1171 {
1172 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
1173 return 8;
1174 }
1175
1176 return 0;
1177 }
1178
1179
1180 SIM_RC
1181 sim_create_inferior (sd, abfd, argv,env)
1182 SIM_DESC sd;
1183 struct _bfd *abfd;
1184 char **argv;
1185 char **env;
1186 {
1187
1188 #ifdef DEBUG
1189 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1190 pr_addr(PC));
1191 #endif /* DEBUG */
1192
1193 ColdReset(sd);
1194
1195 if (abfd != NULL)
1196 {
1197 /* override PC value set by ColdReset () */
1198 int cpu_nr;
1199 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1200 {
1201 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1202 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1203 }
1204 }
1205
1206 #if 0 /* def DEBUG */
1207 if (argv || env)
1208 {
1209 /* We should really place the argv slot values into the argument
1210 registers, and onto the stack as required. However, this
1211 assumes that we have a stack defined, which is not
1212 necessarily true at the moment. */
1213 char **cptr;
1214 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1215 for (cptr = argv; (cptr && *cptr); cptr++)
1216 printf("DBG: arg \"%s\"\n",*cptr);
1217 }
1218 #endif /* DEBUG */
1219
1220 return SIM_RC_OK;
1221 }
1222
1223 void
1224 sim_do_command (sd,cmd)
1225 SIM_DESC sd;
1226 char *cmd;
1227 {
1228 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1229 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1230 cmd);
1231 }
1232
1233 /*---------------------------------------------------------------------------*/
1234 /*-- Private simulator support interface ------------------------------------*/
1235 /*---------------------------------------------------------------------------*/
1236
1237 /* Read a null terminated string from memory, return in a buffer */
1238 static char *
1239 fetch_str (sd, addr)
1240 SIM_DESC sd;
1241 address_word addr;
1242 {
1243 char *buf;
1244 int nr = 0;
1245 char null;
1246 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1247 nr++;
1248 buf = NZALLOC (char, nr + 1);
1249 sim_read (sd, addr, buf, nr);
1250 return buf;
1251 }
1252
1253 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1254 static void
1255 sim_monitor (SIM_DESC sd,
1256 sim_cpu *cpu,
1257 address_word cia,
1258 unsigned int reason)
1259 {
1260 #ifdef DEBUG
1261 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1262 #endif /* DEBUG */
1263
1264 /* The IDT monitor actually allows two instructions per vector
1265 slot. However, the simulator currently causes a trap on each
1266 individual instruction. We cheat, and lose the bottom bit. */
1267 reason >>= 1;
1268
1269 /* The following callback functions are available, however the
1270 monitor we are simulating does not make use of them: get_errno,
1271 isatty, lseek, rename, system, time and unlink */
1272 switch (reason)
1273 {
1274
1275 case 6: /* int open(char *path,int flags) */
1276 {
1277 char *path = fetch_str (sd, A0);
1278 V0 = sim_io_open (sd, path, (int)A1);
1279 zfree (path);
1280 break;
1281 }
1282
1283 case 7: /* int read(int file,char *ptr,int len) */
1284 {
1285 int fd = A0;
1286 int nr = A2;
1287 char *buf = zalloc (nr);
1288 V0 = sim_io_read (sd, fd, buf, nr);
1289 sim_write (sd, A1, buf, nr);
1290 zfree (buf);
1291 }
1292 break;
1293
1294 case 8: /* int write(int file,char *ptr,int len) */
1295 {
1296 int fd = A0;
1297 int nr = A2;
1298 char *buf = zalloc (nr);
1299 sim_read (sd, A1, buf, nr);
1300 V0 = sim_io_write (sd, fd, buf, nr);
1301 zfree (buf);
1302 break;
1303 }
1304
1305 case 10: /* int close(int file) */
1306 {
1307 V0 = sim_io_close (sd, (int)A0);
1308 break;
1309 }
1310
1311 case 2: /* Densan monitor: char inbyte(int waitflag) */
1312 {
1313 if (A0 == 0) /* waitflag == NOWAIT */
1314 V0 = (unsigned_word)-1;
1315 }
1316 /* Drop through to case 11 */
1317
1318 case 11: /* char inbyte(void) */
1319 {
1320 char tmp;
1321 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1322 {
1323 sim_io_error(sd,"Invalid return from character read");
1324 V0 = (unsigned_word)-1;
1325 }
1326 else
1327 V0 = (unsigned_word)tmp;
1328 break;
1329 }
1330
1331 case 3: /* Densan monitor: void co(char chr) */
1332 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1333 {
1334 char tmp = (char)(A0 & 0xFF);
1335 sim_io_write_stdout (sd, &tmp, sizeof(char));
1336 break;
1337 }
1338
1339 case 17: /* void _exit() */
1340 {
1341 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1342 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1343 (unsigned int)(A0 & 0xFFFFFFFF));
1344 break;
1345 }
1346
1347 case 28 : /* PMON flush_cache */
1348 break;
1349
1350 case 55: /* void get_mem_info(unsigned int *ptr) */
1351 /* in: A0 = pointer to three word memory location */
1352 /* out: [A0 + 0] = size */
1353 /* [A0 + 4] = instruction cache size */
1354 /* [A0 + 8] = data cache size */
1355 {
1356 unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
1357 unsigned_4 zero = 0;
1358 H2T (value);
1359 sim_write (sd, A0 + 0, (char *)&value, 4);
1360 sim_write (sd, A0 + 4, (char *)&zero, 4);
1361 sim_write (sd, A0 + 8, (char *)&zero, 4);
1362 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1363 break;
1364 }
1365
1366 case 158 : /* PMON printf */
1367 /* in: A0 = pointer to format string */
1368 /* A1 = optional argument 1 */
1369 /* A2 = optional argument 2 */
1370 /* A3 = optional argument 3 */
1371 /* out: void */
1372 /* The following is based on the PMON printf source */
1373 {
1374 address_word s = A0;
1375 char c;
1376 signed_word *ap = &A1; /* 1st argument */
1377 /* This isn't the quickest way, since we call the host print
1378 routine for every character almost. But it does avoid
1379 having to allocate and manage a temporary string buffer. */
1380 /* TODO: Include check that we only use three arguments (A1,
1381 A2 and A3) */
1382 while (sim_read (sd, s++, &c, 1) && c != '\0')
1383 {
1384 if (c == '%')
1385 {
1386 char tmp[40];
1387 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1388 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1389 while (sim_read (sd, s++, &c, 1) && c != '\0')
1390 {
1391 if (strchr ("dobxXulscefg%", c))
1392 break;
1393 else if (c == '-')
1394 fmt = FMT_LJUST;
1395 else if (c == '0')
1396 fmt = FMT_RJUST0;
1397 else if (c == '~')
1398 fmt = FMT_CENTER;
1399 else if (c == '*')
1400 {
1401 if (haddot)
1402 trunc = (int)*ap++;
1403 else
1404 width = (int)*ap++;
1405 }
1406 else if (c >= '1' && c <= '9')
1407 {
1408 address_word t = s;
1409 unsigned int n;
1410 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1411 tmp[s - t] = c;
1412 tmp[s - t] = '\0';
1413 n = (unsigned int)strtol(tmp,NULL,10);
1414 if (haddot)
1415 trunc = n;
1416 else
1417 width = n;
1418 s--;
1419 }
1420 else if (c == '.')
1421 haddot = 1;
1422 }
1423 switch (c)
1424 {
1425 case '%':
1426 sim_io_printf (sd, "%%");
1427 break;
1428 case 's':
1429 if ((int)*ap != 0)
1430 {
1431 address_word p = *ap++;
1432 char ch;
1433 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1434 sim_io_printf(sd, "%c", ch);
1435 }
1436 else
1437 sim_io_printf(sd,"(null)");
1438 break;
1439 case 'c':
1440 sim_io_printf (sd, "%c", (int)*ap++);
1441 break;
1442 default:
1443 if (c == 'l')
1444 {
1445 sim_read (sd, s++, &c, 1);
1446 if (c == 'l')
1447 {
1448 longlong = 1;
1449 sim_read (sd, s++, &c, 1);
1450 }
1451 }
1452 if (strchr ("dobxXu", c))
1453 {
1454 word64 lv = (word64) *ap++;
1455 if (c == 'b')
1456 sim_io_printf(sd,"<binary not supported>");
1457 else
1458 {
1459 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1460 if (longlong)
1461 sim_io_printf(sd, tmp, lv);
1462 else
1463 sim_io_printf(sd, tmp, (int)lv);
1464 }
1465 }
1466 else if (strchr ("eEfgG", c))
1467 {
1468 double dbl = *(double*)(ap++);
1469 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1470 sim_io_printf (sd, tmp, dbl);
1471 trunc = 0;
1472 }
1473 }
1474 }
1475 else
1476 sim_io_printf(sd, "%c", c);
1477 }
1478 break;
1479 }
1480
1481 default:
1482 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1483 reason, pr_addr(cia));
1484 break;
1485 }
1486 return;
1487 }
1488
1489 /* Store a word into memory. */
1490
1491 static void
1492 store_word (SIM_DESC sd,
1493 sim_cpu *cpu,
1494 address_word cia,
1495 uword64 vaddr,
1496 signed_word val)
1497 {
1498 address_word paddr;
1499 int uncached;
1500
1501 if ((vaddr & 3) != 0)
1502 SignalExceptionAddressStore ();
1503 else
1504 {
1505 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1506 isTARGET, isREAL))
1507 {
1508 const uword64 mask = 7;
1509 uword64 memval;
1510 unsigned int byte;
1511
1512 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1513 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1514 memval = ((uword64) val) << (8 * byte);
1515 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1516 isREAL);
1517 }
1518 }
1519 }
1520
1521 /* Load a word from memory. */
1522
1523 static signed_word
1524 load_word (SIM_DESC sd,
1525 sim_cpu *cpu,
1526 address_word cia,
1527 uword64 vaddr)
1528 {
1529 if ((vaddr & 3) != 0)
1530 SignalExceptionAddressLoad ();
1531 else
1532 {
1533 address_word paddr;
1534 int uncached;
1535
1536 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1537 isTARGET, isREAL))
1538 {
1539 const uword64 mask = 0x7;
1540 const unsigned int reverse = ReverseEndian ? 1 : 0;
1541 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1542 uword64 memval;
1543 unsigned int byte;
1544
1545 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1546 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1547 isDATA, isREAL);
1548 byte = (vaddr & mask) ^ (bigend << 2);
1549 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1550 }
1551 }
1552
1553 return 0;
1554 }
1555
1556 /* Simulate the mips16 entry and exit pseudo-instructions. These
1557 would normally be handled by the reserved instruction exception
1558 code, but for ease of simulation we just handle them directly. */
1559
1560 static void
1561 mips16_entry (SIM_DESC sd,
1562 sim_cpu *cpu,
1563 address_word cia,
1564 unsigned int insn)
1565 {
1566 int aregs, sregs, rreg;
1567
1568 #ifdef DEBUG
1569 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1570 #endif /* DEBUG */
1571
1572 aregs = (insn & 0x700) >> 8;
1573 sregs = (insn & 0x0c0) >> 6;
1574 rreg = (insn & 0x020) >> 5;
1575
1576 /* This should be checked by the caller. */
1577 if (sregs == 3)
1578 abort ();
1579
1580 if (aregs < 5)
1581 {
1582 int i;
1583 signed_word tsp;
1584
1585 /* This is the entry pseudo-instruction. */
1586
1587 for (i = 0; i < aregs; i++)
1588 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1589
1590 tsp = SP;
1591 SP -= 32;
1592
1593 if (rreg)
1594 {
1595 tsp -= 4;
1596 store_word (SD, CPU, cia, (uword64) tsp, RA);
1597 }
1598
1599 for (i = 0; i < sregs; i++)
1600 {
1601 tsp -= 4;
1602 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1603 }
1604 }
1605 else
1606 {
1607 int i;
1608 signed_word tsp;
1609
1610 /* This is the exit pseudo-instruction. */
1611
1612 tsp = SP + 32;
1613
1614 if (rreg)
1615 {
1616 tsp -= 4;
1617 RA = load_word (SD, CPU, cia, (uword64) tsp);
1618 }
1619
1620 for (i = 0; i < sregs; i++)
1621 {
1622 tsp -= 4;
1623 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1624 }
1625
1626 SP += 32;
1627
1628 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1629 {
1630 if (aregs == 5)
1631 {
1632 FGR[0] = WORD64LO (GPR[4]);
1633 FPR_STATE[0] = fmt_uninterpreted;
1634 }
1635 else if (aregs == 6)
1636 {
1637 FGR[0] = WORD64LO (GPR[5]);
1638 FGR[1] = WORD64LO (GPR[4]);
1639 FPR_STATE[0] = fmt_uninterpreted;
1640 FPR_STATE[1] = fmt_uninterpreted;
1641 }
1642 }
1643
1644 PC = RA;
1645 }
1646
1647 }
1648
1649 /*-- trace support ----------------------------------------------------------*/
1650
1651 /* The TRACE support is provided (if required) in the memory accessing
1652 routines. Since we are also providing the architecture specific
1653 features, the architecture simulation code can also deal with
1654 notifying the TRACE world of cache flushes, etc. Similarly we do
1655 not need to provide profiling support in the simulator engine,
1656 since we can sample in the instruction fetch control loop. By
1657 defining the TRACE manifest, we add tracing as a run-time
1658 option. */
1659
1660 #if defined(TRACE)
1661 /* Tracing by default produces "din" format (as required by
1662 dineroIII). Each line of such a trace file *MUST* have a din label
1663 and address field. The rest of the line is ignored, so comments can
1664 be included if desired. The first field is the label which must be
1665 one of the following values:
1666
1667 0 read data
1668 1 write data
1669 2 instruction fetch
1670 3 escape record (treated as unknown access type)
1671 4 escape record (causes cache flush)
1672
1673 The address field is a 32bit (lower-case) hexadecimal address
1674 value. The address should *NOT* be preceded by "0x".
1675
1676 The size of the memory transfer is not important when dealing with
1677 cache lines (as long as no more than a cache line can be
1678 transferred in a single operation :-), however more information
1679 could be given following the dineroIII requirement to allow more
1680 complete memory and cache simulators to provide better
1681 results. i.e. the University of Pisa has a cache simulator that can
1682 also take bus size and speed as (variable) inputs to calculate
1683 complete system performance (a much more useful ability when trying
1684 to construct an end product, rather than a processor). They
1685 currently have an ARM version of their tool called ChARM. */
1686
1687
1688 void
1689 dotrace (SIM_DESC sd,
1690 sim_cpu *cpu,
1691 FILE *tracefh,
1692 int type,
1693 SIM_ADDR address,
1694 int width,
1695 char *comment,...)
1696 {
1697 if (STATE & simTRACE) {
1698 va_list ap;
1699 fprintf(tracefh,"%d %s ; width %d ; ",
1700 type,
1701 pr_addr(address),
1702 width);
1703 va_start(ap,comment);
1704 vfprintf(tracefh,comment,ap);
1705 va_end(ap);
1706 fprintf(tracefh,"\n");
1707 }
1708 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1709 we may be generating 64bit ones, we should put the hi-32bits of the
1710 address into the comment field. */
1711
1712 /* TODO: Provide a buffer for the trace lines. We can then avoid
1713 performing writes until the buffer is filled, or the file is
1714 being closed. */
1715
1716 /* NOTE: We could consider adding a comment field to the "din" file
1717 produced using type 3 markers (unknown access). This would then
1718 allow information about the program that the "din" is for, and
1719 the MIPs world that was being simulated, to be placed into the
1720 trace file. */
1721
1722 return;
1723 }
1724 #endif /* TRACE */
1725
1726 /*---------------------------------------------------------------------------*/
1727 /*-- simulator engine -------------------------------------------------------*/
1728 /*---------------------------------------------------------------------------*/
1729
1730 static void
1731 ColdReset (SIM_DESC sd)
1732 {
1733 int cpu_nr;
1734 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1735 {
1736 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1737 /* RESET: Fixed PC address: */
1738 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1739 /* The reset vector address is in the unmapped, uncached memory space. */
1740
1741 SR &= ~(status_SR | status_TS | status_RP);
1742 SR |= (status_ERL | status_BEV);
1743
1744 /* Cheat and allow access to the complete register set immediately */
1745 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1746 && WITH_TARGET_WORD_BITSIZE == 64)
1747 SR |= status_FR; /* 64bit registers */
1748
1749 /* Ensure that any instructions with pending register updates are
1750 cleared: */
1751 PENDING_INVALIDATE();
1752
1753 /* Initialise the FPU registers to the unknown state */
1754 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1755 {
1756 int rn;
1757 for (rn = 0; (rn < 32); rn++)
1758 FPR_STATE[rn] = fmt_uninterpreted;
1759 }
1760
1761 }
1762 }
1763
1764 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1765 /* Signal an exception condition. This will result in an exception
1766 that aborts the instruction. The instruction operation pseudocode
1767 will never see a return from this function call. */
1768
1769 void
1770 signal_exception (SIM_DESC sd,
1771 sim_cpu *cpu,
1772 address_word cia,
1773 int exception,...)
1774 {
1775 /* int vector; */
1776
1777 #ifdef DEBUG
1778 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1779 #endif /* DEBUG */
1780
1781 /* Ensure that any active atomic read/modify/write operation will fail: */
1782 LLBIT = 0;
1783
1784 switch (exception) {
1785
1786 case DebugBreakPoint :
1787 if (! (Debug & Debug_DM))
1788 {
1789 if (INDELAYSLOT())
1790 {
1791 CANCELDELAYSLOT();
1792
1793 Debug |= Debug_DBD; /* signaled from within in delay slot */
1794 DEPC = cia - 4; /* reference the branch instruction */
1795 }
1796 else
1797 {
1798 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1799 DEPC = cia;
1800 }
1801
1802 Debug |= Debug_DM; /* in debugging mode */
1803 Debug |= Debug_DBp; /* raising a DBp exception */
1804 PC = 0xBFC00200;
1805 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1806 }
1807 break;
1808
1809 case ReservedInstruction :
1810 {
1811 va_list ap;
1812 unsigned int instruction;
1813 va_start(ap,exception);
1814 instruction = va_arg(ap,unsigned int);
1815 va_end(ap);
1816 /* Provide simple monitor support using ReservedInstruction
1817 exceptions. The following code simulates the fixed vector
1818 entry points into the IDT monitor by causing a simulator
1819 trap, performing the monitor operation, and returning to
1820 the address held in the $ra register (standard PCS return
1821 address). This means we only need to pre-load the vector
1822 space with suitable instruction values. For systems were
1823 actual trap instructions are used, we would not need to
1824 perform this magic. */
1825 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1826 {
1827 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1828 /* NOTE: This assumes that a branch-and-link style
1829 instruction was used to enter the vector (which is the
1830 case with the current IDT monitor). */
1831 sim_engine_restart (SD, CPU, NULL, RA);
1832 }
1833 /* Look for the mips16 entry and exit instructions, and
1834 simulate a handler for them. */
1835 else if ((cia & 1) != 0
1836 && (instruction & 0xf81f) == 0xe809
1837 && (instruction & 0x0c0) != 0x0c0)
1838 {
1839 mips16_entry (SD, CPU, cia, instruction);
1840 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1841 }
1842 /* else fall through to normal exception processing */
1843 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1844 }
1845
1846 default:
1847 /* Store exception code into current exception id variable (used
1848 by exit code): */
1849
1850 /* TODO: If not simulating exceptions then stop the simulator
1851 execution. At the moment we always stop the simulation. */
1852
1853 #ifdef SUBTARGET_R3900
1854 /* update interrupt-related registers */
1855
1856 /* insert exception code in bits 6:2 */
1857 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1858 /* shift IE/KU history bits left */
1859 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1860
1861 if (STATE & simDELAYSLOT)
1862 {
1863 STATE &= ~simDELAYSLOT;
1864 CAUSE |= cause_BD;
1865 EPC = (cia - 4); /* reference the branch instruction */
1866 }
1867 else
1868 EPC = cia;
1869
1870 if (SR & status_BEV)
1871 PC = (signed)0xBFC00000 + 0x180;
1872 else
1873 PC = (signed)0x80000000 + 0x080;
1874 #else
1875 /* See figure 5-17 for an outline of the code below */
1876 if (! (SR & status_EXL))
1877 {
1878 CAUSE = (exception << 2);
1879 if (STATE & simDELAYSLOT)
1880 {
1881 STATE &= ~simDELAYSLOT;
1882 CAUSE |= cause_BD;
1883 EPC = (cia - 4); /* reference the branch instruction */
1884 }
1885 else
1886 EPC = cia;
1887 /* FIXME: TLB et.al. */
1888 /* vector = 0x180; */
1889 }
1890 else
1891 {
1892 CAUSE = (exception << 2);
1893 /* vector = 0x180; */
1894 }
1895 SR |= status_EXL;
1896 /* Store exception code into current exception id variable (used
1897 by exit code): */
1898
1899 if (SR & status_BEV)
1900 PC = (signed)0xBFC00200 + 0x180;
1901 else
1902 PC = (signed)0x80000000 + 0x180;
1903 #endif
1904
1905 switch ((CAUSE >> 2) & 0x1F)
1906 {
1907 case Interrupt:
1908 /* Interrupts arrive during event processing, no need to
1909 restart */
1910 return;
1911
1912 case NMIReset:
1913 /* Ditto */
1914 #ifdef SUBTARGET_3900
1915 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1916 PC = (signed)0xBFC00000;
1917 #endif SUBTARGET_3900
1918 return;
1919
1920 case TLBModification:
1921 case TLBLoad:
1922 case TLBStore:
1923 case AddressLoad:
1924 case AddressStore:
1925 case InstructionFetch:
1926 case DataReference:
1927 /* The following is so that the simulator will continue from the
1928 exception address on breakpoint operations. */
1929 PC = EPC;
1930 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1931 sim_stopped, SIM_SIGBUS);
1932
1933 case ReservedInstruction:
1934 case CoProcessorUnusable:
1935 PC = EPC;
1936 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1937 sim_stopped, SIM_SIGILL);
1938
1939 case IntegerOverflow:
1940 case FPE:
1941 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1942 sim_stopped, SIM_SIGFPE);
1943
1944 case BreakPoint:
1945 case SystemCall:
1946 case Trap:
1947 sim_engine_restart (SD, CPU, NULL, PC);
1948 break;
1949
1950 case Watch:
1951 PC = EPC;
1952 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1953 sim_stopped, SIM_SIGTRAP);
1954
1955 default : /* Unknown internal exception */
1956 PC = EPC;
1957 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1958 sim_stopped, SIM_SIGABRT);
1959
1960 }
1961
1962 case SimulatorFault:
1963 {
1964 va_list ap;
1965 char *msg;
1966 va_start(ap,exception);
1967 msg = va_arg(ap,char *);
1968 va_end(ap);
1969 sim_engine_abort (SD, CPU, NULL_CIA,
1970 "FATAL: Simulator error \"%s\"\n",msg);
1971 }
1972 }
1973
1974 return;
1975 }
1976
1977 #if defined(WARN_RESULT)
1978 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1979 /* This function indicates that the result of the operation is
1980 undefined. However, this should not affect the instruction
1981 stream. All that is meant to happen is that the destination
1982 register is set to an undefined result. To keep the simulator
1983 simple, we just don't bother updating the destination register, so
1984 the overall result will be undefined. If desired we can stop the
1985 simulator by raising a pseudo-exception. */
1986 #define UndefinedResult() undefined_result (sd,cia)
1987 static void
1988 undefined_result(sd,cia)
1989 SIM_DESC sd;
1990 address_word cia;
1991 {
1992 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
1993 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1994 state |= simSTOP;
1995 #endif
1996 return;
1997 }
1998 #endif /* WARN_RESULT */
1999
2000 /*-- FPU support routines ---------------------------------------------------*/
2001
2002 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2003 formats conform to ANSI/IEEE Std 754-1985. */
2004 /* SINGLE precision floating:
2005 * seeeeeeeefffffffffffffffffffffff
2006 * s = 1bit = sign
2007 * e = 8bits = exponent
2008 * f = 23bits = fraction
2009 */
2010 /* SINGLE precision fixed:
2011 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2012 * s = 1bit = sign
2013 * i = 31bits = integer
2014 */
2015 /* DOUBLE precision floating:
2016 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2017 * s = 1bit = sign
2018 * e = 11bits = exponent
2019 * f = 52bits = fraction
2020 */
2021 /* DOUBLE precision fixed:
2022 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2023 * s = 1bit = sign
2024 * i = 63bits = integer
2025 */
2026
2027 /* Extract sign-bit: */
2028 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2029 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2030 /* Extract biased exponent: */
2031 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2032 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2033 /* Extract unbiased Exponent: */
2034 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2035 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2036 /* Extract complete fraction field: */
2037 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2038 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2039 /* Extract numbered fraction bit: */
2040 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2041 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2042
2043 /* Explicit QNaN values used when value required: */
2044 #define FPQNaN_SINGLE (0x7FBFFFFF)
2045 #define FPQNaN_WORD (0x7FFFFFFF)
2046 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2047 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2048
2049 /* Explicit Infinity values used when required: */
2050 #define FPINF_SINGLE (0x7F800000)
2051 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2052
2053 #if 1 /* def DEBUG */
2054 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2055 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2056 #endif /* DEBUG */
2057
2058 uword64
2059 value_fpr (SIM_DESC sd,
2060 sim_cpu *cpu,
2061 address_word cia,
2062 int fpr,
2063 FP_formats fmt)
2064 {
2065 uword64 value = 0;
2066 int err = 0;
2067
2068 /* Treat unused register values, as fixed-point 64bit values: */
2069 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
2070 #if 1
2071 /* If request to read data as "uninterpreted", then use the current
2072 encoding: */
2073 fmt = FPR_STATE[fpr];
2074 #else
2075 fmt = fmt_long;
2076 #endif
2077
2078 /* For values not yet accessed, set to the desired format: */
2079 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2080 FPR_STATE[fpr] = fmt;
2081 #ifdef DEBUG
2082 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2083 #endif /* DEBUG */
2084 }
2085 if (fmt != FPR_STATE[fpr]) {
2086 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2087 FPR_STATE[fpr] = fmt_unknown;
2088 }
2089
2090 if (FPR_STATE[fpr] == fmt_unknown) {
2091 /* Set QNaN value: */
2092 switch (fmt) {
2093 case fmt_single:
2094 value = FPQNaN_SINGLE;
2095 break;
2096
2097 case fmt_double:
2098 value = FPQNaN_DOUBLE;
2099 break;
2100
2101 case fmt_word:
2102 value = FPQNaN_WORD;
2103 break;
2104
2105 case fmt_long:
2106 value = FPQNaN_LONG;
2107 break;
2108
2109 default:
2110 err = -1;
2111 break;
2112 }
2113 } else if (SizeFGR() == 64) {
2114 switch (fmt) {
2115 case fmt_single:
2116 case fmt_word:
2117 value = (FGR[fpr] & 0xFFFFFFFF);
2118 break;
2119
2120 case fmt_uninterpreted:
2121 case fmt_double:
2122 case fmt_long:
2123 value = FGR[fpr];
2124 break;
2125
2126 default :
2127 err = -1;
2128 break;
2129 }
2130 } else {
2131 switch (fmt) {
2132 case fmt_single:
2133 case fmt_word:
2134 value = (FGR[fpr] & 0xFFFFFFFF);
2135 break;
2136
2137 case fmt_uninterpreted:
2138 case fmt_double:
2139 case fmt_long:
2140 if ((fpr & 1) == 0) { /* even registers only */
2141 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2142 } else {
2143 SignalException(ReservedInstruction,0);
2144 }
2145 break;
2146
2147 default :
2148 err = -1;
2149 break;
2150 }
2151 }
2152
2153 if (err)
2154 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2155
2156 #ifdef DEBUG
2157 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2158 #endif /* DEBUG */
2159
2160 return(value);
2161 }
2162
2163 void
2164 store_fpr (SIM_DESC sd,
2165 sim_cpu *cpu,
2166 address_word cia,
2167 int fpr,
2168 FP_formats fmt,
2169 uword64 value)
2170 {
2171 int err = 0;
2172
2173 #ifdef DEBUG
2174 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2175 #endif /* DEBUG */
2176
2177 if (SizeFGR() == 64) {
2178 switch (fmt) {
2179 case fmt_uninterpreted_32:
2180 fmt = fmt_uninterpreted;
2181 case fmt_single :
2182 case fmt_word :
2183 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2184 FPR_STATE[fpr] = fmt;
2185 break;
2186
2187 case fmt_uninterpreted_64:
2188 fmt = fmt_uninterpreted;
2189 case fmt_uninterpreted:
2190 case fmt_double :
2191 case fmt_long :
2192 FGR[fpr] = value;
2193 FPR_STATE[fpr] = fmt;
2194 break;
2195
2196 default :
2197 FPR_STATE[fpr] = fmt_unknown;
2198 err = -1;
2199 break;
2200 }
2201 } else {
2202 switch (fmt) {
2203 case fmt_uninterpreted_32:
2204 fmt = fmt_uninterpreted;
2205 case fmt_single :
2206 case fmt_word :
2207 FGR[fpr] = (value & 0xFFFFFFFF);
2208 FPR_STATE[fpr] = fmt;
2209 break;
2210
2211 case fmt_uninterpreted_64:
2212 fmt = fmt_uninterpreted;
2213 case fmt_uninterpreted:
2214 case fmt_double :
2215 case fmt_long :
2216 if ((fpr & 1) == 0) { /* even register number only */
2217 FGR[fpr+1] = (value >> 32);
2218 FGR[fpr] = (value & 0xFFFFFFFF);
2219 FPR_STATE[fpr + 1] = fmt;
2220 FPR_STATE[fpr] = fmt;
2221 } else {
2222 FPR_STATE[fpr] = fmt_unknown;
2223 FPR_STATE[fpr + 1] = fmt_unknown;
2224 SignalException(ReservedInstruction,0);
2225 }
2226 break;
2227
2228 default :
2229 FPR_STATE[fpr] = fmt_unknown;
2230 err = -1;
2231 break;
2232 }
2233 }
2234 #if defined(WARN_RESULT)
2235 else
2236 UndefinedResult();
2237 #endif /* WARN_RESULT */
2238
2239 if (err)
2240 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2241
2242 #ifdef DEBUG
2243 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2244 #endif /* DEBUG */
2245
2246 return;
2247 }
2248
2249 int
2250 NaN(op,fmt)
2251 uword64 op;
2252 FP_formats fmt;
2253 {
2254 int boolean = 0;
2255 switch (fmt) {
2256 case fmt_single:
2257 case fmt_word:
2258 {
2259 sim_fpu wop;
2260 sim_fpu_32to (&wop, op);
2261 boolean = sim_fpu_is_nan (&wop);
2262 break;
2263 }
2264 case fmt_double:
2265 case fmt_long:
2266 {
2267 sim_fpu wop;
2268 sim_fpu_64to (&wop, op);
2269 boolean = sim_fpu_is_nan (&wop);
2270 break;
2271 }
2272 default:
2273 fprintf (stderr, "Bad switch\n");
2274 abort ();
2275 }
2276
2277 #ifdef DEBUG
2278 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2279 #endif /* DEBUG */
2280
2281 return(boolean);
2282 }
2283
2284 int
2285 Infinity(op,fmt)
2286 uword64 op;
2287 FP_formats fmt;
2288 {
2289 int boolean = 0;
2290
2291 #ifdef DEBUG
2292 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2293 #endif /* DEBUG */
2294
2295 switch (fmt) {
2296 case fmt_single:
2297 {
2298 sim_fpu wop;
2299 sim_fpu_32to (&wop, op);
2300 boolean = sim_fpu_is_infinity (&wop);
2301 break;
2302 }
2303 case fmt_double:
2304 {
2305 sim_fpu wop;
2306 sim_fpu_64to (&wop, op);
2307 boolean = sim_fpu_is_infinity (&wop);
2308 break;
2309 }
2310 default:
2311 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2312 break;
2313 }
2314
2315 #ifdef DEBUG
2316 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2317 #endif /* DEBUG */
2318
2319 return(boolean);
2320 }
2321
2322 int
2323 Less(op1,op2,fmt)
2324 uword64 op1;
2325 uword64 op2;
2326 FP_formats fmt;
2327 {
2328 int boolean = 0;
2329
2330 /* Argument checking already performed by the FPCOMPARE code */
2331
2332 #ifdef DEBUG
2333 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2334 #endif /* DEBUG */
2335
2336 /* The format type should already have been checked: */
2337 switch (fmt) {
2338 case fmt_single:
2339 {
2340 sim_fpu wop1;
2341 sim_fpu wop2;
2342 sim_fpu_32to (&wop1, op1);
2343 sim_fpu_32to (&wop2, op2);
2344 boolean = sim_fpu_is_lt (&wop1, &wop2);
2345 break;
2346 }
2347 case fmt_double:
2348 {
2349 sim_fpu wop1;
2350 sim_fpu wop2;
2351 sim_fpu_64to (&wop1, op1);
2352 sim_fpu_64to (&wop2, op2);
2353 boolean = sim_fpu_is_lt (&wop1, &wop2);
2354 break;
2355 }
2356 default:
2357 fprintf (stderr, "Bad switch\n");
2358 abort ();
2359 }
2360
2361 #ifdef DEBUG
2362 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2363 #endif /* DEBUG */
2364
2365 return(boolean);
2366 }
2367
2368 int
2369 Equal(op1,op2,fmt)
2370 uword64 op1;
2371 uword64 op2;
2372 FP_formats fmt;
2373 {
2374 int boolean = 0;
2375
2376 /* Argument checking already performed by the FPCOMPARE code */
2377
2378 #ifdef DEBUG
2379 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2380 #endif /* DEBUG */
2381
2382 /* The format type should already have been checked: */
2383 switch (fmt) {
2384 case fmt_single:
2385 {
2386 sim_fpu wop1;
2387 sim_fpu wop2;
2388 sim_fpu_32to (&wop1, op1);
2389 sim_fpu_32to (&wop2, op2);
2390 boolean = sim_fpu_is_eq (&wop1, &wop2);
2391 break;
2392 }
2393 case fmt_double:
2394 {
2395 sim_fpu wop1;
2396 sim_fpu wop2;
2397 sim_fpu_64to (&wop1, op1);
2398 sim_fpu_64to (&wop2, op2);
2399 boolean = sim_fpu_is_eq (&wop1, &wop2);
2400 break;
2401 }
2402 default:
2403 fprintf (stderr, "Bad switch\n");
2404 abort ();
2405 }
2406
2407 #ifdef DEBUG
2408 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2409 #endif /* DEBUG */
2410
2411 return(boolean);
2412 }
2413
2414 uword64
2415 AbsoluteValue(op,fmt)
2416 uword64 op;
2417 FP_formats fmt;
2418 {
2419 uword64 result = 0;
2420
2421 #ifdef DEBUG
2422 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2423 #endif /* DEBUG */
2424
2425 /* The format type should already have been checked: */
2426 switch (fmt) {
2427 case fmt_single:
2428 {
2429 sim_fpu wop;
2430 unsigned32 ans;
2431 sim_fpu_32to (&wop, op);
2432 sim_fpu_abs (&wop, &wop);
2433 sim_fpu_to32 (&ans, &wop);
2434 result = ans;
2435 break;
2436 }
2437 case fmt_double:
2438 {
2439 sim_fpu wop;
2440 unsigned64 ans;
2441 sim_fpu_64to (&wop, op);
2442 sim_fpu_abs (&wop, &wop);
2443 sim_fpu_to64 (&ans, &wop);
2444 result = ans;
2445 break;
2446 }
2447 default:
2448 fprintf (stderr, "Bad switch\n");
2449 abort ();
2450 }
2451
2452 return(result);
2453 }
2454
2455 uword64
2456 Negate(op,fmt)
2457 uword64 op;
2458 FP_formats fmt;
2459 {
2460 uword64 result = 0;
2461
2462 #ifdef DEBUG
2463 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2464 #endif /* DEBUG */
2465
2466 /* The format type should already have been checked: */
2467 switch (fmt) {
2468 case fmt_single:
2469 {
2470 sim_fpu wop;
2471 unsigned32 ans;
2472 sim_fpu_32to (&wop, op);
2473 sim_fpu_neg (&wop, &wop);
2474 sim_fpu_to32 (&ans, &wop);
2475 result = ans;
2476 break;
2477 }
2478 case fmt_double:
2479 {
2480 sim_fpu wop;
2481 unsigned64 ans;
2482 sim_fpu_64to (&wop, op);
2483 sim_fpu_neg (&wop, &wop);
2484 sim_fpu_to64 (&ans, &wop);
2485 result = ans;
2486 break;
2487 }
2488 default:
2489 fprintf (stderr, "Bad switch\n");
2490 abort ();
2491 }
2492
2493 return(result);
2494 }
2495
2496 uword64
2497 Add(op1,op2,fmt)
2498 uword64 op1;
2499 uword64 op2;
2500 FP_formats fmt;
2501 {
2502 uword64 result = 0;
2503
2504 #ifdef DEBUG
2505 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2506 #endif /* DEBUG */
2507
2508 /* The registers must specify FPRs valid for operands of type
2509 "fmt". If they are not valid, the result is undefined. */
2510
2511 /* The format type should already have been checked: */
2512 switch (fmt) {
2513 case fmt_single:
2514 {
2515 sim_fpu wop1;
2516 sim_fpu wop2;
2517 sim_fpu ans;
2518 unsigned32 res;
2519 sim_fpu_32to (&wop1, op1);
2520 sim_fpu_32to (&wop2, op2);
2521 sim_fpu_add (&ans, &wop1, &wop2);
2522 sim_fpu_to32 (&res, &ans);
2523 result = res;
2524 break;
2525 }
2526 case fmt_double:
2527 {
2528 sim_fpu wop1;
2529 sim_fpu wop2;
2530 sim_fpu ans;
2531 unsigned64 res;
2532 sim_fpu_64to (&wop1, op1);
2533 sim_fpu_64to (&wop2, op2);
2534 sim_fpu_add (&ans, &wop1, &wop2);
2535 sim_fpu_to64 (&res, &ans);
2536 result = res;
2537 break;
2538 }
2539 default:
2540 fprintf (stderr, "Bad switch\n");
2541 abort ();
2542 }
2543
2544 #ifdef DEBUG
2545 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2546 #endif /* DEBUG */
2547
2548 return(result);
2549 }
2550
2551 uword64
2552 Sub(op1,op2,fmt)
2553 uword64 op1;
2554 uword64 op2;
2555 FP_formats fmt;
2556 {
2557 uword64 result = 0;
2558
2559 #ifdef DEBUG
2560 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2561 #endif /* DEBUG */
2562
2563 /* The registers must specify FPRs valid for operands of type
2564 "fmt". If they are not valid, the result is undefined. */
2565
2566 /* The format type should already have been checked: */
2567 switch (fmt) {
2568 case fmt_single:
2569 {
2570 sim_fpu wop1;
2571 sim_fpu wop2;
2572 sim_fpu ans;
2573 unsigned32 res;
2574 sim_fpu_32to (&wop1, op1);
2575 sim_fpu_32to (&wop2, op2);
2576 sim_fpu_sub (&ans, &wop1, &wop2);
2577 sim_fpu_to32 (&res, &ans);
2578 result = res;
2579 }
2580 break;
2581 case fmt_double:
2582 {
2583 sim_fpu wop1;
2584 sim_fpu wop2;
2585 sim_fpu ans;
2586 unsigned64 res;
2587 sim_fpu_64to (&wop1, op1);
2588 sim_fpu_64to (&wop2, op2);
2589 sim_fpu_sub (&ans, &wop1, &wop2);
2590 sim_fpu_to64 (&res, &ans);
2591 result = res;
2592 }
2593 break;
2594 default:
2595 fprintf (stderr, "Bad switch\n");
2596 abort ();
2597 }
2598
2599 #ifdef DEBUG
2600 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2601 #endif /* DEBUG */
2602
2603 return(result);
2604 }
2605
2606 uword64
2607 Multiply(op1,op2,fmt)
2608 uword64 op1;
2609 uword64 op2;
2610 FP_formats fmt;
2611 {
2612 uword64 result = 0;
2613
2614 #ifdef DEBUG
2615 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2616 #endif /* DEBUG */
2617
2618 /* The registers must specify FPRs valid for operands of type
2619 "fmt". If they are not valid, the result is undefined. */
2620
2621 /* The format type should already have been checked: */
2622 switch (fmt) {
2623 case fmt_single:
2624 {
2625 sim_fpu wop1;
2626 sim_fpu wop2;
2627 sim_fpu ans;
2628 unsigned32 res;
2629 sim_fpu_32to (&wop1, op1);
2630 sim_fpu_32to (&wop2, op2);
2631 sim_fpu_mul (&ans, &wop1, &wop2);
2632 sim_fpu_to32 (&res, &ans);
2633 result = res;
2634 break;
2635 }
2636 case fmt_double:
2637 {
2638 sim_fpu wop1;
2639 sim_fpu wop2;
2640 sim_fpu ans;
2641 unsigned64 res;
2642 sim_fpu_64to (&wop1, op1);
2643 sim_fpu_64to (&wop2, op2);
2644 sim_fpu_mul (&ans, &wop1, &wop2);
2645 sim_fpu_to64 (&res, &ans);
2646 result = res;
2647 break;
2648 }
2649 default:
2650 fprintf (stderr, "Bad switch\n");
2651 abort ();
2652 }
2653
2654 #ifdef DEBUG
2655 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2656 #endif /* DEBUG */
2657
2658 return(result);
2659 }
2660
2661 uword64
2662 Divide(op1,op2,fmt)
2663 uword64 op1;
2664 uword64 op2;
2665 FP_formats fmt;
2666 {
2667 uword64 result = 0;
2668
2669 #ifdef DEBUG
2670 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2671 #endif /* DEBUG */
2672
2673 /* The registers must specify FPRs valid for operands of type
2674 "fmt". If they are not valid, the result is undefined. */
2675
2676 /* The format type should already have been checked: */
2677 switch (fmt) {
2678 case fmt_single:
2679 {
2680 sim_fpu wop1;
2681 sim_fpu wop2;
2682 sim_fpu ans;
2683 unsigned32 res;
2684 sim_fpu_32to (&wop1, op1);
2685 sim_fpu_32to (&wop2, op2);
2686 sim_fpu_div (&ans, &wop1, &wop2);
2687 sim_fpu_to32 (&res, &ans);
2688 result = res;
2689 break;
2690 }
2691 case fmt_double:
2692 {
2693 sim_fpu wop1;
2694 sim_fpu wop2;
2695 sim_fpu ans;
2696 unsigned64 res;
2697 sim_fpu_64to (&wop1, op1);
2698 sim_fpu_64to (&wop2, op2);
2699 sim_fpu_div (&ans, &wop1, &wop2);
2700 sim_fpu_to64 (&res, &ans);
2701 result = res;
2702 break;
2703 }
2704 default:
2705 fprintf (stderr, "Bad switch\n");
2706 abort ();
2707 }
2708
2709 #ifdef DEBUG
2710 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2711 #endif /* DEBUG */
2712
2713 return(result);
2714 }
2715
2716 uword64 UNUSED
2717 Recip(op,fmt)
2718 uword64 op;
2719 FP_formats fmt;
2720 {
2721 uword64 result = 0;
2722
2723 #ifdef DEBUG
2724 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2725 #endif /* DEBUG */
2726
2727 /* The registers must specify FPRs valid for operands of type
2728 "fmt". If they are not valid, the result is undefined. */
2729
2730 /* The format type should already have been checked: */
2731 switch (fmt) {
2732 case fmt_single:
2733 {
2734 sim_fpu wop;
2735 sim_fpu ans;
2736 unsigned32 res;
2737 sim_fpu_32to (&wop, op);
2738 sim_fpu_inv (&ans, &wop);
2739 sim_fpu_to32 (&res, &ans);
2740 result = res;
2741 break;
2742 }
2743 case fmt_double:
2744 {
2745 sim_fpu wop;
2746 sim_fpu ans;
2747 unsigned64 res;
2748 sim_fpu_64to (&wop, op);
2749 sim_fpu_inv (&ans, &wop);
2750 sim_fpu_to64 (&res, &ans);
2751 result = res;
2752 break;
2753 }
2754 default:
2755 fprintf (stderr, "Bad switch\n");
2756 abort ();
2757 }
2758
2759 #ifdef DEBUG
2760 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2761 #endif /* DEBUG */
2762
2763 return(result);
2764 }
2765
2766 uword64
2767 SquareRoot(op,fmt)
2768 uword64 op;
2769 FP_formats fmt;
2770 {
2771 uword64 result = 0;
2772
2773 #ifdef DEBUG
2774 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2775 #endif /* DEBUG */
2776
2777 /* The registers must specify FPRs valid for operands of type
2778 "fmt". If they are not valid, the result is undefined. */
2779
2780 /* The format type should already have been checked: */
2781 switch (fmt) {
2782 case fmt_single:
2783 {
2784 sim_fpu wop;
2785 sim_fpu ans;
2786 unsigned32 res;
2787 sim_fpu_32to (&wop, op);
2788 sim_fpu_sqrt (&ans, &wop);
2789 sim_fpu_to32 (&res, &ans);
2790 result = res;
2791 break;
2792 }
2793 case fmt_double:
2794 {
2795 sim_fpu wop;
2796 sim_fpu ans;
2797 unsigned64 res;
2798 sim_fpu_64to (&wop, op);
2799 sim_fpu_sqrt (&ans, &wop);
2800 sim_fpu_to64 (&res, &ans);
2801 result = res;
2802 break;
2803 }
2804 default:
2805 fprintf (stderr, "Bad switch\n");
2806 abort ();
2807 }
2808
2809 #ifdef DEBUG
2810 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2811 #endif /* DEBUG */
2812
2813 return(result);
2814 }
2815
2816 #if 0
2817 uword64
2818 Max (uword64 op1,
2819 uword64 op2,
2820 FP_formats fmt)
2821 {
2822 int cmp;
2823 unsigned64 result;
2824
2825 #ifdef DEBUG
2826 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2827 #endif /* DEBUG */
2828
2829 /* The registers must specify FPRs valid for operands of type
2830 "fmt". If they are not valid, the result is undefined. */
2831
2832 /* The format type should already have been checked: */
2833 switch (fmt)
2834 {
2835 case fmt_single:
2836 {
2837 sim_fpu wop1;
2838 sim_fpu wop2;
2839 sim_fpu_32to (&wop1, op1);
2840 sim_fpu_32to (&wop2, op2);
2841 cmp = sim_fpu_cmp (&wop1, &wop2);
2842 break;
2843 }
2844 case fmt_double:
2845 {
2846 sim_fpu wop1;
2847 sim_fpu wop2;
2848 sim_fpu_64to (&wop1, op1);
2849 sim_fpu_64to (&wop2, op2);
2850 cmp = sim_fpu_cmp (&wop1, &wop2);
2851 break;
2852 }
2853 default:
2854 fprintf (stderr, "Bad switch\n");
2855 abort ();
2856 }
2857
2858 switch (cmp)
2859 {
2860 case SIM_FPU_IS_SNAN:
2861 case SIM_FPU_IS_QNAN:
2862 result = op1;
2863 case SIM_FPU_IS_NINF:
2864 case SIM_FPU_IS_NNUMBER:
2865 case SIM_FPU_IS_NDENORM:
2866 case SIM_FPU_IS_NZERO:
2867 result = op2; /* op1 - op2 < 0 */
2868 case SIM_FPU_IS_PINF:
2869 case SIM_FPU_IS_PNUMBER:
2870 case SIM_FPU_IS_PDENORM:
2871 case SIM_FPU_IS_PZERO:
2872 result = op1; /* op1 - op2 > 0 */
2873 default:
2874 fprintf (stderr, "Bad switch\n");
2875 abort ();
2876 }
2877
2878 #ifdef DEBUG
2879 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2880 #endif /* DEBUG */
2881
2882 return(result);
2883 }
2884 #endif
2885
2886 #if 0
2887 uword64
2888 Min (uword64 op1,
2889 uword64 op2,
2890 FP_formats fmt)
2891 {
2892 int cmp;
2893 unsigned64 result;
2894
2895 #ifdef DEBUG
2896 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2897 #endif /* DEBUG */
2898
2899 /* The registers must specify FPRs valid for operands of type
2900 "fmt". If they are not valid, the result is undefined. */
2901
2902 /* The format type should already have been checked: */
2903 switch (fmt)
2904 {
2905 case fmt_single:
2906 {
2907 sim_fpu wop1;
2908 sim_fpu wop2;
2909 sim_fpu_32to (&wop1, op1);
2910 sim_fpu_32to (&wop2, op2);
2911 cmp = sim_fpu_cmp (&wop1, &wop2);
2912 break;
2913 }
2914 case fmt_double:
2915 {
2916 sim_fpu wop1;
2917 sim_fpu wop2;
2918 sim_fpu_64to (&wop1, op1);
2919 sim_fpu_64to (&wop2, op2);
2920 cmp = sim_fpu_cmp (&wop1, &wop2);
2921 break;
2922 }
2923 default:
2924 fprintf (stderr, "Bad switch\n");
2925 abort ();
2926 }
2927
2928 switch (cmp)
2929 {
2930 case SIM_FPU_IS_SNAN:
2931 case SIM_FPU_IS_QNAN:
2932 result = op1;
2933 case SIM_FPU_IS_NINF:
2934 case SIM_FPU_IS_NNUMBER:
2935 case SIM_FPU_IS_NDENORM:
2936 case SIM_FPU_IS_NZERO:
2937 result = op1; /* op1 - op2 < 0 */
2938 case SIM_FPU_IS_PINF:
2939 case SIM_FPU_IS_PNUMBER:
2940 case SIM_FPU_IS_PDENORM:
2941 case SIM_FPU_IS_PZERO:
2942 result = op2; /* op1 - op2 > 0 */
2943 default:
2944 fprintf (stderr, "Bad switch\n");
2945 abort ();
2946 }
2947
2948 #ifdef DEBUG
2949 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2950 #endif /* DEBUG */
2951
2952 return(result);
2953 }
2954 #endif
2955
2956 uword64
2957 convert (SIM_DESC sd,
2958 sim_cpu *cpu,
2959 address_word cia,
2960 int rm,
2961 uword64 op,
2962 FP_formats from,
2963 FP_formats to)
2964 {
2965 sim_fpu wop;
2966 sim_fpu_round round;
2967 unsigned32 result32;
2968 unsigned64 result64;
2969
2970 #ifdef DEBUG
2971 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
2972 #endif /* DEBUG */
2973
2974 switch (rm)
2975 {
2976 case FP_RM_NEAREST:
2977 /* Round result to nearest representable value. When two
2978 representable values are equally near, round to the value
2979 that has a least significant bit of zero (i.e. is even). */
2980 round = sim_fpu_round_near;
2981 break;
2982 case FP_RM_TOZERO:
2983 /* Round result to the value closest to, and not greater in
2984 magnitude than, the result. */
2985 round = sim_fpu_round_zero;
2986 break;
2987 case FP_RM_TOPINF:
2988 /* Round result to the value closest to, and not less than,
2989 the result. */
2990 round = sim_fpu_round_up;
2991 break;
2992
2993 case FP_RM_TOMINF:
2994 /* Round result to the value closest to, and not greater than,
2995 the result. */
2996 round = sim_fpu_round_down;
2997 break;
2998 default:
2999 round = 0;
3000 fprintf (stderr, "Bad switch\n");
3001 abort ();
3002 }
3003
3004 /* Convert the input to sim_fpu internal format */
3005 switch (from)
3006 {
3007 case fmt_double:
3008 sim_fpu_64to (&wop, op);
3009 break;
3010 case fmt_single:
3011 sim_fpu_32to (&wop, op);
3012 break;
3013 case fmt_word:
3014 sim_fpu_i32to (&wop, op, round);
3015 break;
3016 case fmt_long:
3017 sim_fpu_i64to (&wop, op, round);
3018 break;
3019 default:
3020 fprintf (stderr, "Bad switch\n");
3021 abort ();
3022 }
3023
3024 /* Convert sim_fpu format into the output */
3025 /* The value WOP is converted to the destination format, rounding
3026 using mode RM. When the destination is a fixed-point format, then
3027 a source value of Infinity, NaN or one which would round to an
3028 integer outside the fixed point range then an IEEE Invalid
3029 Operation condition is raised. */
3030 switch (to)
3031 {
3032 case fmt_single:
3033 sim_fpu_round_32 (&wop, round, 0);
3034 sim_fpu_to32 (&result32, &wop);
3035 result64 = result32;
3036 break;
3037 case fmt_double:
3038 sim_fpu_round_64 (&wop, round, 0);
3039 sim_fpu_to64 (&result64, &wop);
3040 break;
3041 case fmt_word:
3042 sim_fpu_to32i (&result32, &wop, round);
3043 result64 = result32;
3044 break;
3045 case fmt_long:
3046 sim_fpu_to64i (&result64, &wop, round);
3047 break;
3048 default:
3049 result64 = 0;
3050 fprintf (stderr, "Bad switch\n");
3051 abort ();
3052 }
3053
3054 #ifdef DEBUG
3055 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
3056 #endif /* DEBUG */
3057
3058 return(result64);
3059 }
3060
3061
3062 /*-- co-processor support routines ------------------------------------------*/
3063
3064 static int UNUSED
3065 CoProcPresent(coproc_number)
3066 unsigned int coproc_number;
3067 {
3068 /* Return TRUE if simulator provides a model for the given co-processor number */
3069 return(0);
3070 }
3071
3072 void
3073 cop_lw (SIM_DESC sd,
3074 sim_cpu *cpu,
3075 address_word cia,
3076 int coproc_num,
3077 int coproc_reg,
3078 unsigned int memword)
3079 {
3080 switch (coproc_num)
3081 {
3082 case 1:
3083 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3084 {
3085 #ifdef DEBUG
3086 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
3087 #endif
3088 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
3089 FPR_STATE[coproc_reg] = fmt_uninterpreted;
3090 break;
3091 }
3092
3093 default:
3094 #if 0 /* this should be controlled by a configuration option */
3095 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
3096 #endif
3097 break;
3098 }
3099
3100 return;
3101 }
3102
3103 void
3104 cop_ld (SIM_DESC sd,
3105 sim_cpu *cpu,
3106 address_word cia,
3107 int coproc_num,
3108 int coproc_reg,
3109 uword64 memword)
3110 {
3111 switch (coproc_num) {
3112 case 1:
3113 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3114 {
3115 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
3116 break;
3117 }
3118
3119 default:
3120 #if 0 /* this message should be controlled by a configuration option */
3121 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
3122 #endif
3123 break;
3124 }
3125
3126 return;
3127 }
3128
3129
3130 /* start-sanitize-sky */
3131 #ifdef TARGET_SKY
3132 void
3133 cop_lq (SIM_DESC sd,
3134 sim_cpu *cpu,
3135 address_word cia,
3136 int coproc_num,
3137 int coproc_reg,
3138 unsigned128 memword)
3139 {
3140 switch (coproc_num)
3141 {
3142 case 2:
3143 {
3144 int i;
3145
3146 while(vu0_busy())
3147 vu0_issue(sd);
3148
3149 /* one word at a time, argh! */
3150 for(i=0; i<4; i++)
3151 {
3152 unsigned_4 value;
3153 value = H2T_4(*A4_16(& memword, 3-i));
3154 write_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3155 }
3156 }
3157 break;
3158
3159 default:
3160 sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3161 coproc_num,coproc_reg,pr_addr(cia));
3162 break;
3163 }
3164
3165 return;
3166 }
3167 #endif /* TARGET_SKY */
3168 /* end-sanitize-sky */
3169
3170
3171 unsigned int
3172 cop_sw (SIM_DESC sd,
3173 sim_cpu *cpu,
3174 address_word cia,
3175 int coproc_num,
3176 int coproc_reg)
3177 {
3178 unsigned int value = 0;
3179
3180 switch (coproc_num)
3181 {
3182 case 1:
3183 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3184 {
3185 FP_formats hold;
3186 hold = FPR_STATE[coproc_reg];
3187 FPR_STATE[coproc_reg] = fmt_word;
3188 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
3189 FPR_STATE[coproc_reg] = hold;
3190 break;
3191 }
3192
3193 default:
3194 #if 0 /* should be controlled by configuration option */
3195 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3196 #endif
3197 break;
3198 }
3199
3200 return(value);
3201 }
3202
3203 uword64
3204 cop_sd (SIM_DESC sd,
3205 sim_cpu *cpu,
3206 address_word cia,
3207 int coproc_num,
3208 int coproc_reg)
3209 {
3210 uword64 value = 0;
3211 switch (coproc_num)
3212 {
3213 case 1:
3214 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3215 {
3216 value = ValueFPR(coproc_reg,fmt_uninterpreted);
3217 break;
3218 }
3219
3220 default:
3221 #if 0 /* should be controlled by configuration option */
3222 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3223 #endif
3224 break;
3225 }
3226
3227 return(value);
3228 }
3229
3230
3231 /* start-sanitize-sky */
3232 #ifdef TARGET_SKY
3233 unsigned128
3234 cop_sq (SIM_DESC sd,
3235 sim_cpu *cpu,
3236 address_word cia,
3237 int coproc_num,
3238 int coproc_reg)
3239 {
3240 unsigned128 value = U16_8(0, 0);
3241 switch (coproc_num)
3242 {
3243 case 2:
3244 {
3245 unsigned_16 xyzw;
3246 int i;
3247
3248 while(vu0_busy())
3249 vu0_issue(sd);
3250
3251 /* one word at a time, argh! */
3252 for(i=0; i<4; i++)
3253 {
3254 unsigned_4 value;
3255 read_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3256 *A4_16(& xyzw, 3-i) = T2H_4(value);
3257 }
3258 return xyzw;
3259 }
3260 break;
3261
3262 default:
3263 sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3264 coproc_num,coproc_reg,pr_addr(cia));
3265 break;
3266 }
3267
3268 return(value);
3269 }
3270 #endif /* TARGET_SKY */
3271 /* end-sanitize-sky */
3272
3273
3274 void
3275 decode_coproc (SIM_DESC sd,
3276 sim_cpu *cpu,
3277 address_word cia,
3278 unsigned int instruction)
3279 {
3280 int coprocnum = ((instruction >> 26) & 3);
3281
3282 switch (coprocnum)
3283 {
3284 case 0: /* standard CPU control and cache registers */
3285 {
3286 int code = ((instruction >> 21) & 0x1F);
3287 /* R4000 Users Manual (second edition) lists the following CP0
3288 instructions:
3289 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3290 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3291 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3292 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3293 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3294 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3295 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3296 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3297 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3298 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3299 */
3300 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
3301 {
3302 int rt = ((instruction >> 16) & 0x1F);
3303 int rd = ((instruction >> 11) & 0x1F);
3304
3305 switch (rd) /* NOTEs: Standard CP0 registers */
3306 {
3307 /* 0 = Index R4000 VR4100 VR4300 */
3308 /* 1 = Random R4000 VR4100 VR4300 */
3309 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3310 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3311 /* 4 = Context R4000 VR4100 VR4300 */
3312 /* 5 = PageMask R4000 VR4100 VR4300 */
3313 /* 6 = Wired R4000 VR4100 VR4300 */
3314 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3315 /* 9 = Count R4000 VR4100 VR4300 */
3316 /* 10 = EntryHi R4000 VR4100 VR4300 */
3317 /* 11 = Compare R4000 VR4100 VR4300 */
3318 /* 12 = SR R4000 VR4100 VR4300 */
3319 #ifdef SUBTARGET_R3900
3320 case 3:
3321 /* ignore */
3322 break;
3323 /* 3 = Config R3900 */
3324 #endif /* SUBTARGET_R3900 */
3325 case 12:
3326 if (code == 0x00)
3327 GPR[rt] = SR;
3328 else
3329 SR = GPR[rt];
3330 break;
3331 /* 13 = Cause R4000 VR4100 VR4300 */
3332 case 13:
3333 if (code == 0x00)
3334 GPR[rt] = CAUSE;
3335 else
3336 CAUSE = GPR[rt];
3337 break;
3338 /* 14 = EPC R4000 VR4100 VR4300 */
3339 case 14:
3340 if (code == 0x00)
3341 GPR[rt] = (signed_word) (signed_address) EPC;
3342 else
3343 EPC = GPR[rt];
3344 break;
3345 /* 15 = PRId R4000 VR4100 VR4300 */
3346 #ifdef SUBTARGET_R3900
3347 /* 16 = Debug */
3348 case 16:
3349 if (code == 0x00)
3350 GPR[rt] = Debug;
3351 else
3352 Debug = GPR[rt];
3353 break;
3354 #else
3355 /* 16 = Config R4000 VR4100 VR4300 */
3356 case 16:
3357 if (code == 0x00)
3358 GPR[rt] = C0_CONFIG;
3359 else
3360 C0_CONFIG = GPR[rt];
3361 break;
3362 #endif
3363 #ifdef SUBTARGET_R3900
3364 /* 17 = Debug */
3365 case 17:
3366 if (code == 0x00)
3367 GPR[rt] = DEPC;
3368 else
3369 DEPC = GPR[rt];
3370 break;
3371 #else
3372 /* 17 = LLAddr R4000 VR4100 VR4300 */
3373 #endif
3374 /* 18 = WatchLo R4000 VR4100 VR4300 */
3375 /* 19 = WatchHi R4000 VR4100 VR4300 */
3376 /* 20 = XContext R4000 VR4100 VR4300 */
3377 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3378 /* 27 = CacheErr R4000 VR4100 */
3379 /* 28 = TagLo R4000 VR4100 VR4300 */
3380 /* 29 = TagHi R4000 VR4100 VR4300 */
3381 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3382 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3383 /* CPR[0,rd] = GPR[rt]; */
3384 default:
3385 if (code == 0x00)
3386 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3387 else
3388 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3389 }
3390 }
3391 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3392 {
3393 /* ERET */
3394 if (SR & status_ERL)
3395 {
3396 /* Oops, not yet available */
3397 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3398 PC = EPC;
3399 SR &= ~status_ERL;
3400 }
3401 else
3402 {
3403 PC = EPC;
3404 SR &= ~status_EXL;
3405 }
3406 }
3407 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3408 {
3409 /* RFE */
3410 #ifdef SUBTARGET_R3900
3411 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3412
3413 /* shift IE/KU history bits right */
3414 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
3415
3416 /* TODO: CACHE register */
3417 #endif /* SUBTARGET_R3900 */
3418 }
3419 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3420 {
3421 /* DERET */
3422 Debug &= ~Debug_DM;
3423 DELAYSLOT();
3424 DSPC = DEPC;
3425 }
3426 else
3427 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3428 /* TODO: When executing an ERET or RFE instruction we should
3429 clear LLBIT, to ensure that any out-standing atomic
3430 read/modify/write sequence fails. */
3431 }
3432 break;
3433
3434 case 2: /* co-processor 2 */
3435 {
3436 int handle = 0;
3437
3438 /* start-sanitize-sky */
3439 #ifdef TARGET_SKY
3440 /* On the R5900, this refers to a "VU" vector co-processor. */
3441
3442 int i_25_21 = (instruction >> 21) & 0x1f;
3443 int i_20_16 = (instruction >> 16) & 0x1f;
3444 int i_20_6 = (instruction >> 6) & 0x7fff;
3445 int i_15_11 = (instruction >> 11) & 0x1f;
3446 int i_15_0 = instruction & 0xffff;
3447 int i_10_1 = (instruction >> 1) & 0x3ff;
3448 int i_10_0 = instruction & 0x7ff;
3449 int i_10_6 = (instruction >> 6) & 0x1f;
3450 int i_5_0 = instruction & 0x03f;
3451 int interlock = instruction & 0x01;
3452 /* setup for semantic.c-like actions below */
3453 typedef unsigned_4 instruction_word;
3454 int CIA = cia;
3455 int NIA = cia + 4;
3456
3457 handle = 1;
3458
3459 /* test COP2 usability */
3460 if(! (SR & status_CU2))
3461 {
3462 SignalException(CoProcessorUnusable,instruction);
3463 /* NOTREACHED */
3464 }
3465
3466 #define MY_INDEX itable_COPz_NORMAL
3467 #define MY_PREFIX COPz_NORMAL
3468 #define MY_NAME "COPz_NORMAL"
3469
3470 /* classify & execute basic COP2 instructions */
3471 if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
3472 {
3473 address_word offset = EXTEND16(i_15_0) << 2;
3474 if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3475 }
3476 else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
3477 {
3478 address_word offset = EXTEND16(i_15_0) << 2;
3479 if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3480 else NULLIFY_NEXT_INSTRUCTION();
3481 }
3482 else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
3483 {
3484 address_word offset = EXTEND16(i_15_0) << 2;
3485 if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3486 }
3487 else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
3488 {
3489 address_word offset = EXTEND16(i_15_0) << 2;
3490 if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3491 else NULLIFY_NEXT_INSTRUCTION();
3492 }
3493 else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
3494 (i_25_21 == 0x01)) /* QMFC2 */
3495 {
3496 int rt = i_20_16;
3497 int id = i_15_11;
3498
3499 /* interlock checking */
3500 /* POLICY: never busy in macro mode */
3501 while(vu0_busy() && interlock)
3502 vu0_issue(sd);
3503
3504 /* perform VU register address */
3505 if(i_25_21 == 0x01) /* QMFC2 */
3506 {
3507 unsigned_16 xyzw;
3508 /* one word at a time, argh! */
3509 read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
3510 read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
3511 read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
3512 read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
3513 GPR[rt] = T2H_8(* A8_16(& xyzw, 1));
3514 GPR1[rt] = T2H_8(* A8_16(& xyzw, 0));
3515 }
3516 else /* CFC2 */
3517 {
3518 unsigned_4 data;
3519 /* enum + int calculation, argh! */
3520 id = VU_REG_MST + 16 * id;
3521 if (id >= VU_REG_CMSAR0)
3522 read_vu_special_reg(&vu0_device, id, & data);
3523 else
3524 read_vu_misc_reg(&(vu0_device.regs), id, & data);
3525 GPR[rt] = EXTEND32(T2H_4(data));
3526 }
3527 }
3528 else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
3529 (i_25_21 == 0x05)) /* QMTC2 */
3530 {
3531 int rt = i_20_16;
3532 int id = i_15_11;
3533
3534 /* interlock checking: wait until M or E bits set */
3535 /* POLICY: never busy in macro mode */
3536 while(vu0_busy() && interlock)
3537 {
3538 if(vu0_micro_interlock_released())
3539 {
3540 vu0_micro_interlock_clear();
3541 break;
3542 }
3543
3544 vu0_issue(sd);
3545 }
3546
3547 /* perform VU register address */
3548 if(i_25_21 == 0x05) /* QMTC2 */
3549 {
3550 unsigned_16 xyzw = U16_8(GPR1[rt], GPR[rt]);
3551
3552 xyzw = H2T_16(xyzw);
3553 /* one word at a time, argh! */
3554 write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
3555 write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
3556 write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
3557 write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
3558 }
3559 else /* CTC2 */
3560 {
3561 unsigned_4 data = H2T_4(GPR[rt]);
3562 /* enum + int calculation, argh! */
3563 id = VU_REG_VI + 16 * id;
3564 if (id >= VU_REG_CMSAR0)
3565 write_vu_special_reg(&vu0_device, id, & data);
3566 else
3567 write_vu_misc_reg(&(vu0_device.regs), id, & data);
3568 }
3569 }
3570 else if(i_10_0 == 0x3bf) /* VWAITQ */
3571 {
3572 while(vu0_q_busy())
3573 vu0_issue(sd);
3574 }
3575 else if(i_5_0 == 0x38) /* VCALLMS */
3576 {
3577 unsigned_4 data = H2T_2(i_20_6);
3578
3579 while(vu0_busy())
3580 vu0_issue(sd);
3581
3582 /* write to reserved CIA register to get VU0 moving */
3583 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3584
3585 ASSERT(vu0_busy());
3586 }
3587 else if(i_5_0 == 0x39) /* VCALLMSR */
3588 {
3589 unsigned_4 data;
3590
3591 while(vu0_busy())
3592 vu0_issue(sd);
3593
3594 read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
3595 /* write to reserved CIA register to get VU0 moving */
3596 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3597
3598 ASSERT(vu0_busy());
3599 }
3600 /* handle all remaining UPPER VU instructions in one block */
3601 else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
3602 (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
3603 {
3604 unsigned_4 vu_upper, vu_lower;
3605 vu_upper =
3606 0x00000000 | /* bits 31 .. 25 */
3607 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3608 vu_lower = 0x8000033c; /* NOP */
3609
3610 /* POLICY: never busy in macro mode */
3611 while(vu0_busy())
3612 vu0_issue(sd);
3613
3614 vu0_macro_issue(vu_upper, vu_lower);
3615
3616 /* POLICY: wait for completion of macro-instruction */
3617 while(vu0_busy())
3618 vu0_issue(sd);
3619 }
3620 /* handle all remaining LOWER VU instructions in one block */
3621 else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
3622 (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
3623 { /* N.B.: VWAITQ already covered by prior case */
3624 unsigned_4 vu_upper, vu_lower;
3625 vu_upper = 0x000002ff; /* NOP/NOP */
3626 vu_lower =
3627 0x80000000 | /* bits 31 .. 25 */
3628 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3629
3630 /* POLICY: never busy in macro mode */
3631 while(vu0_busy())
3632 vu0_issue(sd);
3633
3634 vu0_macro_issue(vu_upper, vu_lower);
3635
3636 /* POLICY: wait for completion of macro-instruction */
3637 while(vu0_busy())
3638 vu0_issue(sd);
3639 }
3640 /* ... no other COP2 instructions ... */
3641 else
3642 {
3643 SignalException(ReservedInstruction, instruction);
3644 /* NOTREACHED */
3645 }
3646
3647 /* cleanup for semantic.c-like actions above */
3648 PC = NIA;
3649
3650 #undef MY_INDEX
3651 #undef MY_PREFIX
3652 #undef MY_NAME
3653
3654 #endif /* TARGET_SKY */
3655 /* end-sanitize-sky */
3656
3657 if(! handle)
3658 {
3659 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3660 instruction,pr_addr(cia));
3661 }
3662 }
3663 break;
3664
3665 case 1: /* should not occur (FPU co-processor) */
3666 case 3: /* should not occur (FPU co-processor) */
3667 SignalException(ReservedInstruction,instruction);
3668 break;
3669 }
3670
3671 return;
3672 }
3673
3674
3675 /*-- instruction simulation -------------------------------------------------*/
3676
3677 /* When the IGEN simulator is being built, the function below is be
3678 replaced by a generated version. However, WITH_IGEN == 2 indicates
3679 that the fubction below should be compiled but under a different
3680 name (to allow backward compatibility) */
3681
3682 #if (WITH_IGEN != 1)
3683 #if (WITH_IGEN > 1)
3684 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3685 void
3686 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3687 #else
3688 void
3689 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3690 #endif
3691 SIM_DESC sd;
3692 int next_cpu_nr; /* ignore */
3693 int nr_cpus; /* ignore */
3694 int siggnal; /* ignore */
3695 {
3696 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
3697 #if !defined(FASTSIM)
3698 unsigned int pipeline_count = 1;
3699 #endif
3700
3701 #ifdef DEBUG
3702 if (STATE_MEMORY (sd) == NULL) {
3703 printf("DBG: simulate() entered with no memory\n");
3704 exit(1);
3705 }
3706 #endif /* DEBUG */
3707
3708 #if 0 /* Disabled to check that everything works OK */
3709 /* The VR4300 seems to sign-extend the PC on its first
3710 access. However, this may just be because it is currently
3711 configured in 32bit mode. However... */
3712 PC = SIGNEXTEND(PC,32);
3713 #endif
3714
3715 /* main controlling loop */
3716 while (1) {
3717 /* vaddr is slowly being replaced with cia - current instruction
3718 address */
3719 address_word cia = (uword64)PC;
3720 address_word vaddr = cia;
3721 address_word paddr;
3722 int cca;
3723 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3724
3725 #ifdef DEBUG
3726 {
3727 printf("DBG: state = 0x%08X :",state);
3728 if (state & simHALTEX) printf(" simHALTEX");
3729 if (state & simHALTIN) printf(" simHALTIN");
3730 printf("\n");
3731 }
3732 #endif /* DEBUG */
3733
3734 DSSTATE = (STATE & simDELAYSLOT);
3735 #ifdef DEBUG
3736 if (dsstate)
3737 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3738 #endif /* DEBUG */
3739
3740 /* Fetch the next instruction from the simulator memory: */
3741 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3742 if ((vaddr & 1) == 0) {
3743 /* Copy the action of the LW instruction */
3744 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3745 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3746 uword64 value;
3747 unsigned int byte;
3748 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3749 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3750 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3751 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3752 } else {
3753 /* Copy the action of the LH instruction */
3754 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3755 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3756 uword64 value;
3757 unsigned int byte;
3758 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3759 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3760 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3761 paddr & ~ (uword64) 1,
3762 vaddr, isINSTRUCTION, isREAL);
3763 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3764 instruction = ((value >> (8 * byte)) & 0xFFFF);
3765 }
3766 } else {
3767 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3768 exit(1);
3769 }
3770
3771 #ifdef DEBUG
3772 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3773 #endif /* DEBUG */
3774
3775 /* This is required by exception processing, to ensure that we can
3776 cope with exceptions in the delay slots of branches that may
3777 already have changed the PC. */
3778 if ((vaddr & 1) == 0)
3779 PC += 4; /* increment ready for the next fetch */
3780 else
3781 PC += 2;
3782 /* NOTE: If we perform a delay slot change to the PC, this
3783 increment is not requuired. However, it would make the
3784 simulator more complicated to try and avoid this small hit. */
3785
3786 /* Currently this code provides a simple model. For more
3787 complicated models we could perform exception status checks at
3788 this point, and set the simSTOP state as required. This could
3789 also include processing any hardware interrupts raised by any
3790 I/O model attached to the simulator context.
3791
3792 Support for "asynchronous" I/O events within the simulated world
3793 could be providing by managing a counter, and calling a I/O
3794 specific handler when a particular threshold is reached. On most
3795 architectures a decrement and check for zero operation is
3796 usually quicker than an increment and compare. However, the
3797 process of managing a known value decrement to zero, is higher
3798 than the cost of using an explicit value UINT_MAX into the
3799 future. Which system is used will depend on how complicated the
3800 I/O model is, and how much it is likely to affect the simulator
3801 bandwidth.
3802
3803 If events need to be scheduled further in the future than
3804 UINT_MAX event ticks, then the I/O model should just provide its
3805 own counter, triggered from the event system. */
3806
3807 /* MIPS pipeline ticks. To allow for future support where the
3808 pipeline hit of individual instructions is known, this control
3809 loop manages a "pipeline_count" variable. It is initialised to
3810 1 (one), and will only be changed by the simulator engine when
3811 executing an instruction. If the engine does not have access to
3812 pipeline cycle count information then all instructions will be
3813 treated as using a single cycle. NOTE: A standard system is not
3814 provided by the default simulator because different MIPS
3815 architectures have different cycle counts for the same
3816 instructions.
3817
3818 [NOTE: pipeline_count has been replaced the event queue] */
3819
3820 /* shuffle the floating point status pipeline state */
3821 ENGINE_ISSUE_PREFIX_HOOK();
3822
3823 /* NOTE: For multi-context simulation environments the "instruction"
3824 variable should be local to this routine. */
3825
3826 /* Shorthand accesses for engine. Note: If we wanted to use global
3827 variables (and a single-threaded simulator engine), then we can
3828 create the actual variables with these names. */
3829
3830 if (!(STATE & simSKIPNEXT)) {
3831 /* Include the simulator engine */
3832 #include "oengine.c"
3833 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3834 #error "Mismatch between run-time simulator code and simulation engine"
3835 #endif
3836 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3837 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3838 #endif
3839 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3840 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3841 #endif
3842
3843 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3844 should check for it being changed. It is better doing it here,
3845 than within the simulator, since it will help keep the simulator
3846 small. */
3847 if (ZERO != 0) {
3848 #if defined(WARN_ZERO)
3849 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3850 #endif /* WARN_ZERO */
3851 ZERO = 0; /* reset back to zero before next instruction */
3852 }
3853 } else /* simSKIPNEXT check */
3854 STATE &= ~simSKIPNEXT;
3855
3856 /* If the delay slot was active before the instruction is
3857 executed, then update the PC to its new value: */
3858 if (DSSTATE) {
3859 #ifdef DEBUG
3860 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3861 #endif /* DEBUG */
3862 PC = DSPC;
3863 CANCELDELAYSLOT();
3864 }
3865
3866 if (MIPSISA < 4)
3867 PENDING_TICK();
3868
3869 #if !defined(FASTSIM)
3870 if (sim_events_tickn (sd, pipeline_count))
3871 {
3872 /* cpu->cia = cia; */
3873 sim_events_process (sd);
3874 }
3875 #else
3876 if (sim_events_tick (sd))
3877 {
3878 /* cpu->cia = cia; */
3879 sim_events_process (sd);
3880 }
3881 #endif /* FASTSIM */
3882 }
3883 }
3884 #endif
3885
3886
3887 /* This code copied from gdb's utils.c. Would like to share this code,
3888 but don't know of a common place where both could get to it. */
3889
3890 /* Temporary storage using circular buffer */
3891 #define NUMCELLS 16
3892 #define CELLSIZE 32
3893 static char*
3894 get_cell()
3895 {
3896 static char buf[NUMCELLS][CELLSIZE];
3897 static int cell=0;
3898 if (++cell>=NUMCELLS) cell=0;
3899 return buf[cell];
3900 }
3901
3902 /* Print routines to handle variable size regs, etc */
3903
3904 /* Eliminate warning from compiler on 32-bit systems */
3905 static int thirty_two = 32;
3906
3907 char*
3908 pr_addr(addr)
3909 SIM_ADDR addr;
3910 {
3911 char *paddr_str=get_cell();
3912 switch (sizeof(addr))
3913 {
3914 case 8:
3915 sprintf(paddr_str,"%08lx%08lx",
3916 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3917 break;
3918 case 4:
3919 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3920 break;
3921 case 2:
3922 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3923 break;
3924 default:
3925 sprintf(paddr_str,"%x",addr);
3926 }
3927 return paddr_str;
3928 }
3929
3930 char*
3931 pr_uword64(addr)
3932 uword64 addr;
3933 {
3934 char *paddr_str=get_cell();
3935 sprintf(paddr_str,"%08lx%08lx",
3936 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3937 return paddr_str;
3938 }
3939
3940
3941
3942 /*---------------------------------------------------------------------------*/
3943 /*> EOF interp.c <*/
GDB Binutils - Deliverables
This page took 0.138131 seconds and 4 git commands to generate.