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[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 NOTEs:
17
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
21 code on the hardware.
22
23 */
24
25 /* The TRACE manifests enable the provision of extra features. If they
26 are not defined then a simpler (quicker) simulator is constructed
27 without the required run-time checks, etc. */
28 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
29 #define TRACE (1)
30 #endif
31
32 #include "bfd.h"
33 #include "sim-main.h"
34 #include "sim-utils.h"
35 #include "sim-options.h"
36 #include "sim-assert.h"
37 #include "sim-hw.h"
38
39 #include "itable.h"
40
41
42 #include "config.h"
43
44 #include <stdio.h>
45 #include <stdarg.h>
46 #include <ansidecl.h>
47 #include <ctype.h>
48 #include <limits.h>
49 #include <math.h>
50 #ifdef HAVE_STDLIB_H
51 #include <stdlib.h>
52 #endif
53 #ifdef HAVE_STRING_H
54 #include <string.h>
55 #else
56 #ifdef HAVE_STRINGS_H
57 #include <strings.h>
58 #endif
59 #endif
60
61 #include "getopt.h"
62 #include "libiberty.h"
63 #include "bfd.h"
64 #include "gdb/callback.h" /* GDB simulator callback interface */
65 #include "gdb/remote-sim.h" /* GDB simulator interface */
66
67 #include "sysdep.h"
68
69 #ifndef PARAMS
70 #define PARAMS(x)
71 #endif
72
73 char* pr_addr PARAMS ((SIM_ADDR addr));
74 char* pr_uword64 PARAMS ((uword64 addr));
75
76
77 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
78 #define CPU cpu
79 #define SD sd
80
81
82 /* The following reserved instruction value is used when a simulator
83 trap is required. NOTE: Care must be taken, since this value may be
84 used in later revisions of the MIPS ISA. */
85
86 #define RSVD_INSTRUCTION (0x00000005)
87 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
88
89 #define RSVD_INSTRUCTION_ARG_SHIFT 6
90 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
91
92
93 /* Bits in the Debug register */
94 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
95 #define Debug_DM 0x40000000 /* Debug Mode */
96 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
97
98 /*---------------------------------------------------------------------------*/
99 /*-- GDB simulator interface ------------------------------------------------*/
100 /*---------------------------------------------------------------------------*/
101
102 static void ColdReset PARAMS((SIM_DESC sd));
103
104 /*---------------------------------------------------------------------------*/
105
106
107
108 #define DELAYSLOT() {\
109 if (STATE & simDELAYSLOT)\
110 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
111 STATE |= simDELAYSLOT;\
112 }
113
114 #define JALDELAYSLOT() {\
115 DELAYSLOT ();\
116 STATE |= simJALDELAYSLOT;\
117 }
118
119 #define NULLIFY() {\
120 STATE &= ~simDELAYSLOT;\
121 STATE |= simSKIPNEXT;\
122 }
123
124 #define CANCELDELAYSLOT() {\
125 DSSTATE = 0;\
126 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
127 }
128
129 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
130 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
131
132 /* Note that the monitor code essentially assumes this layout of memory.
133 If you change these, change the monitor code, too. */
134 /* FIXME Currently addresses are truncated to 32-bits, see
135 mips/sim-main.c:address_translation(). If that changes, then these
136 values will need to be extended, and tested for more carefully. */
137 #define K0BASE (0x80000000)
138 #define K0SIZE (0x20000000)
139 #define K1BASE (0xA0000000)
140 #define K1SIZE (0x20000000)
141
142 /* Simple run-time monitor support.
143
144 We emulate the monitor by placing magic reserved instructions at
145 the monitor's entry points; when we hit these instructions, instead
146 of raising an exception (as we would normally), we look at the
147 instruction and perform the appropriate monitory operation.
148
149 `*_monitor_base' are the physical addresses at which the corresponding
150 monitor vectors are located. `0' means none. By default,
151 install all three.
152 The RSVD_INSTRUCTION... macros specify the magic instructions we
153 use at the monitor entry points. */
154 static int firmware_option_p = 0;
155 static SIM_ADDR idt_monitor_base = 0xBFC00000;
156 static SIM_ADDR pmon_monitor_base = 0xBFC00500;
157 static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
158
159 static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
160
161
162 #define MEM_SIZE (8 << 20) /* 8 MBytes */
163
164
165 #if defined(TRACE)
166 static char *tracefile = "trace.din"; /* default filename for trace log */
167 FILE *tracefh = NULL;
168 static void open_trace PARAMS((SIM_DESC sd));
169 #endif /* TRACE */
170
171 static const char * get_insn_name (sim_cpu *, int);
172
173 /* simulation target board. NULL=canonical */
174 static char* board = NULL;
175
176
177 static DECLARE_OPTION_HANDLER (mips_option_handler);
178
179 enum {
180 OPTION_DINERO_TRACE = OPTION_START,
181 OPTION_DINERO_FILE,
182 OPTION_FIRMWARE,
183 OPTION_BOARD
184 };
185
186
187 static SIM_RC
188 mips_option_handler (sd, cpu, opt, arg, is_command)
189 SIM_DESC sd;
190 sim_cpu *cpu;
191 int opt;
192 char *arg;
193 int is_command;
194 {
195 int cpu_nr;
196 switch (opt)
197 {
198 case OPTION_DINERO_TRACE: /* ??? */
199 #if defined(TRACE)
200 /* Eventually the simTRACE flag could be treated as a toggle, to
201 allow external control of the program points being traced
202 (i.e. only from main onwards, excluding the run-time setup,
203 etc.). */
204 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
205 {
206 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
207 if (arg == NULL)
208 STATE |= simTRACE;
209 else if (strcmp (arg, "yes") == 0)
210 STATE |= simTRACE;
211 else if (strcmp (arg, "no") == 0)
212 STATE &= ~simTRACE;
213 else if (strcmp (arg, "on") == 0)
214 STATE |= simTRACE;
215 else if (strcmp (arg, "off") == 0)
216 STATE &= ~simTRACE;
217 else
218 {
219 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
220 return SIM_RC_FAIL;
221 }
222 }
223 return SIM_RC_OK;
224 #else /* !TRACE */
225 fprintf(stderr,"\
226 Simulator constructed without dinero tracing support (for performance).\n\
227 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
228 return SIM_RC_FAIL;
229 #endif /* !TRACE */
230
231 case OPTION_DINERO_FILE:
232 #if defined(TRACE)
233 if (optarg != NULL) {
234 char *tmp;
235 tmp = (char *)malloc(strlen(optarg) + 1);
236 if (tmp == NULL)
237 {
238 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
239 return SIM_RC_FAIL;
240 }
241 else {
242 strcpy(tmp,optarg);
243 tracefile = tmp;
244 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
245 }
246 }
247 #endif /* TRACE */
248 return SIM_RC_OK;
249
250 case OPTION_FIRMWARE:
251 return sim_firmware_command (sd, arg);
252
253 case OPTION_BOARD:
254 {
255 if (arg)
256 {
257 board = zalloc(strlen(arg) + 1);
258 strcpy(board, arg);
259 }
260 return SIM_RC_OK;
261 }
262 }
263
264 return SIM_RC_OK;
265 }
266
267
268 static const OPTION mips_options[] =
269 {
270 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
271 '\0', "on|off", "Enable dinero tracing",
272 mips_option_handler },
273 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
274 '\0', "FILE", "Write dinero trace to FILE",
275 mips_option_handler },
276 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
277 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
278 mips_option_handler },
279 { {"board", required_argument, NULL, OPTION_BOARD},
280 '\0', "none" /* rely on compile-time string concatenation for other options */
281
282 #define BOARD_JMR3904 "jmr3904"
283 "|" BOARD_JMR3904
284 #define BOARD_JMR3904_PAL "jmr3904pal"
285 "|" BOARD_JMR3904_PAL
286 #define BOARD_JMR3904_DEBUG "jmr3904debug"
287 "|" BOARD_JMR3904_DEBUG
288 #define BOARD_BSP "bsp"
289 "|" BOARD_BSP
290
291 , "Customize simulation for a particular board.", mips_option_handler },
292
293 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
294 };
295
296
297 int interrupt_pending;
298
299 void
300 interrupt_event (SIM_DESC sd, void *data)
301 {
302 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
303 address_word cia = CIA_GET (cpu);
304 if (SR & status_IE)
305 {
306 interrupt_pending = 0;
307 SignalExceptionInterrupt (1); /* interrupt "1" */
308 }
309 else if (!interrupt_pending)
310 sim_events_schedule (sd, 1, interrupt_event, data);
311 }
312
313
314 /*---------------------------------------------------------------------------*/
315 /*-- Device registration hook -----------------------------------------------*/
316 /*---------------------------------------------------------------------------*/
317 static void device_init(SIM_DESC sd) {
318 #ifdef DEVICE_INIT
319 extern void register_devices(SIM_DESC);
320 register_devices(sd);
321 #endif
322 }
323
324 /*---------------------------------------------------------------------------*/
325 /*-- GDB simulator interface ------------------------------------------------*/
326 /*---------------------------------------------------------------------------*/
327
328 SIM_DESC
329 sim_open (kind, cb, abfd, argv)
330 SIM_OPEN_KIND kind;
331 host_callback *cb;
332 struct bfd *abfd;
333 char **argv;
334 {
335 SIM_DESC sd = sim_state_alloc (kind, cb);
336 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
337
338 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
339
340 /* FIXME: watchpoints code shouldn't need this */
341 STATE_WATCHPOINTS (sd)->pc = &(PC);
342 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
343 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
344
345 /* Initialize the mechanism for doing insn profiling. */
346 CPU_INSN_NAME (cpu) = get_insn_name;
347 CPU_MAX_INSNS (cpu) = nr_itable_entries;
348
349 STATE = 0;
350
351 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
352 return 0;
353 sim_add_option_table (sd, NULL, mips_options);
354
355
356 /* getopt will print the error message so we just have to exit if this fails.
357 FIXME: Hmmm... in the case of gdb we need getopt to call
358 print_filtered. */
359 if (sim_parse_args (sd, argv) != SIM_RC_OK)
360 {
361 /* Uninstall the modules to avoid memory leaks,
362 file descriptor leaks, etc. */
363 sim_module_uninstall (sd);
364 return 0;
365 }
366
367 /* handle board-specific memory maps */
368 if (board == NULL)
369 {
370 /* Allocate core managed memory */
371 sim_memopt *entry, *match = NULL;
372 address_word mem_size = 0;
373 int mapped = 0;
374
375 /* For compatibility with the old code - under this (at level one)
376 are the kernel spaces K0 & K1. Both of these map to a single
377 smaller sub region */
378 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
379
380 /* Look for largest memory region defined on command-line at
381 phys address 0. */
382 #ifdef SIM_HAVE_FLATMEM
383 mem_size = STATE_MEM_SIZE (sd);
384 #endif
385 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
386 {
387 /* If we find an entry at address 0, then we will end up
388 allocating a new buffer in the "memory alias" command
389 below. The region at address 0 will be deleted. */
390 address_word size = (entry->modulo != 0
391 ? entry->modulo : entry->nr_bytes);
392 if (entry->addr == 0
393 && (!match || entry->level < match->level))
394 match = entry;
395 else if (entry->addr == K0BASE || entry->addr == K1BASE)
396 mapped = 1;
397 else
398 {
399 sim_memopt *alias;
400 for (alias = entry->alias; alias != NULL; alias = alias->next)
401 {
402 if (alias->addr == 0
403 && (!match || entry->level < match->level))
404 match = entry;
405 else if (alias->addr == K0BASE || alias->addr == K1BASE)
406 mapped = 1;
407 }
408 }
409 }
410
411 if (!mapped)
412 {
413 if (match)
414 {
415 /* Get existing memory region size. */
416 mem_size = (match->modulo != 0
417 ? match->modulo : match->nr_bytes);
418 /* Delete old region. */
419 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
420 match->space, match->addr, match->level);
421 }
422 else if (mem_size == 0)
423 mem_size = MEM_SIZE;
424 /* Limit to KSEG1 size (512MB) */
425 if (mem_size > K1SIZE)
426 mem_size = K1SIZE;
427 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
428 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
429 K1BASE, K1SIZE, (long)mem_size, K0BASE);
430 }
431
432 device_init(sd);
433 }
434 else if (board != NULL
435 && (strcmp(board, BOARD_BSP) == 0))
436 {
437 int i;
438
439 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
440
441 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
442 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
443 0x9FC00000,
444 4 * 1024 * 1024, /* 4 MB */
445 0xBFC00000);
446
447 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
448 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
449 0x80000000,
450 4 * 1024 * 1024, /* 4 MB */
451 0xA0000000);
452
453 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
454 for (i=0; i<8; i++) /* 32 MB total */
455 {
456 unsigned size = 4 * 1024 * 1024; /* 4 MB */
457 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
458 0x88000000 + (i * size),
459 size,
460 0xA8000000 + (i * size));
461 }
462 }
463 #if (WITH_HW)
464 else if (board != NULL
465 && (strcmp(board, BOARD_JMR3904) == 0 ||
466 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
467 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
468 {
469 /* match VIRTUAL memory layout of JMR-TX3904 board */
470 int i;
471
472 /* --- disable monitor unless forced on by user --- */
473
474 if (! firmware_option_p)
475 {
476 idt_monitor_base = 0;
477 pmon_monitor_base = 0;
478 lsipmon_monitor_base = 0;
479 }
480
481 /* --- environment --- */
482
483 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
484
485 /* --- memory --- */
486
487 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
488 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
489 0x9FC00000,
490 4 * 1024 * 1024, /* 4 MB */
491 0xBFC00000);
492
493 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
494 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
495 0x80000000,
496 4 * 1024 * 1024, /* 4 MB */
497 0xA0000000);
498
499 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
500 for (i=0; i<8; i++) /* 32 MB total */
501 {
502 unsigned size = 4 * 1024 * 1024; /* 4 MB */
503 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
504 0x88000000 + (i * size),
505 size,
506 0xA8000000 + (i * size));
507 }
508
509 /* Dummy memory regions for unsimulated devices - sorted by address */
510
511 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
512 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
513 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
514 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
515 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
516 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
517 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
518 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
519 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
520
521
522 /* --- simulated devices --- */
523 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
524 sim_hw_parse (sd, "/tx3904cpu");
525 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
526 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
527 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
528 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
529 {
530 /* FIXME: poking at dv-sockser internals, use tcp backend if
531 --sockser_addr option was given.*/
532 extern char* sockser_addr;
533 if(sockser_addr == NULL)
534 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
535 else
536 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
537 }
538 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
539 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
540
541 /* -- device connections --- */
542 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
543 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
544 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
545 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
546 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
547 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
548
549 /* add PAL timer & I/O module */
550 if(! strcmp(board, BOARD_JMR3904_PAL))
551 {
552 /* the device */
553 sim_hw_parse (sd, "/pal@0xffff0000");
554 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
555
556 /* wire up interrupt ports to irc */
557 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
558 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
559 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
560 }
561
562 if(! strcmp(board, BOARD_JMR3904_DEBUG))
563 {
564 /* -- DEBUG: glue interrupt generators --- */
565 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
566 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
567 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
568 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
569 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
570 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
571 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
572 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
573 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
574 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
575 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
576 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
577 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
578 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
579 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
580 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
581 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
582 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
583 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
584 }
585
586 device_init(sd);
587 }
588 #endif
589
590
591 /* check for/establish the a reference program image */
592 if (sim_analyze_program (sd,
593 (STATE_PROG_ARGV (sd) != NULL
594 ? *STATE_PROG_ARGV (sd)
595 : NULL),
596 abfd) != SIM_RC_OK)
597 {
598 sim_module_uninstall (sd);
599 return 0;
600 }
601
602 /* Configure/verify the target byte order and other runtime
603 configuration options */
604 if (sim_config (sd) != SIM_RC_OK)
605 {
606 sim_module_uninstall (sd);
607 return 0;
608 }
609
610 if (sim_post_argv_init (sd) != SIM_RC_OK)
611 {
612 /* Uninstall the modules to avoid memory leaks,
613 file descriptor leaks, etc. */
614 sim_module_uninstall (sd);
615 return 0;
616 }
617
618 /* verify assumptions the simulator made about the host type system.
619 This macro does not return if there is a problem */
620 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
621 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
622
623 /* This is NASTY, in that we are assuming the size of specific
624 registers: */
625 {
626 int rn;
627 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
628 {
629 if (rn < 32)
630 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
631 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
632 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
633 else if ((rn >= 33) && (rn <= 37))
634 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
635 else if ((rn == SRIDX)
636 || (rn == FCR0IDX)
637 || (rn == FCR31IDX)
638 || ((rn >= 72) && (rn <= 89)))
639 cpu->register_widths[rn] = 32;
640 else
641 cpu->register_widths[rn] = 0;
642 }
643
644
645 }
646
647 #if defined(TRACE)
648 if (STATE & simTRACE)
649 open_trace(sd);
650 #endif /* TRACE */
651
652 /*
653 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
654 idt_monitor_base,
655 pmon_monitor_base,
656 lsipmon_monitor_base);
657 */
658
659 /* Write the monitor trap address handlers into the monitor (eeprom)
660 address space. This can only be done once the target endianness
661 has been determined. */
662 if (idt_monitor_base != 0)
663 {
664 unsigned loop;
665 unsigned idt_monitor_size = 1 << 11;
666
667 /* the default monitor region */
668 sim_do_commandf (sd, "memory region 0x%x,0x%x",
669 idt_monitor_base, idt_monitor_size);
670
671 /* Entry into the IDT monitor is via fixed address vectors, and
672 not using machine instructions. To avoid clashing with use of
673 the MIPS TRAP system, we place our own (simulator specific)
674 "undefined" instructions into the relevant vector slots. */
675 for (loop = 0; (loop < idt_monitor_size); loop += 4)
676 {
677 address_word vaddr = (idt_monitor_base + loop);
678 unsigned32 insn = (RSVD_INSTRUCTION |
679 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
680 << RSVD_INSTRUCTION_ARG_SHIFT));
681 H2T (insn);
682 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
683 }
684 }
685
686 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
687 {
688 /* The PMON monitor uses the same address space, but rather than
689 branching into it the address of a routine is loaded. We can
690 cheat for the moment, and direct the PMON routine to IDT style
691 instructions within the monitor space. This relies on the IDT
692 monitor not using the locations from 0xBFC00500 onwards as its
693 entry points.*/
694 unsigned loop;
695 for (loop = 0; (loop < 24); loop++)
696 {
697 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
698 switch (loop)
699 {
700 case 0: /* read */
701 value = 7;
702 break;
703 case 1: /* write */
704 value = 8;
705 break;
706 case 2: /* open */
707 value = 6;
708 break;
709 case 3: /* close */
710 value = 10;
711 break;
712 case 5: /* printf */
713 value = ((0x500 - 16) / 8); /* not an IDT reason code */
714 break;
715 case 8: /* cliexit */
716 value = 17;
717 break;
718 case 11: /* flush_cache */
719 value = 28;
720 break;
721 }
722
723 SIM_ASSERT (idt_monitor_base != 0);
724 value = ((unsigned int) idt_monitor_base + (value * 8));
725 H2T (value);
726
727 if (pmon_monitor_base != 0)
728 {
729 address_word vaddr = (pmon_monitor_base + (loop * 4));
730 sim_write (sd, vaddr, (char *)&value, sizeof (value));
731 }
732
733 if (lsipmon_monitor_base != 0)
734 {
735 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
736 sim_write (sd, vaddr, (char *)&value, sizeof (value));
737 }
738 }
739
740 /* Write an abort sequence into the TRAP (common) exception vector
741 addresses. This is to catch code executing a TRAP (et.al.)
742 instruction without installing a trap handler. */
743 if ((idt_monitor_base != 0) ||
744 (pmon_monitor_base != 0) ||
745 (lsipmon_monitor_base != 0))
746 {
747 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
748 HALT_INSTRUCTION /* BREAK */ };
749 H2T (halt[0]);
750 H2T (halt[1]);
751 sim_write (sd, 0x80000000, (char *) halt, sizeof (halt));
752 sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
753 sim_write (sd, 0x80000200, (char *) halt, sizeof (halt));
754 /* XXX: Write here unconditionally? */
755 sim_write (sd, 0xBFC00200, (char *) halt, sizeof (halt));
756 sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
757 sim_write (sd, 0xBFC00400, (char *) halt, sizeof (halt));
758 }
759 }
760
761
762
763 return sd;
764 }
765
766 #if defined(TRACE)
767 static void
768 open_trace(sd)
769 SIM_DESC sd;
770 {
771 tracefh = fopen(tracefile,"wb+");
772 if (tracefh == NULL)
773 {
774 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
775 tracefh = stderr;
776 }
777 }
778 #endif /* TRACE */
779
780 /* Return name of an insn, used by insn profiling. */
781 static const char *
782 get_insn_name (sim_cpu *cpu, int i)
783 {
784 return itable[i].name;
785 }
786
787 void
788 sim_close (sd, quitting)
789 SIM_DESC sd;
790 int quitting;
791 {
792 #ifdef DEBUG
793 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
794 #endif
795
796
797 /* "quitting" is non-zero if we cannot hang on errors */
798
799 /* shut down modules */
800 sim_module_uninstall (sd);
801
802 /* Ensure that any resources allocated through the callback
803 mechanism are released: */
804 sim_io_shutdown (sd);
805
806 #if defined(TRACE)
807 if (tracefh != NULL && tracefh != stderr)
808 fclose(tracefh);
809 tracefh = NULL;
810 #endif /* TRACE */
811
812 /* FIXME - free SD */
813
814 return;
815 }
816
817
818 int
819 sim_write (sd,addr,buffer,size)
820 SIM_DESC sd;
821 SIM_ADDR addr;
822 unsigned char *buffer;
823 int size;
824 {
825 int index;
826 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
827
828 /* Return the number of bytes written, or zero if error. */
829 #ifdef DEBUG
830 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
831 #endif
832
833 /* We use raw read and write routines, since we do not want to count
834 the GDB memory accesses in our statistics gathering. */
835
836 for (index = 0; index < size; index++)
837 {
838 address_word vaddr = (address_word)addr + index;
839 address_word paddr;
840 int cca;
841 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
842 break;
843 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
844 break;
845 }
846
847 return(index);
848 }
849
850 int
851 sim_read (sd,addr,buffer,size)
852 SIM_DESC sd;
853 SIM_ADDR addr;
854 unsigned char *buffer;
855 int size;
856 {
857 int index;
858 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
859
860 /* Return the number of bytes read, or zero if error. */
861 #ifdef DEBUG
862 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
863 #endif /* DEBUG */
864
865 for (index = 0; (index < size); index++)
866 {
867 address_word vaddr = (address_word)addr + index;
868 address_word paddr;
869 int cca;
870 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
871 break;
872 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
873 break;
874 }
875
876 return(index);
877 }
878
879 int
880 sim_store_register (sd,rn,memory,length)
881 SIM_DESC sd;
882 int rn;
883 unsigned char *memory;
884 int length;
885 {
886 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
887 /* NOTE: gdb (the client) stores registers in target byte order
888 while the simulator uses host byte order */
889 #ifdef DEBUG
890 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
891 #endif /* DEBUG */
892
893 /* Unfortunately this suffers from the same problem as the register
894 numbering one. We need to know what the width of each logical
895 register number is for the architecture being simulated. */
896
897 if (cpu->register_widths[rn] == 0)
898 {
899 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
900 return 0;
901 }
902
903
904
905 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
906 {
907 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
908 if (cpu->register_widths[rn] == 32)
909 {
910 if (length == 8)
911 {
912 cpu->fgr[rn - FGR_BASE] =
913 (unsigned32) T2H_8 (*(unsigned64*)memory);
914 return 8;
915 }
916 else
917 {
918 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
919 return 4;
920 }
921 }
922 else
923 {
924 if (length == 8)
925 {
926 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
927 return 8;
928 }
929 else
930 {
931 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
932 return 4;
933 }
934 }
935 }
936
937 if (cpu->register_widths[rn] == 32)
938 {
939 if (length == 8)
940 {
941 cpu->registers[rn] =
942 (unsigned32) T2H_8 (*(unsigned64*)memory);
943 return 8;
944 }
945 else
946 {
947 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
948 return 4;
949 }
950 }
951 else
952 {
953 if (length == 8)
954 {
955 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
956 return 8;
957 }
958 else
959 {
960 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
961 return 4;
962 }
963 }
964
965 return 0;
966 }
967
968 int
969 sim_fetch_register (sd,rn,memory,length)
970 SIM_DESC sd;
971 int rn;
972 unsigned char *memory;
973 int length;
974 {
975 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
976 /* NOTE: gdb (the client) stores registers in target byte order
977 while the simulator uses host byte order */
978 #ifdef DEBUG
979 #if 0 /* FIXME: doesn't compile */
980 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
981 #endif
982 #endif /* DEBUG */
983
984 if (cpu->register_widths[rn] == 0)
985 {
986 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
987 return 0;
988 }
989
990
991
992 /* Any floating point register */
993 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
994 {
995 if (cpu->register_widths[rn] == 32)
996 {
997 if (length == 8)
998 {
999 *(unsigned64*)memory =
1000 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
1001 return 8;
1002 }
1003 else
1004 {
1005 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
1006 return 4;
1007 }
1008 }
1009 else
1010 {
1011 if (length == 8)
1012 {
1013 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
1014 return 8;
1015 }
1016 else
1017 {
1018 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
1019 return 4;
1020 }
1021 }
1022 }
1023
1024 if (cpu->register_widths[rn] == 32)
1025 {
1026 if (length == 8)
1027 {
1028 *(unsigned64*)memory =
1029 H2T_8 ((unsigned32) (cpu->registers[rn]));
1030 return 8;
1031 }
1032 else
1033 {
1034 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1035 return 4;
1036 }
1037 }
1038 else
1039 {
1040 if (length == 8)
1041 {
1042 *(unsigned64*)memory =
1043 H2T_8 ((unsigned64) (cpu->registers[rn]));
1044 return 8;
1045 }
1046 else
1047 {
1048 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1049 return 4;
1050 }
1051 }
1052
1053 return 0;
1054 }
1055
1056
1057 SIM_RC
1058 sim_create_inferior (sd, abfd, argv,env)
1059 SIM_DESC sd;
1060 struct bfd *abfd;
1061 char **argv;
1062 char **env;
1063 {
1064
1065 #ifdef DEBUG
1066 #if 0 /* FIXME: doesn't compile */
1067 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1068 pr_addr(PC));
1069 #endif
1070 #endif /* DEBUG */
1071
1072 ColdReset(sd);
1073
1074 if (abfd != NULL)
1075 {
1076 /* override PC value set by ColdReset () */
1077 int cpu_nr;
1078 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1079 {
1080 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1081 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1082 }
1083 }
1084
1085 #if 0 /* def DEBUG */
1086 if (argv || env)
1087 {
1088 /* We should really place the argv slot values into the argument
1089 registers, and onto the stack as required. However, this
1090 assumes that we have a stack defined, which is not
1091 necessarily true at the moment. */
1092 char **cptr;
1093 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1094 for (cptr = argv; (cptr && *cptr); cptr++)
1095 printf("DBG: arg \"%s\"\n",*cptr);
1096 }
1097 #endif /* DEBUG */
1098
1099 return SIM_RC_OK;
1100 }
1101
1102 void
1103 sim_do_command (sd,cmd)
1104 SIM_DESC sd;
1105 char *cmd;
1106 {
1107 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1108 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1109 cmd);
1110 }
1111
1112 /*---------------------------------------------------------------------------*/
1113 /*-- Private simulator support interface ------------------------------------*/
1114 /*---------------------------------------------------------------------------*/
1115
1116 /* Read a null terminated string from memory, return in a buffer */
1117 static char *
1118 fetch_str (SIM_DESC sd,
1119 address_word addr)
1120 {
1121 char *buf;
1122 int nr = 0;
1123 char null;
1124 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1125 nr++;
1126 buf = NZALLOC (char, nr + 1);
1127 sim_read (sd, addr, buf, nr);
1128 return buf;
1129 }
1130
1131
1132 /* Implements the "sim firmware" command:
1133 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1134 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1135 defaults to the normal address for that monitor.
1136 sim firmware none --- don't emulate any ROM monitor. Useful
1137 if you need a clean address space. */
1138 static SIM_RC
1139 sim_firmware_command (SIM_DESC sd, char *arg)
1140 {
1141 int address_present = 0;
1142 SIM_ADDR address;
1143
1144 /* Signal occurrence of this option. */
1145 firmware_option_p = 1;
1146
1147 /* Parse out the address, if present. */
1148 {
1149 char *p = strchr (arg, '@');
1150 if (p)
1151 {
1152 char *q;
1153 address_present = 1;
1154 p ++; /* skip over @ */
1155
1156 address = strtoul (p, &q, 0);
1157 if (*q != '\0')
1158 {
1159 sim_io_printf (sd, "Invalid address given to the"
1160 "`sim firmware NAME@ADDRESS' command: %s\n",
1161 p);
1162 return SIM_RC_FAIL;
1163 }
1164 }
1165 else
1166 {
1167 address_present = 0;
1168 address = -1; /* Dummy value. */
1169 }
1170 }
1171
1172 if (! strncmp (arg, "idt", 3))
1173 {
1174 idt_monitor_base = address_present ? address : 0xBFC00000;
1175 pmon_monitor_base = 0;
1176 lsipmon_monitor_base = 0;
1177 }
1178 else if (! strncmp (arg, "pmon", 4))
1179 {
1180 /* pmon uses indirect calls. Hook into implied idt. */
1181 pmon_monitor_base = address_present ? address : 0xBFC00500;
1182 idt_monitor_base = pmon_monitor_base - 0x500;
1183 lsipmon_monitor_base = 0;
1184 }
1185 else if (! strncmp (arg, "lsipmon", 7))
1186 {
1187 /* lsipmon uses indirect calls. Hook into implied idt. */
1188 pmon_monitor_base = 0;
1189 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1190 idt_monitor_base = lsipmon_monitor_base - 0x200;
1191 }
1192 else if (! strncmp (arg, "none", 4))
1193 {
1194 if (address_present)
1195 {
1196 sim_io_printf (sd,
1197 "The `sim firmware none' command does "
1198 "not take an `ADDRESS' argument.\n");
1199 return SIM_RC_FAIL;
1200 }
1201 idt_monitor_base = 0;
1202 pmon_monitor_base = 0;
1203 lsipmon_monitor_base = 0;
1204 }
1205 else
1206 {
1207 sim_io_printf (sd, "\
1208 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1209 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1210 arg);
1211 return SIM_RC_FAIL;
1212 }
1213
1214 return SIM_RC_OK;
1215 }
1216
1217
1218
1219 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1220 int
1221 sim_monitor (SIM_DESC sd,
1222 sim_cpu *cpu,
1223 address_word cia,
1224 unsigned int reason)
1225 {
1226 #ifdef DEBUG
1227 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1228 #endif /* DEBUG */
1229
1230 /* The IDT monitor actually allows two instructions per vector
1231 slot. However, the simulator currently causes a trap on each
1232 individual instruction. We cheat, and lose the bottom bit. */
1233 reason >>= 1;
1234
1235 /* The following callback functions are available, however the
1236 monitor we are simulating does not make use of them: get_errno,
1237 isatty, lseek, rename, system, time and unlink */
1238 switch (reason)
1239 {
1240
1241 case 6: /* int open(char *path,int flags) */
1242 {
1243 char *path = fetch_str (sd, A0);
1244 V0 = sim_io_open (sd, path, (int)A1);
1245 zfree (path);
1246 break;
1247 }
1248
1249 case 7: /* int read(int file,char *ptr,int len) */
1250 {
1251 int fd = A0;
1252 int nr = A2;
1253 char *buf = zalloc (nr);
1254 V0 = sim_io_read (sd, fd, buf, nr);
1255 sim_write (sd, A1, buf, nr);
1256 zfree (buf);
1257 }
1258 break;
1259
1260 case 8: /* int write(int file,char *ptr,int len) */
1261 {
1262 int fd = A0;
1263 int nr = A2;
1264 char *buf = zalloc (nr);
1265 sim_read (sd, A1, buf, nr);
1266 V0 = sim_io_write (sd, fd, buf, nr);
1267 zfree (buf);
1268 break;
1269 }
1270
1271 case 10: /* int close(int file) */
1272 {
1273 V0 = sim_io_close (sd, (int)A0);
1274 break;
1275 }
1276
1277 case 2: /* Densan monitor: char inbyte(int waitflag) */
1278 {
1279 if (A0 == 0) /* waitflag == NOWAIT */
1280 V0 = (unsigned_word)-1;
1281 }
1282 /* Drop through to case 11 */
1283
1284 case 11: /* char inbyte(void) */
1285 {
1286 char tmp;
1287 /* ensure that all output has gone... */
1288 sim_io_flush_stdout (sd);
1289 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1290 {
1291 sim_io_error(sd,"Invalid return from character read");
1292 V0 = (unsigned_word)-1;
1293 }
1294 else
1295 V0 = (unsigned_word)tmp;
1296 break;
1297 }
1298
1299 case 3: /* Densan monitor: void co(char chr) */
1300 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1301 {
1302 char tmp = (char)(A0 & 0xFF);
1303 sim_io_write_stdout (sd, &tmp, sizeof(char));
1304 break;
1305 }
1306
1307 case 17: /* void _exit() */
1308 {
1309 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1310 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1311 (unsigned int)(A0 & 0xFFFFFFFF));
1312 break;
1313 }
1314
1315 case 28: /* PMON flush_cache */
1316 break;
1317
1318 case 55: /* void get_mem_info(unsigned int *ptr) */
1319 /* in: A0 = pointer to three word memory location */
1320 /* out: [A0 + 0] = size */
1321 /* [A0 + 4] = instruction cache size */
1322 /* [A0 + 8] = data cache size */
1323 {
1324 unsigned_4 value;
1325 unsigned_4 zero = 0;
1326 address_word mem_size;
1327 sim_memopt *entry, *match = NULL;
1328
1329 /* Search for memory region mapped to KSEG0 or KSEG1. */
1330 for (entry = STATE_MEMOPT (sd);
1331 entry != NULL;
1332 entry = entry->next)
1333 {
1334 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1335 && (!match || entry->level < match->level))
1336 match = entry;
1337 else
1338 {
1339 sim_memopt *alias;
1340 for (alias = entry->alias;
1341 alias != NULL;
1342 alias = alias->next)
1343 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1344 && (!match || entry->level < match->level))
1345 match = entry;
1346 }
1347 }
1348
1349 /* Get region size, limit to KSEG1 size (512MB). */
1350 SIM_ASSERT (match != NULL);
1351 mem_size = (match->modulo != 0
1352 ? match->modulo : match->nr_bytes);
1353 if (mem_size > K1SIZE)
1354 mem_size = K1SIZE;
1355
1356 value = mem_size;
1357 H2T (value);
1358 sim_write (sd, A0 + 0, (char *)&value, 4);
1359 sim_write (sd, A0 + 4, (char *)&zero, 4);
1360 sim_write (sd, A0 + 8, (char *)&zero, 4);
1361 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1362 break;
1363 }
1364
1365 case 158: /* PMON printf */
1366 /* in: A0 = pointer to format string */
1367 /* A1 = optional argument 1 */
1368 /* A2 = optional argument 2 */
1369 /* A3 = optional argument 3 */
1370 /* out: void */
1371 /* The following is based on the PMON printf source */
1372 {
1373 address_word s = A0;
1374 char c;
1375 signed_word *ap = &A1; /* 1st argument */
1376 /* This isn't the quickest way, since we call the host print
1377 routine for every character almost. But it does avoid
1378 having to allocate and manage a temporary string buffer. */
1379 /* TODO: Include check that we only use three arguments (A1,
1380 A2 and A3) */
1381 while (sim_read (sd, s++, &c, 1) && c != '\0')
1382 {
1383 if (c == '%')
1384 {
1385 char tmp[40];
1386 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1387 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1388 while (sim_read (sd, s++, &c, 1) && c != '\0')
1389 {
1390 if (strchr ("dobxXulscefg%", c))
1391 break;
1392 else if (c == '-')
1393 fmt = FMT_LJUST;
1394 else if (c == '0')
1395 fmt = FMT_RJUST0;
1396 else if (c == '~')
1397 fmt = FMT_CENTER;
1398 else if (c == '*')
1399 {
1400 if (haddot)
1401 trunc = (int)*ap++;
1402 else
1403 width = (int)*ap++;
1404 }
1405 else if (c >= '1' && c <= '9')
1406 {
1407 address_word t = s;
1408 unsigned int n;
1409 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1410 tmp[s - t] = c;
1411 tmp[s - t] = '\0';
1412 n = (unsigned int)strtol(tmp,NULL,10);
1413 if (haddot)
1414 trunc = n;
1415 else
1416 width = n;
1417 s--;
1418 }
1419 else if (c == '.')
1420 haddot = 1;
1421 }
1422 switch (c)
1423 {
1424 case '%':
1425 sim_io_printf (sd, "%%");
1426 break;
1427 case 's':
1428 if ((int)*ap != 0)
1429 {
1430 address_word p = *ap++;
1431 char ch;
1432 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1433 sim_io_printf(sd, "%c", ch);
1434 }
1435 else
1436 sim_io_printf(sd,"(null)");
1437 break;
1438 case 'c':
1439 sim_io_printf (sd, "%c", (int)*ap++);
1440 break;
1441 default:
1442 if (c == 'l')
1443 {
1444 sim_read (sd, s++, &c, 1);
1445 if (c == 'l')
1446 {
1447 longlong = 1;
1448 sim_read (sd, s++, &c, 1);
1449 }
1450 }
1451 if (strchr ("dobxXu", c))
1452 {
1453 word64 lv = (word64) *ap++;
1454 if (c == 'b')
1455 sim_io_printf(sd,"<binary not supported>");
1456 else
1457 {
1458 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1459 if (longlong)
1460 sim_io_printf(sd, tmp, lv);
1461 else
1462 sim_io_printf(sd, tmp, (int)lv);
1463 }
1464 }
1465 else if (strchr ("eEfgG", c))
1466 {
1467 double dbl = *(double*)(ap++);
1468 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1469 sim_io_printf (sd, tmp, dbl);
1470 trunc = 0;
1471 }
1472 }
1473 }
1474 else
1475 sim_io_printf(sd, "%c", c);
1476 }
1477 break;
1478 }
1479
1480 default:
1481 /* Unknown reason. */
1482 return 0;
1483 }
1484 return 1;
1485 }
1486
1487 /* Store a word into memory. */
1488
1489 static void
1490 store_word (SIM_DESC sd,
1491 sim_cpu *cpu,
1492 address_word cia,
1493 uword64 vaddr,
1494 signed_word val)
1495 {
1496 address_word paddr;
1497 int uncached;
1498
1499 if ((vaddr & 3) != 0)
1500 SignalExceptionAddressStore ();
1501 else
1502 {
1503 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1504 isTARGET, isREAL))
1505 {
1506 const uword64 mask = 7;
1507 uword64 memval;
1508 unsigned int byte;
1509
1510 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1511 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1512 memval = ((uword64) val) << (8 * byte);
1513 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1514 isREAL);
1515 }
1516 }
1517 }
1518
1519 /* Load a word from memory. */
1520
1521 static signed_word
1522 load_word (SIM_DESC sd,
1523 sim_cpu *cpu,
1524 address_word cia,
1525 uword64 vaddr)
1526 {
1527 if ((vaddr & 3) != 0)
1528 {
1529 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1530 }
1531 else
1532 {
1533 address_word paddr;
1534 int uncached;
1535
1536 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1537 isTARGET, isREAL))
1538 {
1539 const uword64 mask = 0x7;
1540 const unsigned int reverse = ReverseEndian ? 1 : 0;
1541 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1542 uword64 memval;
1543 unsigned int byte;
1544
1545 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1546 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1547 isDATA, isREAL);
1548 byte = (vaddr & mask) ^ (bigend << 2);
1549 return EXTEND32 (memval >> (8 * byte));
1550 }
1551 }
1552
1553 return 0;
1554 }
1555
1556 /* Simulate the mips16 entry and exit pseudo-instructions. These
1557 would normally be handled by the reserved instruction exception
1558 code, but for ease of simulation we just handle them directly. */
1559
1560 static void
1561 mips16_entry (SIM_DESC sd,
1562 sim_cpu *cpu,
1563 address_word cia,
1564 unsigned int insn)
1565 {
1566 int aregs, sregs, rreg;
1567
1568 #ifdef DEBUG
1569 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1570 #endif /* DEBUG */
1571
1572 aregs = (insn & 0x700) >> 8;
1573 sregs = (insn & 0x0c0) >> 6;
1574 rreg = (insn & 0x020) >> 5;
1575
1576 /* This should be checked by the caller. */
1577 if (sregs == 3)
1578 abort ();
1579
1580 if (aregs < 5)
1581 {
1582 int i;
1583 signed_word tsp;
1584
1585 /* This is the entry pseudo-instruction. */
1586
1587 for (i = 0; i < aregs; i++)
1588 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1589
1590 tsp = SP;
1591 SP -= 32;
1592
1593 if (rreg)
1594 {
1595 tsp -= 4;
1596 store_word (SD, CPU, cia, (uword64) tsp, RA);
1597 }
1598
1599 for (i = 0; i < sregs; i++)
1600 {
1601 tsp -= 4;
1602 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1603 }
1604 }
1605 else
1606 {
1607 int i;
1608 signed_word tsp;
1609
1610 /* This is the exit pseudo-instruction. */
1611
1612 tsp = SP + 32;
1613
1614 if (rreg)
1615 {
1616 tsp -= 4;
1617 RA = load_word (SD, CPU, cia, (uword64) tsp);
1618 }
1619
1620 for (i = 0; i < sregs; i++)
1621 {
1622 tsp -= 4;
1623 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1624 }
1625
1626 SP += 32;
1627
1628 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1629 {
1630 if (aregs == 5)
1631 {
1632 FGR[0] = WORD64LO (GPR[4]);
1633 FPR_STATE[0] = fmt_uninterpreted;
1634 }
1635 else if (aregs == 6)
1636 {
1637 FGR[0] = WORD64LO (GPR[5]);
1638 FGR[1] = WORD64LO (GPR[4]);
1639 FPR_STATE[0] = fmt_uninterpreted;
1640 FPR_STATE[1] = fmt_uninterpreted;
1641 }
1642 }
1643
1644 PC = RA;
1645 }
1646
1647 }
1648
1649 /*-- trace support ----------------------------------------------------------*/
1650
1651 /* The TRACE support is provided (if required) in the memory accessing
1652 routines. Since we are also providing the architecture specific
1653 features, the architecture simulation code can also deal with
1654 notifying the TRACE world of cache flushes, etc. Similarly we do
1655 not need to provide profiling support in the simulator engine,
1656 since we can sample in the instruction fetch control loop. By
1657 defining the TRACE manifest, we add tracing as a run-time
1658 option. */
1659
1660 #if defined(TRACE)
1661 /* Tracing by default produces "din" format (as required by
1662 dineroIII). Each line of such a trace file *MUST* have a din label
1663 and address field. The rest of the line is ignored, so comments can
1664 be included if desired. The first field is the label which must be
1665 one of the following values:
1666
1667 0 read data
1668 1 write data
1669 2 instruction fetch
1670 3 escape record (treated as unknown access type)
1671 4 escape record (causes cache flush)
1672
1673 The address field is a 32bit (lower-case) hexadecimal address
1674 value. The address should *NOT* be preceded by "0x".
1675
1676 The size of the memory transfer is not important when dealing with
1677 cache lines (as long as no more than a cache line can be
1678 transferred in a single operation :-), however more information
1679 could be given following the dineroIII requirement to allow more
1680 complete memory and cache simulators to provide better
1681 results. i.e. the University of Pisa has a cache simulator that can
1682 also take bus size and speed as (variable) inputs to calculate
1683 complete system performance (a much more useful ability when trying
1684 to construct an end product, rather than a processor). They
1685 currently have an ARM version of their tool called ChARM. */
1686
1687
1688 void
1689 dotrace (SIM_DESC sd,
1690 sim_cpu *cpu,
1691 FILE *tracefh,
1692 int type,
1693 SIM_ADDR address,
1694 int width,
1695 char *comment,...)
1696 {
1697 if (STATE & simTRACE) {
1698 va_list ap;
1699 fprintf(tracefh,"%d %s ; width %d ; ",
1700 type,
1701 pr_addr(address),
1702 width);
1703 va_start(ap,comment);
1704 vfprintf(tracefh,comment,ap);
1705 va_end(ap);
1706 fprintf(tracefh,"\n");
1707 }
1708 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1709 we may be generating 64bit ones, we should put the hi-32bits of the
1710 address into the comment field. */
1711
1712 /* TODO: Provide a buffer for the trace lines. We can then avoid
1713 performing writes until the buffer is filled, or the file is
1714 being closed. */
1715
1716 /* NOTE: We could consider adding a comment field to the "din" file
1717 produced using type 3 markers (unknown access). This would then
1718 allow information about the program that the "din" is for, and
1719 the MIPs world that was being simulated, to be placed into the
1720 trace file. */
1721
1722 return;
1723 }
1724 #endif /* TRACE */
1725
1726 /*---------------------------------------------------------------------------*/
1727 /*-- simulator engine -------------------------------------------------------*/
1728 /*---------------------------------------------------------------------------*/
1729
1730 static void
1731 ColdReset (SIM_DESC sd)
1732 {
1733 int cpu_nr;
1734 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1735 {
1736 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1737 /* RESET: Fixed PC address: */
1738 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1739 /* The reset vector address is in the unmapped, uncached memory space. */
1740
1741 SR &= ~(status_SR | status_TS | status_RP);
1742 SR |= (status_ERL | status_BEV);
1743
1744 /* Cheat and allow access to the complete register set immediately */
1745 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1746 && WITH_TARGET_WORD_BITSIZE == 64)
1747 SR |= status_FR; /* 64bit registers */
1748
1749 /* Ensure that any instructions with pending register updates are
1750 cleared: */
1751 PENDING_INVALIDATE();
1752
1753 /* Initialise the FPU registers to the unknown state */
1754 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1755 {
1756 int rn;
1757 for (rn = 0; (rn < 32); rn++)
1758 FPR_STATE[rn] = fmt_uninterpreted;
1759 }
1760
1761 /* Initialise the Config0 register. */
1762 C0_CONFIG = 0x80000000 /* Config1 present */
1763 | 2; /* KSEG0 uncached */
1764 if (WITH_TARGET_WORD_BITSIZE == 64)
1765 {
1766 /* FIXME Currently mips/sim-main.c:address_translation()
1767 truncates all addresses to 32-bits. */
1768 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1769 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1770 else
1771 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1772 }
1773 if (BigEndianMem)
1774 C0_CONFIG |= 0x00008000; /* Big Endian */
1775 }
1776 }
1777
1778
1779
1780
1781 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1782 /* Signal an exception condition. This will result in an exception
1783 that aborts the instruction. The instruction operation pseudocode
1784 will never see a return from this function call. */
1785
1786 void
1787 signal_exception (SIM_DESC sd,
1788 sim_cpu *cpu,
1789 address_word cia,
1790 int exception,...)
1791 {
1792 /* int vector; */
1793
1794 #ifdef DEBUG
1795 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1796 #endif /* DEBUG */
1797
1798 /* Ensure that any active atomic read/modify/write operation will fail: */
1799 LLBIT = 0;
1800
1801 /* Save registers before interrupt dispatching */
1802 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1803 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1804 #endif
1805
1806 switch (exception) {
1807
1808 case DebugBreakPoint:
1809 if (! (Debug & Debug_DM))
1810 {
1811 if (INDELAYSLOT())
1812 {
1813 CANCELDELAYSLOT();
1814
1815 Debug |= Debug_DBD; /* signaled from within in delay slot */
1816 DEPC = cia - 4; /* reference the branch instruction */
1817 }
1818 else
1819 {
1820 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1821 DEPC = cia;
1822 }
1823
1824 Debug |= Debug_DM; /* in debugging mode */
1825 Debug |= Debug_DBp; /* raising a DBp exception */
1826 PC = 0xBFC00200;
1827 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1828 }
1829 break;
1830
1831 case ReservedInstruction:
1832 {
1833 va_list ap;
1834 unsigned int instruction;
1835 va_start(ap,exception);
1836 instruction = va_arg(ap,unsigned int);
1837 va_end(ap);
1838 /* Provide simple monitor support using ReservedInstruction
1839 exceptions. The following code simulates the fixed vector
1840 entry points into the IDT monitor by causing a simulator
1841 trap, performing the monitor operation, and returning to
1842 the address held in the $ra register (standard PCS return
1843 address). This means we only need to pre-load the vector
1844 space with suitable instruction values. For systems were
1845 actual trap instructions are used, we would not need to
1846 perform this magic. */
1847 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1848 {
1849 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1850 if (!sim_monitor (SD, CPU, cia, reason))
1851 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1852
1853 /* NOTE: This assumes that a branch-and-link style
1854 instruction was used to enter the vector (which is the
1855 case with the current IDT monitor). */
1856 sim_engine_restart (SD, CPU, NULL, RA);
1857 }
1858 /* Look for the mips16 entry and exit instructions, and
1859 simulate a handler for them. */
1860 else if ((cia & 1) != 0
1861 && (instruction & 0xf81f) == 0xe809
1862 && (instruction & 0x0c0) != 0x0c0)
1863 {
1864 mips16_entry (SD, CPU, cia, instruction);
1865 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1866 }
1867 /* else fall through to normal exception processing */
1868 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1869 }
1870
1871 default:
1872 /* Store exception code into current exception id variable (used
1873 by exit code): */
1874
1875 /* TODO: If not simulating exceptions then stop the simulator
1876 execution. At the moment we always stop the simulation. */
1877
1878 #ifdef SUBTARGET_R3900
1879 /* update interrupt-related registers */
1880
1881 /* insert exception code in bits 6:2 */
1882 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1883 /* shift IE/KU history bits left */
1884 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1885
1886 if (STATE & simDELAYSLOT)
1887 {
1888 STATE &= ~simDELAYSLOT;
1889 CAUSE |= cause_BD;
1890 EPC = (cia - 4); /* reference the branch instruction */
1891 }
1892 else
1893 EPC = cia;
1894
1895 if (SR & status_BEV)
1896 PC = (signed)0xBFC00000 + 0x180;
1897 else
1898 PC = (signed)0x80000000 + 0x080;
1899 #else
1900 /* See figure 5-17 for an outline of the code below */
1901 if (! (SR & status_EXL))
1902 {
1903 CAUSE = (exception << 2);
1904 if (STATE & simDELAYSLOT)
1905 {
1906 STATE &= ~simDELAYSLOT;
1907 CAUSE |= cause_BD;
1908 EPC = (cia - 4); /* reference the branch instruction */
1909 }
1910 else
1911 EPC = cia;
1912 /* FIXME: TLB et.al. */
1913 /* vector = 0x180; */
1914 }
1915 else
1916 {
1917 CAUSE = (exception << 2);
1918 /* vector = 0x180; */
1919 }
1920 SR |= status_EXL;
1921 /* Store exception code into current exception id variable (used
1922 by exit code): */
1923
1924 if (SR & status_BEV)
1925 PC = (signed)0xBFC00200 + 0x180;
1926 else
1927 PC = (signed)0x80000000 + 0x180;
1928 #endif
1929
1930 switch ((CAUSE >> 2) & 0x1F)
1931 {
1932 case Interrupt:
1933 /* Interrupts arrive during event processing, no need to
1934 restart */
1935 return;
1936
1937 case NMIReset:
1938 /* Ditto */
1939 #ifdef SUBTARGET_3900
1940 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1941 PC = (signed)0xBFC00000;
1942 #endif /* SUBTARGET_3900 */
1943 return;
1944
1945 case TLBModification:
1946 case TLBLoad:
1947 case TLBStore:
1948 case AddressLoad:
1949 case AddressStore:
1950 case InstructionFetch:
1951 case DataReference:
1952 /* The following is so that the simulator will continue from the
1953 exception handler address. */
1954 sim_engine_halt (SD, CPU, NULL, PC,
1955 sim_stopped, SIM_SIGBUS);
1956
1957 case ReservedInstruction:
1958 case CoProcessorUnusable:
1959 PC = EPC;
1960 sim_engine_halt (SD, CPU, NULL, PC,
1961 sim_stopped, SIM_SIGILL);
1962
1963 case IntegerOverflow:
1964 case FPE:
1965 sim_engine_halt (SD, CPU, NULL, PC,
1966 sim_stopped, SIM_SIGFPE);
1967
1968 case BreakPoint:
1969 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1970 break;
1971
1972 case SystemCall:
1973 case Trap:
1974 sim_engine_restart (SD, CPU, NULL, PC);
1975 break;
1976
1977 case Watch:
1978 PC = EPC;
1979 sim_engine_halt (SD, CPU, NULL, PC,
1980 sim_stopped, SIM_SIGTRAP);
1981
1982 default: /* Unknown internal exception */
1983 PC = EPC;
1984 sim_engine_halt (SD, CPU, NULL, PC,
1985 sim_stopped, SIM_SIGABRT);
1986
1987 }
1988
1989 case SimulatorFault:
1990 {
1991 va_list ap;
1992 char *msg;
1993 va_start(ap,exception);
1994 msg = va_arg(ap,char *);
1995 va_end(ap);
1996 sim_engine_abort (SD, CPU, NULL_CIA,
1997 "FATAL: Simulator error \"%s\"\n",msg);
1998 }
1999 }
2000
2001 return;
2002 }
2003
2004
2005
2006 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2007 "UNPREDICTABLE" behaviour.
2008
2009 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2010 may vary from processor implementation to processor implementation,
2011 instruction to instruction, or as a function of time on the same
2012 implementation or instruction. Software can never depend on results
2013 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2014 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2015 0.95, page 2.)
2016
2017 For UNPREDICTABLE behaviour, we print a message, if possible print
2018 the offending instructions mips.igen instruction name (provided by
2019 the caller), and stop the simulator.
2020
2021 XXX FIXME: eventually, stopping the simulator should be made conditional
2022 on a command-line option. */
2023 void
2024 unpredictable_action(sim_cpu *cpu, address_word cia)
2025 {
2026 SIM_DESC sd = CPU_STATE(cpu);
2027
2028 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
2029 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
2030 }
2031
2032
2033 /*-- co-processor support routines ------------------------------------------*/
2034
2035 static int UNUSED
2036 CoProcPresent(unsigned int coproc_number)
2037 {
2038 /* Return TRUE if simulator provides a model for the given co-processor number */
2039 return(0);
2040 }
2041
2042 void
2043 cop_lw (SIM_DESC sd,
2044 sim_cpu *cpu,
2045 address_word cia,
2046 int coproc_num,
2047 int coproc_reg,
2048 unsigned int memword)
2049 {
2050 switch (coproc_num)
2051 {
2052 case 1:
2053 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2054 {
2055 #ifdef DEBUG
2056 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2057 #endif
2058 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
2059 break;
2060 }
2061
2062 default:
2063 #if 0 /* this should be controlled by a configuration option */
2064 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2065 #endif
2066 break;
2067 }
2068
2069 return;
2070 }
2071
2072 void
2073 cop_ld (SIM_DESC sd,
2074 sim_cpu *cpu,
2075 address_word cia,
2076 int coproc_num,
2077 int coproc_reg,
2078 uword64 memword)
2079 {
2080
2081 #ifdef DEBUG
2082 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2083 #endif
2084
2085 switch (coproc_num) {
2086 case 1:
2087 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2088 {
2089 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
2090 break;
2091 }
2092
2093 default:
2094 #if 0 /* this message should be controlled by a configuration option */
2095 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2096 #endif
2097 break;
2098 }
2099
2100 return;
2101 }
2102
2103
2104
2105
2106 unsigned int
2107 cop_sw (SIM_DESC sd,
2108 sim_cpu *cpu,
2109 address_word cia,
2110 int coproc_num,
2111 int coproc_reg)
2112 {
2113 unsigned int value = 0;
2114
2115 switch (coproc_num)
2116 {
2117 case 1:
2118 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2119 {
2120 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
2121 break;
2122 }
2123
2124 default:
2125 #if 0 /* should be controlled by configuration option */
2126 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2127 #endif
2128 break;
2129 }
2130
2131 return(value);
2132 }
2133
2134 uword64
2135 cop_sd (SIM_DESC sd,
2136 sim_cpu *cpu,
2137 address_word cia,
2138 int coproc_num,
2139 int coproc_reg)
2140 {
2141 uword64 value = 0;
2142 switch (coproc_num)
2143 {
2144 case 1:
2145 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2146 {
2147 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
2148 break;
2149 }
2150
2151 default:
2152 #if 0 /* should be controlled by configuration option */
2153 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2154 #endif
2155 break;
2156 }
2157
2158 return(value);
2159 }
2160
2161
2162
2163
2164 void
2165 decode_coproc (SIM_DESC sd,
2166 sim_cpu *cpu,
2167 address_word cia,
2168 unsigned int instruction)
2169 {
2170 int coprocnum = ((instruction >> 26) & 3);
2171
2172 switch (coprocnum)
2173 {
2174 case 0: /* standard CPU control and cache registers */
2175 {
2176 int code = ((instruction >> 21) & 0x1F);
2177 int rt = ((instruction >> 16) & 0x1F);
2178 int rd = ((instruction >> 11) & 0x1F);
2179 int tail = instruction & 0x3ff;
2180 /* R4000 Users Manual (second edition) lists the following CP0
2181 instructions:
2182 CODE><-RT><RD-><--TAIL--->
2183 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2184 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2185 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2186 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2187 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2188 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2189 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2190 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2191 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2192 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2193 */
2194 if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
2195 || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
2196 && tail == 0)
2197 {
2198 /* Clear double/single coprocessor move bit. */
2199 code &= ~1;
2200
2201 /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
2202
2203 switch (rd) /* NOTEs: Standard CP0 registers */
2204 {
2205 /* 0 = Index R4000 VR4100 VR4300 */
2206 /* 1 = Random R4000 VR4100 VR4300 */
2207 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2208 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2209 /* 4 = Context R4000 VR4100 VR4300 */
2210 /* 5 = PageMask R4000 VR4100 VR4300 */
2211 /* 6 = Wired R4000 VR4100 VR4300 */
2212 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2213 /* 9 = Count R4000 VR4100 VR4300 */
2214 /* 10 = EntryHi R4000 VR4100 VR4300 */
2215 /* 11 = Compare R4000 VR4100 VR4300 */
2216 /* 12 = SR R4000 VR4100 VR4300 */
2217 #ifdef SUBTARGET_R3900
2218 case 3:
2219 /* 3 = Config R3900 */
2220 case 7:
2221 /* 7 = Cache R3900 */
2222 case 15:
2223 /* 15 = PRID R3900 */
2224
2225 /* ignore */
2226 break;
2227
2228 case 8:
2229 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2230 if (code == 0x00)
2231 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
2232 else
2233 COP0_BADVADDR = GPR[rt];
2234 break;
2235
2236 #endif /* SUBTARGET_R3900 */
2237 case 12:
2238 if (code == 0x00)
2239 GPR[rt] = SR;
2240 else
2241 SR = GPR[rt];
2242 break;
2243 /* 13 = Cause R4000 VR4100 VR4300 */
2244 case 13:
2245 if (code == 0x00)
2246 GPR[rt] = CAUSE;
2247 else
2248 CAUSE = GPR[rt];
2249 break;
2250 /* 14 = EPC R4000 VR4100 VR4300 */
2251 case 14:
2252 if (code == 0x00)
2253 GPR[rt] = (signed_word) (signed_address) EPC;
2254 else
2255 EPC = GPR[rt];
2256 break;
2257 /* 15 = PRId R4000 VR4100 VR4300 */
2258 #ifdef SUBTARGET_R3900
2259 /* 16 = Debug */
2260 case 16:
2261 if (code == 0x00)
2262 GPR[rt] = Debug;
2263 else
2264 Debug = GPR[rt];
2265 break;
2266 #else
2267 /* 16 = Config R4000 VR4100 VR4300 */
2268 case 16:
2269 if (code == 0x00)
2270 GPR[rt] = C0_CONFIG;
2271 else
2272 /* only bottom three bits are writable */
2273 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
2274 break;
2275 #endif
2276 #ifdef SUBTARGET_R3900
2277 /* 17 = Debug */
2278 case 17:
2279 if (code == 0x00)
2280 GPR[rt] = DEPC;
2281 else
2282 DEPC = GPR[rt];
2283 break;
2284 #else
2285 /* 17 = LLAddr R4000 VR4100 VR4300 */
2286 #endif
2287 /* 18 = WatchLo R4000 VR4100 VR4300 */
2288 /* 19 = WatchHi R4000 VR4100 VR4300 */
2289 /* 20 = XContext R4000 VR4100 VR4300 */
2290 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2291 /* 27 = CacheErr R4000 VR4100 */
2292 /* 28 = TagLo R4000 VR4100 VR4300 */
2293 /* 29 = TagHi R4000 VR4100 VR4300 */
2294 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2295 if (STATE_VERBOSE_P(SD))
2296 sim_io_eprintf (SD,
2297 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2298 (unsigned long)cia);
2299 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2300 /* CPR[0,rd] = GPR[rt]; */
2301 default:
2302 if (code == 0x00)
2303 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2304 else
2305 COP0_GPR[rd] = GPR[rt];
2306 #if 0
2307 if (code == 0x00)
2308 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2309 else
2310 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2311 #endif
2312 }
2313 }
2314 else if ((code == 0x00 || code == 0x01)
2315 && rd == 16)
2316 {
2317 /* [D]MFC0 RT,C0_CONFIG,SEL */
2318 signed32 cfg = 0;
2319 switch (tail & 0x07)
2320 {
2321 case 0:
2322 cfg = C0_CONFIG;
2323 break;
2324 case 1:
2325 /* MIPS32 r/o Config1:
2326 Config2 present */
2327 cfg = 0x80000000;
2328 /* MIPS16 implemented.
2329 XXX How to check configuration? */
2330 cfg |= 0x0000004;
2331 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2332 /* MDMX & FPU implemented */
2333 cfg |= 0x00000021;
2334 break;
2335 case 2:
2336 /* MIPS32 r/o Config2:
2337 Config3 present. */
2338 cfg = 0x80000000;
2339 break;
2340 case 3:
2341 /* MIPS32 r/o Config3:
2342 SmartMIPS implemented. */
2343 cfg = 0x00000002;
2344 break;
2345 }
2346 GPR[rt] = cfg;
2347 }
2348 else if (code == 0x10 && (tail & 0x3f) == 0x18)
2349 {
2350 /* ERET */
2351 if (SR & status_ERL)
2352 {
2353 /* Oops, not yet available */
2354 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2355 PC = EPC;
2356 SR &= ~status_ERL;
2357 }
2358 else
2359 {
2360 PC = EPC;
2361 SR &= ~status_EXL;
2362 }
2363 }
2364 else if (code == 0x10 && (tail & 0x3f) == 0x10)
2365 {
2366 /* RFE */
2367 #ifdef SUBTARGET_R3900
2368 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2369
2370 /* shift IE/KU history bits right */
2371 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2372
2373 /* TODO: CACHE register */
2374 #endif /* SUBTARGET_R3900 */
2375 }
2376 else if (code == 0x10 && (tail & 0x3f) == 0x1F)
2377 {
2378 /* DERET */
2379 Debug &= ~Debug_DM;
2380 DELAYSLOT();
2381 DSPC = DEPC;
2382 }
2383 else
2384 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2385 /* TODO: When executing an ERET or RFE instruction we should
2386 clear LLBIT, to ensure that any out-standing atomic
2387 read/modify/write sequence fails. */
2388 }
2389 break;
2390
2391 case 2: /* co-processor 2 */
2392 {
2393 int handle = 0;
2394
2395
2396 if(! handle)
2397 {
2398 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2399 instruction,pr_addr(cia));
2400 }
2401 }
2402 break;
2403
2404 case 1: /* should not occur (FPU co-processor) */
2405 case 3: /* should not occur (FPU co-processor) */
2406 SignalException(ReservedInstruction,instruction);
2407 break;
2408 }
2409
2410 return;
2411 }
2412
2413
2414 /* This code copied from gdb's utils.c. Would like to share this code,
2415 but don't know of a common place where both could get to it. */
2416
2417 /* Temporary storage using circular buffer */
2418 #define NUMCELLS 16
2419 #define CELLSIZE 32
2420 static char*
2421 get_cell (void)
2422 {
2423 static char buf[NUMCELLS][CELLSIZE];
2424 static int cell=0;
2425 if (++cell>=NUMCELLS) cell=0;
2426 return buf[cell];
2427 }
2428
2429 /* Print routines to handle variable size regs, etc */
2430
2431 /* Eliminate warning from compiler on 32-bit systems */
2432 static int thirty_two = 32;
2433
2434 char*
2435 pr_addr(addr)
2436 SIM_ADDR addr;
2437 {
2438 char *paddr_str=get_cell();
2439 switch (sizeof(addr))
2440 {
2441 case 8:
2442 sprintf(paddr_str,"%08lx%08lx",
2443 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2444 break;
2445 case 4:
2446 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2447 break;
2448 case 2:
2449 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2450 break;
2451 default:
2452 sprintf(paddr_str,"%x",addr);
2453 }
2454 return paddr_str;
2455 }
2456
2457 char*
2458 pr_uword64(addr)
2459 uword64 addr;
2460 {
2461 char *paddr_str=get_cell();
2462 sprintf(paddr_str,"%08lx%08lx",
2463 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2464 return paddr_str;
2465 }
2466
2467
2468 void
2469 mips_core_signal (SIM_DESC sd,
2470 sim_cpu *cpu,
2471 sim_cia cia,
2472 unsigned map,
2473 int nr_bytes,
2474 address_word addr,
2475 transfer_type transfer,
2476 sim_core_signals sig)
2477 {
2478 const char *copy = (transfer == read_transfer ? "read" : "write");
2479 address_word ip = CIA_ADDR (cia);
2480
2481 switch (sig)
2482 {
2483 case sim_core_unmapped_signal:
2484 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2485 nr_bytes, copy,
2486 (unsigned long) addr, (unsigned long) ip);
2487 COP0_BADVADDR = addr;
2488 SignalExceptionDataReference();
2489 break;
2490
2491 case sim_core_unaligned_signal:
2492 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2493 nr_bytes, copy,
2494 (unsigned long) addr, (unsigned long) ip);
2495 COP0_BADVADDR = addr;
2496 if(transfer == read_transfer)
2497 SignalExceptionAddressLoad();
2498 else
2499 SignalExceptionAddressStore();
2500 break;
2501
2502 default:
2503 sim_engine_abort (sd, cpu, cia,
2504 "mips_core_signal - internal error - bad switch");
2505 }
2506 }
2507
2508
2509 void
2510 mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2511 {
2512 ASSERT(cpu != NULL);
2513
2514 if(cpu->exc_suspended > 0)
2515 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2516
2517 PC = cia;
2518 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2519 cpu->exc_suspended = 0;
2520 }
2521
2522 void
2523 mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2524 {
2525 ASSERT(cpu != NULL);
2526
2527 if(cpu->exc_suspended > 0)
2528 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2529 cpu->exc_suspended, exception);
2530
2531 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2532 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2533 cpu->exc_suspended = exception;
2534 }
2535
2536 void
2537 mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2538 {
2539 ASSERT(cpu != NULL);
2540
2541 if(exception == 0 && cpu->exc_suspended > 0)
2542 {
2543 /* warn not for breakpoints */
2544 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2545 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2546 cpu->exc_suspended);
2547 }
2548 else if(exception != 0 && cpu->exc_suspended > 0)
2549 {
2550 if(exception != cpu->exc_suspended)
2551 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2552 cpu->exc_suspended, exception);
2553
2554 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2555 }
2556 else if(exception != 0 && cpu->exc_suspended == 0)
2557 {
2558 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2559 }
2560 cpu->exc_suspended = 0;
2561 }
2562
2563
2564 /*---------------------------------------------------------------------------*/
2565 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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