2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 We only need to take account of the target endianness when moving data
23 between the simulator and the host. We do not need to worry about the
24 endianness of the host, since this sim code and GDB are executing in
27 The IDT monitor (found on the VR4300 board), seems to lie about
28 register contents. It seems to treat the registers as sign-extended
29 32-bit values. This cause *REAL* problems when single-stepping 64-bit
34 /* The TRACE and PROFILE manifests enable the provision of extra
35 features. If they are not defined then a simpler (quicker)
36 simulator is constructed without the required run-time checks,
38 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
45 #include "sim-utils.h"
46 #include "sim-options.h"
47 #include "sim-assert.h"
69 #include "libiberty.h"
71 #include "callback.h" /* GDB simulator callback interface */
72 #include "remote-sim.h" /* GDB simulator interface */
80 char* pr_addr
PARAMS ((SIM_ADDR addr
));
81 char* pr_uword64
PARAMS ((uword64 addr
));
84 /* Get the simulator engine description, without including the code: */
90 /* The following reserved instruction value is used when a simulator
91 trap is required. NOTE: Care must be taken, since this value may be
92 used in later revisions of the MIPS ISA. */
93 #define RSVD_INSTRUCTION (0x00000005)
94 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
96 #define RSVD_INSTRUCTION_ARG_SHIFT 6
97 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
100 /* The following are generic to all versions of the MIPS architecture
102 /* Memory Access Types (for CCA): */
104 #define CachedNoncoherent (1)
105 #define CachedCoherent (2)
108 #define isINSTRUCTION (1 == 0) /* FALSE */
109 #define isDATA (1 == 1) /* TRUE */
111 #define isLOAD (1 == 0) /* FALSE */
112 #define isSTORE (1 == 1) /* TRUE */
114 #define isREAL (1 == 0) /* FALSE */
115 #define isRAW (1 == 1) /* TRUE */
117 #define isTARGET (1 == 0) /* FALSE */
118 #define isHOST (1 == 1) /* TRUE */
120 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
121 is the number of bytes minus 1. */
122 #define AccessLength_BYTE (0)
123 #define AccessLength_HALFWORD (1)
124 #define AccessLength_TRIPLEBYTE (2)
125 #define AccessLength_WORD (3)
126 #define AccessLength_QUINTIBYTE (4)
127 #define AccessLength_SEXTIBYTE (5)
128 #define AccessLength_SEPTIBYTE (6)
129 #define AccessLength_DOUBLEWORD (7)
130 #define AccessLength_QUADWORD (15)
133 /* Bits in the Debug register */
134 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
135 #define Debug_DM 0x40000000 /* Debug Mode */
136 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
140 /* start-sanitize-r5900 */
142 #define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
143 #define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
144 #define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
145 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
147 #define BYTES_IN_MIPS_REGS (sizeof(signed_word))
148 #define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
149 #define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
150 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
156 SUB_REG_FETCH - return as lvalue some sub-part of a "register"
157 T - type of the sub part
158 TC - # of T's in the mips part of the "register"
159 I - index (from 0) of desired sub part
160 A - low part of "register"
161 A1 - high part of register
163 #define SUB_REG_FETCH(T,TC,A,A1,I) \
164 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
165 + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
166 ? ((TC) - 1 - (I) % (TC)) \
173 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
174 where <type> has two letters:
175 1 is S=signed or U=unsigned
176 2 is B=byte H=halfword W=word D=doubleword
179 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
180 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
181 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
182 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
184 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
185 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
186 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
187 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
189 #define GPR_SB(R,I) SUB_REG_SB(®ISTERS[R], ®ISTERS1[R], I)
190 #define GPR_SH(R,I) SUB_REG_SH(®ISTERS[R], ®ISTERS1[R], I)
191 #define GPR_SW(R,I) SUB_REG_SW(®ISTERS[R], ®ISTERS1[R], I)
192 #define GPR_SD(R,I) SUB_REG_SD(®ISTERS[R], ®ISTERS1[R], I)
194 #define GPR_UB(R,I) SUB_REG_UB(®ISTERS[R], ®ISTERS1[R], I)
195 #define GPR_UH(R,I) SUB_REG_UH(®ISTERS[R], ®ISTERS1[R], I)
196 #define GPR_UW(R,I) SUB_REG_UW(®ISTERS[R], ®ISTERS1[R], I)
197 #define GPR_UD(R,I) SUB_REG_UD(®ISTERS[R], ®ISTERS1[R], I)
200 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
201 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
202 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
203 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
205 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
206 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
207 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
208 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
210 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
211 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
212 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
213 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
215 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
216 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
217 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
218 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
222 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
223 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
224 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
225 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
227 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
228 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
229 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
230 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
232 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
233 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
234 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
235 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
237 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
238 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
239 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
240 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
241 /* end-sanitize-r5900 */
244 /* TODO : these should be the bitmasks for these bits within the
245 status register. At the moment the following are VR4300
247 #define status_KSU_mask (0x3) /* mask for KSU bits */
248 #define status_KSU_shift (3) /* shift for field */
249 #define ksu_kernel (0x0)
250 #define ksu_supervisor (0x1)
251 #define ksu_user (0x2)
252 #define ksu_unknown (0x3)
254 #define status_IE (1 << 0) /* Interrupt enable */
255 #define status_EXL (1 << 1) /* Exception level */
256 #define status_RE (1 << 25) /* Reverse Endian in user mode */
257 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
258 #define status_SR (1 << 20) /* soft reset or NMI */
259 #define status_BEV (1 << 22) /* Location of general exception vectors */
260 #define status_TS (1 << 21) /* TLB shutdown has occurred */
261 #define status_ERL (1 << 2) /* Error level */
262 #define status_RP (1 << 27) /* Reduced Power mode */
264 #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
267 /* Macro to update FPSR condition-code field. This is complicated by
268 the fact that there is a hole in the index range of the bits within
269 the FCSR register. Also, the number of bits visible depends on the
270 MIPS ISA version being supported. */
271 #define SETFCC(cc,v) {\
272 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
273 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
275 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
277 /* This should be the COC1 value at the start of the preceding
279 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
282 /* Standard FCRS bits: */
283 #define IR (0) /* Inexact Result */
284 #define UF (1) /* UnderFlow */
285 #define OF (2) /* OverFlow */
286 #define DZ (3) /* Division by Zero */
287 #define IO (4) /* Invalid Operation */
288 #define UO (5) /* Unimplemented Operation */
290 /* Get masks for individual flags: */
291 #if 1 /* SAFE version */
292 #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
293 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
294 #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
296 #define FP_FLAGS(b) (1 << ((b) + 2))
297 #define FP_ENABLE(b) (1 << ((b) + 7))
298 #define FP_CAUSE(b) (1 << ((b) + 12))
301 #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
303 #define FP_MASK_RM (0x3)
305 #define FP_RM_NEAREST (0) /* Round to nearest (Round) */
306 #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
307 #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
308 #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
309 #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
311 /*---------------------------------------------------------------------------*/
312 /*-- GDB simulator interface ------------------------------------------------*/
313 /*---------------------------------------------------------------------------*/
315 static void dotrace
PARAMS((SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...));
316 static void ColdReset
PARAMS((SIM_DESC sd
));
317 static long getnum
PARAMS((SIM_DESC sd
, char *value
));
318 static unsigned int power2
PARAMS((unsigned int value
));
319 static void mips_set_profile
PARAMS((SIM_DESC sd
, int n
));
320 static void mips_set_profile_size
PARAMS((SIM_DESC sd
, int n
));
321 static void mips_size
PARAMS((SIM_DESC sd
, int n
));
323 /*---------------------------------------------------------------------------*/
325 /* The following are not used for MIPS IV onwards: */
326 #define PENDING_FILL(r,v) {\
327 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
328 if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
329 sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
330 PENDING_SLOT_COUNT[PENDING_IN] = 2;\
331 PENDING_SLOT_REG[PENDING_IN] = (r);\
332 PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
333 /*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
336 if (PENDING_IN == PSLOTS)\
338 /*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
342 /* NOTE: We keep the following status flags as bit values (1 for true,
343 0 for false). This allows them to be used in binary boolean
344 operations without worrying about what exactly the non-zero true
348 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
351 /* Hardware configuration. Affects endianness of LoadMemory and
352 StoreMemory and the endianness of Kernel and Supervisor mode
353 execution. The value is 0 for little-endian; 1 for big-endian. */
354 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
355 /*(state & simBE) ? 1 : 0)*/
358 /* This is true if the host and target have different endianness. */
359 #define ByteSwapMem (CURRENT_TARGET_BYTE_ORDER != CURRENT_HOST_BYTE_ORDER)
362 /* This mode is selected if in User mode with the RE bit being set in
363 SR (Status Register). It reverses the endianness of load and store
365 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
368 /* The endianness for load and store instructions (0=little;1=big). In
369 User mode this endianness may be switched by setting the state_RE
370 bit in the SR register. Thus, BigEndianCPU may be computed as
371 (BigEndianMem EOR ReverseEndian). */
372 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
374 #if !defined(FASTSIM) || defined(PROFILE)
375 /* At the moment these values will be the same, since we do not have
376 access to the pipeline cycle count information from the simulator
378 /* FIXME: These will be replaced by ../common/sim-profile.h */
379 static unsigned int instruction_fetches
= 0;
380 static unsigned int instruction_fetch_overflow
= 0;
383 /* Flags in the "state" variable: */
384 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
385 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
386 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
387 #define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */
388 #define simPCOC0 (1 << 17) /* COC[1] from current */
389 #define simPCOC1 (1 << 18) /* COC[1] from previous */
390 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
391 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
392 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
393 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
395 #define DELAYSLOT() {\
396 if (STATE & simDELAYSLOT)\
397 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
398 STATE |= simDELAYSLOT;\
401 #define JALDELAYSLOT() {\
403 STATE |= simJALDELAYSLOT;\
407 STATE &= ~simDELAYSLOT;\
408 STATE |= simSKIPNEXT;\
411 #define CANCELDELAYSLOT() {\
413 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
416 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
417 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
419 #define K0BASE (0x80000000)
420 #define K0SIZE (0x20000000)
421 #define K1BASE (0xA0000000)
422 #define K1SIZE (0x20000000)
424 /* Simple run-time monitor support */
425 static unsigned char *monitor
= NULL
;
426 static ut_reg monitor_base
= 0xBFC00000;
427 static unsigned monitor_size
= (1 << 11); /* power-of-2 */
429 static char *logfile
= NULL
; /* logging disabled by default */
430 static FILE *logfh
= NULL
;
433 static char *tracefile
= "trace.din"; /* default filename for trace log */
434 static FILE *tracefh
= NULL
;
435 static void open_trace
PARAMS((SIM_DESC sd
));
439 static unsigned profile_frequency
= 256;
440 static unsigned profile_nsamples
= (128 << 10);
441 static unsigned short *profile_hist
= NULL
;
442 static ut_reg profile_minpc
;
443 static ut_reg profile_maxpc
;
444 static int profile_shift
= 0; /* address shift amount */
449 mips_option_handler (sd
, opt
, arg
)
459 tmp
= (char *)malloc(strlen(arg
) + 1);
461 sim_io_printf(sd
,"Failed to allocate buffer for logfile name \"%s\"\n",optarg
);
470 sim_io_printf(sd
,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg
);
475 /* Eventually the simTRACE flag could be treated as a toggle, to
476 allow external control of the program points being traced
477 (i.e. only from main onwards, excluding the run-time setup,
481 else if (strcmp (arg
, "yes") == 0)
483 else if (strcmp (arg
, "no") == 0)
487 fprintf (stderr
, "Unreconized trace option `%s'\n", arg
);
493 Simulator constructed without tracing support (for performance).\n\
494 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
500 if (optarg
!= NULL
) {
502 tmp
= (char *)malloc(strlen(optarg
) + 1);
505 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
511 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
523 Simulator constructed without profiling support (for performance).\n\
524 Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
526 #endif /* !PROFILE */
530 profile_nsamples
= (unsigned)getnum(sd
, optarg
);
536 mips_set_profile(sd
, (int)getnum(sd
, optarg
));
545 static const OPTION mips_options
[] =
547 { {"log", required_argument
, NULL
,'l'},
548 'l', "FILE", "Log file",
549 mips_option_handler
},
550 { {"name", required_argument
, NULL
,'n'},
551 'n', "MODEL", "Select arch model",
552 mips_option_handler
},
553 { {"profile", optional_argument
, NULL
,'p'},
554 'p', "on|off", "Enable profiling",
555 mips_option_handler
},
556 { {"trace", optional_argument
, NULL
,'t'},
557 't', "on|off", "Enable tracing",
558 mips_option_handler
},
559 { {"tracefile",required_argument
, NULL
,'z'},
560 'z', "FILE", "Write trace to file",
561 mips_option_handler
},
562 { {"frequency",required_argument
, NULL
,'y'},
563 'y', "FREQ", "Profile frequency",
564 mips_option_handler
},
565 { {"samples", required_argument
, NULL
,'x'},
566 'x', "SIZE", "Profile sample size",
567 mips_option_handler
},
568 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
572 int interrupt_pending
;
575 interrupt_event (SIM_DESC sd
, void *data
)
579 interrupt_pending
= 0;
580 SignalExceptionInterrupt ();
582 else if (!interrupt_pending
)
583 sim_events_schedule (sd
, 1, interrupt_event
, data
);
588 /*---------------------------------------------------------------------------*/
589 /*-- GDB simulator interface ------------------------------------------------*/
590 /*---------------------------------------------------------------------------*/
593 sim_open (kind
, cb
, abfd
, argv
)
599 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
600 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
602 /* FIXME: watchpoints code shouldn't need this */
603 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
604 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
605 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
607 /* memory defaults (unless sim_size was here first) */
608 if (STATE_MEM_SIZE (sd
) == 0)
609 STATE_MEM_SIZE (sd
) = (2 << 20);
610 STATE_MEM_BASE (sd
) = K1BASE
;
614 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
616 sim_add_option_table (sd
, mips_options
);
618 /* getopt will print the error message so we just have to exit if this fails.
619 FIXME: Hmmm... in the case of gdb we need getopt to call
621 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
623 /* Uninstall the modules to avoid memory leaks,
624 file descriptor leaks, etc. */
625 sim_module_uninstall (sd
);
629 /* check for/establish the a reference program image */
630 if (sim_analyze_program (sd
,
631 (STATE_PROG_ARGV (sd
) != NULL
632 ? *STATE_PROG_ARGV (sd
)
636 sim_module_uninstall (sd
);
640 /* Configure/verify the target byte order and other runtime
641 configuration options */
642 if (sim_config (sd
) != SIM_RC_OK
)
644 sim_module_uninstall (sd
);
648 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
650 /* Uninstall the modules to avoid memory leaks,
651 file descriptor leaks, etc. */
652 sim_module_uninstall (sd
);
656 /* verify assumptions the simulator made about the host type system.
657 This macro does not return if there is a problem */
658 if (sizeof(int) != (4 * sizeof(char)))
659 SignalExceptionSimulatorFault ("sizeof(int) != 4");
660 if (sizeof(word64
) != (8 * sizeof(char)))
661 SignalExceptionSimulatorFault ("sizeof(word64) != 8");
664 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
665 and DOUBLE binary formats. This is a bit nasty, requiring that we
666 trust the explicit manifests held in the source: */
667 /* TODO: We need to cope with the simulated target and the host not
668 having the same endianness. This will require the high and low
669 words of a (double) to be swapped when converting between the
670 host and the simulated target. */
678 s
.d
= (double)523.2939453125;
680 if ((s
.i
[0] == 0 && (s
.f
[1] != (float)4.01102924346923828125
681 || s
.i
[1] != 0x40805A5A))
682 || (s
.i
[1] == 0 && (s
.f
[0] != (float)4.01102924346923828125
683 || s
.i
[0] != 0x40805A5A)))
685 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
691 /* This is NASTY, in that we are assuming the size of specific
695 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
697 cpu
->register_widths
[rn
] = GPRLEN
;
698 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
699 cpu
->register_widths
[rn
] = GPRLEN
;
700 else if ((rn
>= 33) && (rn
<= 37))
701 cpu
->register_widths
[rn
] = GPRLEN
;
702 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
703 cpu
->register_widths
[rn
] = 32;
705 cpu
->register_widths
[rn
] = 0;
707 /* start-sanitize-r5900 */
709 /* set the 5900 "upper" registers to 64 bits */
710 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
711 cpu
->register_widths
[rn
] = 64;
712 /* end-sanitize-r5900 */
716 if (logfile
!= NULL
) {
717 if (strcmp(logfile
,"-") == 0)
720 logfh
= fopen(logfile
,"wb+");
722 sim_io_printf(sd
,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile
);
728 /* FIXME: In the future both of these malloc's can be replaced by
729 calls to sim-core. */
731 /* If the host has "mmap" available we could use it to provide a
732 very large virtual address space for the simulator, since memory
733 would only be allocated within the "mmap" space as it is
734 accessed. This can also be linked to the architecture specific
735 support, required to simulate the MMU. */
736 mips_size(sd
, STATE_MEM_SIZE (sd
));
737 /* NOTE: The above will also have enabled any profiling state! */
739 /* Create the monitor address space as well */
740 monitor
= (unsigned char *)calloc(1,monitor_size
);
742 fprintf(stderr
,"Not enough VM for monitor simulation (%d bytes)\n",
746 if (STATE
& simTRACE
)
750 /* Write the monitor trap address handlers into the monitor (eeprom)
751 address space. This can only be done once the target endianness
752 has been determined. */
755 /* Entry into the IDT monitor is via fixed address vectors, and
756 not using machine instructions. To avoid clashing with use of
757 the MIPS TRAP system, we place our own (simulator specific)
758 "undefined" instructions into the relevant vector slots. */
759 for (loop
= 0; (loop
< monitor_size
); loop
+= 4) {
760 uword64 vaddr
= (monitor_base
+ loop
);
763 if (AddressTranslation(vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isTARGET
, isRAW
))
764 StoreMemory(cca
, AccessLength_WORD
,
765 (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
)),
766 0, paddr
, vaddr
, isRAW
);
768 /* The PMON monitor uses the same address space, but rather than
769 branching into it the address of a routine is loaded. We can
770 cheat for the moment, and direct the PMON routine to IDT style
771 instructions within the monitor space. This relies on the IDT
772 monitor not using the locations from 0xBFC00500 onwards as its
774 for (loop
= 0; (loop
< 24); loop
++)
776 uword64 vaddr
= (monitor_base
+ 0x500 + (loop
* 4));
779 unsigned int value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
799 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
802 case 8: /* cliexit */
806 case 11: /* flush_cache */
810 /* FIXME - should monitor_base be SIM_ADDR?? */
811 value
= ((unsigned int)monitor_base
+ (value
* 8));
812 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
813 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
815 sim_io_error(sd
,"Failed to write to monitor space 0x%s",pr_addr(vaddr
));
817 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
819 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
820 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
822 sim_io_error(sd
,"Failed to write to monitor space 0x%s",pr_addr(vaddr
));
834 tracefh
= fopen(tracefile
,"wb+");
837 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
843 /* For the profile writing, we write the data in the host
844 endianness. This unfortunately means we are assuming that the
845 profile file we create is processed on the same host executing the
846 simulator. The gmon.out file format should either have an explicit
847 endianness, or a method of encoding the endianness in the file
850 writeout32(sd
,fh
,val
)
858 if (CURRENT_HOST_BYTE_ORDER
== BIG_ENDIAN
) {
859 buff
[3] = ((val
>> 0) & 0xFF);
860 buff
[2] = ((val
>> 8) & 0xFF);
861 buff
[1] = ((val
>> 16) & 0xFF);
862 buff
[0] = ((val
>> 24) & 0xFF);
864 buff
[0] = ((val
>> 0) & 0xFF);
865 buff
[1] = ((val
>> 8) & 0xFF);
866 buff
[2] = ((val
>> 16) & 0xFF);
867 buff
[3] = ((val
>> 24) & 0xFF);
869 if (fwrite(buff
,4,1,fh
) != 1) {
870 sim_io_eprintf(sd
,"Failed to write 4bytes to the profile file\n");
877 writeout16(sd
,fh
,val
)
884 if (CURRENT_HOST_BYTE_ORDER
== BIG_ENDIAN
) {
885 buff
[1] = ((val
>> 0) & 0xFF);
886 buff
[0] = ((val
>> 8) & 0xFF);
888 buff
[0] = ((val
>> 0) & 0xFF);
889 buff
[1] = ((val
>> 8) & 0xFF);
891 if (fwrite(buff
,2,1,fh
) != 1) {
892 sim_io_eprintf(sd
,"Failed to write 2bytes to the profile file\n");
899 sim_close (sd
, quitting
)
904 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
907 /* "quitting" is non-zero if we cannot hang on errors */
909 /* Ensure that any resources allocated through the callback
910 mechanism are released: */
911 sim_io_shutdown (sd
);
914 if ((STATE
& simPROFILE
) && (profile_hist
!= NULL
)) {
915 FILE *pf
= fopen("gmon.out","wb");
919 sim_io_eprintf(sd
,"Failed to open \"gmon.out\" profile file\n");
923 printf("DBG: minpc = 0x%s\n",pr_addr(profile_minpc
));
924 printf("DBG: maxpc = 0x%s\n",pr_addr(profile_maxpc
));
926 ok
= writeout32(pf
,(unsigned int)profile_minpc
);
928 ok
= writeout32(pf
,(unsigned int)profile_maxpc
);
930 ok
= writeout32(pf
,(profile_nsamples
* 2) + 12); /* size of sample buffer (+ header) */
932 printf("DBG: nsamples = %d (size = 0x%08X)\n",profile_nsamples
,((profile_nsamples
* 2) + 12));
934 for (loop
= 0; (ok
&& (loop
< profile_nsamples
)); loop
++) {
935 ok
= writeout16(pf
,profile_hist
[loop
]);
945 STATE
&= ~simPROFILE
;
950 if (tracefh
!= NULL
&& tracefh
!= stderr
)
956 if (logfh
!= NULL
&& logfh
!= stdout
&& logfh
!= stderr
)
960 if (STATE_MEMORY (sd
) != NULL
)
961 free(STATE_MEMORY (sd
)); /* cfree not available on all hosts */
962 STATE_MEMORY (sd
) = NULL
;
969 sim_write (sd
,addr
,buffer
,size
)
972 unsigned char *buffer
;
976 uword64 vaddr
= (uword64
)addr
;
978 /* Return the number of bytes written, or zero if error. */
980 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
983 /* We provide raw read and write routines, since we do not want to
984 count the GDB memory accesses in our statistics gathering. */
986 /* There is a lot of code duplication in the individual blocks
987 below, but the variables are declared locally to a block to give
988 the optimiser the best chance of improving the code. We have to
989 perform slow byte reads from the host memory, to ensure that we
990 get the data into the correct endianness for the (simulated)
991 target memory world. */
993 /* Mask count to get odd byte, odd halfword, and odd word out of the
994 way. We can then perform doubleword transfers to and from the
995 simulator memory for optimum performance. */
996 if (index
&& (index
& 1)) {
999 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1000 uword64 value
= ((uword64
)(*buffer
++));
1001 StoreMemory(cca
,AccessLength_BYTE
,value
,0,paddr
,vaddr
,isRAW
);
1004 index
&= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
1006 if (index
&& (index
& 2)) {
1009 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1011 /* We need to perform the following magic to ensure that that
1012 bytes are written into same byte positions in the target memory
1013 world, regardless of the endianness of the host. */
1015 value
= ((uword64
)(*buffer
++) << 8);
1016 value
|= ((uword64
)(*buffer
++) << 0);
1018 value
= ((uword64
)(*buffer
++) << 0);
1019 value
|= ((uword64
)(*buffer
++) << 8);
1021 StoreMemory(cca
,AccessLength_HALFWORD
,value
,0,paddr
,vaddr
,isRAW
);
1026 if (index
&& (index
& 4)) {
1029 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1032 value
= ((uword64
)(*buffer
++) << 24);
1033 value
|= ((uword64
)(*buffer
++) << 16);
1034 value
|= ((uword64
)(*buffer
++) << 8);
1035 value
|= ((uword64
)(*buffer
++) << 0);
1037 value
= ((uword64
)(*buffer
++) << 0);
1038 value
|= ((uword64
)(*buffer
++) << 8);
1039 value
|= ((uword64
)(*buffer
++) << 16);
1040 value
|= ((uword64
)(*buffer
++) << 24);
1042 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1047 for (;index
; index
-= 8) {
1050 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1053 value
= ((uword64
)(*buffer
++) << 56);
1054 value
|= ((uword64
)(*buffer
++) << 48);
1055 value
|= ((uword64
)(*buffer
++) << 40);
1056 value
|= ((uword64
)(*buffer
++) << 32);
1057 value
|= ((uword64
)(*buffer
++) << 24);
1058 value
|= ((uword64
)(*buffer
++) << 16);
1059 value
|= ((uword64
)(*buffer
++) << 8);
1060 value
|= ((uword64
)(*buffer
++) << 0);
1062 value
= ((uword64
)(*buffer
++) << 0);
1063 value
|= ((uword64
)(*buffer
++) << 8);
1064 value
|= ((uword64
)(*buffer
++) << 16);
1065 value
|= ((uword64
)(*buffer
++) << 24);
1066 value
|= ((uword64
)(*buffer
++) << 32);
1067 value
|= ((uword64
)(*buffer
++) << 40);
1068 value
|= ((uword64
)(*buffer
++) << 48);
1069 value
|= ((uword64
)(*buffer
++) << 56);
1071 StoreMemory(cca
,AccessLength_DOUBLEWORD
,value
,0,paddr
,vaddr
,isRAW
);
1080 sim_read (sd
,addr
,buffer
,size
)
1083 unsigned char *buffer
;
1088 /* Return the number of bytes read, or zero if error. */
1090 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
1093 /* TODO: Perform same optimisation as the sim_write() code
1094 above. NOTE: This will require a bit more work since we will need
1095 to ensure that the source physical address is doubleword aligned
1096 before, and then deal with trailing bytes. */
1097 for (index
= 0; (index
< size
); index
++) {
1098 uword64 vaddr
,paddr
,value
;
1100 vaddr
= (uword64
)addr
+ index
;
1101 if (AddressTranslation(vaddr
,isDATA
,isLOAD
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1102 LoadMemory(&value
,NULL
,cca
,AccessLength_BYTE
,paddr
,vaddr
,isDATA
,isRAW
);
1103 buffer
[index
] = (unsigned char)(value
&0xFF);
1112 sim_store_register (sd
,rn
,memory
)
1115 unsigned char *memory
;
1117 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
1118 /* NOTE: gdb (the client) stores registers in target byte order
1119 while the simulator uses host byte order */
1121 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
1124 /* Unfortunately this suffers from the same problem as the register
1125 numbering one. We need to know what the width of each logical
1126 register number is for the architecture being simulated. */
1128 if (cpu
->register_widths
[rn
] == 0)
1129 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
1130 /* start-sanitize-r5900 */
1131 else if (rn
== REGISTER_SA
)
1132 SA
= T2H_8(*(uword64
*)memory
);
1133 else if (rn
> LAST_EMBED_REGNUM
)
1134 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(uword64
*)memory
);
1135 /* end-sanitize-r5900 */
1136 else if (cpu
->register_widths
[rn
] == 32)
1137 cpu
->registers
[rn
] = T2H_4 (*(unsigned int*)memory
);
1139 cpu
->registers
[rn
] = T2H_8 (*(uword64
*)memory
);
1145 sim_fetch_register (sd
,rn
,memory
)
1148 unsigned char *memory
;
1150 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
1151 /* NOTE: gdb (the client) stores registers in target byte order
1152 while the simulator uses host byte order */
1154 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
1157 if (cpu
->register_widths
[rn
] == 0)
1158 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
1159 /* start-sanitize-r5900 */
1160 else if (rn
== REGISTER_SA
)
1161 *((uword64
*)memory
) = H2T_8(SA
);
1162 else if (rn
> LAST_EMBED_REGNUM
)
1163 *((uword64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
1164 /* end-sanitize-r5900 */
1165 else if (cpu
->register_widths
[rn
] == 32)
1166 *((unsigned int *)memory
) = H2T_4 ((unsigned int)(cpu
->registers
[rn
] & 0xFFFFFFFF));
1167 else /* 64bit register */
1168 *((uword64
*)memory
) = H2T_8 (cpu
->registers
[rn
]);
1175 sim_info (sd
,verbose
)
1179 /* Accessed from the GDB "info files" command: */
1180 if (STATE_VERBOSE_P (sd
) || verbose
)
1183 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
1184 (PROCESSOR_64BIT
? 64 : 32),
1185 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
1187 sim_io_printf (sd
, "0x%08X bytes of memory at 0x%s\n",
1188 STATE_MEM_SIZE (sd
),
1189 pr_addr (STATE_MEM_BASE (sd
)));
1191 #if !defined(FASTSIM)
1193 /* at present this simulator executes one instruction per
1194 simulator cycle. Consequently this data never changes */
1195 if (instruction_fetch_overflow
!= 0)
1196 sim_io_printf (sd
, "Instruction fetches = 0x%08X%08X\n",
1197 instruction_fetch_overflow
, instruction_fetches
);
1199 sim_io_printf (sd
, "Instruction fetches = %d\n", instruction_fetches
);
1201 /* It would be a useful feature, if when performing multi-cycle
1202 simulations (rather than single-stepping) we keep the start and
1203 end times of the execution, so that we can give a performance
1204 figure for the simulator. */
1205 #endif /* !FASTSIM */
1206 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
1207 (long) sim_events_time (sd
));
1209 /* print information pertaining to MIPS ISA and architecture being simulated */
1210 /* things that may be interesting */
1211 /* instructions executed - if available */
1212 /* cycles executed - if available */
1213 /* pipeline stalls - if available */
1214 /* virtual time taken */
1215 /* profiling size */
1216 /* profiling frequency */
1224 sim_create_inferior (sd
, abfd
, argv
,env
)
1232 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1237 /* If we were providing a more complete I/O, co-processor or memory
1238 simulation, we should perform any "device" initialisation at this
1239 point. This can include pre-loading memory areas with particular
1240 patterns (e.g. simulating ROM monitors). */
1244 PC
= (unsigned64
) bfd_get_start_address(abfd
);
1248 /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
1249 PC
= SIGNEXTEND(bfd_get_start_address(abfd
),32);
1252 /* Prepare to execute the program to be simulated */
1253 /* argv and env are NULL terminated lists of pointers */
1256 #if 0 /* def DEBUG */
1257 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1260 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1261 printf("DBG: arg \"%s\"\n",*cptr
);
1264 /* We should really place the argv slot values into the argument
1265 registers, and onto the stack as required. However, this
1266 assumes that we have a stack defined, which is not necessarily
1267 true at the moment. */
1273 typedef enum {e_terminate
,e_help
,e_setmemsize
,e_reset
} e_cmds
;
1275 static struct t_sim_command
{
1279 } sim_commands
[] = {
1280 {e_help
, "help", ": Show MIPS simulator private commands"},
1281 {e_setmemsize
,"set-memory-size","<n> : Specify amount of memory simulated"},
1282 {e_reset
, "reset-system", ": Reset the simulated processor"},
1287 sim_do_command (sd
,cmd
)
1291 struct t_sim_command
*cptr
;
1293 if (!(cmd
&& *cmd
!= '\0'))
1296 /* NOTE: Accessed from the GDB "sim" commmand: */
1297 for (cptr
= sim_commands
; cptr
&& cptr
->name
; cptr
++)
1298 if (strncmp (cmd
, cptr
->name
, strlen(cptr
->name
)) == 0)
1300 cmd
+= strlen(cptr
->name
);
1302 case e_help
: /* no arguments */
1303 { /* no arguments */
1304 struct t_sim_command
*lptr
;
1305 sim_io_printf(sd
,"List of MIPS simulator commands:\n");
1306 for (lptr
= sim_commands
; lptr
->name
; lptr
++)
1307 sim_io_printf(sd
,"%s %s\n",lptr
->name
,lptr
->help
);
1308 sim_args_command (sd
, "help");
1312 case e_setmemsize
: /* memory size argument */
1314 unsigned int newsize
= (unsigned int)getnum(sd
, cmd
);
1315 mips_size(sd
, newsize
);
1319 case e_reset
: /* no arguments */
1321 /* NOTE: See the comments in sim_open() relating to device
1326 sim_io_printf(sd
,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd
,cptr
->id
);
1334 /* try for a common command when the sim specific lookup fails */
1335 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
1336 sim_io_printf(sd
,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd
);
1342 /*---------------------------------------------------------------------------*/
1343 /* NOTE: The following routines do not seem to be used by GDB at the
1344 moment. However, they may be useful to the standalone simulator
1348 /* The profiling format is described in the "gmon_out.h" header file */
1350 mips_set_profile (sd
,n
)
1354 #if defined(PROFILE)
1355 profile_frequency
= n
;
1356 STATE
|= simPROFILE
;
1357 #endif /* PROFILE */
1362 mips_set_profile_size (sd
,n
)
1366 #if defined(PROFILE)
1367 if (STATE
& simPROFILE
) {
1370 /* Since we KNOW that the memory banks are a power-of-2 in size: */
1371 profile_nsamples
= power2(n
);
1372 profile_minpc
= STATE_MEM_BASE (sd
);
1373 profile_maxpc
= (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
));
1375 /* Just in-case we are sampling every address: NOTE: The shift
1376 right of 2 is because we only have word-aligned PC addresses. */
1377 if (profile_nsamples
> (STATE_MEM_SIZE (sd
) >> 2))
1378 profile_nsamples
= (STATE_MEM_SIZE (sd
) >> 2);
1380 /* Since we are dealing with power-of-2 values: */
1381 profile_shift
= (((STATE_MEM_SIZE (sd
) >> 2) / profile_nsamples
) - 1);
1383 bsize
= (profile_nsamples
* sizeof(unsigned short));
1384 if (profile_hist
== NULL
)
1385 profile_hist
= (unsigned short *)calloc(64,(bsize
/ 64));
1387 profile_hist
= (unsigned short *)realloc(profile_hist
,bsize
);
1388 if (profile_hist
== NULL
) {
1389 sim_io_eprintf(sd
,"Failed to allocate VM for profiling buffer (0x%08X bytes)\n",bsize
);
1390 STATE
&= ~simPROFILE
;
1393 #endif /* PROFILE */
1399 mips_size(sd
, newsize
)
1404 /* Used by "run", and internally, to set the simulated memory size */
1406 sim_io_printf(sd
,"Zero not valid: Memory size still 0x%08X bytes\n",STATE_MEM_SIZE (sd
));
1409 newsize
= power2(newsize
);
1410 if (STATE_MEMORY (sd
) == NULL
)
1411 new = (char *)calloc(64,(STATE_MEM_SIZE (sd
) / 64));
1413 new = (char *)realloc(STATE_MEMORY (sd
),newsize
);
1415 if (STATE_MEMORY (sd
) == NULL
)
1416 sim_io_error(sd
,"Not enough VM for simulation memory of 0x%08X bytes",STATE_MEM_SIZE (sd
));
1418 sim_io_eprintf(sd
,"Failed to resize memory (still 0x%08X bytes)\n",STATE_MEM_SIZE (sd
));
1420 STATE_MEM_SIZE (sd
) = (unsigned)newsize
;
1421 STATE_MEMORY (sd
) = new;
1422 #if defined(PROFILE)
1423 /* Ensure that we sample across the new memory range */
1424 mips_set_profile_size(sd
, profile_nsamples
);
1425 #endif /* PROFILE */
1432 /*---------------------------------------------------------------------------*/
1433 /*-- Private simulator support interface ------------------------------------*/
1434 /*---------------------------------------------------------------------------*/
1436 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1438 sim_monitor(sd
,reason
)
1440 unsigned int reason
;
1443 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1446 /* The IDT monitor actually allows two instructions per vector
1447 slot. However, the simulator currently causes a trap on each
1448 individual instruction. We cheat, and lose the bottom bit. */
1451 /* The following callback functions are available, however the
1452 monitor we are simulating does not make use of them: get_errno,
1453 isatty, lseek, rename, system, time and unlink */
1455 case 6: /* int open(char *path,int flags) */
1459 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1460 V0
= sim_io_open(sd
,(char *)((int)paddr
),(int)A1
);
1462 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1466 case 7: /* int read(int file,char *ptr,int len) */
1470 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1471 V0
= sim_io_read(sd
,(int)A0
,(char *)((int)paddr
),(int)A2
);
1473 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1477 case 8: /* int write(int file,char *ptr,int len) */
1481 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1482 V0
= sim_io_write(sd
,(int)A0
,(const char *)((int)paddr
),(int)A2
);
1484 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1488 case 10: /* int close(int file) */
1489 V0
= sim_io_close(sd
,(int)A0
);
1492 case 11: /* char inbyte(void) */
1495 if (sim_io_read_stdin(sd
,&tmp
,sizeof(char)) != sizeof(char)) {
1496 sim_io_error(sd
,"Invalid return from character read");
1504 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1506 char tmp
= (char)(A0
& 0xFF);
1507 sim_io_write_stdout(sd
,&tmp
,sizeof(char));
1511 case 17: /* void _exit() */
1512 sim_io_eprintf(sd
,"sim_monitor(17): _exit(int reason) to be coded\n");
1513 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
, sim_exited
,
1514 (unsigned int)(A0
& 0xFFFFFFFF));
1517 case 28 : /* PMON flush_cache */
1520 case 55: /* void get_mem_info(unsigned int *ptr) */
1521 /* in: A0 = pointer to three word memory location */
1522 /* out: [A0 + 0] = size */
1523 /* [A0 + 4] = instruction cache size */
1524 /* [A0 + 8] = data cache size */
1527 uword64 paddr
, value
;
1531 /* NOTE: We use RAW memory writes here, but since we are not
1532 gathering statistics for the monitor calls we are simulating,
1533 it is not an issue. */
1536 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1537 value
= (uword64
)STATE_MEM_SIZE (sd
);
1538 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1539 /* We re-do the address translations, in-case the block
1540 overlaps a memory boundary: */
1542 vaddr
+= (AccessLength_WORD
+ 1);
1543 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1544 StoreMemory(cca
,AccessLength_WORD
,0,value
,paddr
,vaddr
,isRAW
);
1545 vaddr
+= (AccessLength_WORD
+ 1);
1546 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
))
1547 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1556 sim_io_error(sd
,"Invalid pointer passed into monitor call");
1560 case 158 : /* PMON printf */
1561 /* in: A0 = pointer to format string */
1562 /* A1 = optional argument 1 */
1563 /* A2 = optional argument 2 */
1564 /* A3 = optional argument 3 */
1566 /* The following is based on the PMON printf source */
1570 /* This isn't the quickest way, since we call the host print
1571 routine for every character almost. But it does avoid
1572 having to allocate and manage a temporary string buffer. */
1573 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1574 char *s
= (char *)((int)paddr
);
1575 ut_reg
*ap
= &A1
; /* 1st argument */
1576 /* TODO: Include check that we only use three arguments (A1, A2 and A3) */
1580 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1581 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1584 if (strchr ("dobxXulscefg%", *s
))
1592 else if (*s
== '*') {
1597 } else if (*s
>= '1' && *s
<= '9') {
1600 for (t
= s
; isdigit (*s
); s
++);
1601 strncpy (tmp
, t
, s
- t
);
1603 n
= (unsigned int)strtol(tmp
,NULL
,10);
1609 } else if (*s
== '.')
1613 sim_io_printf(sd
,"%%");
1614 } else if (*s
== 's') {
1615 if ((int)*ap
!= 0) {
1616 if (AddressTranslation(*ap
++,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1617 char *p
= (char *)((int)paddr
);;
1618 sim_io_printf(sd
,p
);
1621 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1625 sim_io_printf(sd
,"(null)");
1626 } else if (*s
== 'c') {
1628 sim_io_printf(sd
,"%c",n
);
1636 if (strchr ("dobxXu", *s
)) {
1637 word64 lv
= (word64
) *ap
++;
1639 sim_io_printf(sd
,"<binary not supported>");
1641 sprintf(tmp
,"%%%s%c",longlong
? "ll" : "",*s
);
1643 sim_io_printf(sd
,tmp
,lv
);
1645 sim_io_printf(sd
,tmp
,(int)lv
);
1647 } else if (strchr ("eEfgG", *s
)) {
1648 #ifdef _MSC_VER /* MSVC version 2.x can't convert from uword64 directly */
1649 double dbl
= (double)((word64
)*ap
++);
1651 double dbl
= (double)*ap
++;
1653 sprintf(tmp
,"%%%d.%d%c",width
,trunc
,*s
);
1654 sim_io_printf(sd
,tmp
,dbl
);
1660 sim_io_printf(sd
,"%c",*s
++);
1663 sim_io_error(sd
,"Attempt to pass pointer that does not reference simulated memory");
1668 sim_io_eprintf(sd
,"TODO: sim_monitor(%d) : PC = 0x%s\n",reason
,pr_addr(IPC
));
1669 sim_io_eprintf(sd
,"(Arguments : A0 = 0x%s : A1 = 0x%s : A2 = 0x%s : A3 = 0x%s)\n",pr_addr(A0
),pr_addr(A1
),pr_addr(A2
),pr_addr(A3
));
1675 /* Store a word into memory. */
1678 store_word (sd
, vaddr
, val
)
1686 if ((vaddr
& 3) != 0)
1687 SignalExceptionAddressStore ();
1690 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1693 const uword64 mask
= 7;
1697 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1698 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1699 memval
= ((uword64
) val
) << (8 * byte
);
1700 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1706 /* Load a word from memory. */
1709 load_word (sd
, vaddr
)
1713 if ((vaddr
& 3) != 0)
1714 SignalExceptionAddressLoad ();
1720 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1723 const uword64 mask
= 0x7;
1724 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1725 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1729 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1730 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1732 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1733 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1740 /* Simulate the mips16 entry and exit pseudo-instructions. These
1741 would normally be handled by the reserved instruction exception
1742 code, but for ease of simulation we just handle them directly. */
1745 mips16_entry (sd
,insn
)
1749 int aregs
, sregs
, rreg
;
1752 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1755 aregs
= (insn
& 0x700) >> 8;
1756 sregs
= (insn
& 0x0c0) >> 6;
1757 rreg
= (insn
& 0x020) >> 5;
1759 /* This should be checked by the caller. */
1768 /* This is the entry pseudo-instruction. */
1770 for (i
= 0; i
< aregs
; i
++)
1771 store_word ((uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1779 store_word ((uword64
) tsp
, RA
);
1782 for (i
= 0; i
< sregs
; i
++)
1785 store_word ((uword64
) tsp
, GPR
[16 + i
]);
1793 /* This is the exit pseudo-instruction. */
1800 RA
= load_word ((uword64
) tsp
);
1803 for (i
= 0; i
< sregs
; i
++)
1806 GPR
[i
+ 16] = load_word ((uword64
) tsp
);
1814 FGR
[0] = WORD64LO (GPR
[4]);
1815 FPR_STATE
[0] = fmt_uninterpreted
;
1817 else if (aregs
== 6)
1819 FGR
[0] = WORD64LO (GPR
[5]);
1820 FGR
[1] = WORD64LO (GPR
[4]);
1821 FPR_STATE
[0] = fmt_uninterpreted
;
1822 FPR_STATE
[1] = fmt_uninterpreted
;
1824 #endif /* defined(HASFPU) */
1836 /* Round *UP* to the nearest power-of-2 if not already one */
1837 if (value
!= (value
& ~(value
- 1))) {
1838 for (tmp
= value
, loop
= 0; (tmp
!= 0); loop
++)
1840 value
= (1 << loop
);
1854 num
= strtol(value
,&end
,10);
1856 sim_io_printf(sd
,"Warning: Invalid number \"%s\" ignored, using zero\n",value
);
1858 if (*end
&& ((tolower(*end
) == 'k') || (tolower(*end
) == 'm'))) {
1859 if (tolower(*end
) == 'k')
1866 sim_io_printf(sd
,"Warning: Spurious characters \"%s\" at end of number ignored\n",end
);
1872 /*-- trace support ----------------------------------------------------------*/
1874 /* The TRACE support is provided (if required) in the memory accessing
1875 routines. Since we are also providing the architecture specific
1876 features, the architecture simulation code can also deal with
1877 notifying the TRACE world of cache flushes, etc. Similarly we do
1878 not need to provide profiling support in the simulator engine,
1879 since we can sample in the instruction fetch control loop. By
1880 defining the TRACE manifest, we add tracing as a run-time
1884 /* Tracing by default produces "din" format (as required by
1885 dineroIII). Each line of such a trace file *MUST* have a din label
1886 and address field. The rest of the line is ignored, so comments can
1887 be included if desired. The first field is the label which must be
1888 one of the following values:
1893 3 escape record (treated as unknown access type)
1894 4 escape record (causes cache flush)
1896 The address field is a 32bit (lower-case) hexadecimal address
1897 value. The address should *NOT* be preceded by "0x".
1899 The size of the memory transfer is not important when dealing with
1900 cache lines (as long as no more than a cache line can be
1901 transferred in a single operation :-), however more information
1902 could be given following the dineroIII requirement to allow more
1903 complete memory and cache simulators to provide better
1904 results. i.e. the University of Pisa has a cache simulator that can
1905 also take bus size and speed as (variable) inputs to calculate
1906 complete system performance (a much more useful ability when trying
1907 to construct an end product, rather than a processor). They
1908 currently have an ARM version of their tool called ChARM. */
1912 void dotrace(SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...)
1914 if (STATE
& simTRACE
) {
1916 fprintf(tracefh
,"%d %s ; width %d ; ",
1920 va_start(ap
,comment
);
1921 vfprintf(tracefh
,comment
,ap
);
1923 fprintf(tracefh
,"\n");
1925 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1926 we may be generating 64bit ones, we should put the hi-32bits of the
1927 address into the comment field. */
1929 /* TODO: Provide a buffer for the trace lines. We can then avoid
1930 performing writes until the buffer is filled, or the file is
1933 /* NOTE: We could consider adding a comment field to the "din" file
1934 produced using type 3 markers (unknown access). This would then
1935 allow information about the program that the "din" is for, and
1936 the MIPs world that was being simulated, to be placed into the
1943 /*---------------------------------------------------------------------------*/
1944 /*-- simulator engine -------------------------------------------------------*/
1945 /*---------------------------------------------------------------------------*/
1951 /* RESET: Fixed PC address: */
1952 PC
= (((uword64
)0xFFFFFFFF<<32) | 0xBFC00000);
1953 /* The reset vector address is in the unmapped, uncached memory space. */
1955 SR
&= ~(status_SR
| status_TS
| status_RP
);
1956 SR
|= (status_ERL
| status_BEV
);
1958 #if defined(HASFPU) && (GPRLEN == (64))
1959 /* Cheat and allow access to the complete register set immediately: */
1960 SR
|= status_FR
; /* 64bit registers */
1961 #endif /* HASFPU and 64bit FP registers */
1963 /* Ensure that any instructions with pending register updates are
1967 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1968 PENDING_SLOT_REG
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1969 PENDING_IN
= PENDING_OUT
= PENDING_TOTAL
= 0;
1973 /* Initialise the FPU registers to the unknown state */
1976 for (rn
= 0; (rn
< 32); rn
++)
1977 FPR_STATE
[rn
] = fmt_uninterpreted
;
1984 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1985 /* Translate a virtual address to a physical address and cache
1986 coherence algorithm describing the mechanism used to resolve the
1987 memory reference. Given the virtual address vAddr, and whether the
1988 reference is to Instructions ot Data (IorD), find the corresponding
1989 physical address (pAddr) and the cache coherence algorithm (CCA)
1990 used to resolve the reference. If the virtual address is in one of
1991 the unmapped address spaces the physical address and the CCA are
1992 determined directly by the virtual address. If the virtual address
1993 is in one of the mapped address spaces then the TLB is used to
1994 determine the physical address and access type; if the required
1995 translation is not present in the TLB or the desired access is not
1996 permitted the function fails and an exception is taken.
1998 NOTE: This function is extended to return an exception state. This,
1999 along with the exception generation is used to notify whether a
2000 valid address translation occured */
2003 address_translation(sd
,vAddr
,IorD
,LorS
,pAddr
,CCA
,host
,raw
)
2013 int res
= -1; /* TRUE : Assume good return */
2016 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
2019 /* Check that the address is valid for this memory model */
2021 /* For a simple (flat) memory model, we simply pass virtual
2022 addressess through (mostly) unchanged. */
2023 vAddr
&= 0xFFFFFFFF;
2025 /* Treat the kernel memory spaces identically for the moment: */
2026 if ((STATE_MEM_BASE (sd
) == K1BASE
) && (vAddr
>= K0BASE
) && (vAddr
< (K0BASE
+ K0SIZE
)))
2027 vAddr
+= (K1BASE
- K0BASE
);
2029 /* Also assume that the K1BASE memory wraps. This is required to
2030 allow the PMON run-time __sizemem() routine to function (without
2031 having to provide exception simulation). NOTE: A kludge to work
2032 around the fact that the monitor memory is currently held in the
2034 if (((vAddr
< monitor_base
) || (vAddr
>= (monitor_base
+ monitor_size
))) && (vAddr
>= K1BASE
&& vAddr
< (K1BASE
+ K1SIZE
)))
2035 vAddr
= (K1BASE
| (vAddr
& (STATE_MEM_SIZE (sd
) - 1)));
2037 *pAddr
= vAddr
; /* default for isTARGET */
2038 *CCA
= Uncached
; /* not used for isHOST */
2040 /* NOTE: This is a duplicate of the code that appears in the
2041 LoadMemory and StoreMemory functions. They should be merged into
2042 a single function (that can be in-lined if required). */
2043 if ((vAddr
>= STATE_MEM_BASE (sd
)) && (vAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
2045 *pAddr
= (int)&STATE_MEMORY (sd
)[((unsigned int)(vAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1))];
2046 } else if ((vAddr
>= monitor_base
) && (vAddr
< (monitor_base
+ monitor_size
))) {
2048 *pAddr
= (int)&monitor
[((unsigned int)(vAddr
- monitor_base
) & (monitor_size
- 1))];
2051 sim_io_eprintf(sd
,"Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "isSTORE" : "isLOAD"),pr_addr(IPC
));
2053 res
= 0; /* AddressTranslation has failed */
2054 *pAddr
= (SIM_ADDR
)-1;
2055 if (!raw
) /* only generate exceptions on real memory transfers */
2056 if (LorS
== isSTORE
)
2057 SignalExceptionAddressStore ();
2059 SignalExceptionAddressLoad ();
2062 /* This is a normal occurance during gdb operation, for instance trying
2063 to print parameters at function start before they have been setup,
2064 and hence we should not print a warning except when debugging the
2066 sim_io_eprintf(sd
,"AddressTranslation for %s %s from 0x%s failed\n",(IorD
? "data" : "instruction"),(LorS
? "store" : "load"),pr_addr(vAddr
));
2073 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2074 /* Prefetch data from memory. Prefetch is an advisory instruction for
2075 which an implementation specific action is taken. The action taken
2076 may increase performance, but must not change the meaning of the
2077 program, or alter architecturally-visible state. */
2080 Prefetch(CCA
,pAddr
,vAddr
,DATA
,hint
)
2088 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
2091 /* For our simple memory model we do nothing */
2095 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2096 /* Load a value from memory. Use the cache and main memory as
2097 specified in the Cache Coherence Algorithm (CCA) and the sort of
2098 access (IorD) to find the contents of AccessLength memory bytes
2099 starting at physical location pAddr. The data is returned in the
2100 fixed width naturally-aligned memory element (MemElem). The
2101 low-order two (or three) bits of the address and the AccessLength
2102 indicate which of the bytes within MemElem needs to be given to the
2103 processor. If the memory access type of the reference is uncached
2104 then only the referenced bytes are read from memory and valid
2105 within the memory element. If the access type is cached, and the
2106 data is not present in cache, an implementation specific size and
2107 alignment block of memory is read and loaded into the cache to
2108 satisfy a load reference. At a minimum, the block is the entire
2111 load_memory(sd
,memvalp
,memval1p
,CCA
,AccessLength
,pAddr
,vAddr
,IorD
,raw
)
2126 if (STATE_MEMORY (sd
) == NULL
)
2127 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(raw
? "isRAW" : "isREAL"));
2130 #if defined(WARN_MEM)
2131 if (CCA
!= uncached
)
2132 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
2134 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
) {
2135 /* In reality this should be a Bus Error */
2136 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
2138 #endif /* WARN_MEM */
2140 /* Decide which physical memory locations are being dealt with. At
2141 this point we should be able to split the pAddr bits into the
2142 relevant address map being simulated. If the "raw" variable is
2143 set, the memory read being performed should *NOT* update any I/O
2144 state or affect the CPU state. This also includes avoiding
2145 affecting statistics gathering. */
2147 /* If instruction fetch then we need to check that the two lo-order
2148 bits are zero, otherwise raise a InstructionFetch exception: */
2149 if ((IorD
== isINSTRUCTION
)
2150 && ((pAddr
& 0x3) != 0)
2151 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
2152 SignalExceptionInstructionFetch ();
2154 unsigned int index
= 0;
2155 unsigned char *mem
= NULL
;
2159 dotrace(sd
,tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
2162 /* NOTE: Quicker methods of decoding the address space can be used
2163 when a real memory map is being simulated (i.e. using hi-order
2164 address bits to select device). */
2165 if ((pAddr
>= STATE_MEM_BASE (sd
)) && (pAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
2166 index
= ((unsigned int)(pAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1));
2167 mem
= STATE_MEMORY (sd
);
2168 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
2169 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
2173 sim_io_error(sd
,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
2175 /* If we obtained the endianness of the host, and it is the same
2176 as the target memory system we can optimise the memory
2177 accesses. However, without that information we must perform
2178 slow transfer, and hope that the compiler optimisation will
2179 merge successive loads. */
2181 /* In reality we should always be loading a doubleword value (or
2182 word value in 32bit memory worlds). The external code then
2183 extracts the required bytes. However, to keep performance
2184 high we only load the required bytes into the relevant
2187 switch (AccessLength
) { /* big-endian memory */
2188 case AccessLength_QUADWORD
:
2189 value1
|= ((uword64
)mem
[index
++] << 56);
2190 case 14: /* AccessLength is one less than datalen */
2191 value1
|= ((uword64
)mem
[index
++] << 48);
2193 value1
|= ((uword64
)mem
[index
++] << 40);
2195 value1
|= ((uword64
)mem
[index
++] << 32);
2197 value1
|= ((unsigned int)mem
[index
++] << 24);
2199 value1
|= ((unsigned int)mem
[index
++] << 16);
2201 value1
|= ((unsigned int)mem
[index
++] << 8);
2203 value1
|= mem
[index
];
2205 case AccessLength_DOUBLEWORD
:
2206 value
|= ((uword64
)mem
[index
++] << 56);
2207 case AccessLength_SEPTIBYTE
:
2208 value
|= ((uword64
)mem
[index
++] << 48);
2209 case AccessLength_SEXTIBYTE
:
2210 value
|= ((uword64
)mem
[index
++] << 40);
2211 case AccessLength_QUINTIBYTE
:
2212 value
|= ((uword64
)mem
[index
++] << 32);
2213 case AccessLength_WORD
:
2214 value
|= ((unsigned int)mem
[index
++] << 24);
2215 case AccessLength_TRIPLEBYTE
:
2216 value
|= ((unsigned int)mem
[index
++] << 16);
2217 case AccessLength_HALFWORD
:
2218 value
|= ((unsigned int)mem
[index
++] << 8);
2219 case AccessLength_BYTE
:
2220 value
|= mem
[index
];
2224 index
+= (AccessLength
+ 1);
2225 switch (AccessLength
) { /* little-endian memory */
2226 case AccessLength_QUADWORD
:
2227 value1
|= ((uword64
)mem
[--index
] << 56);
2228 case 14: /* AccessLength is one less than datalen */
2229 value1
|= ((uword64
)mem
[--index
] << 48);
2231 value1
|= ((uword64
)mem
[--index
] << 40);
2233 value1
|= ((uword64
)mem
[--index
] << 32);
2235 value1
|= ((uword64
)mem
[--index
] << 24);
2237 value1
|= ((uword64
)mem
[--index
] << 16);
2239 value1
|= ((uword64
)mem
[--index
] << 8);
2241 value1
|= ((uword64
)mem
[--index
] << 0);
2243 case AccessLength_DOUBLEWORD
:
2244 value
|= ((uword64
)mem
[--index
] << 56);
2245 case AccessLength_SEPTIBYTE
:
2246 value
|= ((uword64
)mem
[--index
] << 48);
2247 case AccessLength_SEXTIBYTE
:
2248 value
|= ((uword64
)mem
[--index
] << 40);
2249 case AccessLength_QUINTIBYTE
:
2250 value
|= ((uword64
)mem
[--index
] << 32);
2251 case AccessLength_WORD
:
2252 value
|= ((uword64
)mem
[--index
] << 24);
2253 case AccessLength_TRIPLEBYTE
:
2254 value
|= ((uword64
)mem
[--index
] << 16);
2255 case AccessLength_HALFWORD
:
2256 value
|= ((uword64
)mem
[--index
] << 8);
2257 case AccessLength_BYTE
:
2258 value
|= ((uword64
)mem
[--index
] << 0);
2264 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
2265 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
2268 /* TODO: We could try and avoid the shifts when dealing with raw
2269 memory accesses. This would mean updating the LoadMemory and
2270 StoreMemory routines to avoid shifting the data before
2271 returning or using it. */
2272 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
2273 if (!raw
) { /* do nothing for raw accessess */
2275 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
2276 else /* little-endian only needs to be shifted up to the correct byte offset */
2277 value
<<= ((pAddr
& LOADDRMASK
) * 8);
2282 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
2283 pr_uword64(value1
),pr_uword64(value
));
2289 if (memval1p
) *memval1p
= value1
;
2293 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
2295 /* Store a value to memory. The specified data is stored into the
2296 physical location pAddr using the memory hierarchy (data caches and
2297 main memory) as specified by the Cache Coherence Algorithm
2298 (CCA). The MemElem contains the data for an aligned, fixed-width
2299 memory element (word for 32-bit processors, doubleword for 64-bit
2300 processors), though only the bytes that will actually be stored to
2301 memory need to be valid. The low-order two (or three) bits of pAddr
2302 and the AccessLength field indicates which of the bytes within the
2303 MemElem data should actually be stored; only these bytes in memory
2307 store_memory(sd
,CCA
,AccessLength
,MemElem
,MemElem1
,pAddr
,vAddr
,raw
)
2312 uword64 MemElem1
; /* High order 64 bits */
2318 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
),(raw
? "isRAW" : "isREAL"));
2321 #if defined(WARN_MEM)
2322 if (CCA
!= uncached
)
2323 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
2325 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
2326 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
2327 #endif /* WARN_MEM */
2331 dotrace(sd
,tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
2334 /* See the comments in the LoadMemory routine about optimising
2335 memory accesses. Also if we wanted to make the simulator smaller,
2336 we could merge a lot of this code with the LoadMemory
2337 routine. However, this would slow the simulator down with
2338 run-time conditionals. */
2340 unsigned int index
= 0;
2341 unsigned char *mem
= NULL
;
2343 if ((pAddr
>= STATE_MEM_BASE (sd
)) && (pAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
2344 index
= ((unsigned int)(pAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1));
2345 mem
= STATE_MEMORY (sd
);
2346 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
2347 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
2352 sim_io_error(sd
,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
2357 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
2360 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
2363 shift
= ((7 - AccessLength
) * 8);
2364 else /* real memory access */
2365 shift
= ((pAddr
& LOADDRMASK
) * 8);
2368 /* no need to shift raw little-endian data */
2370 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
2375 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
2379 switch (AccessLength
) { /* big-endian memory */
2380 case AccessLength_QUADWORD
:
2381 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2384 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2387 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2390 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2393 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2396 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2399 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2402 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2404 case AccessLength_DOUBLEWORD
:
2405 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2407 case AccessLength_SEPTIBYTE
:
2408 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2410 case AccessLength_SEXTIBYTE
:
2411 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2413 case AccessLength_QUINTIBYTE
:
2414 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2416 case AccessLength_WORD
:
2417 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2419 case AccessLength_TRIPLEBYTE
:
2420 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2422 case AccessLength_HALFWORD
:
2423 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2425 case AccessLength_BYTE
:
2426 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2430 index
+= (AccessLength
+ 1);
2431 switch (AccessLength
) { /* little-endian memory */
2432 case AccessLength_QUADWORD
:
2433 mem
[--index
] = (unsigned char)(MemElem1
>> 56);
2435 mem
[--index
] = (unsigned char)(MemElem1
>> 48);
2437 mem
[--index
] = (unsigned char)(MemElem1
>> 40);
2439 mem
[--index
] = (unsigned char)(MemElem1
>> 32);
2441 mem
[--index
] = (unsigned char)(MemElem1
>> 24);
2443 mem
[--index
] = (unsigned char)(MemElem1
>> 16);
2445 mem
[--index
] = (unsigned char)(MemElem1
>> 8);
2447 mem
[--index
] = (unsigned char)(MemElem1
>> 0);
2449 case AccessLength_DOUBLEWORD
:
2450 mem
[--index
] = (unsigned char)(MemElem
>> 56);
2451 case AccessLength_SEPTIBYTE
:
2452 mem
[--index
] = (unsigned char)(MemElem
>> 48);
2453 case AccessLength_SEXTIBYTE
:
2454 mem
[--index
] = (unsigned char)(MemElem
>> 40);
2455 case AccessLength_QUINTIBYTE
:
2456 mem
[--index
] = (unsigned char)(MemElem
>> 32);
2457 case AccessLength_WORD
:
2458 mem
[--index
] = (unsigned char)(MemElem
>> 24);
2459 case AccessLength_TRIPLEBYTE
:
2460 mem
[--index
] = (unsigned char)(MemElem
>> 16);
2461 case AccessLength_HALFWORD
:
2462 mem
[--index
] = (unsigned char)(MemElem
>> 8);
2463 case AccessLength_BYTE
:
2464 mem
[--index
] = (unsigned char)(MemElem
>> 0);
2475 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2476 /* Order loads and stores to synchronise shared memory. Perform the
2477 action necessary to make the effects of groups of synchronizable
2478 loads and stores indicated by stype occur in the same order for all
2481 SyncOperation(stype
)
2485 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
2490 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2491 /* Signal an exception condition. This will result in an exception
2492 that aborts the instruction. The instruction operation pseudocode
2493 will never see a return from this function call. */
2496 signal_exception (SIM_DESC sd
, int exception
,...)
2501 sim_io_printf(sd
,"DBG: SignalException(%d) IPC = 0x%s\n",exception
,pr_addr(IPC
));
2504 /* Ensure that any active atomic read/modify/write operation will fail: */
2507 switch (exception
) {
2508 /* TODO: For testing purposes I have been ignoring TRAPs. In
2509 reality we should either simulate them, or allow the user to
2510 ignore them at run-time.
2513 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(IPC
));
2519 unsigned int instruction
;
2522 va_start(ap
,exception
);
2523 instruction
= va_arg(ap
,unsigned int);
2526 code
= (instruction
>> 6) & 0xFFFFF;
2528 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
2529 code
, pr_addr(IPC
));
2533 case DebugBreakPoint
:
2534 if (! (Debug
& Debug_DM
))
2540 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
2541 DEPC
= IPC
- 4; /* reference the branch instruction */
2545 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
2549 Debug
|= Debug_DM
; /* in debugging mode */
2550 Debug
|= Debug_DBp
; /* raising a DBp exception */
2552 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
2556 case ReservedInstruction
:
2559 unsigned int instruction
;
2560 va_start(ap
,exception
);
2561 instruction
= va_arg(ap
,unsigned int);
2563 /* Provide simple monitor support using ReservedInstruction
2564 exceptions. The following code simulates the fixed vector
2565 entry points into the IDT monitor by causing a simulator
2566 trap, performing the monitor operation, and returning to
2567 the address held in the $ra register (standard PCS return
2568 address). This means we only need to pre-load the vector
2569 space with suitable instruction values. For systems were
2570 actual trap instructions are used, we would not need to
2571 perform this magic. */
2572 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
) {
2573 sim_monitor(sd
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
2574 PC
= RA
; /* simulate the return from the vector entry */
2575 /* NOTE: This assumes that a branch-and-link style
2576 instruction was used to enter the vector (which is the
2577 case with the current IDT monitor). */
2578 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
2580 /* Look for the mips16 entry and exit instructions, and
2581 simulate a handler for them. */
2582 else if ((IPC
& 1) != 0
2583 && (instruction
& 0xf81f) == 0xe809
2584 && (instruction
& 0x0c0) != 0x0c0) {
2585 mips16_entry (instruction
);
2586 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
2587 } /* else fall through to normal exception processing */
2588 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction
,pr_addr(IPC
));
2593 sim_io_printf(sd
,"DBG: SignalException(%d) IPC = 0x%s\n",exception
,pr_addr(IPC
));
2595 /* Keep a copy of the current A0 in-case this is the program exit
2599 unsigned int instruction
;
2600 va_start(ap
,exception
);
2601 instruction
= va_arg(ap
,unsigned int);
2603 /* Check for our special terminating BREAK: */
2604 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
2605 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2606 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
2609 if (STATE
& simDELAYSLOT
)
2610 PC
= IPC
- 4; /* reference the branch instruction */
2613 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2614 sim_stopped
, SIGTRAP
);
2617 /* Store exception code into current exception id variable (used
2620 /* TODO: If not simulating exceptions then stop the simulator
2621 execution. At the moment we always stop the simulation. */
2623 /* See figure 5-17 for an outline of the code below */
2624 if (! (SR
& status_EXL
))
2626 CAUSE
= (exception
<< 2);
2627 if (STATE
& simDELAYSLOT
)
2629 STATE
&= ~simDELAYSLOT
;
2631 EPC
= (IPC
- 4); /* reference the branch instruction */
2635 /* FIXME: TLB et.al. */
2640 CAUSE
= (exception
<< 2);
2644 /* Store exception code into current exception id variable (used
2646 if (SR
& status_BEV
)
2647 PC
= (signed)0xBFC00200 + 0x180;
2649 PC
= (signed)0x80000000 + 0x180;
2651 switch ((CAUSE
>> 2) & 0x1F)
2654 /* Interrupts arrive during event processing, no need to
2658 case TLBModification
:
2663 case InstructionFetch
:
2665 /* The following is so that the simulator will continue from the
2666 exception address on breakpoint operations. */
2668 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2669 sim_stopped
, SIGBUS
);
2671 case ReservedInstruction
:
2672 case CoProcessorUnusable
:
2674 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2675 sim_stopped
, SIGILL
);
2677 case IntegerOverflow
:
2679 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2680 sim_stopped
, SIGFPE
);
2686 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2687 sim_stopped
, SIGTRAP
);
2691 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
2692 "FATAL: Should not encounter a breakpoint\n");
2694 default : /* Unknown internal exception */
2696 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2697 sim_stopped
, SIGQUIT
);
2701 case SimulatorFault
:
2705 va_start(ap
,exception
);
2706 msg
= va_arg(ap
,char *);
2708 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
2709 "FATAL: Simulator error \"%s\"\n",msg
);
2716 #if defined(WARN_RESULT)
2717 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2718 /* This function indicates that the result of the operation is
2719 undefined. However, this should not affect the instruction
2720 stream. All that is meant to happen is that the destination
2721 register is set to an undefined result. To keep the simulator
2722 simple, we just don't bother updating the destination register, so
2723 the overall result will be undefined. If desired we can stop the
2724 simulator by raising a pseudo-exception. */
2728 sim_io_eprintf(sd
,"UndefinedResult: IPC = 0x%s\n",pr_addr(IPC
));
2729 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2734 #endif /* WARN_RESULT */
2737 cache_op(sd
,op
,pAddr
,vAddr
,instruction
)
2742 unsigned int instruction
;
2744 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2745 static int icache_warning
= 1;
2746 static int dcache_warning
= 1;
2748 static int icache_warning
= 0;
2749 static int dcache_warning
= 0;
2752 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2753 enable bit in the Status Register is clear - a coprocessor
2754 unusable exception is taken. */
2756 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC
));
2760 case 0: /* instruction cache */
2762 case 0: /* Index Invalidate */
2763 case 1: /* Index Load Tag */
2764 case 2: /* Index Store Tag */
2765 case 4: /* Hit Invalidate */
2767 case 6: /* Hit Writeback */
2768 if (!icache_warning
)
2770 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2776 SignalException(ReservedInstruction
,instruction
);
2781 case 1: /* data cache */
2783 case 0: /* Index Writeback Invalidate */
2784 case 1: /* Index Load Tag */
2785 case 2: /* Index Store Tag */
2786 case 3: /* Create Dirty */
2787 case 4: /* Hit Invalidate */
2788 case 5: /* Hit Writeback Invalidate */
2789 case 6: /* Hit Writeback */
2790 if (!dcache_warning
)
2792 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2798 SignalException(ReservedInstruction
,instruction
);
2803 default: /* unrecognised cache ID */
2804 SignalException(ReservedInstruction
,instruction
);
2811 /*-- FPU support routines ---------------------------------------------------*/
2813 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
2816 #define SizeFGR() (GPRLEN)
2818 /* They depend on the CPU being simulated */
2819 #define SizeFGR() ((PROCESSOR_64BIT && ((SR & status_FR) == 1)) ? 64 : 32)
2822 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2823 formats conform to ANSI/IEEE Std 754-1985. */
2824 /* SINGLE precision floating:
2825 * seeeeeeeefffffffffffffffffffffff
2827 * e = 8bits = exponent
2828 * f = 23bits = fraction
2830 /* SINGLE precision fixed:
2831 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2833 * i = 31bits = integer
2835 /* DOUBLE precision floating:
2836 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2838 * e = 11bits = exponent
2839 * f = 52bits = fraction
2841 /* DOUBLE precision fixed:
2842 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2844 * i = 63bits = integer
2847 /* Extract sign-bit: */
2848 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2849 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2850 /* Extract biased exponent: */
2851 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2852 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2853 /* Extract unbiased Exponent: */
2854 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2855 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2856 /* Extract complete fraction field: */
2857 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2858 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2859 /* Extract numbered fraction bit: */
2860 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2861 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2863 /* Explicit QNaN values used when value required: */
2864 #define FPQNaN_SINGLE (0x7FBFFFFF)
2865 #define FPQNaN_WORD (0x7FFFFFFF)
2866 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2867 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2869 /* Explicit Infinity values used when required: */
2870 #define FPINF_SINGLE (0x7F800000)
2871 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2873 #if 1 /* def DEBUG */
2874 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2875 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2879 value_fpr(sd
,fpr
,fmt
)
2887 /* Treat unused register values, as fixed-point 64bit values: */
2888 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2890 /* If request to read data as "uninterpreted", then use the current
2892 fmt
= FPR_STATE
[fpr
];
2897 /* For values not yet accessed, set to the desired format: */
2898 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2899 FPR_STATE
[fpr
] = fmt
;
2901 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2904 if (fmt
!= FPR_STATE
[fpr
]) {
2905 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(IPC
));
2906 FPR_STATE
[fpr
] = fmt_unknown
;
2909 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2910 /* Set QNaN value: */
2913 value
= FPQNaN_SINGLE
;
2917 value
= FPQNaN_DOUBLE
;
2921 value
= FPQNaN_WORD
;
2925 value
= FPQNaN_LONG
;
2932 } else if (SizeFGR() == 64) {
2936 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2939 case fmt_uninterpreted
:
2953 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2956 case fmt_uninterpreted
:
2959 if ((fpr
& 1) == 0) { /* even registers only */
2960 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2962 SignalException(ReservedInstruction
,0);
2973 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2976 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
2983 store_fpr(sd
,fpr
,fmt
,value
)
2992 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
2995 if (SizeFGR() == 64) {
2999 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
3000 FPR_STATE
[fpr
] = fmt
;
3003 case fmt_uninterpreted
:
3007 FPR_STATE
[fpr
] = fmt
;
3011 FPR_STATE
[fpr
] = fmt_unknown
;
3019 FGR
[fpr
] = (value
& 0xFFFFFFFF);
3020 FPR_STATE
[fpr
] = fmt
;
3023 case fmt_uninterpreted
:
3026 if ((fpr
& 1) == 0) { /* even register number only */
3027 FGR
[fpr
+1] = (value
>> 32);
3028 FGR
[fpr
] = (value
& 0xFFFFFFFF);
3029 FPR_STATE
[fpr
+ 1] = fmt
;
3030 FPR_STATE
[fpr
] = fmt
;
3032 FPR_STATE
[fpr
] = fmt_unknown
;
3033 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
3034 SignalException(ReservedInstruction
,0);
3039 FPR_STATE
[fpr
] = fmt_unknown
;
3044 #if defined(WARN_RESULT)
3047 #endif /* WARN_RESULT */
3050 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
3053 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
3066 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
3067 know that the exponent field is biased... we we cheat and avoid
3068 removing the bias value. */
3071 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) != 0));
3072 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
3073 dealing with a SNaN or QNaN */
3076 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) != 0));
3077 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
3078 dealing with a SNaN or QNaN */
3081 boolean
= (op
== FPQNaN_WORD
);
3084 boolean
= (op
== FPQNaN_LONG
);
3087 fprintf (stderr
, "Bad switch\n");
3092 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
3106 printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt
),pr_addr(op
),pr_addr(IPC
));
3109 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
3110 know that the exponent field is biased... we we cheat and avoid
3111 removing the bias value. */
3114 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) == 0));
3117 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) == 0));
3120 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
3125 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
3139 /* Argument checking already performed by the FPCOMPARE code */
3142 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3145 /* The format type should already have been checked: */
3149 unsigned int wop1
= (unsigned int)op1
;
3150 unsigned int wop2
= (unsigned int)op2
;
3151 boolean
= (*(float *)&wop1
< *(float *)&wop2
);
3155 boolean
= (*(double *)&op1
< *(double *)&op2
);
3158 fprintf (stderr
, "Bad switch\n");
3163 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
3177 /* Argument checking already performed by the FPCOMPARE code */
3180 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3183 /* The format type should already have been checked: */
3186 boolean
= ((op1
& 0xFFFFFFFF) == (op2
& 0xFFFFFFFF));
3189 boolean
= (op1
== op2
);
3192 fprintf (stderr
, "Bad switch\n");
3197 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
3204 AbsoluteValue(op
,fmt
)
3211 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3214 /* The format type should already have been checked: */
3218 unsigned int wop
= (unsigned int)op
;
3219 float tmp
= ((float)fabs((double)*(float *)&wop
));
3220 result
= (uword64
)*(unsigned int *)&tmp
;
3225 double tmp
= (fabs(*(double *)&op
));
3226 result
= *(uword64
*)&tmp
;
3229 fprintf (stderr
, "Bad switch\n");
3244 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3247 /* The format type should already have been checked: */
3251 unsigned int wop
= (unsigned int)op
;
3252 float tmp
= ((float)0.0 - *(float *)&wop
);
3253 result
= (uword64
)*(unsigned int *)&tmp
;
3258 double tmp
= ((double)0.0 - *(double *)&op
);
3259 result
= *(uword64
*)&tmp
;
3263 fprintf (stderr
, "Bad switch\n");
3279 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3282 /* The registers must specify FPRs valid for operands of type
3283 "fmt". If they are not valid, the result is undefined. */
3285 /* The format type should already have been checked: */
3289 unsigned int wop1
= (unsigned int)op1
;
3290 unsigned int wop2
= (unsigned int)op2
;
3291 float tmp
= (*(float *)&wop1
+ *(float *)&wop2
);
3292 result
= (uword64
)*(unsigned int *)&tmp
;
3297 double tmp
= (*(double *)&op1
+ *(double *)&op2
);
3298 result
= *(uword64
*)&tmp
;
3302 fprintf (stderr
, "Bad switch\n");
3307 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3322 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3325 /* The registers must specify FPRs valid for operands of type
3326 "fmt". If they are not valid, the result is undefined. */
3328 /* The format type should already have been checked: */
3332 unsigned int wop1
= (unsigned int)op1
;
3333 unsigned int wop2
= (unsigned int)op2
;
3334 float tmp
= (*(float *)&wop1
- *(float *)&wop2
);
3335 result
= (uword64
)*(unsigned int *)&tmp
;
3340 double tmp
= (*(double *)&op1
- *(double *)&op2
);
3341 result
= *(uword64
*)&tmp
;
3345 fprintf (stderr
, "Bad switch\n");
3350 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3357 Multiply(op1
,op2
,fmt
)
3365 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3368 /* The registers must specify FPRs valid for operands of type
3369 "fmt". If they are not valid, the result is undefined. */
3371 /* The format type should already have been checked: */
3375 unsigned int wop1
= (unsigned int)op1
;
3376 unsigned int wop2
= (unsigned int)op2
;
3377 float tmp
= (*(float *)&wop1
* *(float *)&wop2
);
3378 result
= (uword64
)*(unsigned int *)&tmp
;
3383 double tmp
= (*(double *)&op1
* *(double *)&op2
);
3384 result
= *(uword64
*)&tmp
;
3388 fprintf (stderr
, "Bad switch\n");
3393 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3408 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3411 /* The registers must specify FPRs valid for operands of type
3412 "fmt". If they are not valid, the result is undefined. */
3414 /* The format type should already have been checked: */
3418 unsigned int wop1
= (unsigned int)op1
;
3419 unsigned int wop2
= (unsigned int)op2
;
3420 float tmp
= (*(float *)&wop1
/ *(float *)&wop2
);
3421 result
= (uword64
)*(unsigned int *)&tmp
;
3426 double tmp
= (*(double *)&op1
/ *(double *)&op2
);
3427 result
= *(uword64
*)&tmp
;
3431 fprintf (stderr
, "Bad switch\n");
3436 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3450 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3453 /* The registers must specify FPRs valid for operands of type
3454 "fmt". If they are not valid, the result is undefined. */
3456 /* The format type should already have been checked: */
3460 unsigned int wop
= (unsigned int)op
;
3461 float tmp
= ((float)1.0 / *(float *)&wop
);
3462 result
= (uword64
)*(unsigned int *)&tmp
;
3467 double tmp
= ((double)1.0 / *(double *)&op
);
3468 result
= *(uword64
*)&tmp
;
3472 fprintf (stderr
, "Bad switch\n");
3477 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3491 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3494 /* The registers must specify FPRs valid for operands of type
3495 "fmt". If they are not valid, the result is undefined. */
3497 /* The format type should already have been checked: */
3501 unsigned int wop
= (unsigned int)op
;
3503 float tmp
= ((float)sqrt((double)*(float *)&wop
));
3504 result
= (uword64
)*(unsigned int *)&tmp
;
3506 /* TODO: Provide square-root */
3507 result
= (uword64
)0;
3514 double tmp
= (sqrt(*(double *)&op
));
3515 result
= *(uword64
*)&tmp
;
3517 /* TODO: Provide square-root */
3518 result
= (uword64
)0;
3523 fprintf (stderr
, "Bad switch\n");
3528 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3535 convert(sd
,rm
,op
,from
,to
)
3545 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3548 /* The value "op" is converted to the destination format, rounding
3549 using mode "rm". When the destination is a fixed-point format,
3550 then a source value of Infinity, NaN or one which would round to
3551 an integer outside the fixed point range then an IEEE Invalid
3552 Operation condition is raised. */
3559 tmp
= (float)(*(double *)&op
);
3563 tmp
= (float)((int)(op
& 0xFFFFFFFF));
3567 tmp
= (float)((word64
)op
);
3570 fprintf (stderr
, "Bad switch\n");
3575 /* FIXME: This code is incorrect. The rounding mode does not
3576 round to integral values; it rounds to the nearest
3577 representable value in the format. */
3581 /* Round result to nearest representable value. When two
3582 representable values are equally near, round to the value
3583 that has a least significant bit of zero (i.e. is even). */
3585 tmp
= (float)anint((double)tmp
);
3587 /* TODO: Provide round-to-nearest */
3592 /* Round result to the value closest to, and not greater in
3593 magnitude than, the result. */
3595 tmp
= (float)aint((double)tmp
);
3597 /* TODO: Provide round-to-zero */
3602 /* Round result to the value closest to, and not less than,
3604 tmp
= (float)ceil((double)tmp
);
3608 /* Round result to the value closest to, and not greater than,
3610 tmp
= (float)floor((double)tmp
);
3615 result
= (uword64
)*(unsigned int *)&tmp
;
3627 unsigned int wop
= (unsigned int)op
;
3628 tmp
= (double)(*(float *)&wop
);
3633 xxx
= SIGNEXTEND((op
& 0xFFFFFFFF),32);
3638 tmp
= (double)((word64
)op
);
3642 fprintf (stderr
, "Bad switch\n");
3647 /* FIXME: This code is incorrect. The rounding mode does not
3648 round to integral values; it rounds to the nearest
3649 representable value in the format. */
3654 tmp
= anint(*(double *)&tmp
);
3656 /* TODO: Provide round-to-nearest */
3662 tmp
= aint(*(double *)&tmp
);
3664 /* TODO: Provide round-to-zero */
3669 tmp
= ceil(*(double *)&tmp
);
3673 tmp
= floor(*(double *)&tmp
);
3678 result
= *(uword64
*)&tmp
;
3684 if (Infinity(op
,from
) || NaN(op
,from
) || (1 == 0/*TODO: check range */)) {
3685 printf("DBG: TODO: update FCSR\n");
3686 SignalExceptionFPE ();
3688 if (to
== fmt_word
) {
3693 unsigned int wop
= (unsigned int)op
;
3694 tmp
= (int)*((float *)&wop
);
3698 tmp
= (int)*((double *)&op
);
3700 printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op
),pr_addr(op
),tmp
);
3704 fprintf (stderr
, "Bad switch\n");
3707 result
= (uword64
)tmp
;
3708 } else { /* fmt_long */
3713 unsigned int wop
= (unsigned int)op
;
3714 tmp
= (word64
)*((float *)&wop
);
3718 tmp
= (word64
)*((double *)&op
);
3721 fprintf (stderr
, "Bad switch\n");
3724 result
= (uword64
)tmp
;
3729 fprintf (stderr
, "Bad switch\n");
3734 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result
),DOFMT(to
));
3741 /*-- co-processor support routines ------------------------------------------*/
3744 CoProcPresent(coproc_number
)
3745 unsigned int coproc_number
;
3747 /* Return TRUE if simulator provides a model for the given co-processor number */
3752 cop_lw(sd
,coproc_num
,coproc_reg
,memword
)
3754 int coproc_num
, coproc_reg
;
3755 unsigned int memword
;
3757 switch (coproc_num
) {
3761 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3763 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3764 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3769 #if 0 /* this should be controlled by a configuration option */
3770 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(IPC
));
3779 cop_ld(sd
,coproc_num
,coproc_reg
,memword
)
3781 int coproc_num
, coproc_reg
;
3784 switch (coproc_num
) {
3787 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3792 #if 0 /* this message should be controlled by a configuration option */
3793 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(IPC
));
3802 cop_sw(sd
,coproc_num
,coproc_reg
)
3804 int coproc_num
, coproc_reg
;
3806 unsigned int value
= 0;
3808 switch (coproc_num
) {
3814 hold
= FPR_STATE
[coproc_reg
];
3815 FPR_STATE
[coproc_reg
] = fmt_word
;
3816 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3817 FPR_STATE
[coproc_reg
] = hold
;
3821 value
= (unsigned int)ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
3824 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE
[coproc_reg
]));
3826 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
3833 #if 0 /* should be controlled by configuration option */
3834 sim_io_printf(sd
,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
3843 cop_sd(sd
,coproc_num
,coproc_reg
)
3845 int coproc_num
, coproc_reg
;
3848 switch (coproc_num
) {
3852 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3855 value
= ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
3858 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE
[coproc_reg
]));
3860 value
= ValueFPR(coproc_reg
,fmt_double
);
3867 #if 0 /* should be controlled by configuration option */
3868 sim_io_printf(sd
,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
3877 decode_coproc(sd
,instruction
)
3879 unsigned int instruction
;
3881 int coprocnum
= ((instruction
>> 26) & 3);
3885 case 0: /* standard CPU control and cache registers */
3887 int code
= ((instruction
>> 21) & 0x1F);
3888 /* R4000 Users Manual (second edition) lists the following CP0
3890 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3891 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3892 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3893 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3894 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3895 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3896 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3897 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3898 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3899 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3901 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3903 int rt
= ((instruction
>> 16) & 0x1F);
3904 int rd
= ((instruction
>> 11) & 0x1F);
3906 switch (rd
) /* NOTEs: Standard CP0 registers */
3908 /* 0 = Index R4000 VR4100 VR4300 */
3909 /* 1 = Random R4000 VR4100 VR4300 */
3910 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3911 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3912 /* 4 = Context R4000 VR4100 VR4300 */
3913 /* 5 = PageMask R4000 VR4100 VR4300 */
3914 /* 6 = Wired R4000 VR4100 VR4300 */
3915 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3916 /* 9 = Count R4000 VR4100 VR4300 */
3917 /* 10 = EntryHi R4000 VR4100 VR4300 */
3918 /* 11 = Compare R4000 VR4100 VR4300 */
3919 /* 12 = SR R4000 VR4100 VR4300 */
3926 /* 13 = Cause R4000 VR4100 VR4300 */
3933 /* 14 = EPC R4000 VR4100 VR4300 */
3934 /* 15 = PRId R4000 VR4100 VR4300 */
3935 #ifdef SUBTARGET_R3900
3944 /* 16 = Config R4000 VR4100 VR4300 */
3946 #ifdef SUBTARGET_R3900
3955 /* 17 = LLAddr R4000 VR4100 VR4300 */
3957 /* 18 = WatchLo R4000 VR4100 VR4300 */
3958 /* 19 = WatchHi R4000 VR4100 VR4300 */
3959 /* 20 = XContext R4000 VR4100 VR4300 */
3960 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3961 /* 27 = CacheErr R4000 VR4100 */
3962 /* 28 = TagLo R4000 VR4100 VR4300 */
3963 /* 29 = TagHi R4000 VR4100 VR4300 */
3964 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3965 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3966 /* CPR[0,rd] = GPR[rt]; */
3969 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3971 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3974 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3977 if (SR
& status_ERL
)
3979 /* Oops, not yet available */
3980 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3990 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3994 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
4002 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction
,pr_addr(IPC
));
4003 /* TODO: When executing an ERET or RFE instruction we should
4004 clear LLBIT, to ensure that any out-standing atomic
4005 read/modify/write sequence fails. */
4009 case 2: /* undefined co-processor */
4010 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction
,pr_addr(IPC
));
4013 case 1: /* should not occur (FPU co-processor) */
4014 case 3: /* should not occur (FPU co-processor) */
4015 SignalException(ReservedInstruction
,instruction
);
4022 /*-- instruction simulation -------------------------------------------------*/
4025 sim_engine_run (sd
, next_cpu_nr
, siggnal
)
4027 int next_cpu_nr
; /* ignore */
4028 int siggnal
; /* ignore */
4030 #if !defined(FASTSIM)
4031 unsigned int pipeline_count
= 1;
4035 if (STATE_MEMORY (sd
) == NULL
) {
4036 printf("DBG: simulate() entered with no memory\n");
4041 #if 0 /* Disabled to check that everything works OK */
4042 /* The VR4300 seems to sign-extend the PC on its first
4043 access. However, this may just be because it is currently
4044 configured in 32bit mode. However... */
4045 PC
= SIGNEXTEND(PC
,32);
4048 /* main controlling loop */
4050 /* Fetch the next instruction from the simulator memory: */
4051 uword64 vaddr
= (uword64
)PC
;
4054 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
4058 printf("DBG: state = 0x%08X :",state
);
4060 if (state
& simSTOP
) printf(" simSTOP");
4061 if (state
& simSTEP
) printf(" simSTEP");
4063 if (state
& simHALTEX
) printf(" simHALTEX");
4064 if (state
& simHALTIN
) printf(" simHALTIN");
4066 if (state
& simBE
) printf(" simBE");
4072 DSSTATE
= (STATE
& simDELAYSLOT
);
4075 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
4078 if (AddressTranslation(PC
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
4079 if ((vaddr
& 1) == 0) {
4080 /* Copy the action of the LW instruction */
4081 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
4082 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
4085 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
4086 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
4087 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
4088 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
4090 /* Copy the action of the LH instruction */
4091 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
4092 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
4095 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
4096 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
4097 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
4098 paddr
& ~ (uword64
) 1,
4099 vaddr
, isINSTRUCTION
, isREAL
);
4100 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
4101 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
4104 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
4109 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
4112 #if !defined(FASTSIM) || defined(PROFILE)
4113 instruction_fetches
++;
4114 /* Since we increment above, the value should only ever be zero if
4115 we have just overflowed: */
4116 if (instruction_fetches
== 0)
4117 instruction_fetch_overflow
++;
4118 #if defined(PROFILE)
4119 if ((STATE
& simPROFILE
) && ((instruction_fetches
% profile_frequency
) == 0) && profile_hist
) {
4120 unsigned n
= ((unsigned int)(PC
- profile_minpc
) >> (profile_shift
+ 2));
4121 if (n
< profile_nsamples
) {
4122 /* NOTE: The counts for the profiling bins are only 16bits wide */
4123 if (profile_hist
[n
] != USHRT_MAX
)
4124 (profile_hist
[n
])++;
4127 #endif /* PROFILE */
4128 #endif /* !FASTSIM && PROFILE */
4130 IPC
= PC
; /* copy PC for this instruction */
4131 /* This is required by exception processing, to ensure that we can
4132 cope with exceptions in the delay slots of branches that may
4133 already have changed the PC. */
4134 if ((vaddr
& 1) == 0)
4135 PC
+= 4; /* increment ready for the next fetch */
4138 /* NOTE: If we perform a delay slot change to the PC, this
4139 increment is not requuired. However, it would make the
4140 simulator more complicated to try and avoid this small hit. */
4142 /* Currently this code provides a simple model. For more
4143 complicated models we could perform exception status checks at
4144 this point, and set the simSTOP state as required. This could
4145 also include processing any hardware interrupts raised by any
4146 I/O model attached to the simulator context.
4148 Support for "asynchronous" I/O events within the simulated world
4149 could be providing by managing a counter, and calling a I/O
4150 specific handler when a particular threshold is reached. On most
4151 architectures a decrement and check for zero operation is
4152 usually quicker than an increment and compare. However, the
4153 process of managing a known value decrement to zero, is higher
4154 than the cost of using an explicit value UINT_MAX into the
4155 future. Which system is used will depend on how complicated the
4156 I/O model is, and how much it is likely to affect the simulator
4159 If events need to be scheduled further in the future than
4160 UINT_MAX event ticks, then the I/O model should just provide its
4161 own counter, triggered from the event system. */
4163 /* MIPS pipeline ticks. To allow for future support where the
4164 pipeline hit of individual instructions is known, this control
4165 loop manages a "pipeline_count" variable. It is initialised to
4166 1 (one), and will only be changed by the simulator engine when
4167 executing an instruction. If the engine does not have access to
4168 pipeline cycle count information then all instructions will be
4169 treated as using a single cycle. NOTE: A standard system is not
4170 provided by the default simulator because different MIPS
4171 architectures have different cycle counts for the same
4174 [NOTE: pipeline_count has been replaced the event queue] */
4177 /* Set previous flag, depending on current: */
4178 if (STATE
& simPCOC0
)
4182 /* and update the current value: */
4189 /* NOTE: For multi-context simulation environments the "instruction"
4190 variable should be local to this routine. */
4192 /* Shorthand accesses for engine. Note: If we wanted to use global
4193 variables (and a single-threaded simulator engine), then we can
4194 create the actual variables with these names. */
4196 if (!(STATE
& simSKIPNEXT
)) {
4197 /* Include the simulator engine */
4198 #include "oengine.c"
4199 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
4200 #error "Mismatch between run-time simulator code and simulation engine"
4202 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
4203 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
4205 #if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU))
4206 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
4209 #if defined(WARN_LOHI)
4210 /* Decrement the HI/LO validity ticks */
4219 #endif /* WARN_LOHI */
4221 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
4222 should check for it being changed. It is better doing it here,
4223 than within the simulator, since it will help keep the simulator
4226 #if defined(WARN_ZERO)
4227 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(IPC
));
4228 #endif /* WARN_ZERO */
4229 ZERO
= 0; /* reset back to zero before next instruction */
4231 } else /* simSKIPNEXT check */
4232 STATE
&= ~simSKIPNEXT
;
4234 /* If the delay slot was active before the instruction is
4235 executed, then update the PC to its new value: */
4238 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
4244 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
4245 /* Deal with pending register updates: */
4247 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
4249 if (PENDING_OUT
!= PENDING_IN
) {
4251 int index
= PENDING_OUT
;
4252 int total
= PENDING_TOTAL
;
4253 if (PENDING_TOTAL
== 0) {
4254 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
4257 for (loop
= 0; (loop
< total
); loop
++) {
4259 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
4261 if (PENDING_SLOT_REG
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
4263 printf("pending_slot_count[%d] = %d\n",index
,PENDING_SLOT_COUNT
[index
]);
4265 if (--(PENDING_SLOT_COUNT
[index
]) == 0) {
4267 printf("pending_slot_reg[%d] = %d\n",index
,PENDING_SLOT_REG
[index
]);
4268 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(PENDING_SLOT_VALUE
[index
]));
4270 if (PENDING_SLOT_REG
[index
] == COCIDX
) {
4272 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
4277 REGISTERS
[PENDING_SLOT_REG
[index
]] = PENDING_SLOT_VALUE
[index
];
4279 /* The only time we have PENDING updates to FPU
4280 registers, is when performing binary transfers. This
4281 means we should update the register type field. */
4282 if ((PENDING_SLOT_REG
[index
] >= FGRIDX
) && (PENDING_SLOT_REG
[index
] < (FGRIDX
+ 32)))
4283 FPR_STATE
[PENDING_SLOT_REG
[index
] - FGRIDX
] = fmt_uninterpreted
;
4287 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG
[index
],pr_addr(REGISTERS
[PENDING_SLOT_REG
[index
]]));
4289 PENDING_SLOT_REG
[index
] = (LAST_EMBED_REGNUM
+ 1);
4291 if (PENDING_OUT
== PSLOTS
)
4297 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
4300 if (index
== PSLOTS
)
4305 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN
,PENDING_OUT
,PENDING_TOTAL
);
4309 #if !defined(FASTSIM)
4310 if (sim_events_tickn (sd
, pipeline_count
))
4312 /* cpu->cia = cia; */
4313 sim_events_process (sd
);
4316 if (sim_events_tick (sd
))
4318 /* cpu->cia = cia; */
4319 sim_events_process (sd
);
4321 #endif /* FASTSIM */
4325 /* This code copied from gdb's utils.c. Would like to share this code,
4326 but don't know of a common place where both could get to it. */
4328 /* Temporary storage using circular buffer */
4334 static char buf
[NUMCELLS
][CELLSIZE
];
4336 if (++cell
>=NUMCELLS
) cell
=0;
4340 /* Print routines to handle variable size regs, etc */
4342 /* Eliminate warning from compiler on 32-bit systems */
4343 static int thirty_two
= 32;
4349 char *paddr_str
=get_cell();
4350 switch (sizeof(addr
))
4353 sprintf(paddr_str
,"%08lx%08lx",
4354 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
4357 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
4360 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
4363 sprintf(paddr_str
,"%x",addr
);
4372 char *paddr_str
=get_cell();
4373 sprintf(paddr_str
,"%08lx%08lx",
4374 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
4379 /*---------------------------------------------------------------------------*/
4380 /*> EOF interp.c <*/