2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 We only need to take account of the target endianness when moving data
23 between the simulator and the host. We do not need to worry about the
24 endianness of the host, since this sim code and GDB are executing in
27 The IDT monitor (found on the VR4300 board), seems to lie about
28 register contents. It seems to treat the registers as sign-extended
29 32-bit values. This cause *REAL* problems when single-stepping 64-bit
34 /* The TRACE manifests enable the provision of extra features. If they
35 are not defined then a simpler (quicker) simulator is constructed
36 without the required run-time checks, etc. */
37 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
43 #include "sim-utils.h"
44 #include "sim-options.h"
45 #include "sim-assert.h"
67 #include "libiberty.h"
69 #include "callback.h" /* GDB simulator callback interface */
70 #include "remote-sim.h" /* GDB simulator interface */
78 char* pr_addr
PARAMS ((SIM_ADDR addr
));
79 char* pr_uword64
PARAMS ((uword64 addr
));
82 /* Get the simulator engine description, without including the code: */
88 /* The following reserved instruction value is used when a simulator
89 trap is required. NOTE: Care must be taken, since this value may be
90 used in later revisions of the MIPS ISA. */
91 #define RSVD_INSTRUCTION (0x00000005)
92 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
94 #define RSVD_INSTRUCTION_ARG_SHIFT 6
95 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
98 /* Bits in the Debug register */
99 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
100 #define Debug_DM 0x40000000 /* Debug Mode */
101 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
107 /*---------------------------------------------------------------------------*/
108 /*-- GDB simulator interface ------------------------------------------------*/
109 /*---------------------------------------------------------------------------*/
111 static void dotrace
PARAMS((SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...));
112 static void ColdReset
PARAMS((SIM_DESC sd
));
113 static long getnum
PARAMS((SIM_DESC sd
, char *value
));
114 static unsigned int power2
PARAMS((unsigned int value
));
115 static void mips_size
PARAMS((SIM_DESC sd
, int n
));
117 /*---------------------------------------------------------------------------*/
121 #define DELAYSLOT() {\
122 if (STATE & simDELAYSLOT)\
123 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
124 STATE |= simDELAYSLOT;\
127 #define JALDELAYSLOT() {\
129 STATE |= simJALDELAYSLOT;\
133 STATE &= ~simDELAYSLOT;\
134 STATE |= simSKIPNEXT;\
137 #define CANCELDELAYSLOT() {\
139 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
142 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
143 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
145 #define K0BASE (0x80000000)
146 #define K0SIZE (0x20000000)
147 #define K1BASE (0xA0000000)
148 #define K1SIZE (0x20000000)
149 #define MONITOR_BASE (0xBFC00000)
150 #define MONITOR_SIZE (1 << 11)
151 #define MEM_SIZE (2 << 20)
153 /* Simple run-time monitor support */
154 static unsigned char *monitor
= NULL
;
155 static ut_reg monitor_base
= MONITOR_BASE
;
156 static unsigned monitor_size
= MONITOR_SIZE
; /* power-of-2 */
159 static char *tracefile
= "trace.din"; /* default filename for trace log */
160 static FILE *tracefh
= NULL
;
161 static void open_trace
PARAMS((SIM_DESC sd
));
164 #define OPTION_DINERO_TRACE 200
165 #define OPTION_DINERO_FILE 201
168 mips_option_handler (sd
, opt
, arg
)
175 case OPTION_DINERO_TRACE
: /* ??? */
177 /* Eventually the simTRACE flag could be treated as a toggle, to
178 allow external control of the program points being traced
179 (i.e. only from main onwards, excluding the run-time setup,
183 else if (strcmp (arg
, "yes") == 0)
185 else if (strcmp (arg
, "no") == 0)
187 else if (strcmp (arg
, "on") == 0)
189 else if (strcmp (arg
, "off") == 0)
193 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
199 Simulator constructed without dinero tracing support (for performance).\n\
200 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
204 case OPTION_DINERO_FILE
:
206 if (optarg
!= NULL
) {
208 tmp
= (char *)malloc(strlen(optarg
) + 1);
211 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
217 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
228 static const OPTION mips_options
[] =
230 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
231 '\0', "on|off", "Enable dinero tracing",
232 mips_option_handler
},
233 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
234 '\0', "FILE", "Write dinero trace to FILE",
235 mips_option_handler
},
236 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
240 int interrupt_pending
;
243 interrupt_event (SIM_DESC sd
, void *data
)
247 interrupt_pending
= 0;
248 SignalExceptionInterrupt ();
250 else if (!interrupt_pending
)
251 sim_events_schedule (sd
, 1, interrupt_event
, data
);
256 /*---------------------------------------------------------------------------*/
257 /*-- GDB simulator interface ------------------------------------------------*/
258 /*---------------------------------------------------------------------------*/
261 sim_open (kind
, cb
, abfd
, argv
)
267 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
268 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
270 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
272 /* FIXME: watchpoints code shouldn't need this */
273 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
274 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
275 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
277 /* memory defaults (unless sim_size was here first) */
278 if (STATE_MEM_SIZE (sd
) == 0)
279 STATE_MEM_SIZE (sd
) = MEM_SIZE
;
280 STATE_MEM_BASE (sd
) = K1BASE
;
284 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
286 sim_add_option_table (sd
, mips_options
);
288 /* getopt will print the error message so we just have to exit if this fails.
289 FIXME: Hmmm... in the case of gdb we need getopt to call
291 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
293 /* Uninstall the modules to avoid memory leaks,
294 file descriptor leaks, etc. */
295 sim_module_uninstall (sd
);
299 /* check for/establish the a reference program image */
300 if (sim_analyze_program (sd
,
301 (STATE_PROG_ARGV (sd
) != NULL
302 ? *STATE_PROG_ARGV (sd
)
306 sim_module_uninstall (sd
);
310 /* Configure/verify the target byte order and other runtime
311 configuration options */
312 if (sim_config (sd
) != SIM_RC_OK
)
314 sim_module_uninstall (sd
);
318 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
320 /* Uninstall the modules to avoid memory leaks,
321 file descriptor leaks, etc. */
322 sim_module_uninstall (sd
);
326 /* verify assumptions the simulator made about the host type system.
327 This macro does not return if there is a problem */
328 if (sizeof(int) != (4 * sizeof(char)))
329 SignalExceptionSimulatorFault ("sizeof(int) != 4");
330 if (sizeof(word64
) != (8 * sizeof(char)))
331 SignalExceptionSimulatorFault ("sizeof(word64) != 8");
334 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
335 and DOUBLE binary formats. This is a bit nasty, requiring that we
336 trust the explicit manifests held in the source: */
337 /* TODO: We need to cope with the simulated target and the host not
338 having the same endianness. This will require the high and low
339 words of a (double) to be swapped when converting between the
340 host and the simulated target. */
348 s
.d
= (double)523.2939453125;
350 if ((s
.i
[0] == 0 && (s
.f
[1] != (float)4.01102924346923828125
351 || s
.i
[1] != 0x40805A5A))
352 || (s
.i
[1] == 0 && (s
.f
[0] != (float)4.01102924346923828125
353 || s
.i
[0] != 0x40805A5A)))
355 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
361 /* This is NASTY, in that we are assuming the size of specific
365 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
367 cpu
->register_widths
[rn
] = GPRLEN
;
368 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
369 cpu
->register_widths
[rn
] = GPRLEN
;
370 else if ((rn
>= 33) && (rn
<= 37))
371 cpu
->register_widths
[rn
] = GPRLEN
;
372 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
373 cpu
->register_widths
[rn
] = 32;
375 cpu
->register_widths
[rn
] = 0;
377 /* start-sanitize-r5900 */
379 /* set the 5900 "upper" registers to 64 bits */
380 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
381 cpu
->register_widths
[rn
] = 64;
382 /* end-sanitize-r5900 */
386 /* FIXME: In the future both of these malloc's can be replaced by
387 calls to sim-core. */
389 /* If the host has "mmap" available we could use it to provide a
390 very large virtual address space for the simulator, since memory
391 would only be allocated within the "mmap" space as it is
392 accessed. This can also be linked to the architecture specific
393 support, required to simulate the MMU. */
394 mips_size(sd
, STATE_MEM_SIZE (sd
));
395 /* NOTE: The above will also have enabled any profiling state! */
397 /* Create the monitor address space as well */
398 monitor
= (unsigned char *)calloc(1,monitor_size
);
400 fprintf(stderr
,"Not enough VM for monitor simulation (%d bytes)\n",
404 if (STATE
& simTRACE
)
408 /* Write the monitor trap address handlers into the monitor (eeprom)
409 address space. This can only be done once the target endianness
410 has been determined. */
413 /* Entry into the IDT monitor is via fixed address vectors, and
414 not using machine instructions. To avoid clashing with use of
415 the MIPS TRAP system, we place our own (simulator specific)
416 "undefined" instructions into the relevant vector slots. */
417 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
419 address_word vaddr
= (MONITOR_BASE
+ loop
);
420 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
422 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
424 /* The PMON monitor uses the same address space, but rather than
425 branching into it the address of a routine is loaded. We can
426 cheat for the moment, and direct the PMON routine to IDT style
427 instructions within the monitor space. This relies on the IDT
428 monitor not using the locations from 0xBFC00500 onwards as its
430 for (loop
= 0; (loop
< 24); loop
++)
432 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
433 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
449 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
451 case 8: /* cliexit */
454 case 11: /* flush_cache */
458 /* FIXME - should monitor_base be SIM_ADDR?? */
459 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
461 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
463 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
465 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
477 tracefh
= fopen(tracefile
,"wb+");
480 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
487 sim_close (sd
, quitting
)
492 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
495 /* "quitting" is non-zero if we cannot hang on errors */
497 /* Ensure that any resources allocated through the callback
498 mechanism are released: */
499 sim_io_shutdown (sd
);
502 if (tracefh
!= NULL
&& tracefh
!= stderr
)
508 if (STATE_MEMORY (sd
) != NULL
)
509 free(STATE_MEMORY (sd
)); /* cfree not available on all hosts */
510 STATE_MEMORY (sd
) = NULL
;
517 sim_write (sd
,addr
,buffer
,size
)
520 unsigned char *buffer
;
525 /* Return the number of bytes written, or zero if error. */
527 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
530 /* We use raw read and write routines, since we do not want to count
531 the GDB memory accesses in our statistics gathering. */
533 for (index
= 0; index
< size
; index
++)
535 address_word vaddr
= (address_word
)addr
+ index
;
538 if (!AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isTARGET
, isRAW
))
540 StoreMemory (cca
, AccessLength_BYTE
, buffer
[index
], 0, paddr
, vaddr
, isRAW
);
547 sim_read (sd
,addr
,buffer
,size
)
550 unsigned char *buffer
;
555 /* Return the number of bytes read, or zero if error. */
557 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
560 for (index
= 0; (index
< size
); index
++)
562 address_word vaddr
= (address_word
)addr
+ index
;
566 if (!AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isTARGET
, isRAW
))
568 LoadMemory (&value
, NULL
, cca
, AccessLength_BYTE
, paddr
, vaddr
, isDATA
, isRAW
);
569 buffer
[index
] = (unsigned char)(value
&0xFF);
576 sim_store_register (sd
,rn
,memory
)
579 unsigned char *memory
;
581 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
582 /* NOTE: gdb (the client) stores registers in target byte order
583 while the simulator uses host byte order */
585 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
588 /* Unfortunately this suffers from the same problem as the register
589 numbering one. We need to know what the width of each logical
590 register number is for the architecture being simulated. */
592 if (cpu
->register_widths
[rn
] == 0)
593 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
594 /* start-sanitize-r5900 */
595 else if (rn
== REGISTER_SA
)
596 SA
= T2H_8(*(uword64
*)memory
);
597 else if (rn
> LAST_EMBED_REGNUM
)
598 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(uword64
*)memory
);
599 /* end-sanitize-r5900 */
600 else if (cpu
->register_widths
[rn
] == 32)
601 cpu
->registers
[rn
] = T2H_4 (*(unsigned int*)memory
);
603 cpu
->registers
[rn
] = T2H_8 (*(uword64
*)memory
);
609 sim_fetch_register (sd
,rn
,memory
)
612 unsigned char *memory
;
614 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
615 /* NOTE: gdb (the client) stores registers in target byte order
616 while the simulator uses host byte order */
618 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
621 if (cpu
->register_widths
[rn
] == 0)
622 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
623 /* start-sanitize-r5900 */
624 else if (rn
== REGISTER_SA
)
625 *((uword64
*)memory
) = H2T_8(SA
);
626 else if (rn
> LAST_EMBED_REGNUM
)
627 *((uword64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
628 /* end-sanitize-r5900 */
629 else if (cpu
->register_widths
[rn
] == 32)
630 *((unsigned int *)memory
) = H2T_4 ((unsigned int)(cpu
->registers
[rn
] & 0xFFFFFFFF));
631 else /* 64bit register */
632 *((uword64
*)memory
) = H2T_8 (cpu
->registers
[rn
]);
639 sim_info (sd
,verbose
)
643 /* Accessed from the GDB "info files" command: */
644 if (STATE_VERBOSE_P (sd
) || verbose
)
647 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
648 (PROCESSOR_64BIT
? 64 : 32),
649 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
651 sim_io_printf (sd
, "0x%08X bytes of memory at 0x%s\n",
653 pr_addr (STATE_MEM_BASE (sd
)));
655 #if !defined(FASTSIM)
656 /* It would be a useful feature, if when performing multi-cycle
657 simulations (rather than single-stepping) we keep the start and
658 end times of the execution, so that we can give a performance
659 figure for the simulator. */
660 #endif /* !FASTSIM */
661 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
662 (long) sim_events_time (sd
));
664 /* print information pertaining to MIPS ISA and architecture being simulated */
665 /* things that may be interesting */
666 /* instructions executed - if available */
667 /* cycles executed - if available */
668 /* pipeline stalls - if available */
669 /* virtual time taken */
671 /* profiling frequency */
675 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
680 sim_create_inferior (sd
, abfd
, argv
,env
)
688 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
695 /* override PC value set by ColdReset () */
696 PC
= (unsigned64
) bfd_get_start_address (abfd
);
698 #if 0 /* def DEBUG */
701 /* We should really place the argv slot values into the argument
702 registers, and onto the stack as required. However, this
703 assumes that we have a stack defined, which is not
704 necessarily true at the moment. */
706 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
707 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
708 printf("DBG: arg \"%s\"\n",*cptr
);
715 typedef enum {e_terminate
,e_help
,e_setmemsize
,e_reset
} e_cmds
;
717 static struct t_sim_command
{
722 {e_help
, "help", ": Show MIPS simulator private commands"},
723 {e_setmemsize
,"set-memory-size","<n> : Specify amount of memory simulated"},
724 {e_reset
, "reset-system", ": Reset the simulated processor"},
729 sim_do_command (sd
,cmd
)
733 struct t_sim_command
*cptr
;
735 if (!(cmd
&& *cmd
!= '\0'))
738 /* NOTE: Accessed from the GDB "sim" commmand: */
739 for (cptr
= sim_commands
; cptr
&& cptr
->name
; cptr
++)
740 if (strncmp (cmd
, cptr
->name
, strlen(cptr
->name
)) == 0)
742 cmd
+= strlen(cptr
->name
);
744 case e_help
: /* no arguments */
746 struct t_sim_command
*lptr
;
747 sim_io_printf(sd
,"List of MIPS simulator commands:\n");
748 for (lptr
= sim_commands
; lptr
->name
; lptr
++)
749 sim_io_printf(sd
,"%s %s\n",lptr
->name
,lptr
->help
);
750 sim_args_command (sd
, "help");
754 case e_setmemsize
: /* memory size argument */
756 unsigned int newsize
= (unsigned int)getnum(sd
, cmd
);
757 mips_size(sd
, newsize
);
761 case e_reset
: /* no arguments */
763 /* NOTE: See the comments in sim_open() relating to device
768 sim_io_printf(sd
,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd
,cptr
->id
);
776 /* try for a common command when the sim specific lookup fails */
777 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
778 sim_io_printf(sd
,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd
);
784 /*---------------------------------------------------------------------------*/
785 /* NOTE: The following routines do not seem to be used by GDB at the
786 moment. However, they may be useful to the standalone simulator
791 mips_size(sd
, newsize
)
796 /* Used by "run", and internally, to set the simulated memory size */
798 sim_io_printf(sd
,"Zero not valid: Memory size still 0x%08X bytes\n",STATE_MEM_SIZE (sd
));
801 newsize
= power2(newsize
);
802 if (STATE_MEMORY (sd
) == NULL
)
803 new = (char *)calloc(64,(STATE_MEM_SIZE (sd
) / 64));
805 new = (char *)realloc(STATE_MEMORY (sd
),newsize
);
807 if (STATE_MEMORY (sd
) == NULL
)
808 sim_io_error(sd
,"Not enough VM for simulation memory of 0x%08X bytes",STATE_MEM_SIZE (sd
));
810 sim_io_eprintf(sd
,"Failed to resize memory (still 0x%08X bytes)\n",STATE_MEM_SIZE (sd
));
812 STATE_MEM_SIZE (sd
) = (unsigned)newsize
;
813 STATE_MEMORY (sd
) = new;
819 /*---------------------------------------------------------------------------*/
820 /*-- Private simulator support interface ------------------------------------*/
821 /*---------------------------------------------------------------------------*/
823 /* Read a null terminated string from memory, return in a buffer */
832 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
834 buf
= NZALLOC (char, nr
+ 1);
835 sim_read (sd
, addr
, buf
, nr
);
839 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
841 sim_monitor(sd
,reason
)
846 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
849 /* The IDT monitor actually allows two instructions per vector
850 slot. However, the simulator currently causes a trap on each
851 individual instruction. We cheat, and lose the bottom bit. */
854 /* The following callback functions are available, however the
855 monitor we are simulating does not make use of them: get_errno,
856 isatty, lseek, rename, system, time and unlink */
860 case 6: /* int open(char *path,int flags) */
862 char *path
= fetch_str (sd
, A0
);
863 V0
= sim_io_open (sd
, path
, (int)A1
);
868 case 7: /* int read(int file,char *ptr,int len) */
872 char *buf
= zalloc (nr
);
873 V0
= sim_io_read (sd
, fd
, buf
, nr
);
874 sim_write (sd
, A1
, buf
, nr
);
879 case 8: /* int write(int file,char *ptr,int len) */
883 char *buf
= zalloc (nr
);
884 sim_read (sd
, A1
, buf
, nr
);
885 V0
= sim_io_write (sd
, fd
, buf
, nr
);
890 case 10: /* int close(int file) */
892 V0
= sim_io_close (sd
, (int)A0
);
896 case 11: /* char inbyte(void) */
899 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
901 sim_io_error(sd
,"Invalid return from character read");
909 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
911 char tmp
= (char)(A0
& 0xFF);
912 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
916 case 17: /* void _exit() */
918 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
919 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
, sim_exited
,
920 (unsigned int)(A0
& 0xFFFFFFFF));
924 case 28 : /* PMON flush_cache */
927 case 55: /* void get_mem_info(unsigned int *ptr) */
928 /* in: A0 = pointer to three word memory location */
929 /* out: [A0 + 0] = size */
930 /* [A0 + 4] = instruction cache size */
931 /* [A0 + 8] = data cache size */
933 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
935 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
936 sim_io_eprintf (sd
, "sim: get_mem_info() depreciated\n");
940 case 158 : /* PMON printf */
941 /* in: A0 = pointer to format string */
942 /* A1 = optional argument 1 */
943 /* A2 = optional argument 2 */
944 /* A3 = optional argument 3 */
946 /* The following is based on the PMON printf source */
950 signed_word
*ap
= &A1
; /* 1st argument */
951 /* This isn't the quickest way, since we call the host print
952 routine for every character almost. But it does avoid
953 having to allocate and manage a temporary string buffer. */
954 /* TODO: Include check that we only use three arguments (A1,
956 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
961 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
962 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
963 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
965 if (strchr ("dobxXulscefg%", s
))
980 else if (c
>= '1' && c
<= '9')
984 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
987 n
= (unsigned int)strtol(tmp
,NULL
,10);
1000 sim_io_printf (sd
, "%%");
1005 address_word p
= *ap
++;
1007 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1008 sim_io_printf(sd
, "%c", ch
);
1011 sim_io_printf(sd
,"(null)");
1014 sim_io_printf (sd
, "%c", (int)*ap
++);
1019 sim_read (sd
, s
++, &c
, 1);
1023 sim_read (sd
, s
++, &c
, 1);
1026 if (strchr ("dobxXu", c
))
1028 word64 lv
= (word64
) *ap
++;
1030 sim_io_printf(sd
,"<binary not supported>");
1033 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1035 sim_io_printf(sd
, tmp
, lv
);
1037 sim_io_printf(sd
, tmp
, (int)lv
);
1040 else if (strchr ("eEfgG", c
))
1042 double dbl
= *(double*)(ap
++);
1043 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1044 sim_io_printf (sd
, tmp
, dbl
);
1050 sim_io_printf(sd
, "%c", c
);
1056 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1057 reason
, pr_addr(IPC
));
1063 /* Store a word into memory. */
1066 store_word (sd
, vaddr
, val
)
1074 if ((vaddr
& 3) != 0)
1075 SignalExceptionAddressStore ();
1078 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1081 const uword64 mask
= 7;
1085 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1086 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1087 memval
= ((uword64
) val
) << (8 * byte
);
1088 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1094 /* Load a word from memory. */
1097 load_word (sd
, vaddr
)
1101 if ((vaddr
& 3) != 0)
1102 SignalExceptionAddressLoad ();
1108 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1111 const uword64 mask
= 0x7;
1112 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1113 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1117 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1118 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1120 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1121 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1128 /* Simulate the mips16 entry and exit pseudo-instructions. These
1129 would normally be handled by the reserved instruction exception
1130 code, but for ease of simulation we just handle them directly. */
1133 mips16_entry (sd
,insn
)
1137 int aregs
, sregs
, rreg
;
1140 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1143 aregs
= (insn
& 0x700) >> 8;
1144 sregs
= (insn
& 0x0c0) >> 6;
1145 rreg
= (insn
& 0x020) >> 5;
1147 /* This should be checked by the caller. */
1156 /* This is the entry pseudo-instruction. */
1158 for (i
= 0; i
< aregs
; i
++)
1159 store_word ((uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1167 store_word ((uword64
) tsp
, RA
);
1170 for (i
= 0; i
< sregs
; i
++)
1173 store_word ((uword64
) tsp
, GPR
[16 + i
]);
1181 /* This is the exit pseudo-instruction. */
1188 RA
= load_word ((uword64
) tsp
);
1191 for (i
= 0; i
< sregs
; i
++)
1194 GPR
[i
+ 16] = load_word ((uword64
) tsp
);
1202 FGR
[0] = WORD64LO (GPR
[4]);
1203 FPR_STATE
[0] = fmt_uninterpreted
;
1205 else if (aregs
== 6)
1207 FGR
[0] = WORD64LO (GPR
[5]);
1208 FGR
[1] = WORD64LO (GPR
[4]);
1209 FPR_STATE
[0] = fmt_uninterpreted
;
1210 FPR_STATE
[1] = fmt_uninterpreted
;
1212 #endif /* defined(HASFPU) */
1224 /* Round *UP* to the nearest power-of-2 if not already one */
1225 if (value
!= (value
& ~(value
- 1))) {
1226 for (tmp
= value
, loop
= 0; (tmp
!= 0); loop
++)
1228 value
= (1 << loop
);
1242 num
= strtol(value
,&end
,10);
1244 sim_io_printf(sd
,"Warning: Invalid number \"%s\" ignored, using zero\n",value
);
1246 if (*end
&& ((tolower(*end
) == 'k') || (tolower(*end
) == 'm'))) {
1247 if (tolower(*end
) == 'k')
1254 sim_io_printf(sd
,"Warning: Spurious characters \"%s\" at end of number ignored\n",end
);
1260 /*-- trace support ----------------------------------------------------------*/
1262 /* The TRACE support is provided (if required) in the memory accessing
1263 routines. Since we are also providing the architecture specific
1264 features, the architecture simulation code can also deal with
1265 notifying the TRACE world of cache flushes, etc. Similarly we do
1266 not need to provide profiling support in the simulator engine,
1267 since we can sample in the instruction fetch control loop. By
1268 defining the TRACE manifest, we add tracing as a run-time
1272 /* Tracing by default produces "din" format (as required by
1273 dineroIII). Each line of such a trace file *MUST* have a din label
1274 and address field. The rest of the line is ignored, so comments can
1275 be included if desired. The first field is the label which must be
1276 one of the following values:
1281 3 escape record (treated as unknown access type)
1282 4 escape record (causes cache flush)
1284 The address field is a 32bit (lower-case) hexadecimal address
1285 value. The address should *NOT* be preceded by "0x".
1287 The size of the memory transfer is not important when dealing with
1288 cache lines (as long as no more than a cache line can be
1289 transferred in a single operation :-), however more information
1290 could be given following the dineroIII requirement to allow more
1291 complete memory and cache simulators to provide better
1292 results. i.e. the University of Pisa has a cache simulator that can
1293 also take bus size and speed as (variable) inputs to calculate
1294 complete system performance (a much more useful ability when trying
1295 to construct an end product, rather than a processor). They
1296 currently have an ARM version of their tool called ChARM. */
1300 void dotrace(SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...)
1302 if (STATE
& simTRACE
) {
1304 fprintf(tracefh
,"%d %s ; width %d ; ",
1308 va_start(ap
,comment
);
1309 vfprintf(tracefh
,comment
,ap
);
1311 fprintf(tracefh
,"\n");
1313 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1314 we may be generating 64bit ones, we should put the hi-32bits of the
1315 address into the comment field. */
1317 /* TODO: Provide a buffer for the trace lines. We can then avoid
1318 performing writes until the buffer is filled, or the file is
1321 /* NOTE: We could consider adding a comment field to the "din" file
1322 produced using type 3 markers (unknown access). This would then
1323 allow information about the program that the "din" is for, and
1324 the MIPs world that was being simulated, to be placed into the
1331 /*---------------------------------------------------------------------------*/
1332 /*-- simulator engine -------------------------------------------------------*/
1333 /*---------------------------------------------------------------------------*/
1339 /* RESET: Fixed PC address: */
1340 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1341 /* The reset vector address is in the unmapped, uncached memory space. */
1343 SR
&= ~(status_SR
| status_TS
| status_RP
);
1344 SR
|= (status_ERL
| status_BEV
);
1346 /* Cheat and allow access to the complete register set immediately */
1347 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1348 && WITH_TARGET_WORD_BITSIZE
== 64)
1349 SR
|= status_FR
; /* 64bit registers */
1351 /* Ensure that any instructions with pending register updates are
1355 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1356 PENDING_SLOT_REG
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1357 PENDING_IN
= PENDING_OUT
= PENDING_TOTAL
= 0;
1360 /* Initialise the FPU registers to the unknown state */
1361 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1364 for (rn
= 0; (rn
< 32); rn
++)
1365 FPR_STATE
[rn
] = fmt_uninterpreted
;
1371 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1373 /* Translate a virtual address to a physical address and cache
1374 coherence algorithm describing the mechanism used to resolve the
1375 memory reference. Given the virtual address vAddr, and whether the
1376 reference is to Instructions ot Data (IorD), find the corresponding
1377 physical address (pAddr) and the cache coherence algorithm (CCA)
1378 used to resolve the reference. If the virtual address is in one of
1379 the unmapped address spaces the physical address and the CCA are
1380 determined directly by the virtual address. If the virtual address
1381 is in one of the mapped address spaces then the TLB is used to
1382 determine the physical address and access type; if the required
1383 translation is not present in the TLB or the desired access is not
1384 permitted the function fails and an exception is taken.
1386 NOTE: Normally (RAW == 0), when address translation fails, this
1387 function raises an exception and does not return. */
1390 address_translation(sd
,vAddr
,IorD
,LorS
,pAddr
,CCA
,raw
)
1395 address_word
*pAddr
;
1399 int res
= -1; /* TRUE : Assume good return */
1402 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1405 /* Check that the address is valid for this memory model */
1407 /* For a simple (flat) memory model, we simply pass virtual
1408 addressess through (mostly) unchanged. */
1409 vAddr
&= 0xFFFFFFFF;
1411 /* Treat the kernel memory spaces identically for the moment: */
1412 if ((STATE_MEM_BASE (sd
) == K1BASE
) && (vAddr
>= K0BASE
) && (vAddr
< (K0BASE
+ K0SIZE
)))
1413 vAddr
+= (K1BASE
- K0BASE
);
1415 /* Also assume that the K1BASE memory wraps. This is required to
1416 allow the PMON run-time __sizemem() routine to function (without
1417 having to provide exception simulation). NOTE: A kludge to work
1418 around the fact that the monitor memory is currently held in the
1420 if (((vAddr
< monitor_base
) || (vAddr
>= (monitor_base
+ monitor_size
))) && (vAddr
>= K1BASE
&& vAddr
< (K1BASE
+ K1SIZE
)))
1421 vAddr
= (K1BASE
| (vAddr
& (STATE_MEM_SIZE (sd
) - 1)));
1423 *pAddr
= vAddr
; /* default for isTARGET */
1424 *CCA
= Uncached
; /* not used for isHOST */
1426 /* NOTE: This is a duplicate of the code that appears in the
1427 LoadMemory and StoreMemory functions. They should be merged into
1428 a single function (that can be in-lined if required). */
1429 if ((vAddr
>= STATE_MEM_BASE (sd
)) && (vAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
1431 } else if ((vAddr
>= monitor_base
) && (vAddr
< (monitor_base
+ monitor_size
))) {
1435 sim_io_eprintf(sd
,"Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "isSTORE" : "isLOAD"),pr_addr(IPC
));
1437 res
= 0; /* AddressTranslation has failed */
1438 *pAddr
= (SIM_ADDR
)-1;
1439 if (!raw
) /* only generate exceptions on real memory transfers */
1441 if (IorD
== isINSTRUCTION
)
1442 SignalExceptionInstructionFetch ();
1443 else if (LorS
== isSTORE
)
1444 SignalExceptionAddressStore ();
1446 SignalExceptionAddressLoad ();
1450 /* This is a normal occurance during gdb operation, for instance
1451 trying to print parameters at function start before they have
1452 been setup, and hence we should not print a warning except
1453 when debugging the simulator. */
1454 sim_io_eprintf(sd
,"AddressTranslation for %s %s from 0x%s failed\n",(IorD
? "data" : "instruction"),(LorS
? "store" : "load"),pr_addr(vAddr
));
1461 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1462 /* Prefetch data from memory. Prefetch is an advisory instruction for
1463 which an implementation specific action is taken. The action taken
1464 may increase performance, but must not change the meaning of the
1465 program, or alter architecturally-visible state. */
1468 prefetch(sd
,CCA
,pAddr
,vAddr
,DATA
,hint
)
1477 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1480 /* For our simple memory model we do nothing */
1484 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1485 /* Load a value from memory. Use the cache and main memory as
1486 specified in the Cache Coherence Algorithm (CCA) and the sort of
1487 access (IorD) to find the contents of AccessLength memory bytes
1488 starting at physical location pAddr. The data is returned in the
1489 fixed width naturally-aligned memory element (MemElem). The
1490 low-order two (or three) bits of the address and the AccessLength
1491 indicate which of the bytes within MemElem needs to be given to the
1492 processor. If the memory access type of the reference is uncached
1493 then only the referenced bytes are read from memory and valid
1494 within the memory element. If the access type is cached, and the
1495 data is not present in cache, an implementation specific size and
1496 alignment block of memory is read and loaded into the cache to
1497 satisfy a load reference. At a minimum, the block is the entire
1500 load_memory(sd
,memvalp
,memval1p
,CCA
,AccessLength
,pAddr
,vAddr
,IorD
,raw
)
1515 if (STATE_MEMORY (sd
) == NULL
)
1516 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(raw
? "isRAW" : "isREAL"));
1519 #if defined(WARN_MEM)
1520 if (CCA
!= uncached
)
1521 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1523 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
) {
1524 /* In reality this should be a Bus Error */
1525 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1527 #endif /* WARN_MEM */
1529 /* Decide which physical memory locations are being dealt with. At
1530 this point we should be able to split the pAddr bits into the
1531 relevant address map being simulated. */
1532 /* If the "raw" variable is set, the memory read being performed
1533 should *NOT* update any I/O state or affect the CPU state
1534 (including statistics gathering). The parameter MEMVALP is least
1535 significant byte justified. */
1537 /* If instruction fetch then we need to check that the two lo-order
1538 bits are zero, otherwise raise a InstructionFetch exception: */
1539 if ((IorD
== isINSTRUCTION
)
1540 && ((pAddr
& 0x3) != 0)
1541 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1542 SignalExceptionInstructionFetch ();
1544 unsigned int index
= 0;
1545 unsigned char *mem
= NULL
;
1549 dotrace(sd
,tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1552 /* NOTE: Quicker methods of decoding the address space can be used
1553 when a real memory map is being simulated (i.e. using hi-order
1554 address bits to select device). */
1555 if ((pAddr
>= STATE_MEM_BASE (sd
)) && (pAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
1556 index
= ((unsigned int)(pAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1));
1557 mem
= STATE_MEMORY (sd
);
1558 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
1559 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
1563 sim_io_error(sd
,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
1565 /* If we obtained the endianness of the host, and it is the same
1566 as the target memory system we can optimise the memory
1567 accesses. However, without that information we must perform
1568 slow transfer, and hope that the compiler optimisation will
1569 merge successive loads. */
1571 /* In reality we should always be loading a doubleword value (or
1572 word value in 32bit memory worlds). The external code then
1573 extracts the required bytes. However, to keep performance
1574 high we only load the required bytes into the relevant
1577 switch (AccessLength
) { /* big-endian memory */
1578 case AccessLength_QUADWORD
:
1579 value1
|= ((uword64
)mem
[index
++] << 56);
1580 case 14: /* AccessLength is one less than datalen */
1581 value1
|= ((uword64
)mem
[index
++] << 48);
1583 value1
|= ((uword64
)mem
[index
++] << 40);
1585 value1
|= ((uword64
)mem
[index
++] << 32);
1587 value1
|= ((unsigned int)mem
[index
++] << 24);
1589 value1
|= ((unsigned int)mem
[index
++] << 16);
1591 value1
|= ((unsigned int)mem
[index
++] << 8);
1593 value1
|= mem
[index
];
1595 case AccessLength_DOUBLEWORD
:
1596 value
|= ((uword64
)mem
[index
++] << 56);
1597 case AccessLength_SEPTIBYTE
:
1598 value
|= ((uword64
)mem
[index
++] << 48);
1599 case AccessLength_SEXTIBYTE
:
1600 value
|= ((uword64
)mem
[index
++] << 40);
1601 case AccessLength_QUINTIBYTE
:
1602 value
|= ((uword64
)mem
[index
++] << 32);
1603 case AccessLength_WORD
:
1604 value
|= ((unsigned int)mem
[index
++] << 24);
1605 case AccessLength_TRIPLEBYTE
:
1606 value
|= ((unsigned int)mem
[index
++] << 16);
1607 case AccessLength_HALFWORD
:
1608 value
|= ((unsigned int)mem
[index
++] << 8);
1609 case AccessLength_BYTE
:
1610 value
|= mem
[index
];
1614 index
+= (AccessLength
+ 1);
1615 switch (AccessLength
) { /* little-endian memory */
1616 case AccessLength_QUADWORD
:
1617 value1
|= ((uword64
)mem
[--index
] << 56);
1618 case 14: /* AccessLength is one less than datalen */
1619 value1
|= ((uword64
)mem
[--index
] << 48);
1621 value1
|= ((uword64
)mem
[--index
] << 40);
1623 value1
|= ((uword64
)mem
[--index
] << 32);
1625 value1
|= ((uword64
)mem
[--index
] << 24);
1627 value1
|= ((uword64
)mem
[--index
] << 16);
1629 value1
|= ((uword64
)mem
[--index
] << 8);
1631 value1
|= ((uword64
)mem
[--index
] << 0);
1633 case AccessLength_DOUBLEWORD
:
1634 value
|= ((uword64
)mem
[--index
] << 56);
1635 case AccessLength_SEPTIBYTE
:
1636 value
|= ((uword64
)mem
[--index
] << 48);
1637 case AccessLength_SEXTIBYTE
:
1638 value
|= ((uword64
)mem
[--index
] << 40);
1639 case AccessLength_QUINTIBYTE
:
1640 value
|= ((uword64
)mem
[--index
] << 32);
1641 case AccessLength_WORD
:
1642 value
|= ((uword64
)mem
[--index
] << 24);
1643 case AccessLength_TRIPLEBYTE
:
1644 value
|= ((uword64
)mem
[--index
] << 16);
1645 case AccessLength_HALFWORD
:
1646 value
|= ((uword64
)mem
[--index
] << 8);
1647 case AccessLength_BYTE
:
1648 value
|= ((uword64
)mem
[--index
] << 0);
1654 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1655 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1658 /* When dealing with raw memory accesses there is no need to
1659 deal with shifts. */
1660 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
1661 if (!raw
) { /* do nothing for raw accessess */
1663 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1664 else /* little-endian only needs to be shifted up to the correct byte offset */
1665 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1670 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1671 pr_uword64(value1
),pr_uword64(value
));
1677 if (memval1p
) *memval1p
= value1
;
1681 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1683 /* Store a value to memory. The specified data is stored into the
1684 physical location pAddr using the memory hierarchy (data caches and
1685 main memory) as specified by the Cache Coherence Algorithm
1686 (CCA). The MemElem contains the data for an aligned, fixed-width
1687 memory element (word for 32-bit processors, doubleword for 64-bit
1688 processors), though only the bytes that will actually be stored to
1689 memory need to be valid. The low-order two (or three) bits of pAddr
1690 and the AccessLength field indicates which of the bytes within the
1691 MemElem data should actually be stored; only these bytes in memory
1695 store_memory(sd
,CCA
,AccessLength
,MemElem
,MemElem1
,pAddr
,vAddr
,raw
)
1700 uword64 MemElem1
; /* High order 64 bits */
1706 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
),(raw
? "isRAW" : "isREAL"));
1709 #if defined(WARN_MEM)
1710 if (CCA
!= uncached
)
1711 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1713 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1714 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1715 #endif /* WARN_MEM */
1719 dotrace(sd
,tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1722 /* See the comments in the LoadMemory routine about optimising
1723 memory accesses. Also if we wanted to make the simulator smaller,
1724 we could merge a lot of this code with the LoadMemory
1725 routine. However, this would slow the simulator down with
1726 run-time conditionals. */
1728 /* If the "raw" variable is set, the memory read being performed
1729 should *NOT* update any I/O state or affect the CPU state
1730 (including statistics gathering). The parameter MEMELEM is least
1731 significant byte justified. */
1733 unsigned int index
= 0;
1734 unsigned char *mem
= NULL
;
1736 if ((pAddr
>= STATE_MEM_BASE (sd
)) && (pAddr
< (STATE_MEM_BASE (sd
) + STATE_MEM_SIZE (sd
)))) {
1737 index
= ((unsigned int)(pAddr
- STATE_MEM_BASE (sd
)) & (STATE_MEM_SIZE (sd
) - 1));
1738 mem
= STATE_MEMORY (sd
);
1739 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
1740 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
1745 sim_io_error(sd
,"Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
1750 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1753 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
1756 /* need to shift raw (least significant byte aligned) data
1757 into correct byte slots */
1758 shift
= ((7 - AccessLength
) * 8);
1759 else /* real memory access */
1760 shift
= ((pAddr
& LOADDRMASK
) * 8);
1763 /* no need to shift raw little-endian data */
1765 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1770 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1774 switch (AccessLength
) { /* big-endian memory */
1775 case AccessLength_QUADWORD
:
1776 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1779 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1782 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1785 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1788 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1791 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1794 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1797 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
1799 case AccessLength_DOUBLEWORD
:
1800 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1802 case AccessLength_SEPTIBYTE
:
1803 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1805 case AccessLength_SEXTIBYTE
:
1806 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1808 case AccessLength_QUINTIBYTE
:
1809 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1811 case AccessLength_WORD
:
1812 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1814 case AccessLength_TRIPLEBYTE
:
1815 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1817 case AccessLength_HALFWORD
:
1818 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1820 case AccessLength_BYTE
:
1821 mem
[index
++] = (unsigned char)(MemElem
>> 56);
1825 index
+= (AccessLength
+ 1);
1826 switch (AccessLength
) { /* little-endian memory */
1827 case AccessLength_QUADWORD
:
1828 mem
[--index
] = (unsigned char)(MemElem1
>> 56);
1830 mem
[--index
] = (unsigned char)(MemElem1
>> 48);
1832 mem
[--index
] = (unsigned char)(MemElem1
>> 40);
1834 mem
[--index
] = (unsigned char)(MemElem1
>> 32);
1836 mem
[--index
] = (unsigned char)(MemElem1
>> 24);
1838 mem
[--index
] = (unsigned char)(MemElem1
>> 16);
1840 mem
[--index
] = (unsigned char)(MemElem1
>> 8);
1842 mem
[--index
] = (unsigned char)(MemElem1
>> 0);
1844 case AccessLength_DOUBLEWORD
:
1845 mem
[--index
] = (unsigned char)(MemElem
>> 56);
1846 case AccessLength_SEPTIBYTE
:
1847 mem
[--index
] = (unsigned char)(MemElem
>> 48);
1848 case AccessLength_SEXTIBYTE
:
1849 mem
[--index
] = (unsigned char)(MemElem
>> 40);
1850 case AccessLength_QUINTIBYTE
:
1851 mem
[--index
] = (unsigned char)(MemElem
>> 32);
1852 case AccessLength_WORD
:
1853 mem
[--index
] = (unsigned char)(MemElem
>> 24);
1854 case AccessLength_TRIPLEBYTE
:
1855 mem
[--index
] = (unsigned char)(MemElem
>> 16);
1856 case AccessLength_HALFWORD
:
1857 mem
[--index
] = (unsigned char)(MemElem
>> 8);
1858 case AccessLength_BYTE
:
1859 mem
[--index
] = (unsigned char)(MemElem
>> 0);
1871 ifetch32 (SIM_DESC sd
, address_word vaddr
)
1873 /* Copy the action of the LW instruction */
1874 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1875 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1878 unsigned32 instruction
;
1881 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1882 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1883 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1884 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1885 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1890 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1891 /* Order loads and stores to synchronise shared memory. Perform the
1892 action necessary to make the effects of groups of synchronizable
1893 loads and stores indicated by stype occur in the same order for all
1896 sync_operation(sd
,stype
)
1901 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1906 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1907 /* Signal an exception condition. This will result in an exception
1908 that aborts the instruction. The instruction operation pseudocode
1909 will never see a return from this function call. */
1912 signal_exception (SIM_DESC sd
, int exception
,...)
1917 sim_io_printf(sd
,"DBG: SignalException(%d) IPC = 0x%s\n",exception
,pr_addr(IPC
));
1920 /* Ensure that any active atomic read/modify/write operation will fail: */
1923 switch (exception
) {
1924 /* TODO: For testing purposes I have been ignoring TRAPs. In
1925 reality we should either simulate them, or allow the user to
1926 ignore them at run-time.
1929 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(IPC
));
1935 unsigned int instruction
;
1938 va_start(ap
,exception
);
1939 instruction
= va_arg(ap
,unsigned int);
1942 code
= (instruction
>> 6) & 0xFFFFF;
1944 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1945 code
, pr_addr(IPC
));
1949 case DebugBreakPoint
:
1950 if (! (Debug
& Debug_DM
))
1956 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1957 DEPC
= IPC
- 4; /* reference the branch instruction */
1961 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1965 Debug
|= Debug_DM
; /* in debugging mode */
1966 Debug
|= Debug_DBp
; /* raising a DBp exception */
1968 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
1972 case ReservedInstruction
:
1975 unsigned int instruction
;
1976 va_start(ap
,exception
);
1977 instruction
= va_arg(ap
,unsigned int);
1979 /* Provide simple monitor support using ReservedInstruction
1980 exceptions. The following code simulates the fixed vector
1981 entry points into the IDT monitor by causing a simulator
1982 trap, performing the monitor operation, and returning to
1983 the address held in the $ra register (standard PCS return
1984 address). This means we only need to pre-load the vector
1985 space with suitable instruction values. For systems were
1986 actual trap instructions are used, we would not need to
1987 perform this magic. */
1988 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
) {
1989 sim_monitor(sd
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1990 PC
= RA
; /* simulate the return from the vector entry */
1991 /* NOTE: This assumes that a branch-and-link style
1992 instruction was used to enter the vector (which is the
1993 case with the current IDT monitor). */
1994 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
1996 /* Look for the mips16 entry and exit instructions, and
1997 simulate a handler for them. */
1998 else if ((IPC
& 1) != 0
1999 && (instruction
& 0xf81f) == 0xe809
2000 && (instruction
& 0x0c0) != 0x0c0) {
2001 mips16_entry (instruction
);
2002 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
2003 } /* else fall through to normal exception processing */
2004 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction
,pr_addr(IPC
));
2009 sim_io_printf(sd
,"DBG: SignalException(%d) IPC = 0x%s\n",exception
,pr_addr(IPC
));
2011 /* Keep a copy of the current A0 in-case this is the program exit
2015 unsigned int instruction
;
2016 va_start(ap
,exception
);
2017 instruction
= va_arg(ap
,unsigned int);
2019 /* Check for our special terminating BREAK: */
2020 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
2021 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2022 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
2025 if (STATE
& simDELAYSLOT
)
2026 PC
= IPC
- 4; /* reference the branch instruction */
2029 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2030 sim_stopped
, SIGTRAP
);
2033 /* Store exception code into current exception id variable (used
2036 /* TODO: If not simulating exceptions then stop the simulator
2037 execution. At the moment we always stop the simulation. */
2039 /* See figure 5-17 for an outline of the code below */
2040 if (! (SR
& status_EXL
))
2042 CAUSE
= (exception
<< 2);
2043 if (STATE
& simDELAYSLOT
)
2045 STATE
&= ~simDELAYSLOT
;
2047 EPC
= (IPC
- 4); /* reference the branch instruction */
2051 /* FIXME: TLB et.al. */
2056 CAUSE
= (exception
<< 2);
2060 /* Store exception code into current exception id variable (used
2062 if (SR
& status_BEV
)
2063 PC
= (signed)0xBFC00200 + 0x180;
2065 PC
= (signed)0x80000000 + 0x180;
2067 switch ((CAUSE
>> 2) & 0x1F)
2070 /* Interrupts arrive during event processing, no need to
2074 case TLBModification
:
2079 case InstructionFetch
:
2081 /* The following is so that the simulator will continue from the
2082 exception address on breakpoint operations. */
2084 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2085 sim_stopped
, SIGBUS
);
2087 case ReservedInstruction
:
2088 case CoProcessorUnusable
:
2090 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2091 sim_stopped
, SIGILL
);
2093 case IntegerOverflow
:
2095 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2096 sim_stopped
, SIGFPE
);
2102 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2103 sim_stopped
, SIGTRAP
);
2107 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
2108 "FATAL: Should not encounter a breakpoint\n");
2110 default : /* Unknown internal exception */
2112 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
2113 sim_stopped
, SIGQUIT
);
2117 case SimulatorFault
:
2121 va_start(ap
,exception
);
2122 msg
= va_arg(ap
,char *);
2124 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
2125 "FATAL: Simulator error \"%s\"\n",msg
);
2132 #if defined(WARN_RESULT)
2133 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2134 /* This function indicates that the result of the operation is
2135 undefined. However, this should not affect the instruction
2136 stream. All that is meant to happen is that the destination
2137 register is set to an undefined result. To keep the simulator
2138 simple, we just don't bother updating the destination register, so
2139 the overall result will be undefined. If desired we can stop the
2140 simulator by raising a pseudo-exception. */
2144 sim_io_eprintf(sd
,"UndefinedResult: IPC = 0x%s\n",pr_addr(IPC
));
2145 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2150 #endif /* WARN_RESULT */
2153 cache_op(sd
,op
,pAddr
,vAddr
,instruction
)
2158 unsigned int instruction
;
2160 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2161 static int icache_warning
= 1;
2162 static int dcache_warning
= 1;
2164 static int icache_warning
= 0;
2165 static int dcache_warning
= 0;
2168 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2169 enable bit in the Status Register is clear - a coprocessor
2170 unusable exception is taken. */
2172 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC
));
2176 case 0: /* instruction cache */
2178 case 0: /* Index Invalidate */
2179 case 1: /* Index Load Tag */
2180 case 2: /* Index Store Tag */
2181 case 4: /* Hit Invalidate */
2183 case 6: /* Hit Writeback */
2184 if (!icache_warning
)
2186 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2192 SignalException(ReservedInstruction
,instruction
);
2197 case 1: /* data cache */
2199 case 0: /* Index Writeback Invalidate */
2200 case 1: /* Index Load Tag */
2201 case 2: /* Index Store Tag */
2202 case 3: /* Create Dirty */
2203 case 4: /* Hit Invalidate */
2204 case 5: /* Hit Writeback Invalidate */
2205 case 6: /* Hit Writeback */
2206 if (!dcache_warning
)
2208 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2214 SignalException(ReservedInstruction
,instruction
);
2219 default: /* unrecognised cache ID */
2220 SignalException(ReservedInstruction
,instruction
);
2227 /*-- FPU support routines ---------------------------------------------------*/
2229 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
2231 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2232 formats conform to ANSI/IEEE Std 754-1985. */
2233 /* SINGLE precision floating:
2234 * seeeeeeeefffffffffffffffffffffff
2236 * e = 8bits = exponent
2237 * f = 23bits = fraction
2239 /* SINGLE precision fixed:
2240 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2242 * i = 31bits = integer
2244 /* DOUBLE precision floating:
2245 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2247 * e = 11bits = exponent
2248 * f = 52bits = fraction
2250 /* DOUBLE precision fixed:
2251 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2253 * i = 63bits = integer
2256 /* Extract sign-bit: */
2257 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2258 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2259 /* Extract biased exponent: */
2260 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2261 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2262 /* Extract unbiased Exponent: */
2263 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2264 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2265 /* Extract complete fraction field: */
2266 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2267 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2268 /* Extract numbered fraction bit: */
2269 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2270 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2272 /* Explicit QNaN values used when value required: */
2273 #define FPQNaN_SINGLE (0x7FBFFFFF)
2274 #define FPQNaN_WORD (0x7FFFFFFF)
2275 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2276 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2278 /* Explicit Infinity values used when required: */
2279 #define FPINF_SINGLE (0x7F800000)
2280 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2282 #if 1 /* def DEBUG */
2283 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2284 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2288 value_fpr(sd
,fpr
,fmt
)
2296 /* Treat unused register values, as fixed-point 64bit values: */
2297 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2299 /* If request to read data as "uninterpreted", then use the current
2301 fmt
= FPR_STATE
[fpr
];
2306 /* For values not yet accessed, set to the desired format: */
2307 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2308 FPR_STATE
[fpr
] = fmt
;
2310 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2313 if (fmt
!= FPR_STATE
[fpr
]) {
2314 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(IPC
));
2315 FPR_STATE
[fpr
] = fmt_unknown
;
2318 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2319 /* Set QNaN value: */
2322 value
= FPQNaN_SINGLE
;
2326 value
= FPQNaN_DOUBLE
;
2330 value
= FPQNaN_WORD
;
2334 value
= FPQNaN_LONG
;
2341 } else if (SizeFGR() == 64) {
2345 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2348 case fmt_uninterpreted
:
2362 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2365 case fmt_uninterpreted
:
2368 if ((fpr
& 1) == 0) { /* even registers only */
2369 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2371 SignalException(ReservedInstruction
,0);
2382 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2385 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
2392 store_fpr(sd
,fpr
,fmt
,value
)
2401 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
2404 if (SizeFGR() == 64) {
2408 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2409 FPR_STATE
[fpr
] = fmt
;
2412 case fmt_uninterpreted
:
2416 FPR_STATE
[fpr
] = fmt
;
2420 FPR_STATE
[fpr
] = fmt_unknown
;
2428 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2429 FPR_STATE
[fpr
] = fmt
;
2432 case fmt_uninterpreted
:
2435 if ((fpr
& 1) == 0) { /* even register number only */
2436 FGR
[fpr
+1] = (value
>> 32);
2437 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2438 FPR_STATE
[fpr
+ 1] = fmt
;
2439 FPR_STATE
[fpr
] = fmt
;
2441 FPR_STATE
[fpr
] = fmt_unknown
;
2442 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2443 SignalException(ReservedInstruction
,0);
2448 FPR_STATE
[fpr
] = fmt_unknown
;
2453 #if defined(WARN_RESULT)
2456 #endif /* WARN_RESULT */
2459 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2462 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2475 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
2476 know that the exponent field is biased... we we cheat and avoid
2477 removing the bias value. */
2480 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) != 0));
2481 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2482 dealing with a SNaN or QNaN */
2485 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) != 0));
2486 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2487 dealing with a SNaN or QNaN */
2490 boolean
= (op
== FPQNaN_WORD
);
2493 boolean
= (op
== FPQNaN_LONG
);
2496 fprintf (stderr
, "Bad switch\n");
2501 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2515 printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt
),pr_addr(op
),pr_addr(IPC
));
2518 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
2519 know that the exponent field is biased... we we cheat and avoid
2520 removing the bias value. */
2523 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) == 0));
2526 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) == 0));
2529 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2534 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2548 /* Argument checking already performed by the FPCOMPARE code */
2551 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2554 /* The format type should already have been checked: */
2558 unsigned int wop1
= (unsigned int)op1
;
2559 unsigned int wop2
= (unsigned int)op2
;
2560 boolean
= (*(float *)&wop1
< *(float *)&wop2
);
2564 boolean
= (*(double *)&op1
< *(double *)&op2
);
2567 fprintf (stderr
, "Bad switch\n");
2572 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2586 /* Argument checking already performed by the FPCOMPARE code */
2589 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2592 /* The format type should already have been checked: */
2595 boolean
= ((op1
& 0xFFFFFFFF) == (op2
& 0xFFFFFFFF));
2598 boolean
= (op1
== op2
);
2601 fprintf (stderr
, "Bad switch\n");
2606 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2613 AbsoluteValue(op
,fmt
)
2620 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2623 /* The format type should already have been checked: */
2627 unsigned int wop
= (unsigned int)op
;
2628 float tmp
= ((float)fabs((double)*(float *)&wop
));
2629 result
= (uword64
)*(unsigned int *)&tmp
;
2634 double tmp
= (fabs(*(double *)&op
));
2635 result
= *(uword64
*)&tmp
;
2638 fprintf (stderr
, "Bad switch\n");
2653 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2656 /* The format type should already have been checked: */
2660 unsigned int wop
= (unsigned int)op
;
2661 float tmp
= ((float)0.0 - *(float *)&wop
);
2662 result
= (uword64
)*(unsigned int *)&tmp
;
2667 double tmp
= ((double)0.0 - *(double *)&op
);
2668 result
= *(uword64
*)&tmp
;
2672 fprintf (stderr
, "Bad switch\n");
2688 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2691 /* The registers must specify FPRs valid for operands of type
2692 "fmt". If they are not valid, the result is undefined. */
2694 /* The format type should already have been checked: */
2698 unsigned int wop1
= (unsigned int)op1
;
2699 unsigned int wop2
= (unsigned int)op2
;
2700 float tmp
= (*(float *)&wop1
+ *(float *)&wop2
);
2701 result
= (uword64
)*(unsigned int *)&tmp
;
2706 double tmp
= (*(double *)&op1
+ *(double *)&op2
);
2707 result
= *(uword64
*)&tmp
;
2711 fprintf (stderr
, "Bad switch\n");
2716 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2731 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2734 /* The registers must specify FPRs valid for operands of type
2735 "fmt". If they are not valid, the result is undefined. */
2737 /* The format type should already have been checked: */
2741 unsigned int wop1
= (unsigned int)op1
;
2742 unsigned int wop2
= (unsigned int)op2
;
2743 float tmp
= (*(float *)&wop1
- *(float *)&wop2
);
2744 result
= (uword64
)*(unsigned int *)&tmp
;
2749 double tmp
= (*(double *)&op1
- *(double *)&op2
);
2750 result
= *(uword64
*)&tmp
;
2754 fprintf (stderr
, "Bad switch\n");
2759 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2766 Multiply(op1
,op2
,fmt
)
2774 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2777 /* The registers must specify FPRs valid for operands of type
2778 "fmt". If they are not valid, the result is undefined. */
2780 /* The format type should already have been checked: */
2784 unsigned int wop1
= (unsigned int)op1
;
2785 unsigned int wop2
= (unsigned int)op2
;
2786 float tmp
= (*(float *)&wop1
* *(float *)&wop2
);
2787 result
= (uword64
)*(unsigned int *)&tmp
;
2792 double tmp
= (*(double *)&op1
* *(double *)&op2
);
2793 result
= *(uword64
*)&tmp
;
2797 fprintf (stderr
, "Bad switch\n");
2802 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2817 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2820 /* The registers must specify FPRs valid for operands of type
2821 "fmt". If they are not valid, the result is undefined. */
2823 /* The format type should already have been checked: */
2827 unsigned int wop1
= (unsigned int)op1
;
2828 unsigned int wop2
= (unsigned int)op2
;
2829 float tmp
= (*(float *)&wop1
/ *(float *)&wop2
);
2830 result
= (uword64
)*(unsigned int *)&tmp
;
2835 double tmp
= (*(double *)&op1
/ *(double *)&op2
);
2836 result
= *(uword64
*)&tmp
;
2840 fprintf (stderr
, "Bad switch\n");
2845 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2859 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2862 /* The registers must specify FPRs valid for operands of type
2863 "fmt". If they are not valid, the result is undefined. */
2865 /* The format type should already have been checked: */
2869 unsigned int wop
= (unsigned int)op
;
2870 float tmp
= ((float)1.0 / *(float *)&wop
);
2871 result
= (uword64
)*(unsigned int *)&tmp
;
2876 double tmp
= ((double)1.0 / *(double *)&op
);
2877 result
= *(uword64
*)&tmp
;
2881 fprintf (stderr
, "Bad switch\n");
2886 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2900 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2903 /* The registers must specify FPRs valid for operands of type
2904 "fmt". If they are not valid, the result is undefined. */
2906 /* The format type should already have been checked: */
2910 unsigned int wop
= (unsigned int)op
;
2912 float tmp
= ((float)sqrt((double)*(float *)&wop
));
2913 result
= (uword64
)*(unsigned int *)&tmp
;
2915 /* TODO: Provide square-root */
2916 result
= (uword64
)0;
2923 double tmp
= (sqrt(*(double *)&op
));
2924 result
= *(uword64
*)&tmp
;
2926 /* TODO: Provide square-root */
2927 result
= (uword64
)0;
2932 fprintf (stderr
, "Bad switch\n");
2937 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2944 convert(sd
,rm
,op
,from
,to
)
2954 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2957 /* The value "op" is converted to the destination format, rounding
2958 using mode "rm". When the destination is a fixed-point format,
2959 then a source value of Infinity, NaN or one which would round to
2960 an integer outside the fixed point range then an IEEE Invalid
2961 Operation condition is raised. */
2968 tmp
= (float)(*(double *)&op
);
2972 tmp
= (float)((int)(op
& 0xFFFFFFFF));
2976 tmp
= (float)((word64
)op
);
2979 fprintf (stderr
, "Bad switch\n");
2984 /* FIXME: This code is incorrect. The rounding mode does not
2985 round to integral values; it rounds to the nearest
2986 representable value in the format. */
2990 /* Round result to nearest representable value. When two
2991 representable values are equally near, round to the value
2992 that has a least significant bit of zero (i.e. is even). */
2994 tmp
= (float)anint((double)tmp
);
2996 /* TODO: Provide round-to-nearest */
3001 /* Round result to the value closest to, and not greater in
3002 magnitude than, the result. */
3004 tmp
= (float)aint((double)tmp
);
3006 /* TODO: Provide round-to-zero */
3011 /* Round result to the value closest to, and not less than,
3013 tmp
= (float)ceil((double)tmp
);
3017 /* Round result to the value closest to, and not greater than,
3019 tmp
= (float)floor((double)tmp
);
3024 result
= (uword64
)*(unsigned int *)&tmp
;
3036 unsigned int wop
= (unsigned int)op
;
3037 tmp
= (double)(*(float *)&wop
);
3042 xxx
= SIGNEXTEND((op
& 0xFFFFFFFF),32);
3047 tmp
= (double)((word64
)op
);
3051 fprintf (stderr
, "Bad switch\n");
3056 /* FIXME: This code is incorrect. The rounding mode does not
3057 round to integral values; it rounds to the nearest
3058 representable value in the format. */
3063 tmp
= anint(*(double *)&tmp
);
3065 /* TODO: Provide round-to-nearest */
3071 tmp
= aint(*(double *)&tmp
);
3073 /* TODO: Provide round-to-zero */
3078 tmp
= ceil(*(double *)&tmp
);
3082 tmp
= floor(*(double *)&tmp
);
3087 result
= *(uword64
*)&tmp
;
3093 if (Infinity(op
,from
) || NaN(op
,from
) || (1 == 0/*TODO: check range */)) {
3094 printf("DBG: TODO: update FCSR\n");
3095 SignalExceptionFPE ();
3097 if (to
== fmt_word
) {
3102 unsigned int wop
= (unsigned int)op
;
3103 tmp
= (int)*((float *)&wop
);
3107 tmp
= (int)*((double *)&op
);
3109 printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op
),pr_addr(op
),tmp
);
3113 fprintf (stderr
, "Bad switch\n");
3116 result
= (uword64
)tmp
;
3117 } else { /* fmt_long */
3122 unsigned int wop
= (unsigned int)op
;
3123 tmp
= (word64
)*((float *)&wop
);
3127 tmp
= (word64
)*((double *)&op
);
3130 fprintf (stderr
, "Bad switch\n");
3133 result
= (uword64
)tmp
;
3138 fprintf (stderr
, "Bad switch\n");
3143 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result
),DOFMT(to
));
3150 /*-- co-processor support routines ------------------------------------------*/
3153 CoProcPresent(coproc_number
)
3154 unsigned int coproc_number
;
3156 /* Return TRUE if simulator provides a model for the given co-processor number */
3161 cop_lw(sd
,coproc_num
,coproc_reg
,memword
)
3163 int coproc_num
, coproc_reg
;
3164 unsigned int memword
;
3166 switch (coproc_num
) {
3170 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3172 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3173 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3178 #if 0 /* this should be controlled by a configuration option */
3179 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(IPC
));
3188 cop_ld(sd
,coproc_num
,coproc_reg
,memword
)
3190 int coproc_num
, coproc_reg
;
3193 switch (coproc_num
) {
3196 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3201 #if 0 /* this message should be controlled by a configuration option */
3202 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(IPC
));
3211 cop_sw(sd
,coproc_num
,coproc_reg
)
3213 int coproc_num
, coproc_reg
;
3215 unsigned int value
= 0;
3217 switch (coproc_num
) {
3223 hold
= FPR_STATE
[coproc_reg
];
3224 FPR_STATE
[coproc_reg
] = fmt_word
;
3225 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3226 FPR_STATE
[coproc_reg
] = hold
;
3230 value
= (unsigned int)ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
3233 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE
[coproc_reg
]));
3235 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
3242 #if 0 /* should be controlled by configuration option */
3243 sim_io_printf(sd
,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
3252 cop_sd(sd
,coproc_num
,coproc_reg
)
3254 int coproc_num
, coproc_reg
;
3257 switch (coproc_num
) {
3261 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3264 value
= ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
3267 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE
[coproc_reg
]));
3269 value
= ValueFPR(coproc_reg
,fmt_double
);
3276 #if 0 /* should be controlled by configuration option */
3277 sim_io_printf(sd
,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
3286 decode_coproc(sd
,instruction
)
3288 unsigned int instruction
;
3290 int coprocnum
= ((instruction
>> 26) & 3);
3294 case 0: /* standard CPU control and cache registers */
3296 int code
= ((instruction
>> 21) & 0x1F);
3297 /* R4000 Users Manual (second edition) lists the following CP0
3299 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3300 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3301 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3302 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3303 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3304 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3305 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3306 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3307 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3308 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3310 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3312 int rt
= ((instruction
>> 16) & 0x1F);
3313 int rd
= ((instruction
>> 11) & 0x1F);
3315 switch (rd
) /* NOTEs: Standard CP0 registers */
3317 /* 0 = Index R4000 VR4100 VR4300 */
3318 /* 1 = Random R4000 VR4100 VR4300 */
3319 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3320 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3321 /* 4 = Context R4000 VR4100 VR4300 */
3322 /* 5 = PageMask R4000 VR4100 VR4300 */
3323 /* 6 = Wired R4000 VR4100 VR4300 */
3324 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3325 /* 9 = Count R4000 VR4100 VR4300 */
3326 /* 10 = EntryHi R4000 VR4100 VR4300 */
3327 /* 11 = Compare R4000 VR4100 VR4300 */
3328 /* 12 = SR R4000 VR4100 VR4300 */
3335 /* 13 = Cause R4000 VR4100 VR4300 */
3342 /* 14 = EPC R4000 VR4100 VR4300 */
3343 /* 15 = PRId R4000 VR4100 VR4300 */
3344 #ifdef SUBTARGET_R3900
3353 /* 16 = Config R4000 VR4100 VR4300 */
3355 #ifdef SUBTARGET_R3900
3364 /* 17 = LLAddr R4000 VR4100 VR4300 */
3366 /* 18 = WatchLo R4000 VR4100 VR4300 */
3367 /* 19 = WatchHi R4000 VR4100 VR4300 */
3368 /* 20 = XContext R4000 VR4100 VR4300 */
3369 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3370 /* 27 = CacheErr R4000 VR4100 */
3371 /* 28 = TagLo R4000 VR4100 VR4300 */
3372 /* 29 = TagHi R4000 VR4100 VR4300 */
3373 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3374 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3375 /* CPR[0,rd] = GPR[rt]; */
3378 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3380 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3383 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3386 if (SR
& status_ERL
)
3388 /* Oops, not yet available */
3389 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3399 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3403 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3411 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction
,pr_addr(IPC
));
3412 /* TODO: When executing an ERET or RFE instruction we should
3413 clear LLBIT, to ensure that any out-standing atomic
3414 read/modify/write sequence fails. */
3418 case 2: /* undefined co-processor */
3419 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction
,pr_addr(IPC
));
3422 case 1: /* should not occur (FPU co-processor) */
3423 case 3: /* should not occur (FPU co-processor) */
3424 SignalException(ReservedInstruction
,instruction
);
3431 /*-- instruction simulation -------------------------------------------------*/
3433 /* When the IGEN simulator is being built, the function below is be
3434 replaced by a generated version. However, WITH_IGEN == 2 indicates
3435 that the fubction below should be compiled but under a different
3436 name (to allow backward compatibility) */
3438 #if (WITH_IGEN != 1)
3440 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3442 old_engine_run (sd
, next_cpu_nr
, siggnal
)
3445 sim_engine_run (sd
, next_cpu_nr
, siggnal
)
3448 int next_cpu_nr
; /* ignore */
3449 int siggnal
; /* ignore */
3451 #if !defined(FASTSIM)
3452 unsigned int pipeline_count
= 1;
3456 if (STATE_MEMORY (sd
) == NULL
) {
3457 printf("DBG: simulate() entered with no memory\n");
3462 #if 0 /* Disabled to check that everything works OK */
3463 /* The VR4300 seems to sign-extend the PC on its first
3464 access. However, this may just be because it is currently
3465 configured in 32bit mode. However... */
3466 PC
= SIGNEXTEND(PC
,32);
3469 /* main controlling loop */
3471 /* Fetch the next instruction from the simulator memory: */
3472 address_word vaddr
= (uword64
)PC
;
3475 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3479 printf("DBG: state = 0x%08X :",state
);
3480 if (state
& simHALTEX
) printf(" simHALTEX");
3481 if (state
& simHALTIN
) printf(" simHALTIN");
3486 DSSTATE
= (STATE
& simDELAYSLOT
);
3489 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3492 if (AddressTranslation(PC
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3493 if ((vaddr
& 1) == 0) {
3494 /* Copy the action of the LW instruction */
3495 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3496 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3499 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3500 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3501 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3502 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3504 /* Copy the action of the LH instruction */
3505 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3506 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3509 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3510 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3511 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3512 paddr
& ~ (uword64
) 1,
3513 vaddr
, isINSTRUCTION
, isREAL
);
3514 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3515 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3518 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3523 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3526 IPC
= PC
; /* copy PC for this instruction */
3527 /* This is required by exception processing, to ensure that we can
3528 cope with exceptions in the delay slots of branches that may
3529 already have changed the PC. */
3530 if ((vaddr
& 1) == 0)
3531 PC
+= 4; /* increment ready for the next fetch */
3534 /* NOTE: If we perform a delay slot change to the PC, this
3535 increment is not requuired. However, it would make the
3536 simulator more complicated to try and avoid this small hit. */
3538 /* Currently this code provides a simple model. For more
3539 complicated models we could perform exception status checks at
3540 this point, and set the simSTOP state as required. This could
3541 also include processing any hardware interrupts raised by any
3542 I/O model attached to the simulator context.
3544 Support for "asynchronous" I/O events within the simulated world
3545 could be providing by managing a counter, and calling a I/O
3546 specific handler when a particular threshold is reached. On most
3547 architectures a decrement and check for zero operation is
3548 usually quicker than an increment and compare. However, the
3549 process of managing a known value decrement to zero, is higher
3550 than the cost of using an explicit value UINT_MAX into the
3551 future. Which system is used will depend on how complicated the
3552 I/O model is, and how much it is likely to affect the simulator
3555 If events need to be scheduled further in the future than
3556 UINT_MAX event ticks, then the I/O model should just provide its
3557 own counter, triggered from the event system. */
3559 /* MIPS pipeline ticks. To allow for future support where the
3560 pipeline hit of individual instructions is known, this control
3561 loop manages a "pipeline_count" variable. It is initialised to
3562 1 (one), and will only be changed by the simulator engine when
3563 executing an instruction. If the engine does not have access to
3564 pipeline cycle count information then all instructions will be
3565 treated as using a single cycle. NOTE: A standard system is not
3566 provided by the default simulator because different MIPS
3567 architectures have different cycle counts for the same
3570 [NOTE: pipeline_count has been replaced the event queue] */
3573 /* Set previous flag, depending on current: */
3574 if (STATE
& simPCOC0
)
3578 /* and update the current value: */
3585 /* NOTE: For multi-context simulation environments the "instruction"
3586 variable should be local to this routine. */
3588 /* Shorthand accesses for engine. Note: If we wanted to use global
3589 variables (and a single-threaded simulator engine), then we can
3590 create the actual variables with these names. */
3592 if (!(STATE
& simSKIPNEXT
)) {
3593 /* Include the simulator engine */
3594 #include "oengine.c"
3595 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3596 #error "Mismatch between run-time simulator code and simulation engine"
3598 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3599 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3601 #if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU))
3602 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3605 #if defined(WARN_LOHI)
3606 /* Decrement the HI/LO validity ticks */
3611 /* start-sanitize-r5900 */
3616 /* end-sanitize-r5900 */
3617 #endif /* WARN_LOHI */
3619 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3620 should check for it being changed. It is better doing it here,
3621 than within the simulator, since it will help keep the simulator
3624 #if defined(WARN_ZERO)
3625 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(IPC
));
3626 #endif /* WARN_ZERO */
3627 ZERO
= 0; /* reset back to zero before next instruction */
3629 } else /* simSKIPNEXT check */
3630 STATE
&= ~simSKIPNEXT
;
3632 /* If the delay slot was active before the instruction is
3633 executed, then update the PC to its new value: */
3636 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3642 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3643 /* Deal with pending register updates: */
3645 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3647 if (PENDING_OUT
!= PENDING_IN
) {
3649 int index
= PENDING_OUT
;
3650 int total
= PENDING_TOTAL
;
3651 if (PENDING_TOTAL
== 0) {
3652 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3655 for (loop
= 0; (loop
< total
); loop
++) {
3657 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3659 if (PENDING_SLOT_REG
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3661 printf("pending_slot_count[%d] = %d\n",index
,PENDING_SLOT_COUNT
[index
]);
3663 if (--(PENDING_SLOT_COUNT
[index
]) == 0) {
3665 printf("pending_slot_reg[%d] = %d\n",index
,PENDING_SLOT_REG
[index
]);
3666 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(PENDING_SLOT_VALUE
[index
]));
3668 if (PENDING_SLOT_REG
[index
] == COCIDX
) {
3670 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3675 REGISTERS
[PENDING_SLOT_REG
[index
]] = PENDING_SLOT_VALUE
[index
];
3677 /* The only time we have PENDING updates to FPU
3678 registers, is when performing binary transfers. This
3679 means we should update the register type field. */
3680 if ((PENDING_SLOT_REG
[index
] >= FGRIDX
) && (PENDING_SLOT_REG
[index
] < (FGRIDX
+ 32)))
3681 FPR_STATE
[PENDING_SLOT_REG
[index
] - FGRIDX
] = fmt_uninterpreted
;
3685 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG
[index
],pr_addr(REGISTERS
[PENDING_SLOT_REG
[index
]]));
3687 PENDING_SLOT_REG
[index
] = (LAST_EMBED_REGNUM
+ 1);
3689 if (PENDING_OUT
== PSLOTS
)
3695 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3698 if (index
== PSLOTS
)
3703 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN
,PENDING_OUT
,PENDING_TOTAL
);
3707 #if !defined(FASTSIM)
3708 if (sim_events_tickn (sd
, pipeline_count
))
3710 /* cpu->cia = cia; */
3711 sim_events_process (sd
);
3714 if (sim_events_tick (sd
))
3716 /* cpu->cia = cia; */
3717 sim_events_process (sd
);
3719 #endif /* FASTSIM */
3725 /* This code copied from gdb's utils.c. Would like to share this code,
3726 but don't know of a common place where both could get to it. */
3728 /* Temporary storage using circular buffer */
3734 static char buf
[NUMCELLS
][CELLSIZE
];
3736 if (++cell
>=NUMCELLS
) cell
=0;
3740 /* Print routines to handle variable size regs, etc */
3742 /* Eliminate warning from compiler on 32-bit systems */
3743 static int thirty_two
= 32;
3749 char *paddr_str
=get_cell();
3750 switch (sizeof(addr
))
3753 sprintf(paddr_str
,"%08lx%08lx",
3754 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3757 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3760 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3763 sprintf(paddr_str
,"%x",addr
);
3772 char *paddr_str
=get_cell();
3773 sprintf(paddr_str
,"%08lx%08lx",
3774 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3779 /*---------------------------------------------------------------------------*/
3780 /*> EOF interp.c <*/