2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 /* The TRACE manifests enable the provision of extra features. If they
26 are not defined then a simpler (quicker) simulator is constructed
27 without the required run-time checks, etc. */
28 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
35 #include "sim-utils.h"
36 #include "sim-options.h"
37 #include "sim-assert.h"
63 #include "libiberty.h"
65 #include "gdb/callback.h" /* GDB simulator callback interface */
66 #include "gdb/remote-sim.h" /* GDB simulator interface */
68 char* pr_addr (SIM_ADDR addr
);
69 char* pr_uword64 (uword64 addr
);
72 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
77 /* The following reserved instruction value is used when a simulator
78 trap is required. NOTE: Care must be taken, since this value may be
79 used in later revisions of the MIPS ISA. */
81 #define RSVD_INSTRUCTION (0x00000005)
82 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
84 #define RSVD_INSTRUCTION_ARG_SHIFT 6
85 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
88 /* Bits in the Debug register */
89 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
90 #define Debug_DM 0x40000000 /* Debug Mode */
91 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
93 /*---------------------------------------------------------------------------*/
94 /*-- GDB simulator interface ------------------------------------------------*/
95 /*---------------------------------------------------------------------------*/
97 static void ColdReset (SIM_DESC sd
);
99 /*---------------------------------------------------------------------------*/
103 #define DELAYSLOT() {\
104 if (STATE & simDELAYSLOT)\
105 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
106 STATE |= simDELAYSLOT;\
109 #define JALDELAYSLOT() {\
111 STATE |= simJALDELAYSLOT;\
115 STATE &= ~simDELAYSLOT;\
116 STATE |= simSKIPNEXT;\
119 #define CANCELDELAYSLOT() {\
121 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
124 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
125 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
127 /* Note that the monitor code essentially assumes this layout of memory.
128 If you change these, change the monitor code, too. */
129 /* FIXME Currently addresses are truncated to 32-bits, see
130 mips/sim-main.c:address_translation(). If that changes, then these
131 values will need to be extended, and tested for more carefully. */
132 #define K0BASE (0x80000000)
133 #define K0SIZE (0x20000000)
134 #define K1BASE (0xA0000000)
135 #define K1SIZE (0x20000000)
137 /* Simple run-time monitor support.
139 We emulate the monitor by placing magic reserved instructions at
140 the monitor's entry points; when we hit these instructions, instead
141 of raising an exception (as we would normally), we look at the
142 instruction and perform the appropriate monitory operation.
144 `*_monitor_base' are the physical addresses at which the corresponding
145 monitor vectors are located. `0' means none. By default,
147 The RSVD_INSTRUCTION... macros specify the magic instructions we
148 use at the monitor entry points. */
149 static int firmware_option_p
= 0;
150 static SIM_ADDR idt_monitor_base
= 0xBFC00000;
151 static SIM_ADDR pmon_monitor_base
= 0xBFC00500;
152 static SIM_ADDR lsipmon_monitor_base
= 0xBFC00200;
154 static SIM_RC
sim_firmware_command (SIM_DESC sd
, char* arg
);
157 #define MEM_SIZE (8 << 20) /* 8 MBytes */
161 static char *tracefile
= "trace.din"; /* default filename for trace log */
162 FILE *tracefh
= NULL
;
163 static void open_trace (SIM_DESC sd
);
166 static const char * get_insn_name (sim_cpu
*, int);
168 /* simulation target board. NULL=canonical */
169 static char* board
= NULL
;
172 static DECLARE_OPTION_HANDLER (mips_option_handler
);
175 OPTION_DINERO_TRACE
= OPTION_START
,
182 static int display_mem_info
= 0;
185 mips_option_handler (SIM_DESC sd
, sim_cpu
*cpu
, int opt
, char *arg
,
191 case OPTION_DINERO_TRACE
: /* ??? */
193 /* Eventually the simTRACE flag could be treated as a toggle, to
194 allow external control of the program points being traced
195 (i.e. only from main onwards, excluding the run-time setup,
197 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
199 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
202 else if (strcmp (arg
, "yes") == 0)
204 else if (strcmp (arg
, "no") == 0)
206 else if (strcmp (arg
, "on") == 0)
208 else if (strcmp (arg
, "off") == 0)
212 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
219 Simulator constructed without dinero tracing support (for performance).\n\
220 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
224 case OPTION_DINERO_FILE
:
226 if (optarg
!= NULL
) {
228 tmp
= (char *)malloc(strlen(optarg
) + 1);
231 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
237 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
243 case OPTION_FIRMWARE
:
244 return sim_firmware_command (sd
, arg
);
250 board
= zalloc(strlen(arg
) + 1);
256 case OPTION_INFO_MEMORY
:
257 display_mem_info
= 1;
265 static const OPTION mips_options
[] =
267 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
268 '\0', "on|off", "Enable dinero tracing",
269 mips_option_handler
},
270 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
271 '\0', "FILE", "Write dinero trace to FILE",
272 mips_option_handler
},
273 { {"firmware", required_argument
, NULL
, OPTION_FIRMWARE
},
274 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
275 mips_option_handler
},
276 { {"board", required_argument
, NULL
, OPTION_BOARD
},
277 '\0', "none" /* rely on compile-time string concatenation for other options */
279 #define BOARD_JMR3904 "jmr3904"
281 #define BOARD_JMR3904_PAL "jmr3904pal"
282 "|" BOARD_JMR3904_PAL
283 #define BOARD_JMR3904_DEBUG "jmr3904debug"
284 "|" BOARD_JMR3904_DEBUG
285 #define BOARD_BSP "bsp"
288 , "Customize simulation for a particular board.", mips_option_handler
},
290 /* These next two options have the same names as ones found in the
291 memory_options[] array in common/sim-memopt.c. This is because
292 the intention is to provide an alternative handler for those two
293 options. We need an alternative handler because the memory
294 regions are not set up until after the command line arguments
295 have been parsed, and so we cannot display the memory info whilst
296 processing the command line. There is a hack in sim_open to
297 remove these handlers when we want the real --memory-info option
299 { { "info-memory", no_argument
, NULL
, OPTION_INFO_MEMORY
},
300 '\0', NULL
, "List configured memory regions", mips_option_handler
},
301 { { "memory-info", no_argument
, NULL
, OPTION_INFO_MEMORY
},
302 '\0', NULL
, NULL
, mips_option_handler
},
304 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
308 int interrupt_pending
;
311 interrupt_event (SIM_DESC sd
, void *data
)
313 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
314 address_word cia
= CPU_PC_GET (cpu
);
317 interrupt_pending
= 0;
318 SignalExceptionInterrupt (1); /* interrupt "1" */
320 else if (!interrupt_pending
)
321 sim_events_schedule (sd
, 1, interrupt_event
, data
);
325 /*---------------------------------------------------------------------------*/
326 /*-- Device registration hook -----------------------------------------------*/
327 /*---------------------------------------------------------------------------*/
328 static void device_init(SIM_DESC sd
) {
330 extern void register_devices(SIM_DESC
);
331 register_devices(sd
);
335 /*---------------------------------------------------------------------------*/
336 /*-- GDB simulator interface ------------------------------------------------*/
337 /*---------------------------------------------------------------------------*/
340 mips_pc_get (sim_cpu
*cpu
)
346 mips_pc_set (sim_cpu
*cpu
, sim_cia pc
)
352 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
355 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
358 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
360 /* The cpu data is kept in a separately allocated chunk of memory. */
361 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
364 cpu
= STATE_CPU (sd
, 0); /* FIXME */
366 /* FIXME: watchpoints code shouldn't need this */
367 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
368 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
369 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
371 /* Initialize the mechanism for doing insn profiling. */
372 CPU_INSN_NAME (cpu
) = get_insn_name
;
373 CPU_MAX_INSNS (cpu
) = nr_itable_entries
;
377 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
379 sim_add_option_table (sd
, NULL
, mips_options
);
382 /* getopt will print the error message so we just have to exit if this fails.
383 FIXME: Hmmm... in the case of gdb we need getopt to call
385 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
387 /* Uninstall the modules to avoid memory leaks,
388 file descriptor leaks, etc. */
389 sim_module_uninstall (sd
);
393 /* handle board-specific memory maps */
396 /* Allocate core managed memory */
397 sim_memopt
*entry
, *match
= NULL
;
398 address_word mem_size
= 0;
401 /* For compatibility with the old code - under this (at level one)
402 are the kernel spaces K0 & K1. Both of these map to a single
403 smaller sub region */
404 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
406 /* Look for largest memory region defined on command-line at
408 #ifdef SIM_HAVE_FLATMEM
409 mem_size
= STATE_MEM_SIZE (sd
);
411 for (entry
= STATE_MEMOPT (sd
); entry
!= NULL
; entry
= entry
->next
)
413 /* If we find an entry at address 0, then we will end up
414 allocating a new buffer in the "memory alias" command
415 below. The region at address 0 will be deleted. */
416 address_word size
= (entry
->modulo
!= 0
417 ? entry
->modulo
: entry
->nr_bytes
);
419 && (!match
|| entry
->level
< match
->level
))
421 else if (entry
->addr
== K0BASE
|| entry
->addr
== K1BASE
)
426 for (alias
= entry
->alias
; alias
!= NULL
; alias
= alias
->next
)
429 && (!match
|| entry
->level
< match
->level
))
431 else if (alias
->addr
== K0BASE
|| alias
->addr
== K1BASE
)
441 /* Get existing memory region size. */
442 mem_size
= (match
->modulo
!= 0
443 ? match
->modulo
: match
->nr_bytes
);
444 /* Delete old region. */
445 sim_do_commandf (sd
, "memory delete %d:0x%lx@%d",
446 match
->space
, match
->addr
, match
->level
);
448 else if (mem_size
== 0)
450 /* Limit to KSEG1 size (512MB) */
451 if (mem_size
> K1SIZE
)
453 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
454 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
455 K1BASE
, K1SIZE
, (long)mem_size
, K0BASE
);
460 else if (board
!= NULL
461 && (strcmp(board
, BOARD_BSP
) == 0))
465 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
467 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
468 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
470 4 * 1024 * 1024, /* 4 MB */
473 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
474 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
476 4 * 1024 * 1024, /* 4 MB */
479 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
480 for (i
=0; i
<8; i
++) /* 32 MB total */
482 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
483 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
484 0x88000000 + (i
* size
),
486 0xA8000000 + (i
* size
));
490 else if (board
!= NULL
491 && (strcmp(board
, BOARD_JMR3904
) == 0 ||
492 strcmp(board
, BOARD_JMR3904_PAL
) == 0 ||
493 strcmp(board
, BOARD_JMR3904_DEBUG
) == 0))
495 /* match VIRTUAL memory layout of JMR-TX3904 board */
498 /* --- disable monitor unless forced on by user --- */
500 if (! firmware_option_p
)
502 idt_monitor_base
= 0;
503 pmon_monitor_base
= 0;
504 lsipmon_monitor_base
= 0;
507 /* --- environment --- */
509 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
513 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
514 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
516 4 * 1024 * 1024, /* 4 MB */
519 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
520 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
522 4 * 1024 * 1024, /* 4 MB */
525 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
526 for (i
=0; i
<8; i
++) /* 32 MB total */
528 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
529 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
530 0x88000000 + (i
* size
),
532 0xA8000000 + (i
* size
));
535 /* Dummy memory regions for unsimulated devices - sorted by address */
537 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
538 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
539 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
540 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
541 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
542 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
543 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
544 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
545 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
548 /* --- simulated devices --- */
549 sim_hw_parse (sd
, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
550 sim_hw_parse (sd
, "/tx3904cpu");
551 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
552 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
553 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
554 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
556 /* FIXME: poking at dv-sockser internals, use tcp backend if
557 --sockser_addr option was given.*/
558 extern char* sockser_addr
;
559 if(sockser_addr
== NULL
)
560 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend stdio");
562 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend tcp");
564 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
565 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/backend stdio");
567 /* -- device connections --- */
568 sim_hw_parse (sd
, "/tx3904irc > ip level /tx3904cpu");
569 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
570 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
571 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
572 sim_hw_parse (sd
, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
573 sim_hw_parse (sd
, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
575 /* add PAL timer & I/O module */
576 if(! strcmp(board
, BOARD_JMR3904_PAL
))
579 sim_hw_parse (sd
, "/pal@0xffff0000");
580 sim_hw_parse (sd
, "/pal@0xffff0000/reg 0xffff0000 64");
582 /* wire up interrupt ports to irc */
583 sim_hw_parse (sd
, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
584 sim_hw_parse (sd
, "/pal@0x31000000 > timer tmr1 /tx3904irc");
585 sim_hw_parse (sd
, "/pal@0x31000000 > int int0 /tx3904irc");
588 if(! strcmp(board
, BOARD_JMR3904_DEBUG
))
590 /* -- DEBUG: glue interrupt generators --- */
591 sim_hw_parse (sd
, "/glue@0xffff0000/reg 0xffff0000 0x50");
592 sim_hw_parse (sd
, "/glue@0xffff0000 > int0 int0 /tx3904irc");
593 sim_hw_parse (sd
, "/glue@0xffff0000 > int1 int1 /tx3904irc");
594 sim_hw_parse (sd
, "/glue@0xffff0000 > int2 int2 /tx3904irc");
595 sim_hw_parse (sd
, "/glue@0xffff0000 > int3 int3 /tx3904irc");
596 sim_hw_parse (sd
, "/glue@0xffff0000 > int4 int4 /tx3904irc");
597 sim_hw_parse (sd
, "/glue@0xffff0000 > int5 int5 /tx3904irc");
598 sim_hw_parse (sd
, "/glue@0xffff0000 > int6 int6 /tx3904irc");
599 sim_hw_parse (sd
, "/glue@0xffff0000 > int7 int7 /tx3904irc");
600 sim_hw_parse (sd
, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
601 sim_hw_parse (sd
, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
602 sim_hw_parse (sd
, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
603 sim_hw_parse (sd
, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
604 sim_hw_parse (sd
, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
605 sim_hw_parse (sd
, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
606 sim_hw_parse (sd
, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
607 sim_hw_parse (sd
, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
608 sim_hw_parse (sd
, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
609 sim_hw_parse (sd
, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
616 if (display_mem_info
)
618 struct option_list
* ol
;
619 struct option_list
* prev
;
621 /* This is a hack. We want to execute the real --memory-info command
622 line switch which is handled in common/sim-memopts.c, not the
623 override we have defined in this file. So we remove the
624 mips_options array from the state options list. This is safe
625 because we have now processed all of the command line. */
626 for (ol
= STATE_OPTIONS (sd
), prev
= NULL
;
628 prev
= ol
, ol
= ol
->next
)
629 if (ol
->options
== mips_options
)
632 SIM_ASSERT (ol
!= NULL
);
635 STATE_OPTIONS (sd
) = ol
->next
;
637 prev
->next
= ol
->next
;
639 sim_do_commandf (sd
, "memory-info");
642 /* check for/establish the a reference program image */
643 if (sim_analyze_program (sd
,
644 (STATE_PROG_ARGV (sd
) != NULL
645 ? *STATE_PROG_ARGV (sd
)
649 sim_module_uninstall (sd
);
653 /* Configure/verify the target byte order and other runtime
654 configuration options */
655 if (sim_config (sd
) != SIM_RC_OK
)
657 sim_module_uninstall (sd
);
661 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
663 /* Uninstall the modules to avoid memory leaks,
664 file descriptor leaks, etc. */
665 sim_module_uninstall (sd
);
669 /* verify assumptions the simulator made about the host type system.
670 This macro does not return if there is a problem */
671 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
672 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
674 /* This is NASTY, in that we are assuming the size of specific
678 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
681 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
682 else if ((rn
>= FGR_BASE
) && (rn
< (FGR_BASE
+ NR_FGR
)))
683 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
684 else if ((rn
>= 33) && (rn
<= 37))
685 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
686 else if ((rn
== SRIDX
)
689 || ((rn
>= 72) && (rn
<= 89)))
690 cpu
->register_widths
[rn
] = 32;
692 cpu
->register_widths
[rn
] = 0;
699 if (STATE
& simTRACE
)
704 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
707 lsipmon_monitor_base);
710 /* Write the monitor trap address handlers into the monitor (eeprom)
711 address space. This can only be done once the target endianness
712 has been determined. */
713 if (idt_monitor_base
!= 0)
716 unsigned idt_monitor_size
= 1 << 11;
718 /* the default monitor region */
719 sim_do_commandf (sd
, "memory region 0x%x,0x%x",
720 idt_monitor_base
, idt_monitor_size
);
722 /* Entry into the IDT monitor is via fixed address vectors, and
723 not using machine instructions. To avoid clashing with use of
724 the MIPS TRAP system, we place our own (simulator specific)
725 "undefined" instructions into the relevant vector slots. */
726 for (loop
= 0; (loop
< idt_monitor_size
); loop
+= 4)
728 address_word vaddr
= (idt_monitor_base
+ loop
);
729 unsigned32 insn
= (RSVD_INSTRUCTION
|
730 (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
)
731 << RSVD_INSTRUCTION_ARG_SHIFT
));
733 sim_write (sd
, vaddr
, (unsigned char *)&insn
, sizeof (insn
));
737 if ((pmon_monitor_base
!= 0) || (lsipmon_monitor_base
!= 0))
739 /* The PMON monitor uses the same address space, but rather than
740 branching into it the address of a routine is loaded. We can
741 cheat for the moment, and direct the PMON routine to IDT style
742 instructions within the monitor space. This relies on the IDT
743 monitor not using the locations from 0xBFC00500 onwards as its
746 for (loop
= 0; (loop
< 24); loop
++)
748 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
764 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
766 case 8: /* cliexit */
769 case 11: /* flush_cache */
774 SIM_ASSERT (idt_monitor_base
!= 0);
775 value
= ((unsigned int) idt_monitor_base
+ (value
* 8));
778 if (pmon_monitor_base
!= 0)
780 address_word vaddr
= (pmon_monitor_base
+ (loop
* 4));
781 sim_write (sd
, vaddr
, (unsigned char *)&value
, sizeof (value
));
784 if (lsipmon_monitor_base
!= 0)
786 address_word vaddr
= (lsipmon_monitor_base
+ (loop
* 4));
787 sim_write (sd
, vaddr
, (unsigned char *)&value
, sizeof (value
));
791 /* Write an abort sequence into the TRAP (common) exception vector
792 addresses. This is to catch code executing a TRAP (et.al.)
793 instruction without installing a trap handler. */
794 if ((idt_monitor_base
!= 0) ||
795 (pmon_monitor_base
!= 0) ||
796 (lsipmon_monitor_base
!= 0))
798 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
799 HALT_INSTRUCTION
/* BREAK */ };
802 sim_write (sd
, 0x80000000, (unsigned char *) halt
, sizeof (halt
));
803 sim_write (sd
, 0x80000180, (unsigned char *) halt
, sizeof (halt
));
804 sim_write (sd
, 0x80000200, (unsigned char *) halt
, sizeof (halt
));
805 /* XXX: Write here unconditionally? */
806 sim_write (sd
, 0xBFC00200, (unsigned char *) halt
, sizeof (halt
));
807 sim_write (sd
, 0xBFC00380, (unsigned char *) halt
, sizeof (halt
));
808 sim_write (sd
, 0xBFC00400, (unsigned char *) halt
, sizeof (halt
));
812 /* CPU specific initialization. */
813 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
815 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
817 CPU_PC_FETCH (cpu
) = mips_pc_get
;
818 CPU_PC_STORE (cpu
) = mips_pc_set
;
826 open_trace (SIM_DESC sd
)
828 tracefh
= fopen(tracefile
,"wb+");
831 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
837 /* Return name of an insn, used by insn profiling. */
839 get_insn_name (sim_cpu
*cpu
, int i
)
841 return itable
[i
].name
;
845 sim_close (SIM_DESC sd
, int quitting
)
848 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
852 /* "quitting" is non-zero if we cannot hang on errors */
854 /* shut down modules */
855 sim_module_uninstall (sd
);
857 /* Ensure that any resources allocated through the callback
858 mechanism are released: */
859 sim_io_shutdown (sd
);
862 if (tracefh
!= NULL
&& tracefh
!= stderr
)
867 /* FIXME - free SD */
874 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
877 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
879 /* Return the number of bytes written, or zero if error. */
881 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
884 /* We use raw read and write routines, since we do not want to count
885 the GDB memory accesses in our statistics gathering. */
887 for (index
= 0; index
< size
; index
++)
889 address_word vaddr
= (address_word
)addr
+ index
;
892 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
894 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
902 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
905 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
907 /* Return the number of bytes read, or zero if error. */
909 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
912 for (index
= 0; (index
< size
); index
++)
914 address_word vaddr
= (address_word
)addr
+ index
;
917 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
919 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
927 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
929 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
930 /* NOTE: gdb (the client) stores registers in target byte order
931 while the simulator uses host byte order */
933 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
936 /* Unfortunately this suffers from the same problem as the register
937 numbering one. We need to know what the width of each logical
938 register number is for the architecture being simulated. */
940 if (cpu
->register_widths
[rn
] == 0)
942 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
948 if (rn
>= FGR_BASE
&& rn
< FGR_BASE
+ NR_FGR
)
950 cpu
->fpr_state
[rn
- FGR_BASE
] = fmt_uninterpreted
;
951 if (cpu
->register_widths
[rn
] == 32)
955 cpu
->fgr
[rn
- FGR_BASE
] =
956 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
961 cpu
->fgr
[rn
- FGR_BASE
] = T2H_4 (*(unsigned32
*)memory
);
969 cpu
->fgr
[rn
- FGR_BASE
] = T2H_8 (*(unsigned64
*)memory
);
974 cpu
->fgr
[rn
- FGR_BASE
] = T2H_4 (*(unsigned32
*)memory
);
980 if (cpu
->register_widths
[rn
] == 32)
985 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
990 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
998 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
1003 cpu
->registers
[rn
] = (signed32
) T2H_4(*(unsigned32
*)memory
);
1012 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1014 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
1015 /* NOTE: gdb (the client) stores registers in target byte order
1016 while the simulator uses host byte order */
1018 #if 0 /* FIXME: doesn't compile */
1019 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
1023 if (cpu
->register_widths
[rn
] == 0)
1025 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
1031 /* Any floating point register */
1032 if (rn
>= FGR_BASE
&& rn
< FGR_BASE
+ NR_FGR
)
1034 if (cpu
->register_widths
[rn
] == 32)
1038 *(unsigned64
*)memory
=
1039 H2T_8 ((unsigned32
) (cpu
->fgr
[rn
- FGR_BASE
]));
1044 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGR_BASE
]);
1052 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGR_BASE
]);
1057 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->fgr
[rn
- FGR_BASE
]));
1063 if (cpu
->register_widths
[rn
] == 32)
1067 *(unsigned64
*)memory
=
1068 H2T_8 ((unsigned32
) (cpu
->registers
[rn
]));
1073 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
1081 *(unsigned64
*)memory
=
1082 H2T_8 ((unsigned64
) (cpu
->registers
[rn
]));
1087 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
1096 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
1100 #if 0 /* FIXME: doesn't compile */
1101 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1110 /* override PC value set by ColdReset () */
1112 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1114 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1115 CPU_PC_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
1119 #if 0 /* def DEBUG */
1122 /* We should really place the argv slot values into the argument
1123 registers, and onto the stack as required. However, this
1124 assumes that we have a stack defined, which is not
1125 necessarily true at the moment. */
1127 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1128 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1129 printf("DBG: arg \"%s\"\n",*cptr
);
1136 /*---------------------------------------------------------------------------*/
1137 /*-- Private simulator support interface ------------------------------------*/
1138 /*---------------------------------------------------------------------------*/
1140 /* Read a null terminated string from memory, return in a buffer */
1142 fetch_str (SIM_DESC sd
,
1148 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1150 buf
= NZALLOC (char, nr
+ 1);
1151 sim_read (sd
, addr
, (unsigned char *)buf
, nr
);
1156 /* Implements the "sim firmware" command:
1157 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1158 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1159 defaults to the normal address for that monitor.
1160 sim firmware none --- don't emulate any ROM monitor. Useful
1161 if you need a clean address space. */
1163 sim_firmware_command (SIM_DESC sd
, char *arg
)
1165 int address_present
= 0;
1168 /* Signal occurrence of this option. */
1169 firmware_option_p
= 1;
1171 /* Parse out the address, if present. */
1173 char *p
= strchr (arg
, '@');
1177 address_present
= 1;
1178 p
++; /* skip over @ */
1180 address
= strtoul (p
, &q
, 0);
1183 sim_io_printf (sd
, "Invalid address given to the"
1184 "`sim firmware NAME@ADDRESS' command: %s\n",
1191 address_present
= 0;
1192 address
= -1; /* Dummy value. */
1196 if (! strncmp (arg
, "idt", 3))
1198 idt_monitor_base
= address_present
? address
: 0xBFC00000;
1199 pmon_monitor_base
= 0;
1200 lsipmon_monitor_base
= 0;
1202 else if (! strncmp (arg
, "pmon", 4))
1204 /* pmon uses indirect calls. Hook into implied idt. */
1205 pmon_monitor_base
= address_present
? address
: 0xBFC00500;
1206 idt_monitor_base
= pmon_monitor_base
- 0x500;
1207 lsipmon_monitor_base
= 0;
1209 else if (! strncmp (arg
, "lsipmon", 7))
1211 /* lsipmon uses indirect calls. Hook into implied idt. */
1212 pmon_monitor_base
= 0;
1213 lsipmon_monitor_base
= address_present
? address
: 0xBFC00200;
1214 idt_monitor_base
= lsipmon_monitor_base
- 0x200;
1216 else if (! strncmp (arg
, "none", 4))
1218 if (address_present
)
1221 "The `sim firmware none' command does "
1222 "not take an `ADDRESS' argument.\n");
1225 idt_monitor_base
= 0;
1226 pmon_monitor_base
= 0;
1227 lsipmon_monitor_base
= 0;
1231 sim_io_printf (sd
, "\
1232 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1233 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1243 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1245 sim_monitor (SIM_DESC sd
,
1248 unsigned int reason
)
1251 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1254 /* The IDT monitor actually allows two instructions per vector
1255 slot. However, the simulator currently causes a trap on each
1256 individual instruction. We cheat, and lose the bottom bit. */
1259 /* The following callback functions are available, however the
1260 monitor we are simulating does not make use of them: get_errno,
1261 isatty, lseek, rename, system, time and unlink */
1265 case 6: /* int open(char *path,int flags) */
1267 char *path
= fetch_str (sd
, A0
);
1268 V0
= sim_io_open (sd
, path
, (int)A1
);
1273 case 7: /* int read(int file,char *ptr,int len) */
1277 char *buf
= zalloc (nr
);
1278 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1279 sim_write (sd
, A1
, (unsigned char *)buf
, nr
);
1284 case 8: /* int write(int file,char *ptr,int len) */
1288 char *buf
= zalloc (nr
);
1289 sim_read (sd
, A1
, (unsigned char *)buf
, nr
);
1290 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1292 sim_io_flush_stdout (sd
);
1294 sim_io_flush_stderr (sd
);
1299 case 10: /* int close(int file) */
1301 V0
= sim_io_close (sd
, (int)A0
);
1305 case 2: /* Densan monitor: char inbyte(int waitflag) */
1307 if (A0
== 0) /* waitflag == NOWAIT */
1308 V0
= (unsigned_word
)-1;
1310 /* Drop through to case 11 */
1312 case 11: /* char inbyte(void) */
1315 /* ensure that all output has gone... */
1316 sim_io_flush_stdout (sd
);
1317 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1319 sim_io_error(sd
,"Invalid return from character read");
1320 V0
= (unsigned_word
)-1;
1323 V0
= (unsigned_word
)tmp
;
1327 case 3: /* Densan monitor: void co(char chr) */
1328 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1330 char tmp
= (char)(A0
& 0xFF);
1331 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1335 case 17: /* void _exit() */
1337 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1338 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1339 (unsigned int)(A0
& 0xFFFFFFFF));
1343 case 28: /* PMON flush_cache */
1346 case 55: /* void get_mem_info(unsigned int *ptr) */
1347 /* in: A0 = pointer to three word memory location */
1348 /* out: [A0 + 0] = size */
1349 /* [A0 + 4] = instruction cache size */
1350 /* [A0 + 8] = data cache size */
1353 unsigned_4 zero
= 0;
1354 address_word mem_size
;
1355 sim_memopt
*entry
, *match
= NULL
;
1357 /* Search for memory region mapped to KSEG0 or KSEG1. */
1358 for (entry
= STATE_MEMOPT (sd
);
1360 entry
= entry
->next
)
1362 if ((entry
->addr
== K0BASE
|| entry
->addr
== K1BASE
)
1363 && (!match
|| entry
->level
< match
->level
))
1368 for (alias
= entry
->alias
;
1370 alias
= alias
->next
)
1371 if ((alias
->addr
== K0BASE
|| alias
->addr
== K1BASE
)
1372 && (!match
|| entry
->level
< match
->level
))
1377 /* Get region size, limit to KSEG1 size (512MB). */
1378 SIM_ASSERT (match
!= NULL
);
1379 mem_size
= (match
->modulo
!= 0
1380 ? match
->modulo
: match
->nr_bytes
);
1381 if (mem_size
> K1SIZE
)
1386 sim_write (sd
, A0
+ 0, (unsigned char *)&value
, 4);
1387 sim_write (sd
, A0
+ 4, (unsigned char *)&zero
, 4);
1388 sim_write (sd
, A0
+ 8, (unsigned char *)&zero
, 4);
1389 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1393 case 158: /* PMON printf */
1394 /* in: A0 = pointer to format string */
1395 /* A1 = optional argument 1 */
1396 /* A2 = optional argument 2 */
1397 /* A3 = optional argument 3 */
1399 /* The following is based on the PMON printf source */
1401 address_word s
= A0
;
1403 signed_word
*ap
= &A1
; /* 1st argument */
1404 /* This isn't the quickest way, since we call the host print
1405 routine for every character almost. But it does avoid
1406 having to allocate and manage a temporary string buffer. */
1407 /* TODO: Include check that we only use three arguments (A1,
1409 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1414 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1415 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1416 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1418 if (strchr ("dobxXulscefg%", c
))
1433 else if (c
>= '1' && c
<= '9')
1437 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1440 n
= (unsigned int)strtol(tmp
,NULL
,10);
1453 sim_io_printf (sd
, "%%");
1458 address_word p
= *ap
++;
1460 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1461 sim_io_printf(sd
, "%c", ch
);
1464 sim_io_printf(sd
,"(null)");
1467 sim_io_printf (sd
, "%c", (int)*ap
++);
1472 sim_read (sd
, s
++, &c
, 1);
1476 sim_read (sd
, s
++, &c
, 1);
1479 if (strchr ("dobxXu", c
))
1481 word64 lv
= (word64
) *ap
++;
1483 sim_io_printf(sd
,"<binary not supported>");
1486 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1488 sim_io_printf(sd
, tmp
, lv
);
1490 sim_io_printf(sd
, tmp
, (int)lv
);
1493 else if (strchr ("eEfgG", c
))
1495 double dbl
= *(double*)(ap
++);
1496 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1497 sim_io_printf (sd
, tmp
, dbl
);
1503 sim_io_printf(sd
, "%c", c
);
1509 /* Unknown reason. */
1515 /* Store a word into memory. */
1518 store_word (SIM_DESC sd
,
1527 if ((vaddr
& 3) != 0)
1528 SignalExceptionAddressStore ();
1531 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1534 const uword64 mask
= 7;
1538 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1539 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1540 memval
= ((uword64
) val
) << (8 * byte
);
1541 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1547 /* Load a word from memory. */
1550 load_word (SIM_DESC sd
,
1555 if ((vaddr
& 3) != 0)
1557 SIM_CORE_SIGNAL (SD
, cpu
, cia
, read_map
, AccessLength_WORD
+1, vaddr
, read_transfer
, sim_core_unaligned_signal
);
1564 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1567 const uword64 mask
= 0x7;
1568 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1569 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1573 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1574 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1576 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1577 return EXTEND32 (memval
>> (8 * byte
));
1584 /* Simulate the mips16 entry and exit pseudo-instructions. These
1585 would normally be handled by the reserved instruction exception
1586 code, but for ease of simulation we just handle them directly. */
1589 mips16_entry (SIM_DESC sd
,
1594 int aregs
, sregs
, rreg
;
1597 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1600 aregs
= (insn
& 0x700) >> 8;
1601 sregs
= (insn
& 0x0c0) >> 6;
1602 rreg
= (insn
& 0x020) >> 5;
1604 /* This should be checked by the caller. */
1613 /* This is the entry pseudo-instruction. */
1615 for (i
= 0; i
< aregs
; i
++)
1616 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1624 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1627 for (i
= 0; i
< sregs
; i
++)
1630 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1638 /* This is the exit pseudo-instruction. */
1645 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1648 for (i
= 0; i
< sregs
; i
++)
1651 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1656 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1660 FGR
[0] = WORD64LO (GPR
[4]);
1661 FPR_STATE
[0] = fmt_uninterpreted
;
1663 else if (aregs
== 6)
1665 FGR
[0] = WORD64LO (GPR
[5]);
1666 FGR
[1] = WORD64LO (GPR
[4]);
1667 FPR_STATE
[0] = fmt_uninterpreted
;
1668 FPR_STATE
[1] = fmt_uninterpreted
;
1677 /*-- trace support ----------------------------------------------------------*/
1679 /* The TRACE support is provided (if required) in the memory accessing
1680 routines. Since we are also providing the architecture specific
1681 features, the architecture simulation code can also deal with
1682 notifying the TRACE world of cache flushes, etc. Similarly we do
1683 not need to provide profiling support in the simulator engine,
1684 since we can sample in the instruction fetch control loop. By
1685 defining the TRACE manifest, we add tracing as a run-time
1689 /* Tracing by default produces "din" format (as required by
1690 dineroIII). Each line of such a trace file *MUST* have a din label
1691 and address field. The rest of the line is ignored, so comments can
1692 be included if desired. The first field is the label which must be
1693 one of the following values:
1698 3 escape record (treated as unknown access type)
1699 4 escape record (causes cache flush)
1701 The address field is a 32bit (lower-case) hexadecimal address
1702 value. The address should *NOT* be preceded by "0x".
1704 The size of the memory transfer is not important when dealing with
1705 cache lines (as long as no more than a cache line can be
1706 transferred in a single operation :-), however more information
1707 could be given following the dineroIII requirement to allow more
1708 complete memory and cache simulators to provide better
1709 results. i.e. the University of Pisa has a cache simulator that can
1710 also take bus size and speed as (variable) inputs to calculate
1711 complete system performance (a much more useful ability when trying
1712 to construct an end product, rather than a processor). They
1713 currently have an ARM version of their tool called ChARM. */
1717 dotrace (SIM_DESC sd
,
1725 if (STATE
& simTRACE
) {
1727 fprintf(tracefh
,"%d %s ; width %d ; ",
1731 va_start(ap
,comment
);
1732 vfprintf(tracefh
,comment
,ap
);
1734 fprintf(tracefh
,"\n");
1736 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1737 we may be generating 64bit ones, we should put the hi-32bits of the
1738 address into the comment field. */
1740 /* TODO: Provide a buffer for the trace lines. We can then avoid
1741 performing writes until the buffer is filled, or the file is
1744 /* NOTE: We could consider adding a comment field to the "din" file
1745 produced using type 3 markers (unknown access). This would then
1746 allow information about the program that the "din" is for, and
1747 the MIPs world that was being simulated, to be placed into the
1754 /*---------------------------------------------------------------------------*/
1755 /*-- simulator engine -------------------------------------------------------*/
1756 /*---------------------------------------------------------------------------*/
1759 ColdReset (SIM_DESC sd
)
1762 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1764 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1765 /* RESET: Fixed PC address: */
1766 PC
= (unsigned_word
) UNSIGNED64 (0xFFFFFFFFBFC00000);
1767 /* The reset vector address is in the unmapped, uncached memory space. */
1769 SR
&= ~(status_SR
| status_TS
| status_RP
);
1770 SR
|= (status_ERL
| status_BEV
);
1772 /* Cheat and allow access to the complete register set immediately */
1773 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1774 && WITH_TARGET_WORD_BITSIZE
== 64)
1775 SR
|= status_FR
; /* 64bit registers */
1777 /* Ensure that any instructions with pending register updates are
1779 PENDING_INVALIDATE();
1781 /* Initialise the FPU registers to the unknown state */
1782 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1785 for (rn
= 0; (rn
< 32); rn
++)
1786 FPR_STATE
[rn
] = fmt_uninterpreted
;
1789 /* Initialise the Config0 register. */
1790 C0_CONFIG
= 0x80000000 /* Config1 present */
1791 | 2; /* KSEG0 uncached */
1792 if (WITH_TARGET_WORD_BITSIZE
== 64)
1794 /* FIXME Currently mips/sim-main.c:address_translation()
1795 truncates all addresses to 32-bits. */
1796 if (0 && WITH_TARGET_ADDRESS_BITSIZE
== 64)
1797 C0_CONFIG
|= (2 << 13); /* MIPS64, 64-bit addresses */
1799 C0_CONFIG
|= (1 << 13); /* MIPS64, 32-bit addresses */
1802 C0_CONFIG
|= 0x00008000; /* Big Endian */
1809 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1810 /* Signal an exception condition. This will result in an exception
1811 that aborts the instruction. The instruction operation pseudocode
1812 will never see a return from this function call. */
1815 signal_exception (SIM_DESC sd
,
1823 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1826 /* Ensure that any active atomic read/modify/write operation will fail: */
1829 /* Save registers before interrupt dispatching */
1830 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1831 SIM_CPU_EXCEPTION_TRIGGER(sd
, cpu
, cia
);
1834 switch (exception
) {
1836 case DebugBreakPoint
:
1837 if (! (Debug
& Debug_DM
))
1843 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1844 DEPC
= cia
- 4; /* reference the branch instruction */
1848 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1852 Debug
|= Debug_DM
; /* in debugging mode */
1853 Debug
|= Debug_DBp
; /* raising a DBp exception */
1855 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1859 case ReservedInstruction
:
1862 unsigned int instruction
;
1863 va_start(ap
,exception
);
1864 instruction
= va_arg(ap
,unsigned int);
1866 /* Provide simple monitor support using ReservedInstruction
1867 exceptions. The following code simulates the fixed vector
1868 entry points into the IDT monitor by causing a simulator
1869 trap, performing the monitor operation, and returning to
1870 the address held in the $ra register (standard PCS return
1871 address). This means we only need to pre-load the vector
1872 space with suitable instruction values. For systems were
1873 actual trap instructions are used, we would not need to
1874 perform this magic. */
1875 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1877 int reason
= (instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
;
1878 if (!sim_monitor (SD
, CPU
, cia
, reason
))
1879 sim_io_error (sd
, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason
, pr_addr (cia
));
1881 /* NOTE: This assumes that a branch-and-link style
1882 instruction was used to enter the vector (which is the
1883 case with the current IDT monitor). */
1884 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1886 /* Look for the mips16 entry and exit instructions, and
1887 simulate a handler for them. */
1888 else if ((cia
& 1) != 0
1889 && (instruction
& 0xf81f) == 0xe809
1890 && (instruction
& 0x0c0) != 0x0c0)
1892 mips16_entry (SD
, CPU
, cia
, instruction
);
1893 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1895 /* else fall through to normal exception processing */
1896 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1900 /* Store exception code into current exception id variable (used
1903 /* TODO: If not simulating exceptions then stop the simulator
1904 execution. At the moment we always stop the simulation. */
1906 #ifdef SUBTARGET_R3900
1907 /* update interrupt-related registers */
1909 /* insert exception code in bits 6:2 */
1910 CAUSE
= LSMASKED32(CAUSE
, 31, 7) | LSINSERTED32(exception
, 6, 2);
1911 /* shift IE/KU history bits left */
1912 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 3, 0), 5, 2);
1914 if (STATE
& simDELAYSLOT
)
1916 STATE
&= ~simDELAYSLOT
;
1918 EPC
= (cia
- 4); /* reference the branch instruction */
1923 if (SR
& status_BEV
)
1924 PC
= (signed)0xBFC00000 + 0x180;
1926 PC
= (signed)0x80000000 + 0x080;
1928 /* See figure 5-17 for an outline of the code below */
1929 if (! (SR
& status_EXL
))
1931 CAUSE
= (exception
<< 2);
1932 if (STATE
& simDELAYSLOT
)
1934 STATE
&= ~simDELAYSLOT
;
1936 EPC
= (cia
- 4); /* reference the branch instruction */
1940 /* FIXME: TLB et.al. */
1941 /* vector = 0x180; */
1945 CAUSE
= (exception
<< 2);
1946 /* vector = 0x180; */
1949 /* Store exception code into current exception id variable (used
1952 if (SR
& status_BEV
)
1953 PC
= (signed)0xBFC00200 + 0x180;
1955 PC
= (signed)0x80000000 + 0x180;
1958 switch ((CAUSE
>> 2) & 0x1F)
1961 /* Interrupts arrive during event processing, no need to
1967 #ifdef SUBTARGET_3900
1968 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1969 PC
= (signed)0xBFC00000;
1970 #endif /* SUBTARGET_3900 */
1973 case TLBModification
:
1978 case InstructionFetch
:
1980 /* The following is so that the simulator will continue from the
1981 exception handler address. */
1982 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1983 sim_stopped
, SIM_SIGBUS
);
1985 case ReservedInstruction
:
1986 case CoProcessorUnusable
:
1988 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1989 sim_stopped
, SIM_SIGILL
);
1991 case IntegerOverflow
:
1993 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1994 sim_stopped
, SIM_SIGFPE
);
1997 sim_engine_halt (SD
, CPU
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
2002 sim_engine_restart (SD
, CPU
, NULL
, PC
);
2007 sim_engine_halt (SD
, CPU
, NULL
, PC
,
2008 sim_stopped
, SIM_SIGTRAP
);
2010 default: /* Unknown internal exception */
2012 sim_engine_halt (SD
, CPU
, NULL
, PC
,
2013 sim_stopped
, SIM_SIGABRT
);
2017 case SimulatorFault
:
2021 va_start(ap
,exception
);
2022 msg
= va_arg(ap
,char *);
2024 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2025 "FATAL: Simulator error \"%s\"\n",msg
);
2034 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2035 "UNPREDICTABLE" behaviour.
2037 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2038 may vary from processor implementation to processor implementation,
2039 instruction to instruction, or as a function of time on the same
2040 implementation or instruction. Software can never depend on results
2041 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2042 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2045 For UNPREDICTABLE behaviour, we print a message, if possible print
2046 the offending instructions mips.igen instruction name (provided by
2047 the caller), and stop the simulator.
2049 XXX FIXME: eventually, stopping the simulator should be made conditional
2050 on a command-line option. */
2052 unpredictable_action(sim_cpu
*cpu
, address_word cia
)
2054 SIM_DESC sd
= CPU_STATE(cpu
);
2056 sim_io_eprintf(sd
, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia
));
2057 sim_engine_halt (SD
, CPU
, NULL
, cia
, sim_stopped
, SIM_SIGABRT
);
2061 /*-- co-processor support routines ------------------------------------------*/
2064 CoProcPresent(unsigned int coproc_number
)
2066 /* Return TRUE if simulator provides a model for the given co-processor number */
2071 cop_lw (SIM_DESC sd
,
2076 unsigned int memword
)
2081 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2084 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2086 StoreFPR(coproc_reg
,fmt_uninterpreted_32
,(uword64
)memword
);
2091 #if 0 /* this should be controlled by a configuration option */
2092 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2101 cop_ld (SIM_DESC sd
,
2110 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num
, coproc_reg
, pr_uword64(memword
), pr_addr(cia
) );
2113 switch (coproc_num
) {
2115 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2117 StoreFPR(coproc_reg
,fmt_uninterpreted_64
,memword
);
2122 #if 0 /* this message should be controlled by a configuration option */
2123 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2135 cop_sw (SIM_DESC sd
,
2141 unsigned int value
= 0;
2146 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2148 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted_32
);
2153 #if 0 /* should be controlled by configuration option */
2154 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2163 cop_sd (SIM_DESC sd
,
2173 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2175 value
= ValueFPR(coproc_reg
,fmt_uninterpreted_64
);
2180 #if 0 /* should be controlled by configuration option */
2181 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2193 decode_coproc (SIM_DESC sd
,
2196 unsigned int instruction
)
2198 int coprocnum
= ((instruction
>> 26) & 3);
2202 case 0: /* standard CPU control and cache registers */
2204 int code
= ((instruction
>> 21) & 0x1F);
2205 int rt
= ((instruction
>> 16) & 0x1F);
2206 int rd
= ((instruction
>> 11) & 0x1F);
2207 int tail
= instruction
& 0x3ff;
2208 /* R4000 Users Manual (second edition) lists the following CP0
2210 CODE><-RT><RD-><--TAIL--->
2211 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2212 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2213 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2214 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2215 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2216 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2217 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2218 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2219 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2220 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2222 if (((code
== 0x00) || (code
== 0x04) /* MFC0 / MTC0 */
2223 || (code
== 0x01) || (code
== 0x05)) /* DMFC0 / DMTC0 */
2226 /* Clear double/single coprocessor move bit. */
2229 /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
2231 switch (rd
) /* NOTEs: Standard CP0 registers */
2233 /* 0 = Index R4000 VR4100 VR4300 */
2234 /* 1 = Random R4000 VR4100 VR4300 */
2235 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2236 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2237 /* 4 = Context R4000 VR4100 VR4300 */
2238 /* 5 = PageMask R4000 VR4100 VR4300 */
2239 /* 6 = Wired R4000 VR4100 VR4300 */
2240 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2241 /* 9 = Count R4000 VR4100 VR4300 */
2242 /* 10 = EntryHi R4000 VR4100 VR4300 */
2243 /* 11 = Compare R4000 VR4100 VR4300 */
2244 /* 12 = SR R4000 VR4100 VR4300 */
2245 #ifdef SUBTARGET_R3900
2247 /* 3 = Config R3900 */
2249 /* 7 = Cache R3900 */
2251 /* 15 = PRID R3900 */
2257 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2259 GPR
[rt
] = (signed_word
) (signed_address
) COP0_BADVADDR
;
2261 COP0_BADVADDR
= GPR
[rt
];
2264 #endif /* SUBTARGET_R3900 */
2271 /* 13 = Cause R4000 VR4100 VR4300 */
2278 /* 14 = EPC R4000 VR4100 VR4300 */
2281 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
2285 /* 15 = PRId R4000 VR4100 VR4300 */
2286 #ifdef SUBTARGET_R3900
2295 /* 16 = Config R4000 VR4100 VR4300 */
2298 GPR
[rt
] = C0_CONFIG
;
2300 /* only bottom three bits are writable */
2301 C0_CONFIG
= (C0_CONFIG
& ~0x7) | (GPR
[rt
] & 0x7);
2304 #ifdef SUBTARGET_R3900
2313 /* 17 = LLAddr R4000 VR4100 VR4300 */
2315 /* 18 = WatchLo R4000 VR4100 VR4300 */
2316 /* 19 = WatchHi R4000 VR4100 VR4300 */
2317 /* 20 = XContext R4000 VR4100 VR4300 */
2318 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2319 /* 27 = CacheErr R4000 VR4100 */
2320 /* 28 = TagLo R4000 VR4100 VR4300 */
2321 /* 29 = TagHi R4000 VR4100 VR4300 */
2322 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2323 if (STATE_VERBOSE_P(SD
))
2325 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2326 (unsigned long)cia
);
2327 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
2328 /* CPR[0,rd] = GPR[rt]; */
2331 GPR
[rt
] = (signed_word
) (signed32
) COP0_GPR
[rd
];
2333 COP0_GPR
[rd
] = GPR
[rt
];
2336 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
2338 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
2342 else if ((code
== 0x00 || code
== 0x01)
2345 /* [D]MFC0 RT,C0_CONFIG,SEL */
2347 switch (tail
& 0x07)
2353 /* MIPS32 r/o Config1:
2356 /* MIPS16 implemented.
2357 XXX How to check configuration? */
2359 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2360 /* MDMX & FPU implemented */
2364 /* MIPS32 r/o Config2:
2369 /* MIPS32 r/o Config3:
2370 SmartMIPS implemented. */
2376 else if (code
== 0x10 && (tail
& 0x3f) == 0x18)
2379 if (SR
& status_ERL
)
2381 /* Oops, not yet available */
2382 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
2392 else if (code
== 0x10 && (tail
& 0x3f) == 0x10)
2395 #ifdef SUBTARGET_R3900
2396 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2398 /* shift IE/KU history bits right */
2399 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 5, 2), 3, 0);
2401 /* TODO: CACHE register */
2402 #endif /* SUBTARGET_R3900 */
2404 else if (code
== 0x10 && (tail
& 0x3f) == 0x1F)
2412 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
2413 /* TODO: When executing an ERET or RFE instruction we should
2414 clear LLBIT, to ensure that any out-standing atomic
2415 read/modify/write sequence fails. */
2419 case 2: /* co-processor 2 */
2426 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2427 instruction
,pr_addr(cia
));
2432 case 1: /* should not occur (FPU co-processor) */
2433 case 3: /* should not occur (FPU co-processor) */
2434 SignalException(ReservedInstruction
,instruction
);
2442 /* This code copied from gdb's utils.c. Would like to share this code,
2443 but don't know of a common place where both could get to it. */
2445 /* Temporary storage using circular buffer */
2451 static char buf
[NUMCELLS
][CELLSIZE
];
2453 if (++cell
>=NUMCELLS
) cell
=0;
2457 /* Print routines to handle variable size regs, etc */
2459 /* Eliminate warning from compiler on 32-bit systems */
2460 static int thirty_two
= 32;
2463 pr_addr (SIM_ADDR addr
)
2465 char *paddr_str
=get_cell();
2466 switch (sizeof(addr
))
2469 sprintf(paddr_str
,"%08lx%08lx",
2470 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
2473 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
2476 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
2479 sprintf(paddr_str
,"%x",addr
);
2485 pr_uword64 (uword64 addr
)
2487 char *paddr_str
=get_cell();
2488 sprintf(paddr_str
,"%08lx%08lx",
2489 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
2495 mips_core_signal (SIM_DESC sd
,
2501 transfer_type transfer
,
2502 sim_core_signals sig
)
2504 const char *copy
= (transfer
== read_transfer
? "read" : "write");
2505 address_word ip
= CIA_ADDR (cia
);
2509 case sim_core_unmapped_signal
:
2510 sim_io_eprintf (sd
, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2512 (unsigned long) addr
, (unsigned long) ip
);
2513 COP0_BADVADDR
= addr
;
2514 SignalExceptionDataReference();
2517 case sim_core_unaligned_signal
:
2518 sim_io_eprintf (sd
, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2520 (unsigned long) addr
, (unsigned long) ip
);
2521 COP0_BADVADDR
= addr
;
2522 if(transfer
== read_transfer
)
2523 SignalExceptionAddressLoad();
2525 SignalExceptionAddressStore();
2529 sim_engine_abort (sd
, cpu
, cia
,
2530 "mips_core_signal - internal error - bad switch");
2536 mips_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word cia
)
2538 ASSERT(cpu
!= NULL
);
2540 if(cpu
->exc_suspended
> 0)
2541 sim_io_eprintf(sd
, "Warning, nested exception triggered (%d)\n", cpu
->exc_suspended
);
2544 memcpy(cpu
->exc_trigger_registers
, cpu
->registers
, sizeof(cpu
->exc_trigger_registers
));
2545 cpu
->exc_suspended
= 0;
2549 mips_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
2551 ASSERT(cpu
!= NULL
);
2553 if(cpu
->exc_suspended
> 0)
2554 sim_io_eprintf(sd
, "Warning, nested exception signal (%d then %d)\n",
2555 cpu
->exc_suspended
, exception
);
2557 memcpy(cpu
->exc_suspend_registers
, cpu
->registers
, sizeof(cpu
->exc_suspend_registers
));
2558 memcpy(cpu
->registers
, cpu
->exc_trigger_registers
, sizeof(cpu
->registers
));
2559 cpu
->exc_suspended
= exception
;
2563 mips_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
2565 ASSERT(cpu
!= NULL
);
2567 if(exception
== 0 && cpu
->exc_suspended
> 0)
2569 /* warn not for breakpoints */
2570 if(cpu
->exc_suspended
!= sim_signal_to_host(sd
, SIM_SIGTRAP
))
2571 sim_io_eprintf(sd
, "Warning, resuming but ignoring pending exception signal (%d)\n",
2572 cpu
->exc_suspended
);
2574 else if(exception
!= 0 && cpu
->exc_suspended
> 0)
2576 if(exception
!= cpu
->exc_suspended
)
2577 sim_io_eprintf(sd
, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2578 cpu
->exc_suspended
, exception
);
2580 memcpy(cpu
->registers
, cpu
->exc_suspend_registers
, sizeof(cpu
->registers
));
2582 else if(exception
!= 0 && cpu
->exc_suspended
== 0)
2584 sim_io_eprintf(sd
, "Warning, ignoring spontanous exception signal (%d)\n", exception
);
2586 cpu
->exc_suspended
= 0;
2590 /*---------------------------------------------------------------------------*/
2591 /*> EOF interp.c <*/