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sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 NOTEs:
17
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
21 code on the hardware.
22
23 */
24
25 /* The TRACE manifests enable the provision of extra features. If they
26 are not defined then a simpler (quicker) simulator is constructed
27 without the required run-time checks, etc. */
28 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
29 #define TRACE (1)
30 #endif
31
32 #include "config.h"
33 #include "bfd.h"
34 #include "sim-main.h"
35 #include "sim-utils.h"
36 #include "sim-options.h"
37 #include "sim-assert.h"
38 #include "sim-hw.h"
39
40 #include "itable.h"
41
42
43 #include "config.h"
44
45 #include <stdio.h>
46 #include <stdarg.h>
47 #include <ansidecl.h>
48 #include <ctype.h>
49 #include <limits.h>
50 #include <math.h>
51 #ifdef HAVE_STDLIB_H
52 #include <stdlib.h>
53 #endif
54 #ifdef HAVE_STRING_H
55 #include <string.h>
56 #else
57 #ifdef HAVE_STRINGS_H
58 #include <strings.h>
59 #endif
60 #endif
61
62 #include "getopt.h"
63 #include "libiberty.h"
64 #include "bfd.h"
65 #include "gdb/callback.h" /* GDB simulator callback interface */
66 #include "gdb/remote-sim.h" /* GDB simulator interface */
67
68 char* pr_addr (SIM_ADDR addr);
69 char* pr_uword64 (uword64 addr);
70
71
72 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
73 #define CPU cpu
74 #define SD sd
75
76
77 /* The following reserved instruction value is used when a simulator
78 trap is required. NOTE: Care must be taken, since this value may be
79 used in later revisions of the MIPS ISA. */
80
81 #define RSVD_INSTRUCTION (0x00000005)
82 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
83
84 #define RSVD_INSTRUCTION_ARG_SHIFT 6
85 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
86
87
88 /* Bits in the Debug register */
89 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
90 #define Debug_DM 0x40000000 /* Debug Mode */
91 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
92
93 /*---------------------------------------------------------------------------*/
94 /*-- GDB simulator interface ------------------------------------------------*/
95 /*---------------------------------------------------------------------------*/
96
97 static void ColdReset (SIM_DESC sd);
98
99 /*---------------------------------------------------------------------------*/
100
101
102
103 #define DELAYSLOT() {\
104 if (STATE & simDELAYSLOT)\
105 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
106 STATE |= simDELAYSLOT;\
107 }
108
109 #define JALDELAYSLOT() {\
110 DELAYSLOT ();\
111 STATE |= simJALDELAYSLOT;\
112 }
113
114 #define NULLIFY() {\
115 STATE &= ~simDELAYSLOT;\
116 STATE |= simSKIPNEXT;\
117 }
118
119 #define CANCELDELAYSLOT() {\
120 DSSTATE = 0;\
121 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
122 }
123
124 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
125 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
126
127 /* Note that the monitor code essentially assumes this layout of memory.
128 If you change these, change the monitor code, too. */
129 /* FIXME Currently addresses are truncated to 32-bits, see
130 mips/sim-main.c:address_translation(). If that changes, then these
131 values will need to be extended, and tested for more carefully. */
132 #define K0BASE (0x80000000)
133 #define K0SIZE (0x20000000)
134 #define K1BASE (0xA0000000)
135 #define K1SIZE (0x20000000)
136
137 /* Simple run-time monitor support.
138
139 We emulate the monitor by placing magic reserved instructions at
140 the monitor's entry points; when we hit these instructions, instead
141 of raising an exception (as we would normally), we look at the
142 instruction and perform the appropriate monitory operation.
143
144 `*_monitor_base' are the physical addresses at which the corresponding
145 monitor vectors are located. `0' means none. By default,
146 install all three.
147 The RSVD_INSTRUCTION... macros specify the magic instructions we
148 use at the monitor entry points. */
149 static int firmware_option_p = 0;
150 static SIM_ADDR idt_monitor_base = 0xBFC00000;
151 static SIM_ADDR pmon_monitor_base = 0xBFC00500;
152 static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
153
154 static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
155
156
157 #define MEM_SIZE (8 << 20) /* 8 MBytes */
158
159
160 #if defined(TRACE)
161 static char *tracefile = "trace.din"; /* default filename for trace log */
162 FILE *tracefh = NULL;
163 static void open_trace (SIM_DESC sd);
164 #endif /* TRACE */
165
166 static const char * get_insn_name (sim_cpu *, int);
167
168 /* simulation target board. NULL=canonical */
169 static char* board = NULL;
170
171
172 static DECLARE_OPTION_HANDLER (mips_option_handler);
173
174 enum {
175 OPTION_DINERO_TRACE = OPTION_START,
176 OPTION_DINERO_FILE,
177 OPTION_FIRMWARE,
178 OPTION_INFO_MEMORY,
179 OPTION_BOARD
180 };
181
182 static int display_mem_info = 0;
183
184 static SIM_RC
185 mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
186 int is_command)
187 {
188 int cpu_nr;
189 switch (opt)
190 {
191 case OPTION_DINERO_TRACE: /* ??? */
192 #if defined(TRACE)
193 /* Eventually the simTRACE flag could be treated as a toggle, to
194 allow external control of the program points being traced
195 (i.e. only from main onwards, excluding the run-time setup,
196 etc.). */
197 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
198 {
199 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
200 if (arg == NULL)
201 STATE |= simTRACE;
202 else if (strcmp (arg, "yes") == 0)
203 STATE |= simTRACE;
204 else if (strcmp (arg, "no") == 0)
205 STATE &= ~simTRACE;
206 else if (strcmp (arg, "on") == 0)
207 STATE |= simTRACE;
208 else if (strcmp (arg, "off") == 0)
209 STATE &= ~simTRACE;
210 else
211 {
212 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
213 return SIM_RC_FAIL;
214 }
215 }
216 return SIM_RC_OK;
217 #else /* !TRACE */
218 fprintf(stderr,"\
219 Simulator constructed without dinero tracing support (for performance).\n\
220 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
221 return SIM_RC_FAIL;
222 #endif /* !TRACE */
223
224 case OPTION_DINERO_FILE:
225 #if defined(TRACE)
226 if (optarg != NULL) {
227 char *tmp;
228 tmp = (char *)malloc(strlen(optarg) + 1);
229 if (tmp == NULL)
230 {
231 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
232 return SIM_RC_FAIL;
233 }
234 else {
235 strcpy(tmp,optarg);
236 tracefile = tmp;
237 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
238 }
239 }
240 #endif /* TRACE */
241 return SIM_RC_OK;
242
243 case OPTION_FIRMWARE:
244 return sim_firmware_command (sd, arg);
245
246 case OPTION_BOARD:
247 {
248 if (arg)
249 {
250 board = zalloc(strlen(arg) + 1);
251 strcpy(board, arg);
252 }
253 return SIM_RC_OK;
254 }
255
256 case OPTION_INFO_MEMORY:
257 display_mem_info = 1;
258 break;
259 }
260
261 return SIM_RC_OK;
262 }
263
264
265 static const OPTION mips_options[] =
266 {
267 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
268 '\0', "on|off", "Enable dinero tracing",
269 mips_option_handler },
270 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
271 '\0', "FILE", "Write dinero trace to FILE",
272 mips_option_handler },
273 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
274 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
275 mips_option_handler },
276 { {"board", required_argument, NULL, OPTION_BOARD},
277 '\0', "none" /* rely on compile-time string concatenation for other options */
278
279 #define BOARD_JMR3904 "jmr3904"
280 "|" BOARD_JMR3904
281 #define BOARD_JMR3904_PAL "jmr3904pal"
282 "|" BOARD_JMR3904_PAL
283 #define BOARD_JMR3904_DEBUG "jmr3904debug"
284 "|" BOARD_JMR3904_DEBUG
285 #define BOARD_BSP "bsp"
286 "|" BOARD_BSP
287
288 , "Customize simulation for a particular board.", mips_option_handler },
289
290 /* These next two options have the same names as ones found in the
291 memory_options[] array in common/sim-memopt.c. This is because
292 the intention is to provide an alternative handler for those two
293 options. We need an alternative handler because the memory
294 regions are not set up until after the command line arguments
295 have been parsed, and so we cannot display the memory info whilst
296 processing the command line. There is a hack in sim_open to
297 remove these handlers when we want the real --memory-info option
298 to work. */
299 { { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
300 '\0', NULL, "List configured memory regions", mips_option_handler },
301 { { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
302 '\0', NULL, NULL, mips_option_handler },
303
304 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
305 };
306
307
308 int interrupt_pending;
309
310 void
311 interrupt_event (SIM_DESC sd, void *data)
312 {
313 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
314 address_word cia = CPU_PC_GET (cpu);
315 if (SR & status_IE)
316 {
317 interrupt_pending = 0;
318 SignalExceptionInterrupt (1); /* interrupt "1" */
319 }
320 else if (!interrupt_pending)
321 sim_events_schedule (sd, 1, interrupt_event, data);
322 }
323
324
325 /*---------------------------------------------------------------------------*/
326 /*-- Device registration hook -----------------------------------------------*/
327 /*---------------------------------------------------------------------------*/
328 static void device_init(SIM_DESC sd) {
329 #ifdef DEVICE_INIT
330 extern void register_devices(SIM_DESC);
331 register_devices(sd);
332 #endif
333 }
334
335 /*---------------------------------------------------------------------------*/
336 /*-- GDB simulator interface ------------------------------------------------*/
337 /*---------------------------------------------------------------------------*/
338
339 static sim_cia
340 mips_pc_get (sim_cpu *cpu)
341 {
342 return PC;
343 }
344
345 static void
346 mips_pc_set (sim_cpu *cpu, sim_cia pc)
347 {
348 PC = pc;
349 }
350
351 SIM_DESC
352 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
353 {
354 int i;
355 SIM_DESC sd = sim_state_alloc (kind, cb);
356 sim_cpu *cpu;
357
358 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
359
360 /* The cpu data is kept in a separately allocated chunk of memory. */
361 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
362 return 0;
363
364 cpu = STATE_CPU (sd, 0); /* FIXME */
365
366 /* FIXME: watchpoints code shouldn't need this */
367 STATE_WATCHPOINTS (sd)->pc = &(PC);
368 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
369 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
370
371 /* Initialize the mechanism for doing insn profiling. */
372 CPU_INSN_NAME (cpu) = get_insn_name;
373 CPU_MAX_INSNS (cpu) = nr_itable_entries;
374
375 STATE = 0;
376
377 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
378 return 0;
379 sim_add_option_table (sd, NULL, mips_options);
380
381
382 /* getopt will print the error message so we just have to exit if this fails.
383 FIXME: Hmmm... in the case of gdb we need getopt to call
384 print_filtered. */
385 if (sim_parse_args (sd, argv) != SIM_RC_OK)
386 {
387 /* Uninstall the modules to avoid memory leaks,
388 file descriptor leaks, etc. */
389 sim_module_uninstall (sd);
390 return 0;
391 }
392
393 /* handle board-specific memory maps */
394 if (board == NULL)
395 {
396 /* Allocate core managed memory */
397 sim_memopt *entry, *match = NULL;
398 address_word mem_size = 0;
399 int mapped = 0;
400
401 /* For compatibility with the old code - under this (at level one)
402 are the kernel spaces K0 & K1. Both of these map to a single
403 smaller sub region */
404 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
405
406 /* Look for largest memory region defined on command-line at
407 phys address 0. */
408 #ifdef SIM_HAVE_FLATMEM
409 mem_size = STATE_MEM_SIZE (sd);
410 #endif
411 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
412 {
413 /* If we find an entry at address 0, then we will end up
414 allocating a new buffer in the "memory alias" command
415 below. The region at address 0 will be deleted. */
416 address_word size = (entry->modulo != 0
417 ? entry->modulo : entry->nr_bytes);
418 if (entry->addr == 0
419 && (!match || entry->level < match->level))
420 match = entry;
421 else if (entry->addr == K0BASE || entry->addr == K1BASE)
422 mapped = 1;
423 else
424 {
425 sim_memopt *alias;
426 for (alias = entry->alias; alias != NULL; alias = alias->next)
427 {
428 if (alias->addr == 0
429 && (!match || entry->level < match->level))
430 match = entry;
431 else if (alias->addr == K0BASE || alias->addr == K1BASE)
432 mapped = 1;
433 }
434 }
435 }
436
437 if (!mapped)
438 {
439 if (match)
440 {
441 /* Get existing memory region size. */
442 mem_size = (match->modulo != 0
443 ? match->modulo : match->nr_bytes);
444 /* Delete old region. */
445 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
446 match->space, match->addr, match->level);
447 }
448 else if (mem_size == 0)
449 mem_size = MEM_SIZE;
450 /* Limit to KSEG1 size (512MB) */
451 if (mem_size > K1SIZE)
452 mem_size = K1SIZE;
453 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
454 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
455 K1BASE, K1SIZE, (long)mem_size, K0BASE);
456 }
457
458 device_init(sd);
459 }
460 else if (board != NULL
461 && (strcmp(board, BOARD_BSP) == 0))
462 {
463 int i;
464
465 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
466
467 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
468 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
469 0x9FC00000,
470 4 * 1024 * 1024, /* 4 MB */
471 0xBFC00000);
472
473 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
474 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
475 0x80000000,
476 4 * 1024 * 1024, /* 4 MB */
477 0xA0000000);
478
479 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
480 for (i=0; i<8; i++) /* 32 MB total */
481 {
482 unsigned size = 4 * 1024 * 1024; /* 4 MB */
483 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
484 0x88000000 + (i * size),
485 size,
486 0xA8000000 + (i * size));
487 }
488 }
489 #if (WITH_HW)
490 else if (board != NULL
491 && (strcmp(board, BOARD_JMR3904) == 0 ||
492 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
493 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
494 {
495 /* match VIRTUAL memory layout of JMR-TX3904 board */
496 int i;
497
498 /* --- disable monitor unless forced on by user --- */
499
500 if (! firmware_option_p)
501 {
502 idt_monitor_base = 0;
503 pmon_monitor_base = 0;
504 lsipmon_monitor_base = 0;
505 }
506
507 /* --- environment --- */
508
509 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
510
511 /* --- memory --- */
512
513 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
514 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
515 0x9FC00000,
516 4 * 1024 * 1024, /* 4 MB */
517 0xBFC00000);
518
519 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
520 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
521 0x80000000,
522 4 * 1024 * 1024, /* 4 MB */
523 0xA0000000);
524
525 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
526 for (i=0; i<8; i++) /* 32 MB total */
527 {
528 unsigned size = 4 * 1024 * 1024; /* 4 MB */
529 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
530 0x88000000 + (i * size),
531 size,
532 0xA8000000 + (i * size));
533 }
534
535 /* Dummy memory regions for unsimulated devices - sorted by address */
536
537 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
538 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
539 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
540 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
541 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
542 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
543 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
544 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
545 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
546
547
548 /* --- simulated devices --- */
549 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
550 sim_hw_parse (sd, "/tx3904cpu");
551 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
552 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
553 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
554 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
555 {
556 /* FIXME: poking at dv-sockser internals, use tcp backend if
557 --sockser_addr option was given.*/
558 extern char* sockser_addr;
559 if(sockser_addr == NULL)
560 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
561 else
562 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
563 }
564 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
565 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
566
567 /* -- device connections --- */
568 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
569 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
570 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
571 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
572 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
573 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
574
575 /* add PAL timer & I/O module */
576 if(! strcmp(board, BOARD_JMR3904_PAL))
577 {
578 /* the device */
579 sim_hw_parse (sd, "/pal@0xffff0000");
580 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
581
582 /* wire up interrupt ports to irc */
583 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
584 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
585 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
586 }
587
588 if(! strcmp(board, BOARD_JMR3904_DEBUG))
589 {
590 /* -- DEBUG: glue interrupt generators --- */
591 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
592 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
593 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
594 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
595 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
596 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
597 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
598 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
599 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
600 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
601 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
602 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
603 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
604 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
605 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
606 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
607 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
608 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
609 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
610 }
611
612 device_init(sd);
613 }
614 #endif
615
616 if (display_mem_info)
617 {
618 struct option_list * ol;
619 struct option_list * prev;
620
621 /* This is a hack. We want to execute the real --memory-info command
622 line switch which is handled in common/sim-memopts.c, not the
623 override we have defined in this file. So we remove the
624 mips_options array from the state options list. This is safe
625 because we have now processed all of the command line. */
626 for (ol = STATE_OPTIONS (sd), prev = NULL;
627 ol != NULL;
628 prev = ol, ol = ol->next)
629 if (ol->options == mips_options)
630 break;
631
632 SIM_ASSERT (ol != NULL);
633
634 if (prev == NULL)
635 STATE_OPTIONS (sd) = ol->next;
636 else
637 prev->next = ol->next;
638
639 sim_do_commandf (sd, "memory-info");
640 }
641
642 /* check for/establish the a reference program image */
643 if (sim_analyze_program (sd,
644 (STATE_PROG_ARGV (sd) != NULL
645 ? *STATE_PROG_ARGV (sd)
646 : NULL),
647 abfd) != SIM_RC_OK)
648 {
649 sim_module_uninstall (sd);
650 return 0;
651 }
652
653 /* Configure/verify the target byte order and other runtime
654 configuration options */
655 if (sim_config (sd) != SIM_RC_OK)
656 {
657 sim_module_uninstall (sd);
658 return 0;
659 }
660
661 if (sim_post_argv_init (sd) != SIM_RC_OK)
662 {
663 /* Uninstall the modules to avoid memory leaks,
664 file descriptor leaks, etc. */
665 sim_module_uninstall (sd);
666 return 0;
667 }
668
669 /* verify assumptions the simulator made about the host type system.
670 This macro does not return if there is a problem */
671 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
672 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
673
674 /* This is NASTY, in that we are assuming the size of specific
675 registers: */
676 {
677 int rn;
678 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
679 {
680 if (rn < 32)
681 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
682 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
683 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
684 else if ((rn >= 33) && (rn <= 37))
685 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
686 else if ((rn == SRIDX)
687 || (rn == FCR0IDX)
688 || (rn == FCR31IDX)
689 || ((rn >= 72) && (rn <= 89)))
690 cpu->register_widths[rn] = 32;
691 else
692 cpu->register_widths[rn] = 0;
693 }
694
695
696 }
697
698 #if defined(TRACE)
699 if (STATE & simTRACE)
700 open_trace(sd);
701 #endif /* TRACE */
702
703 /*
704 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
705 idt_monitor_base,
706 pmon_monitor_base,
707 lsipmon_monitor_base);
708 */
709
710 /* Write the monitor trap address handlers into the monitor (eeprom)
711 address space. This can only be done once the target endianness
712 has been determined. */
713 if (idt_monitor_base != 0)
714 {
715 unsigned loop;
716 unsigned idt_monitor_size = 1 << 11;
717
718 /* the default monitor region */
719 sim_do_commandf (sd, "memory region 0x%x,0x%x",
720 idt_monitor_base, idt_monitor_size);
721
722 /* Entry into the IDT monitor is via fixed address vectors, and
723 not using machine instructions. To avoid clashing with use of
724 the MIPS TRAP system, we place our own (simulator specific)
725 "undefined" instructions into the relevant vector slots. */
726 for (loop = 0; (loop < idt_monitor_size); loop += 4)
727 {
728 address_word vaddr = (idt_monitor_base + loop);
729 unsigned32 insn = (RSVD_INSTRUCTION |
730 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
731 << RSVD_INSTRUCTION_ARG_SHIFT));
732 H2T (insn);
733 sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
734 }
735 }
736
737 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
738 {
739 /* The PMON monitor uses the same address space, but rather than
740 branching into it the address of a routine is loaded. We can
741 cheat for the moment, and direct the PMON routine to IDT style
742 instructions within the monitor space. This relies on the IDT
743 monitor not using the locations from 0xBFC00500 onwards as its
744 entry points.*/
745 unsigned loop;
746 for (loop = 0; (loop < 24); loop++)
747 {
748 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
749 switch (loop)
750 {
751 case 0: /* read */
752 value = 7;
753 break;
754 case 1: /* write */
755 value = 8;
756 break;
757 case 2: /* open */
758 value = 6;
759 break;
760 case 3: /* close */
761 value = 10;
762 break;
763 case 5: /* printf */
764 value = ((0x500 - 16) / 8); /* not an IDT reason code */
765 break;
766 case 8: /* cliexit */
767 value = 17;
768 break;
769 case 11: /* flush_cache */
770 value = 28;
771 break;
772 }
773
774 SIM_ASSERT (idt_monitor_base != 0);
775 value = ((unsigned int) idt_monitor_base + (value * 8));
776 H2T (value);
777
778 if (pmon_monitor_base != 0)
779 {
780 address_word vaddr = (pmon_monitor_base + (loop * 4));
781 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
782 }
783
784 if (lsipmon_monitor_base != 0)
785 {
786 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
787 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
788 }
789 }
790
791 /* Write an abort sequence into the TRAP (common) exception vector
792 addresses. This is to catch code executing a TRAP (et.al.)
793 instruction without installing a trap handler. */
794 if ((idt_monitor_base != 0) ||
795 (pmon_monitor_base != 0) ||
796 (lsipmon_monitor_base != 0))
797 {
798 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
799 HALT_INSTRUCTION /* BREAK */ };
800 H2T (halt[0]);
801 H2T (halt[1]);
802 sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
803 sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
804 sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
805 /* XXX: Write here unconditionally? */
806 sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
807 sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
808 sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
809 }
810 }
811
812 /* CPU specific initialization. */
813 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
814 {
815 SIM_CPU *cpu = STATE_CPU (sd, i);
816
817 CPU_PC_FETCH (cpu) = mips_pc_get;
818 CPU_PC_STORE (cpu) = mips_pc_set;
819 }
820
821 return sd;
822 }
823
824 #if defined(TRACE)
825 static void
826 open_trace (SIM_DESC sd)
827 {
828 tracefh = fopen(tracefile,"wb+");
829 if (tracefh == NULL)
830 {
831 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
832 tracefh = stderr;
833 }
834 }
835 #endif /* TRACE */
836
837 /* Return name of an insn, used by insn profiling. */
838 static const char *
839 get_insn_name (sim_cpu *cpu, int i)
840 {
841 return itable[i].name;
842 }
843
844 void
845 sim_close (SIM_DESC sd, int quitting)
846 {
847 #ifdef DEBUG
848 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
849 #endif
850
851
852 /* "quitting" is non-zero if we cannot hang on errors */
853
854 /* shut down modules */
855 sim_module_uninstall (sd);
856
857 /* Ensure that any resources allocated through the callback
858 mechanism are released: */
859 sim_io_shutdown (sd);
860
861 #if defined(TRACE)
862 if (tracefh != NULL && tracefh != stderr)
863 fclose(tracefh);
864 tracefh = NULL;
865 #endif /* TRACE */
866
867 /* FIXME - free SD */
868
869 return;
870 }
871
872
873 int
874 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
875 {
876 int index;
877 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
878
879 /* Return the number of bytes written, or zero if error. */
880 #ifdef DEBUG
881 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
882 #endif
883
884 /* We use raw read and write routines, since we do not want to count
885 the GDB memory accesses in our statistics gathering. */
886
887 for (index = 0; index < size; index++)
888 {
889 address_word vaddr = (address_word)addr + index;
890 address_word paddr;
891 int cca;
892 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
893 break;
894 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
895 break;
896 }
897
898 return(index);
899 }
900
901 int
902 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
903 {
904 int index;
905 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
906
907 /* Return the number of bytes read, or zero if error. */
908 #ifdef DEBUG
909 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
910 #endif /* DEBUG */
911
912 for (index = 0; (index < size); index++)
913 {
914 address_word vaddr = (address_word)addr + index;
915 address_word paddr;
916 int cca;
917 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
918 break;
919 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
920 break;
921 }
922
923 return(index);
924 }
925
926 int
927 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
928 {
929 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
930 /* NOTE: gdb (the client) stores registers in target byte order
931 while the simulator uses host byte order */
932 #ifdef DEBUG
933 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
934 #endif /* DEBUG */
935
936 /* Unfortunately this suffers from the same problem as the register
937 numbering one. We need to know what the width of each logical
938 register number is for the architecture being simulated. */
939
940 if (cpu->register_widths[rn] == 0)
941 {
942 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
943 return 0;
944 }
945
946
947
948 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
949 {
950 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
951 if (cpu->register_widths[rn] == 32)
952 {
953 if (length == 8)
954 {
955 cpu->fgr[rn - FGR_BASE] =
956 (unsigned32) T2H_8 (*(unsigned64*)memory);
957 return 8;
958 }
959 else
960 {
961 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
962 return 4;
963 }
964 }
965 else
966 {
967 if (length == 8)
968 {
969 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
970 return 8;
971 }
972 else
973 {
974 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
975 return 4;
976 }
977 }
978 }
979
980 if (cpu->register_widths[rn] == 32)
981 {
982 if (length == 8)
983 {
984 cpu->registers[rn] =
985 (unsigned32) T2H_8 (*(unsigned64*)memory);
986 return 8;
987 }
988 else
989 {
990 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
991 return 4;
992 }
993 }
994 else
995 {
996 if (length == 8)
997 {
998 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
999 return 8;
1000 }
1001 else
1002 {
1003 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
1004 return 4;
1005 }
1006 }
1007
1008 return 0;
1009 }
1010
1011 int
1012 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1013 {
1014 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
1015 /* NOTE: gdb (the client) stores registers in target byte order
1016 while the simulator uses host byte order */
1017 #ifdef DEBUG
1018 #if 0 /* FIXME: doesn't compile */
1019 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
1020 #endif
1021 #endif /* DEBUG */
1022
1023 if (cpu->register_widths[rn] == 0)
1024 {
1025 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
1026 return 0;
1027 }
1028
1029
1030
1031 /* Any floating point register */
1032 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
1033 {
1034 if (cpu->register_widths[rn] == 32)
1035 {
1036 if (length == 8)
1037 {
1038 *(unsigned64*)memory =
1039 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
1040 return 8;
1041 }
1042 else
1043 {
1044 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
1045 return 4;
1046 }
1047 }
1048 else
1049 {
1050 if (length == 8)
1051 {
1052 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
1053 return 8;
1054 }
1055 else
1056 {
1057 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
1058 return 4;
1059 }
1060 }
1061 }
1062
1063 if (cpu->register_widths[rn] == 32)
1064 {
1065 if (length == 8)
1066 {
1067 *(unsigned64*)memory =
1068 H2T_8 ((unsigned32) (cpu->registers[rn]));
1069 return 8;
1070 }
1071 else
1072 {
1073 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1074 return 4;
1075 }
1076 }
1077 else
1078 {
1079 if (length == 8)
1080 {
1081 *(unsigned64*)memory =
1082 H2T_8 ((unsigned64) (cpu->registers[rn]));
1083 return 8;
1084 }
1085 else
1086 {
1087 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1088 return 4;
1089 }
1090 }
1091
1092 return 0;
1093 }
1094
1095 SIM_RC
1096 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1097 {
1098
1099 #ifdef DEBUG
1100 #if 0 /* FIXME: doesn't compile */
1101 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1102 pr_addr(PC));
1103 #endif
1104 #endif /* DEBUG */
1105
1106 ColdReset(sd);
1107
1108 if (abfd != NULL)
1109 {
1110 /* override PC value set by ColdReset () */
1111 int cpu_nr;
1112 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1113 {
1114 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1115 CPU_PC_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1116 }
1117 }
1118
1119 #if 0 /* def DEBUG */
1120 if (argv || env)
1121 {
1122 /* We should really place the argv slot values into the argument
1123 registers, and onto the stack as required. However, this
1124 assumes that we have a stack defined, which is not
1125 necessarily true at the moment. */
1126 char **cptr;
1127 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1128 for (cptr = argv; (cptr && *cptr); cptr++)
1129 printf("DBG: arg \"%s\"\n",*cptr);
1130 }
1131 #endif /* DEBUG */
1132
1133 return SIM_RC_OK;
1134 }
1135
1136 /*---------------------------------------------------------------------------*/
1137 /*-- Private simulator support interface ------------------------------------*/
1138 /*---------------------------------------------------------------------------*/
1139
1140 /* Read a null terminated string from memory, return in a buffer */
1141 static char *
1142 fetch_str (SIM_DESC sd,
1143 address_word addr)
1144 {
1145 char *buf;
1146 int nr = 0;
1147 unsigned char null;
1148 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1149 nr++;
1150 buf = NZALLOC (char, nr + 1);
1151 sim_read (sd, addr, (unsigned char *)buf, nr);
1152 return buf;
1153 }
1154
1155
1156 /* Implements the "sim firmware" command:
1157 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1158 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1159 defaults to the normal address for that monitor.
1160 sim firmware none --- don't emulate any ROM monitor. Useful
1161 if you need a clean address space. */
1162 static SIM_RC
1163 sim_firmware_command (SIM_DESC sd, char *arg)
1164 {
1165 int address_present = 0;
1166 SIM_ADDR address;
1167
1168 /* Signal occurrence of this option. */
1169 firmware_option_p = 1;
1170
1171 /* Parse out the address, if present. */
1172 {
1173 char *p = strchr (arg, '@');
1174 if (p)
1175 {
1176 char *q;
1177 address_present = 1;
1178 p ++; /* skip over @ */
1179
1180 address = strtoul (p, &q, 0);
1181 if (*q != '\0')
1182 {
1183 sim_io_printf (sd, "Invalid address given to the"
1184 "`sim firmware NAME@ADDRESS' command: %s\n",
1185 p);
1186 return SIM_RC_FAIL;
1187 }
1188 }
1189 else
1190 {
1191 address_present = 0;
1192 address = -1; /* Dummy value. */
1193 }
1194 }
1195
1196 if (! strncmp (arg, "idt", 3))
1197 {
1198 idt_monitor_base = address_present ? address : 0xBFC00000;
1199 pmon_monitor_base = 0;
1200 lsipmon_monitor_base = 0;
1201 }
1202 else if (! strncmp (arg, "pmon", 4))
1203 {
1204 /* pmon uses indirect calls. Hook into implied idt. */
1205 pmon_monitor_base = address_present ? address : 0xBFC00500;
1206 idt_monitor_base = pmon_monitor_base - 0x500;
1207 lsipmon_monitor_base = 0;
1208 }
1209 else if (! strncmp (arg, "lsipmon", 7))
1210 {
1211 /* lsipmon uses indirect calls. Hook into implied idt. */
1212 pmon_monitor_base = 0;
1213 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1214 idt_monitor_base = lsipmon_monitor_base - 0x200;
1215 }
1216 else if (! strncmp (arg, "none", 4))
1217 {
1218 if (address_present)
1219 {
1220 sim_io_printf (sd,
1221 "The `sim firmware none' command does "
1222 "not take an `ADDRESS' argument.\n");
1223 return SIM_RC_FAIL;
1224 }
1225 idt_monitor_base = 0;
1226 pmon_monitor_base = 0;
1227 lsipmon_monitor_base = 0;
1228 }
1229 else
1230 {
1231 sim_io_printf (sd, "\
1232 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1233 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1234 arg);
1235 return SIM_RC_FAIL;
1236 }
1237
1238 return SIM_RC_OK;
1239 }
1240
1241
1242
1243 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1244 int
1245 sim_monitor (SIM_DESC sd,
1246 sim_cpu *cpu,
1247 address_word cia,
1248 unsigned int reason)
1249 {
1250 #ifdef DEBUG
1251 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1252 #endif /* DEBUG */
1253
1254 /* The IDT monitor actually allows two instructions per vector
1255 slot. However, the simulator currently causes a trap on each
1256 individual instruction. We cheat, and lose the bottom bit. */
1257 reason >>= 1;
1258
1259 /* The following callback functions are available, however the
1260 monitor we are simulating does not make use of them: get_errno,
1261 isatty, lseek, rename, system, time and unlink */
1262 switch (reason)
1263 {
1264
1265 case 6: /* int open(char *path,int flags) */
1266 {
1267 char *path = fetch_str (sd, A0);
1268 V0 = sim_io_open (sd, path, (int)A1);
1269 free (path);
1270 break;
1271 }
1272
1273 case 7: /* int read(int file,char *ptr,int len) */
1274 {
1275 int fd = A0;
1276 int nr = A2;
1277 char *buf = zalloc (nr);
1278 V0 = sim_io_read (sd, fd, buf, nr);
1279 sim_write (sd, A1, (unsigned char *)buf, nr);
1280 free (buf);
1281 }
1282 break;
1283
1284 case 8: /* int write(int file,char *ptr,int len) */
1285 {
1286 int fd = A0;
1287 int nr = A2;
1288 char *buf = zalloc (nr);
1289 sim_read (sd, A1, (unsigned char *)buf, nr);
1290 V0 = sim_io_write (sd, fd, buf, nr);
1291 if (fd == 1)
1292 sim_io_flush_stdout (sd);
1293 else if (fd == 2)
1294 sim_io_flush_stderr (sd);
1295 free (buf);
1296 break;
1297 }
1298
1299 case 10: /* int close(int file) */
1300 {
1301 V0 = sim_io_close (sd, (int)A0);
1302 break;
1303 }
1304
1305 case 2: /* Densan monitor: char inbyte(int waitflag) */
1306 {
1307 if (A0 == 0) /* waitflag == NOWAIT */
1308 V0 = (unsigned_word)-1;
1309 }
1310 /* Drop through to case 11 */
1311
1312 case 11: /* char inbyte(void) */
1313 {
1314 char tmp;
1315 /* ensure that all output has gone... */
1316 sim_io_flush_stdout (sd);
1317 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1318 {
1319 sim_io_error(sd,"Invalid return from character read");
1320 V0 = (unsigned_word)-1;
1321 }
1322 else
1323 V0 = (unsigned_word)tmp;
1324 break;
1325 }
1326
1327 case 3: /* Densan monitor: void co(char chr) */
1328 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1329 {
1330 char tmp = (char)(A0 & 0xFF);
1331 sim_io_write_stdout (sd, &tmp, sizeof(char));
1332 break;
1333 }
1334
1335 case 17: /* void _exit() */
1336 {
1337 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1338 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1339 (unsigned int)(A0 & 0xFFFFFFFF));
1340 break;
1341 }
1342
1343 case 28: /* PMON flush_cache */
1344 break;
1345
1346 case 55: /* void get_mem_info(unsigned int *ptr) */
1347 /* in: A0 = pointer to three word memory location */
1348 /* out: [A0 + 0] = size */
1349 /* [A0 + 4] = instruction cache size */
1350 /* [A0 + 8] = data cache size */
1351 {
1352 unsigned_4 value;
1353 unsigned_4 zero = 0;
1354 address_word mem_size;
1355 sim_memopt *entry, *match = NULL;
1356
1357 /* Search for memory region mapped to KSEG0 or KSEG1. */
1358 for (entry = STATE_MEMOPT (sd);
1359 entry != NULL;
1360 entry = entry->next)
1361 {
1362 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1363 && (!match || entry->level < match->level))
1364 match = entry;
1365 else
1366 {
1367 sim_memopt *alias;
1368 for (alias = entry->alias;
1369 alias != NULL;
1370 alias = alias->next)
1371 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1372 && (!match || entry->level < match->level))
1373 match = entry;
1374 }
1375 }
1376
1377 /* Get region size, limit to KSEG1 size (512MB). */
1378 SIM_ASSERT (match != NULL);
1379 mem_size = (match->modulo != 0
1380 ? match->modulo : match->nr_bytes);
1381 if (mem_size > K1SIZE)
1382 mem_size = K1SIZE;
1383
1384 value = mem_size;
1385 H2T (value);
1386 sim_write (sd, A0 + 0, (unsigned char *)&value, 4);
1387 sim_write (sd, A0 + 4, (unsigned char *)&zero, 4);
1388 sim_write (sd, A0 + 8, (unsigned char *)&zero, 4);
1389 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1390 break;
1391 }
1392
1393 case 158: /* PMON printf */
1394 /* in: A0 = pointer to format string */
1395 /* A1 = optional argument 1 */
1396 /* A2 = optional argument 2 */
1397 /* A3 = optional argument 3 */
1398 /* out: void */
1399 /* The following is based on the PMON printf source */
1400 {
1401 address_word s = A0;
1402 unsigned char c;
1403 signed_word *ap = &A1; /* 1st argument */
1404 /* This isn't the quickest way, since we call the host print
1405 routine for every character almost. But it does avoid
1406 having to allocate and manage a temporary string buffer. */
1407 /* TODO: Include check that we only use three arguments (A1,
1408 A2 and A3) */
1409 while (sim_read (sd, s++, &c, 1) && c != '\0')
1410 {
1411 if (c == '%')
1412 {
1413 char tmp[40];
1414 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1415 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1416 while (sim_read (sd, s++, &c, 1) && c != '\0')
1417 {
1418 if (strchr ("dobxXulscefg%", c))
1419 break;
1420 else if (c == '-')
1421 fmt = FMT_LJUST;
1422 else if (c == '0')
1423 fmt = FMT_RJUST0;
1424 else if (c == '~')
1425 fmt = FMT_CENTER;
1426 else if (c == '*')
1427 {
1428 if (haddot)
1429 trunc = (int)*ap++;
1430 else
1431 width = (int)*ap++;
1432 }
1433 else if (c >= '1' && c <= '9')
1434 {
1435 address_word t = s;
1436 unsigned int n;
1437 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1438 tmp[s - t] = c;
1439 tmp[s - t] = '\0';
1440 n = (unsigned int)strtol(tmp,NULL,10);
1441 if (haddot)
1442 trunc = n;
1443 else
1444 width = n;
1445 s--;
1446 }
1447 else if (c == '.')
1448 haddot = 1;
1449 }
1450 switch (c)
1451 {
1452 case '%':
1453 sim_io_printf (sd, "%%");
1454 break;
1455 case 's':
1456 if ((int)*ap != 0)
1457 {
1458 address_word p = *ap++;
1459 unsigned char ch;
1460 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1461 sim_io_printf(sd, "%c", ch);
1462 }
1463 else
1464 sim_io_printf(sd,"(null)");
1465 break;
1466 case 'c':
1467 sim_io_printf (sd, "%c", (int)*ap++);
1468 break;
1469 default:
1470 if (c == 'l')
1471 {
1472 sim_read (sd, s++, &c, 1);
1473 if (c == 'l')
1474 {
1475 longlong = 1;
1476 sim_read (sd, s++, &c, 1);
1477 }
1478 }
1479 if (strchr ("dobxXu", c))
1480 {
1481 word64 lv = (word64) *ap++;
1482 if (c == 'b')
1483 sim_io_printf(sd,"<binary not supported>");
1484 else
1485 {
1486 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1487 if (longlong)
1488 sim_io_printf(sd, tmp, lv);
1489 else
1490 sim_io_printf(sd, tmp, (int)lv);
1491 }
1492 }
1493 else if (strchr ("eEfgG", c))
1494 {
1495 double dbl = *(double*)(ap++);
1496 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1497 sim_io_printf (sd, tmp, dbl);
1498 trunc = 0;
1499 }
1500 }
1501 }
1502 else
1503 sim_io_printf(sd, "%c", c);
1504 }
1505 break;
1506 }
1507
1508 default:
1509 /* Unknown reason. */
1510 return 0;
1511 }
1512 return 1;
1513 }
1514
1515 /* Store a word into memory. */
1516
1517 static void
1518 store_word (SIM_DESC sd,
1519 sim_cpu *cpu,
1520 address_word cia,
1521 uword64 vaddr,
1522 signed_word val)
1523 {
1524 address_word paddr;
1525 int uncached;
1526
1527 if ((vaddr & 3) != 0)
1528 SignalExceptionAddressStore ();
1529 else
1530 {
1531 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1532 isTARGET, isREAL))
1533 {
1534 const uword64 mask = 7;
1535 uword64 memval;
1536 unsigned int byte;
1537
1538 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1539 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1540 memval = ((uword64) val) << (8 * byte);
1541 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1542 isREAL);
1543 }
1544 }
1545 }
1546
1547 /* Load a word from memory. */
1548
1549 static signed_word
1550 load_word (SIM_DESC sd,
1551 sim_cpu *cpu,
1552 address_word cia,
1553 uword64 vaddr)
1554 {
1555 if ((vaddr & 3) != 0)
1556 {
1557 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1558 }
1559 else
1560 {
1561 address_word paddr;
1562 int uncached;
1563
1564 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1565 isTARGET, isREAL))
1566 {
1567 const uword64 mask = 0x7;
1568 const unsigned int reverse = ReverseEndian ? 1 : 0;
1569 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1570 uword64 memval;
1571 unsigned int byte;
1572
1573 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1574 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1575 isDATA, isREAL);
1576 byte = (vaddr & mask) ^ (bigend << 2);
1577 return EXTEND32 (memval >> (8 * byte));
1578 }
1579 }
1580
1581 return 0;
1582 }
1583
1584 /* Simulate the mips16 entry and exit pseudo-instructions. These
1585 would normally be handled by the reserved instruction exception
1586 code, but for ease of simulation we just handle them directly. */
1587
1588 static void
1589 mips16_entry (SIM_DESC sd,
1590 sim_cpu *cpu,
1591 address_word cia,
1592 unsigned int insn)
1593 {
1594 int aregs, sregs, rreg;
1595
1596 #ifdef DEBUG
1597 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1598 #endif /* DEBUG */
1599
1600 aregs = (insn & 0x700) >> 8;
1601 sregs = (insn & 0x0c0) >> 6;
1602 rreg = (insn & 0x020) >> 5;
1603
1604 /* This should be checked by the caller. */
1605 if (sregs == 3)
1606 abort ();
1607
1608 if (aregs < 5)
1609 {
1610 int i;
1611 signed_word tsp;
1612
1613 /* This is the entry pseudo-instruction. */
1614
1615 for (i = 0; i < aregs; i++)
1616 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1617
1618 tsp = SP;
1619 SP -= 32;
1620
1621 if (rreg)
1622 {
1623 tsp -= 4;
1624 store_word (SD, CPU, cia, (uword64) tsp, RA);
1625 }
1626
1627 for (i = 0; i < sregs; i++)
1628 {
1629 tsp -= 4;
1630 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1631 }
1632 }
1633 else
1634 {
1635 int i;
1636 signed_word tsp;
1637
1638 /* This is the exit pseudo-instruction. */
1639
1640 tsp = SP + 32;
1641
1642 if (rreg)
1643 {
1644 tsp -= 4;
1645 RA = load_word (SD, CPU, cia, (uword64) tsp);
1646 }
1647
1648 for (i = 0; i < sregs; i++)
1649 {
1650 tsp -= 4;
1651 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1652 }
1653
1654 SP += 32;
1655
1656 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1657 {
1658 if (aregs == 5)
1659 {
1660 FGR[0] = WORD64LO (GPR[4]);
1661 FPR_STATE[0] = fmt_uninterpreted;
1662 }
1663 else if (aregs == 6)
1664 {
1665 FGR[0] = WORD64LO (GPR[5]);
1666 FGR[1] = WORD64LO (GPR[4]);
1667 FPR_STATE[0] = fmt_uninterpreted;
1668 FPR_STATE[1] = fmt_uninterpreted;
1669 }
1670 }
1671
1672 PC = RA;
1673 }
1674
1675 }
1676
1677 /*-- trace support ----------------------------------------------------------*/
1678
1679 /* The TRACE support is provided (if required) in the memory accessing
1680 routines. Since we are also providing the architecture specific
1681 features, the architecture simulation code can also deal with
1682 notifying the TRACE world of cache flushes, etc. Similarly we do
1683 not need to provide profiling support in the simulator engine,
1684 since we can sample in the instruction fetch control loop. By
1685 defining the TRACE manifest, we add tracing as a run-time
1686 option. */
1687
1688 #if defined(TRACE)
1689 /* Tracing by default produces "din" format (as required by
1690 dineroIII). Each line of such a trace file *MUST* have a din label
1691 and address field. The rest of the line is ignored, so comments can
1692 be included if desired. The first field is the label which must be
1693 one of the following values:
1694
1695 0 read data
1696 1 write data
1697 2 instruction fetch
1698 3 escape record (treated as unknown access type)
1699 4 escape record (causes cache flush)
1700
1701 The address field is a 32bit (lower-case) hexadecimal address
1702 value. The address should *NOT* be preceded by "0x".
1703
1704 The size of the memory transfer is not important when dealing with
1705 cache lines (as long as no more than a cache line can be
1706 transferred in a single operation :-), however more information
1707 could be given following the dineroIII requirement to allow more
1708 complete memory and cache simulators to provide better
1709 results. i.e. the University of Pisa has a cache simulator that can
1710 also take bus size and speed as (variable) inputs to calculate
1711 complete system performance (a much more useful ability when trying
1712 to construct an end product, rather than a processor). They
1713 currently have an ARM version of their tool called ChARM. */
1714
1715
1716 void
1717 dotrace (SIM_DESC sd,
1718 sim_cpu *cpu,
1719 FILE *tracefh,
1720 int type,
1721 SIM_ADDR address,
1722 int width,
1723 char *comment,...)
1724 {
1725 if (STATE & simTRACE) {
1726 va_list ap;
1727 fprintf(tracefh,"%d %s ; width %d ; ",
1728 type,
1729 pr_addr(address),
1730 width);
1731 va_start(ap,comment);
1732 vfprintf(tracefh,comment,ap);
1733 va_end(ap);
1734 fprintf(tracefh,"\n");
1735 }
1736 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1737 we may be generating 64bit ones, we should put the hi-32bits of the
1738 address into the comment field. */
1739
1740 /* TODO: Provide a buffer for the trace lines. We can then avoid
1741 performing writes until the buffer is filled, or the file is
1742 being closed. */
1743
1744 /* NOTE: We could consider adding a comment field to the "din" file
1745 produced using type 3 markers (unknown access). This would then
1746 allow information about the program that the "din" is for, and
1747 the MIPs world that was being simulated, to be placed into the
1748 trace file. */
1749
1750 return;
1751 }
1752 #endif /* TRACE */
1753
1754 /*---------------------------------------------------------------------------*/
1755 /*-- simulator engine -------------------------------------------------------*/
1756 /*---------------------------------------------------------------------------*/
1757
1758 static void
1759 ColdReset (SIM_DESC sd)
1760 {
1761 int cpu_nr;
1762 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1763 {
1764 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1765 /* RESET: Fixed PC address: */
1766 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1767 /* The reset vector address is in the unmapped, uncached memory space. */
1768
1769 SR &= ~(status_SR | status_TS | status_RP);
1770 SR |= (status_ERL | status_BEV);
1771
1772 /* Cheat and allow access to the complete register set immediately */
1773 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1774 && WITH_TARGET_WORD_BITSIZE == 64)
1775 SR |= status_FR; /* 64bit registers */
1776
1777 /* Ensure that any instructions with pending register updates are
1778 cleared: */
1779 PENDING_INVALIDATE();
1780
1781 /* Initialise the FPU registers to the unknown state */
1782 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1783 {
1784 int rn;
1785 for (rn = 0; (rn < 32); rn++)
1786 FPR_STATE[rn] = fmt_uninterpreted;
1787 }
1788
1789 /* Initialise the Config0 register. */
1790 C0_CONFIG = 0x80000000 /* Config1 present */
1791 | 2; /* KSEG0 uncached */
1792 if (WITH_TARGET_WORD_BITSIZE == 64)
1793 {
1794 /* FIXME Currently mips/sim-main.c:address_translation()
1795 truncates all addresses to 32-bits. */
1796 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1797 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1798 else
1799 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1800 }
1801 if (BigEndianMem)
1802 C0_CONFIG |= 0x00008000; /* Big Endian */
1803 }
1804 }
1805
1806
1807
1808
1809 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1810 /* Signal an exception condition. This will result in an exception
1811 that aborts the instruction. The instruction operation pseudocode
1812 will never see a return from this function call. */
1813
1814 void
1815 signal_exception (SIM_DESC sd,
1816 sim_cpu *cpu,
1817 address_word cia,
1818 int exception,...)
1819 {
1820 /* int vector; */
1821
1822 #ifdef DEBUG
1823 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1824 #endif /* DEBUG */
1825
1826 /* Ensure that any active atomic read/modify/write operation will fail: */
1827 LLBIT = 0;
1828
1829 /* Save registers before interrupt dispatching */
1830 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1831 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1832 #endif
1833
1834 switch (exception) {
1835
1836 case DebugBreakPoint:
1837 if (! (Debug & Debug_DM))
1838 {
1839 if (INDELAYSLOT())
1840 {
1841 CANCELDELAYSLOT();
1842
1843 Debug |= Debug_DBD; /* signaled from within in delay slot */
1844 DEPC = cia - 4; /* reference the branch instruction */
1845 }
1846 else
1847 {
1848 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1849 DEPC = cia;
1850 }
1851
1852 Debug |= Debug_DM; /* in debugging mode */
1853 Debug |= Debug_DBp; /* raising a DBp exception */
1854 PC = 0xBFC00200;
1855 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1856 }
1857 break;
1858
1859 case ReservedInstruction:
1860 {
1861 va_list ap;
1862 unsigned int instruction;
1863 va_start(ap,exception);
1864 instruction = va_arg(ap,unsigned int);
1865 va_end(ap);
1866 /* Provide simple monitor support using ReservedInstruction
1867 exceptions. The following code simulates the fixed vector
1868 entry points into the IDT monitor by causing a simulator
1869 trap, performing the monitor operation, and returning to
1870 the address held in the $ra register (standard PCS return
1871 address). This means we only need to pre-load the vector
1872 space with suitable instruction values. For systems were
1873 actual trap instructions are used, we would not need to
1874 perform this magic. */
1875 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1876 {
1877 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1878 if (!sim_monitor (SD, CPU, cia, reason))
1879 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1880
1881 /* NOTE: This assumes that a branch-and-link style
1882 instruction was used to enter the vector (which is the
1883 case with the current IDT monitor). */
1884 sim_engine_restart (SD, CPU, NULL, RA);
1885 }
1886 /* Look for the mips16 entry and exit instructions, and
1887 simulate a handler for them. */
1888 else if ((cia & 1) != 0
1889 && (instruction & 0xf81f) == 0xe809
1890 && (instruction & 0x0c0) != 0x0c0)
1891 {
1892 mips16_entry (SD, CPU, cia, instruction);
1893 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1894 }
1895 /* else fall through to normal exception processing */
1896 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1897 }
1898
1899 default:
1900 /* Store exception code into current exception id variable (used
1901 by exit code): */
1902
1903 /* TODO: If not simulating exceptions then stop the simulator
1904 execution. At the moment we always stop the simulation. */
1905
1906 #ifdef SUBTARGET_R3900
1907 /* update interrupt-related registers */
1908
1909 /* insert exception code in bits 6:2 */
1910 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1911 /* shift IE/KU history bits left */
1912 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1913
1914 if (STATE & simDELAYSLOT)
1915 {
1916 STATE &= ~simDELAYSLOT;
1917 CAUSE |= cause_BD;
1918 EPC = (cia - 4); /* reference the branch instruction */
1919 }
1920 else
1921 EPC = cia;
1922
1923 if (SR & status_BEV)
1924 PC = (signed)0xBFC00000 + 0x180;
1925 else
1926 PC = (signed)0x80000000 + 0x080;
1927 #else
1928 /* See figure 5-17 for an outline of the code below */
1929 if (! (SR & status_EXL))
1930 {
1931 CAUSE = (exception << 2);
1932 if (STATE & simDELAYSLOT)
1933 {
1934 STATE &= ~simDELAYSLOT;
1935 CAUSE |= cause_BD;
1936 EPC = (cia - 4); /* reference the branch instruction */
1937 }
1938 else
1939 EPC = cia;
1940 /* FIXME: TLB et.al. */
1941 /* vector = 0x180; */
1942 }
1943 else
1944 {
1945 CAUSE = (exception << 2);
1946 /* vector = 0x180; */
1947 }
1948 SR |= status_EXL;
1949 /* Store exception code into current exception id variable (used
1950 by exit code): */
1951
1952 if (SR & status_BEV)
1953 PC = (signed)0xBFC00200 + 0x180;
1954 else
1955 PC = (signed)0x80000000 + 0x180;
1956 #endif
1957
1958 switch ((CAUSE >> 2) & 0x1F)
1959 {
1960 case Interrupt:
1961 /* Interrupts arrive during event processing, no need to
1962 restart */
1963 return;
1964
1965 case NMIReset:
1966 /* Ditto */
1967 #ifdef SUBTARGET_3900
1968 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1969 PC = (signed)0xBFC00000;
1970 #endif /* SUBTARGET_3900 */
1971 return;
1972
1973 case TLBModification:
1974 case TLBLoad:
1975 case TLBStore:
1976 case AddressLoad:
1977 case AddressStore:
1978 case InstructionFetch:
1979 case DataReference:
1980 /* The following is so that the simulator will continue from the
1981 exception handler address. */
1982 sim_engine_halt (SD, CPU, NULL, PC,
1983 sim_stopped, SIM_SIGBUS);
1984
1985 case ReservedInstruction:
1986 case CoProcessorUnusable:
1987 PC = EPC;
1988 sim_engine_halt (SD, CPU, NULL, PC,
1989 sim_stopped, SIM_SIGILL);
1990
1991 case IntegerOverflow:
1992 case FPE:
1993 sim_engine_halt (SD, CPU, NULL, PC,
1994 sim_stopped, SIM_SIGFPE);
1995
1996 case BreakPoint:
1997 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1998 break;
1999
2000 case SystemCall:
2001 case Trap:
2002 sim_engine_restart (SD, CPU, NULL, PC);
2003 break;
2004
2005 case Watch:
2006 PC = EPC;
2007 sim_engine_halt (SD, CPU, NULL, PC,
2008 sim_stopped, SIM_SIGTRAP);
2009
2010 default: /* Unknown internal exception */
2011 PC = EPC;
2012 sim_engine_halt (SD, CPU, NULL, PC,
2013 sim_stopped, SIM_SIGABRT);
2014
2015 }
2016
2017 case SimulatorFault:
2018 {
2019 va_list ap;
2020 char *msg;
2021 va_start(ap,exception);
2022 msg = va_arg(ap,char *);
2023 va_end(ap);
2024 sim_engine_abort (SD, CPU, NULL_CIA,
2025 "FATAL: Simulator error \"%s\"\n",msg);
2026 }
2027 }
2028
2029 return;
2030 }
2031
2032
2033
2034 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2035 "UNPREDICTABLE" behaviour.
2036
2037 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2038 may vary from processor implementation to processor implementation,
2039 instruction to instruction, or as a function of time on the same
2040 implementation or instruction. Software can never depend on results
2041 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2042 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2043 0.95, page 2.)
2044
2045 For UNPREDICTABLE behaviour, we print a message, if possible print
2046 the offending instructions mips.igen instruction name (provided by
2047 the caller), and stop the simulator.
2048
2049 XXX FIXME: eventually, stopping the simulator should be made conditional
2050 on a command-line option. */
2051 void
2052 unpredictable_action(sim_cpu *cpu, address_word cia)
2053 {
2054 SIM_DESC sd = CPU_STATE(cpu);
2055
2056 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
2057 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
2058 }
2059
2060
2061 /*-- co-processor support routines ------------------------------------------*/
2062
2063 static int UNUSED
2064 CoProcPresent(unsigned int coproc_number)
2065 {
2066 /* Return TRUE if simulator provides a model for the given co-processor number */
2067 return(0);
2068 }
2069
2070 void
2071 cop_lw (SIM_DESC sd,
2072 sim_cpu *cpu,
2073 address_word cia,
2074 int coproc_num,
2075 int coproc_reg,
2076 unsigned int memword)
2077 {
2078 switch (coproc_num)
2079 {
2080 case 1:
2081 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2082 {
2083 #ifdef DEBUG
2084 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2085 #endif
2086 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
2087 break;
2088 }
2089
2090 default:
2091 #if 0 /* this should be controlled by a configuration option */
2092 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2093 #endif
2094 break;
2095 }
2096
2097 return;
2098 }
2099
2100 void
2101 cop_ld (SIM_DESC sd,
2102 sim_cpu *cpu,
2103 address_word cia,
2104 int coproc_num,
2105 int coproc_reg,
2106 uword64 memword)
2107 {
2108
2109 #ifdef DEBUG
2110 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2111 #endif
2112
2113 switch (coproc_num) {
2114 case 1:
2115 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2116 {
2117 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
2118 break;
2119 }
2120
2121 default:
2122 #if 0 /* this message should be controlled by a configuration option */
2123 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2124 #endif
2125 break;
2126 }
2127
2128 return;
2129 }
2130
2131
2132
2133
2134 unsigned int
2135 cop_sw (SIM_DESC sd,
2136 sim_cpu *cpu,
2137 address_word cia,
2138 int coproc_num,
2139 int coproc_reg)
2140 {
2141 unsigned int value = 0;
2142
2143 switch (coproc_num)
2144 {
2145 case 1:
2146 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2147 {
2148 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
2149 break;
2150 }
2151
2152 default:
2153 #if 0 /* should be controlled by configuration option */
2154 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2155 #endif
2156 break;
2157 }
2158
2159 return(value);
2160 }
2161
2162 uword64
2163 cop_sd (SIM_DESC sd,
2164 sim_cpu *cpu,
2165 address_word cia,
2166 int coproc_num,
2167 int coproc_reg)
2168 {
2169 uword64 value = 0;
2170 switch (coproc_num)
2171 {
2172 case 1:
2173 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2174 {
2175 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
2176 break;
2177 }
2178
2179 default:
2180 #if 0 /* should be controlled by configuration option */
2181 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2182 #endif
2183 break;
2184 }
2185
2186 return(value);
2187 }
2188
2189
2190
2191
2192 void
2193 decode_coproc (SIM_DESC sd,
2194 sim_cpu *cpu,
2195 address_word cia,
2196 unsigned int instruction)
2197 {
2198 int coprocnum = ((instruction >> 26) & 3);
2199
2200 switch (coprocnum)
2201 {
2202 case 0: /* standard CPU control and cache registers */
2203 {
2204 int code = ((instruction >> 21) & 0x1F);
2205 int rt = ((instruction >> 16) & 0x1F);
2206 int rd = ((instruction >> 11) & 0x1F);
2207 int tail = instruction & 0x3ff;
2208 /* R4000 Users Manual (second edition) lists the following CP0
2209 instructions:
2210 CODE><-RT><RD-><--TAIL--->
2211 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2212 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2213 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2214 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2215 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2216 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2217 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2218 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2219 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2220 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2221 */
2222 if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
2223 || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
2224 && tail == 0)
2225 {
2226 /* Clear double/single coprocessor move bit. */
2227 code &= ~1;
2228
2229 /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
2230
2231 switch (rd) /* NOTEs: Standard CP0 registers */
2232 {
2233 /* 0 = Index R4000 VR4100 VR4300 */
2234 /* 1 = Random R4000 VR4100 VR4300 */
2235 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2236 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2237 /* 4 = Context R4000 VR4100 VR4300 */
2238 /* 5 = PageMask R4000 VR4100 VR4300 */
2239 /* 6 = Wired R4000 VR4100 VR4300 */
2240 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2241 /* 9 = Count R4000 VR4100 VR4300 */
2242 /* 10 = EntryHi R4000 VR4100 VR4300 */
2243 /* 11 = Compare R4000 VR4100 VR4300 */
2244 /* 12 = SR R4000 VR4100 VR4300 */
2245 #ifdef SUBTARGET_R3900
2246 case 3:
2247 /* 3 = Config R3900 */
2248 case 7:
2249 /* 7 = Cache R3900 */
2250 case 15:
2251 /* 15 = PRID R3900 */
2252
2253 /* ignore */
2254 break;
2255
2256 case 8:
2257 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2258 if (code == 0x00)
2259 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
2260 else
2261 COP0_BADVADDR = GPR[rt];
2262 break;
2263
2264 #endif /* SUBTARGET_R3900 */
2265 case 12:
2266 if (code == 0x00)
2267 GPR[rt] = SR;
2268 else
2269 SR = GPR[rt];
2270 break;
2271 /* 13 = Cause R4000 VR4100 VR4300 */
2272 case 13:
2273 if (code == 0x00)
2274 GPR[rt] = CAUSE;
2275 else
2276 CAUSE = GPR[rt];
2277 break;
2278 /* 14 = EPC R4000 VR4100 VR4300 */
2279 case 14:
2280 if (code == 0x00)
2281 GPR[rt] = (signed_word) (signed_address) EPC;
2282 else
2283 EPC = GPR[rt];
2284 break;
2285 /* 15 = PRId R4000 VR4100 VR4300 */
2286 #ifdef SUBTARGET_R3900
2287 /* 16 = Debug */
2288 case 16:
2289 if (code == 0x00)
2290 GPR[rt] = Debug;
2291 else
2292 Debug = GPR[rt];
2293 break;
2294 #else
2295 /* 16 = Config R4000 VR4100 VR4300 */
2296 case 16:
2297 if (code == 0x00)
2298 GPR[rt] = C0_CONFIG;
2299 else
2300 /* only bottom three bits are writable */
2301 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
2302 break;
2303 #endif
2304 #ifdef SUBTARGET_R3900
2305 /* 17 = Debug */
2306 case 17:
2307 if (code == 0x00)
2308 GPR[rt] = DEPC;
2309 else
2310 DEPC = GPR[rt];
2311 break;
2312 #else
2313 /* 17 = LLAddr R4000 VR4100 VR4300 */
2314 #endif
2315 /* 18 = WatchLo R4000 VR4100 VR4300 */
2316 /* 19 = WatchHi R4000 VR4100 VR4300 */
2317 /* 20 = XContext R4000 VR4100 VR4300 */
2318 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2319 /* 27 = CacheErr R4000 VR4100 */
2320 /* 28 = TagLo R4000 VR4100 VR4300 */
2321 /* 29 = TagHi R4000 VR4100 VR4300 */
2322 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2323 if (STATE_VERBOSE_P(SD))
2324 sim_io_eprintf (SD,
2325 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2326 (unsigned long)cia);
2327 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2328 /* CPR[0,rd] = GPR[rt]; */
2329 default:
2330 if (code == 0x00)
2331 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2332 else
2333 COP0_GPR[rd] = GPR[rt];
2334 #if 0
2335 if (code == 0x00)
2336 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2337 else
2338 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2339 #endif
2340 }
2341 }
2342 else if ((code == 0x00 || code == 0x01)
2343 && rd == 16)
2344 {
2345 /* [D]MFC0 RT,C0_CONFIG,SEL */
2346 signed32 cfg = 0;
2347 switch (tail & 0x07)
2348 {
2349 case 0:
2350 cfg = C0_CONFIG;
2351 break;
2352 case 1:
2353 /* MIPS32 r/o Config1:
2354 Config2 present */
2355 cfg = 0x80000000;
2356 /* MIPS16 implemented.
2357 XXX How to check configuration? */
2358 cfg |= 0x0000004;
2359 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2360 /* MDMX & FPU implemented */
2361 cfg |= 0x00000021;
2362 break;
2363 case 2:
2364 /* MIPS32 r/o Config2:
2365 Config3 present. */
2366 cfg = 0x80000000;
2367 break;
2368 case 3:
2369 /* MIPS32 r/o Config3:
2370 SmartMIPS implemented. */
2371 cfg = 0x00000002;
2372 break;
2373 }
2374 GPR[rt] = cfg;
2375 }
2376 else if (code == 0x10 && (tail & 0x3f) == 0x18)
2377 {
2378 /* ERET */
2379 if (SR & status_ERL)
2380 {
2381 /* Oops, not yet available */
2382 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2383 PC = EPC;
2384 SR &= ~status_ERL;
2385 }
2386 else
2387 {
2388 PC = EPC;
2389 SR &= ~status_EXL;
2390 }
2391 }
2392 else if (code == 0x10 && (tail & 0x3f) == 0x10)
2393 {
2394 /* RFE */
2395 #ifdef SUBTARGET_R3900
2396 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2397
2398 /* shift IE/KU history bits right */
2399 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2400
2401 /* TODO: CACHE register */
2402 #endif /* SUBTARGET_R3900 */
2403 }
2404 else if (code == 0x10 && (tail & 0x3f) == 0x1F)
2405 {
2406 /* DERET */
2407 Debug &= ~Debug_DM;
2408 DELAYSLOT();
2409 DSPC = DEPC;
2410 }
2411 else
2412 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2413 /* TODO: When executing an ERET or RFE instruction we should
2414 clear LLBIT, to ensure that any out-standing atomic
2415 read/modify/write sequence fails. */
2416 }
2417 break;
2418
2419 case 2: /* co-processor 2 */
2420 {
2421 int handle = 0;
2422
2423
2424 if(! handle)
2425 {
2426 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2427 instruction,pr_addr(cia));
2428 }
2429 }
2430 break;
2431
2432 case 1: /* should not occur (FPU co-processor) */
2433 case 3: /* should not occur (FPU co-processor) */
2434 SignalException(ReservedInstruction,instruction);
2435 break;
2436 }
2437
2438 return;
2439 }
2440
2441
2442 /* This code copied from gdb's utils.c. Would like to share this code,
2443 but don't know of a common place where both could get to it. */
2444
2445 /* Temporary storage using circular buffer */
2446 #define NUMCELLS 16
2447 #define CELLSIZE 32
2448 static char*
2449 get_cell (void)
2450 {
2451 static char buf[NUMCELLS][CELLSIZE];
2452 static int cell=0;
2453 if (++cell>=NUMCELLS) cell=0;
2454 return buf[cell];
2455 }
2456
2457 /* Print routines to handle variable size regs, etc */
2458
2459 /* Eliminate warning from compiler on 32-bit systems */
2460 static int thirty_two = 32;
2461
2462 char*
2463 pr_addr (SIM_ADDR addr)
2464 {
2465 char *paddr_str=get_cell();
2466 switch (sizeof(addr))
2467 {
2468 case 8:
2469 sprintf(paddr_str,"%08lx%08lx",
2470 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2471 break;
2472 case 4:
2473 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2474 break;
2475 case 2:
2476 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2477 break;
2478 default:
2479 sprintf(paddr_str,"%x",addr);
2480 }
2481 return paddr_str;
2482 }
2483
2484 char*
2485 pr_uword64 (uword64 addr)
2486 {
2487 char *paddr_str=get_cell();
2488 sprintf(paddr_str,"%08lx%08lx",
2489 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2490 return paddr_str;
2491 }
2492
2493
2494 void
2495 mips_core_signal (SIM_DESC sd,
2496 sim_cpu *cpu,
2497 sim_cia cia,
2498 unsigned map,
2499 int nr_bytes,
2500 address_word addr,
2501 transfer_type transfer,
2502 sim_core_signals sig)
2503 {
2504 const char *copy = (transfer == read_transfer ? "read" : "write");
2505 address_word ip = CIA_ADDR (cia);
2506
2507 switch (sig)
2508 {
2509 case sim_core_unmapped_signal:
2510 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2511 nr_bytes, copy,
2512 (unsigned long) addr, (unsigned long) ip);
2513 COP0_BADVADDR = addr;
2514 SignalExceptionDataReference();
2515 break;
2516
2517 case sim_core_unaligned_signal:
2518 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2519 nr_bytes, copy,
2520 (unsigned long) addr, (unsigned long) ip);
2521 COP0_BADVADDR = addr;
2522 if(transfer == read_transfer)
2523 SignalExceptionAddressLoad();
2524 else
2525 SignalExceptionAddressStore();
2526 break;
2527
2528 default:
2529 sim_engine_abort (sd, cpu, cia,
2530 "mips_core_signal - internal error - bad switch");
2531 }
2532 }
2533
2534
2535 void
2536 mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2537 {
2538 ASSERT(cpu != NULL);
2539
2540 if(cpu->exc_suspended > 0)
2541 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2542
2543 PC = cia;
2544 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2545 cpu->exc_suspended = 0;
2546 }
2547
2548 void
2549 mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2550 {
2551 ASSERT(cpu != NULL);
2552
2553 if(cpu->exc_suspended > 0)
2554 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2555 cpu->exc_suspended, exception);
2556
2557 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2558 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2559 cpu->exc_suspended = exception;
2560 }
2561
2562 void
2563 mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2564 {
2565 ASSERT(cpu != NULL);
2566
2567 if(exception == 0 && cpu->exc_suspended > 0)
2568 {
2569 /* warn not for breakpoints */
2570 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2571 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2572 cpu->exc_suspended);
2573 }
2574 else if(exception != 0 && cpu->exc_suspended > 0)
2575 {
2576 if(exception != cpu->exc_suspended)
2577 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2578 cpu->exc_suspended, exception);
2579
2580 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2581 }
2582 else if(exception != 0 && cpu->exc_suspended == 0)
2583 {
2584 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2585 }
2586 cpu->exc_suspended = 0;
2587 }
2588
2589
2590 /*---------------------------------------------------------------------------*/
2591 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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