2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 /* This must come before any other includes. */
30 #include "sim-utils.h"
31 #include "sim-options.h"
32 #include "sim-assert.h"
34 #include "sim-signal.h"
48 #include "libiberty.h"
51 #include "sim/callback.h" /* GDB simulator callback interface */
52 #include "sim/sim.h" /* GDB simulator interface */
53 #include "sim-syscall.h" /* Simulator system call support */
55 char* pr_addr (SIM_ADDR addr
);
56 char* pr_uword64 (uword64 addr
);
59 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
64 /* The following reserved instruction value is used when a simulator
65 trap is required. NOTE: Care must be taken, since this value may be
66 used in later revisions of the MIPS ISA. */
68 #define RSVD_INSTRUCTION (0x00000039)
69 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
71 #define RSVD_INSTRUCTION_ARG_SHIFT 6
72 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
75 /* Bits in the Debug register */
76 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
77 #define Debug_DM 0x40000000 /* Debug Mode */
78 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
80 /*---------------------------------------------------------------------------*/
81 /*-- GDB simulator interface ------------------------------------------------*/
82 /*---------------------------------------------------------------------------*/
84 static void ColdReset (SIM_DESC sd
);
86 /*---------------------------------------------------------------------------*/
90 #define DELAYSLOT() {\
91 if (STATE & simDELAYSLOT)\
92 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
93 STATE |= simDELAYSLOT;\
96 #define JALDELAYSLOT() {\
98 STATE |= simJALDELAYSLOT;\
102 STATE &= ~simDELAYSLOT;\
103 STATE |= simSKIPNEXT;\
106 #define CANCELDELAYSLOT() {\
108 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
111 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
112 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
114 /* Note that the monitor code essentially assumes this layout of memory.
115 If you change these, change the monitor code, too. */
116 /* FIXME Currently addresses are truncated to 32-bits, see
117 mips/sim-main.c:address_translation(). If that changes, then these
118 values will need to be extended, and tested for more carefully. */
119 #define K0BASE (0x80000000)
120 #define K0SIZE (0x20000000)
121 #define K1BASE (0xA0000000)
122 #define K1SIZE (0x20000000)
124 /* Simple run-time monitor support.
126 We emulate the monitor by placing magic reserved instructions at
127 the monitor's entry points; when we hit these instructions, instead
128 of raising an exception (as we would normally), we look at the
129 instruction and perform the appropriate monitory operation.
131 `*_monitor_base' are the physical addresses at which the corresponding
132 monitor vectors are located. `0' means none. By default,
134 The RSVD_INSTRUCTION... macros specify the magic instructions we
135 use at the monitor entry points. */
136 static int firmware_option_p
= 0;
137 static SIM_ADDR idt_monitor_base
= 0xBFC00000;
138 static SIM_ADDR pmon_monitor_base
= 0xBFC00500;
139 static SIM_ADDR lsipmon_monitor_base
= 0xBFC00200;
141 static SIM_RC
sim_firmware_command (SIM_DESC sd
, char* arg
);
143 #define MEM_SIZE (8 << 20) /* 8 MBytes */
147 static char *tracefile
= "trace.din"; /* default filename for trace log */
148 FILE *tracefh
= NULL
;
149 static void open_trace (SIM_DESC sd
);
151 #define open_trace(sd)
154 static const char * get_insn_name (sim_cpu
*, int);
156 /* simulation target board. NULL=canonical */
157 static char* board
= NULL
;
160 static DECLARE_OPTION_HANDLER (mips_option_handler
);
163 OPTION_DINERO_TRACE
= OPTION_START
,
170 static int display_mem_info
= 0;
173 mips_option_handler (SIM_DESC sd
, sim_cpu
*cpu
, int opt
, char *arg
,
179 case OPTION_DINERO_TRACE
: /* ??? */
181 /* Eventually the simTRACE flag could be treated as a toggle, to
182 allow external control of the program points being traced
183 (i.e. only from main onwards, excluding the run-time setup,
185 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
187 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
190 else if (strcmp (arg
, "yes") == 0)
192 else if (strcmp (arg
, "no") == 0)
194 else if (strcmp (arg
, "on") == 0)
196 else if (strcmp (arg
, "off") == 0)
200 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
205 #else /* !WITH_TRACE_ANY_P */
207 Simulator constructed without dinero tracing support (for performance).\n\
208 Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
210 #endif /* !WITH_TRACE_ANY_P */
212 case OPTION_DINERO_FILE
:
214 if (optarg
!= NULL
) {
216 tmp
= (char *)malloc(strlen(optarg
) + 1);
219 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
225 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
228 #endif /* WITH_TRACE_ANY_P */
231 case OPTION_FIRMWARE
:
232 return sim_firmware_command (sd
, arg
);
238 board
= zalloc(strlen(arg
) + 1);
244 case OPTION_INFO_MEMORY
:
245 display_mem_info
= 1;
253 static const OPTION mips_options
[] =
255 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
256 '\0', "on|off", "Enable dinero tracing",
257 mips_option_handler
},
258 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
259 '\0', "FILE", "Write dinero trace to FILE",
260 mips_option_handler
},
261 { {"firmware", required_argument
, NULL
, OPTION_FIRMWARE
},
262 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
263 mips_option_handler
},
264 { {"board", required_argument
, NULL
, OPTION_BOARD
},
265 '\0', "none" /* rely on compile-time string concatenation for other options */
267 #define BOARD_JMR3904 "jmr3904"
269 #define BOARD_JMR3904_PAL "jmr3904pal"
270 "|" BOARD_JMR3904_PAL
271 #define BOARD_JMR3904_DEBUG "jmr3904debug"
272 "|" BOARD_JMR3904_DEBUG
273 #define BOARD_BSP "bsp"
276 , "Customize simulation for a particular board.", mips_option_handler
},
278 /* These next two options have the same names as ones found in the
279 memory_options[] array in common/sim-memopt.c. This is because
280 the intention is to provide an alternative handler for those two
281 options. We need an alternative handler because the memory
282 regions are not set up until after the command line arguments
283 have been parsed, and so we cannot display the memory info whilst
284 processing the command line. There is a hack in sim_open to
285 remove these handlers when we want the real --memory-info option
287 { { "info-memory", no_argument
, NULL
, OPTION_INFO_MEMORY
},
288 '\0', NULL
, "List configured memory regions", mips_option_handler
},
289 { { "memory-info", no_argument
, NULL
, OPTION_INFO_MEMORY
},
290 '\0', NULL
, NULL
, mips_option_handler
},
292 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
296 int interrupt_pending
;
299 interrupt_event (SIM_DESC sd
, void *data
)
301 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
302 address_word cia
= CPU_PC_GET (cpu
);
305 interrupt_pending
= 0;
306 SignalExceptionInterrupt (1); /* interrupt "1" */
308 else if (!interrupt_pending
)
309 sim_events_schedule (sd
, 1, interrupt_event
, data
);
313 /*---------------------------------------------------------------------------*/
314 /*-- Device registration hook -----------------------------------------------*/
315 /*---------------------------------------------------------------------------*/
316 static void device_init(SIM_DESC sd
) {
318 extern void register_devices(SIM_DESC
);
319 register_devices(sd
);
323 /*---------------------------------------------------------------------------*/
324 /*-- GDB simulator interface ------------------------------------------------*/
325 /*---------------------------------------------------------------------------*/
328 mips_pc_get (sim_cpu
*cpu
)
334 mips_pc_set (sim_cpu
*cpu
, sim_cia pc
)
339 static int mips_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
340 static int mips_reg_store (SIM_CPU
*, int, unsigned char *, int);
343 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
344 struct bfd
*abfd
, char * const *argv
)
347 SIM_DESC sd
= sim_state_alloc_extra (kind
, cb
,
348 sizeof (struct mips_sim_state
));
351 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
353 /* The cpu data is kept in a separately allocated chunk of memory. */
354 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
357 cpu
= STATE_CPU (sd
, 0); /* FIXME */
359 /* FIXME: watchpoints code shouldn't need this */
360 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
362 /* Initialize the mechanism for doing insn profiling. */
363 CPU_INSN_NAME (cpu
) = get_insn_name
;
364 CPU_MAX_INSNS (cpu
) = nr_itable_entries
;
368 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
370 sim_add_option_table (sd
, NULL
, mips_options
);
373 /* The parser will print an error message for us, so we silently return. */
374 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
376 /* Uninstall the modules to avoid memory leaks,
377 file descriptor leaks, etc. */
378 sim_module_uninstall (sd
);
382 /* handle board-specific memory maps */
385 /* Allocate core managed memory */
386 sim_memopt
*entry
, *match
= NULL
;
387 address_word mem_size
= 0;
390 /* For compatibility with the old code - under this (at level one)
391 are the kernel spaces K0 & K1. Both of these map to a single
392 smaller sub region */
393 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
395 /* Look for largest memory region defined on command-line at
397 for (entry
= STATE_MEMOPT (sd
); entry
!= NULL
; entry
= entry
->next
)
399 /* If we find an entry at address 0, then we will end up
400 allocating a new buffer in the "memory alias" command
401 below. The region at address 0 will be deleted. */
402 address_word size
= (entry
->modulo
!= 0
403 ? entry
->modulo
: entry
->nr_bytes
);
405 && (!match
|| entry
->level
< match
->level
))
407 else if (entry
->addr
== K0BASE
|| entry
->addr
== K1BASE
)
412 for (alias
= entry
->alias
; alias
!= NULL
; alias
= alias
->next
)
415 && (!match
|| entry
->level
< match
->level
))
417 else if (alias
->addr
== K0BASE
|| alias
->addr
== K1BASE
)
427 /* Get existing memory region size. */
428 mem_size
= (match
->modulo
!= 0
429 ? match
->modulo
: match
->nr_bytes
);
430 /* Delete old region. */
431 sim_do_commandf (sd
, "memory delete %d:0x%" PRIxTW
"@%d",
432 match
->space
, match
->addr
, match
->level
);
434 else if (mem_size
== 0)
436 /* Limit to KSEG1 size (512MB) */
437 if (mem_size
> K1SIZE
)
439 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
440 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x%%0x%lx,0x%0x",
441 K1BASE
, K1SIZE
, (long)mem_size
, K0BASE
);
442 if (WITH_TARGET_WORD_BITSIZE
== 64)
443 sim_do_commandf (sd
, "memory alias 0x%x,0x%" PRIxTW
",0x%" PRIxTA
,
444 (K0BASE
), mem_size
, EXTENDED(K0BASE
));
449 else if (board
!= NULL
450 && (strcmp(board
, BOARD_BSP
) == 0))
454 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
456 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
457 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x,0x%0x",
459 4 * 1024 * 1024, /* 4 MB */
462 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
463 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x,0x%0x",
465 4 * 1024 * 1024, /* 4 MB */
468 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
469 for (i
=0; i
<8; i
++) /* 32 MB total */
471 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
472 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x,0x%0x",
473 0x88000000 + (i
* size
),
475 0xA8000000 + (i
* size
));
479 else if (board
!= NULL
480 && (strcmp(board
, BOARD_JMR3904
) == 0 ||
481 strcmp(board
, BOARD_JMR3904_PAL
) == 0 ||
482 strcmp(board
, BOARD_JMR3904_DEBUG
) == 0))
484 /* match VIRTUAL memory layout of JMR-TX3904 board */
487 /* --- disable monitor unless forced on by user --- */
489 if (! firmware_option_p
)
491 idt_monitor_base
= 0;
492 pmon_monitor_base
= 0;
493 lsipmon_monitor_base
= 0;
496 /* --- environment --- */
498 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
502 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
503 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x,0x%0x",
505 4 * 1024 * 1024, /* 4 MB */
508 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
509 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x,0x%0x",
511 4 * 1024 * 1024, /* 4 MB */
514 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
515 for (i
=0; i
<8; i
++) /* 32 MB total */
517 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
518 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x,0x%0x",
519 0x88000000 + (i
* size
),
521 0xA8000000 + (i
* size
));
524 /* Dummy memory regions for unsimulated devices - sorted by address */
526 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xB1000000, 0x400); /* ISA I/O */
527 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xB2100000, 0x004); /* ISA ctl */
528 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xB2500000, 0x004); /* LED/switch */
529 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xB2700000, 0x004); /* RTC */
530 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xB3C00000, 0x004); /* RTC */
531 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xFFFF8000, 0x900); /* DRAMC */
532 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xFFFF9000, 0x200); /* EBIF */
533 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xFFFFE000, 0x01c); /* EBIF */
534 sim_do_commandf (sd
, "memory alias 0x%x@1,0x%x", 0xFFFFF500, 0x300); /* PIO */
537 /* --- simulated devices --- */
538 sim_hw_parse (sd
, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
539 sim_hw_parse (sd
, "/tx3904cpu");
540 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
541 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
542 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
543 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
545 /* FIXME: poking at dv-sockser internals, use tcp backend if
546 --sockser_addr option was given.*/
547 #ifdef HAVE_DV_SOCKSER
548 extern char* sockser_addr
;
550 # define sockser_addr NULL
552 if (sockser_addr
== NULL
)
553 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend stdio");
555 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend tcp");
557 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
558 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/backend stdio");
560 /* -- device connections --- */
561 sim_hw_parse (sd
, "/tx3904irc > ip level /tx3904cpu");
562 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
563 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
564 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
565 sim_hw_parse (sd
, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
566 sim_hw_parse (sd
, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
568 /* add PAL timer & I/O module */
569 if(! strcmp(board
, BOARD_JMR3904_PAL
))
572 sim_hw_parse (sd
, "/pal@0xffff0000");
573 sim_hw_parse (sd
, "/pal@0xffff0000/reg 0xffff0000 64");
575 /* wire up interrupt ports to irc */
576 sim_hw_parse (sd
, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
577 sim_hw_parse (sd
, "/pal@0x31000000 > timer tmr1 /tx3904irc");
578 sim_hw_parse (sd
, "/pal@0x31000000 > int int0 /tx3904irc");
581 if(! strcmp(board
, BOARD_JMR3904_DEBUG
))
583 /* -- DEBUG: glue interrupt generators --- */
584 sim_hw_parse (sd
, "/glue@0xffff0000/reg 0xffff0000 0x50");
585 sim_hw_parse (sd
, "/glue@0xffff0000 > int0 int0 /tx3904irc");
586 sim_hw_parse (sd
, "/glue@0xffff0000 > int1 int1 /tx3904irc");
587 sim_hw_parse (sd
, "/glue@0xffff0000 > int2 int2 /tx3904irc");
588 sim_hw_parse (sd
, "/glue@0xffff0000 > int3 int3 /tx3904irc");
589 sim_hw_parse (sd
, "/glue@0xffff0000 > int4 int4 /tx3904irc");
590 sim_hw_parse (sd
, "/glue@0xffff0000 > int5 int5 /tx3904irc");
591 sim_hw_parse (sd
, "/glue@0xffff0000 > int6 int6 /tx3904irc");
592 sim_hw_parse (sd
, "/glue@0xffff0000 > int7 int7 /tx3904irc");
593 sim_hw_parse (sd
, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
594 sim_hw_parse (sd
, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
595 sim_hw_parse (sd
, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
596 sim_hw_parse (sd
, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
597 sim_hw_parse (sd
, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
598 sim_hw_parse (sd
, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
599 sim_hw_parse (sd
, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
600 sim_hw_parse (sd
, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
601 sim_hw_parse (sd
, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
602 sim_hw_parse (sd
, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
609 if (display_mem_info
)
611 struct option_list
* ol
;
612 struct option_list
* prev
;
614 /* This is a hack. We want to execute the real --memory-info command
615 line switch which is handled in common/sim-memopts.c, not the
616 override we have defined in this file. So we remove the
617 mips_options array from the state options list. This is safe
618 because we have now processed all of the command line. */
619 for (ol
= STATE_OPTIONS (sd
), prev
= NULL
;
621 prev
= ol
, ol
= ol
->next
)
622 if (ol
->options
== mips_options
)
625 SIM_ASSERT (ol
!= NULL
);
628 STATE_OPTIONS (sd
) = ol
->next
;
630 prev
->next
= ol
->next
;
632 sim_do_commandf (sd
, "memory-info");
635 /* check for/establish the a reference program image */
636 if (sim_analyze_program (sd
,
637 (STATE_PROG_ARGV (sd
) != NULL
638 ? *STATE_PROG_ARGV (sd
)
642 sim_module_uninstall (sd
);
646 /* Configure/verify the target byte order and other runtime
647 configuration options */
648 if (sim_config (sd
) != SIM_RC_OK
)
650 sim_module_uninstall (sd
);
654 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
656 /* Uninstall the modules to avoid memory leaks,
657 file descriptor leaks, etc. */
658 sim_module_uninstall (sd
);
662 /* verify assumptions the simulator made about the host type system.
663 This macro does not return if there is a problem */
664 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
665 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
667 /* This is NASTY, in that we are assuming the size of specific
671 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
674 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
675 else if ((rn
>= FGR_BASE
) && (rn
< (FGR_BASE
+ NR_FGR
)))
676 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
677 else if ((rn
>= 33) && (rn
<= 37))
678 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
679 else if ((rn
== SRIDX
)
682 || ((rn
>= 72) && (rn
<= 89)))
683 cpu
->register_widths
[rn
] = 32;
685 cpu
->register_widths
[rn
] = 0;
691 if (STATE
& simTRACE
)
695 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
698 lsipmon_monitor_base);
701 /* Write the monitor trap address handlers into the monitor (eeprom)
702 address space. This can only be done once the target endianness
703 has been determined. */
704 if (idt_monitor_base
!= 0)
707 address_word idt_monitor_size
= 1 << 11;
709 /* the default monitor region */
710 if (WITH_TARGET_WORD_BITSIZE
== 64)
711 sim_do_commandf (sd
, "memory alias 0x%x,0x%" PRIxTW
",0x%" PRIxTA
,
712 idt_monitor_base
, idt_monitor_size
,
713 EXTENDED (idt_monitor_base
));
715 sim_do_commandf (sd
, "memory region 0x%x,0x%" PRIxTA
,
716 idt_monitor_base
, idt_monitor_size
);
718 /* Entry into the IDT monitor is via fixed address vectors, and
719 not using machine instructions. To avoid clashing with use of
720 the MIPS TRAP system, we place our own (simulator specific)
721 "undefined" instructions into the relevant vector slots. */
722 for (loop
= 0; (loop
< idt_monitor_size
); loop
+= 4)
724 address_word vaddr
= (idt_monitor_base
+ loop
);
725 unsigned32 insn
= (RSVD_INSTRUCTION
|
726 (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
)
727 << RSVD_INSTRUCTION_ARG_SHIFT
));
729 sim_write (sd
, vaddr
, (unsigned char *)&insn
, sizeof (insn
));
733 if ((pmon_monitor_base
!= 0) || (lsipmon_monitor_base
!= 0))
735 /* The PMON monitor uses the same address space, but rather than
736 branching into it the address of a routine is loaded. We can
737 cheat for the moment, and direct the PMON routine to IDT style
738 instructions within the monitor space. This relies on the IDT
739 monitor not using the locations from 0xBFC00500 onwards as its
742 for (loop
= 0; (loop
< 24); loop
++)
744 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
760 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
762 case 8: /* cliexit */
765 case 11: /* flush_cache */
770 SIM_ASSERT (idt_monitor_base
!= 0);
771 value
= ((unsigned int) idt_monitor_base
+ (value
* 8));
774 if (pmon_monitor_base
!= 0)
776 address_word vaddr
= (pmon_monitor_base
+ (loop
* 4));
777 sim_write (sd
, vaddr
, (unsigned char *)&value
, sizeof (value
));
780 if (lsipmon_monitor_base
!= 0)
782 address_word vaddr
= (lsipmon_monitor_base
+ (loop
* 4));
783 sim_write (sd
, vaddr
, (unsigned char *)&value
, sizeof (value
));
787 /* Write an abort sequence into the TRAP (common) exception vector
788 addresses. This is to catch code executing a TRAP (et.al.)
789 instruction without installing a trap handler. */
790 if ((idt_monitor_base
!= 0) ||
791 (pmon_monitor_base
!= 0) ||
792 (lsipmon_monitor_base
!= 0))
794 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
795 HALT_INSTRUCTION
/* BREAK */ };
798 sim_write (sd
, 0x80000000, (unsigned char *) halt
, sizeof (halt
));
799 sim_write (sd
, 0x80000180, (unsigned char *) halt
, sizeof (halt
));
800 sim_write (sd
, 0x80000200, (unsigned char *) halt
, sizeof (halt
));
801 /* XXX: Write here unconditionally? */
802 sim_write (sd
, 0xBFC00200, (unsigned char *) halt
, sizeof (halt
));
803 sim_write (sd
, 0xBFC00380, (unsigned char *) halt
, sizeof (halt
));
804 sim_write (sd
, 0xBFC00400, (unsigned char *) halt
, sizeof (halt
));
808 /* CPU specific initialization. */
809 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
811 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
813 CPU_REG_FETCH (cpu
) = mips_reg_fetch
;
814 CPU_REG_STORE (cpu
) = mips_reg_store
;
815 CPU_PC_FETCH (cpu
) = mips_pc_get
;
816 CPU_PC_STORE (cpu
) = mips_pc_set
;
824 open_trace (SIM_DESC sd
)
826 tracefh
= fopen(tracefile
,"wb+");
829 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
835 /* Return name of an insn, used by insn profiling. */
837 get_insn_name (sim_cpu
*cpu
, int i
)
839 return itable
[i
].name
;
843 mips_sim_close (SIM_DESC sd
, int quitting
)
846 if (tracefh
!= NULL
&& tracefh
!= stderr
)
853 mips_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
855 /* NOTE: gdb (the client) stores registers in target byte order
856 while the simulator uses host byte order */
858 /* Unfortunately this suffers from the same problem as the register
859 numbering one. We need to know what the width of each logical
860 register number is for the architecture being simulated. */
862 if (cpu
->register_widths
[rn
] == 0)
864 sim_io_eprintf (CPU_STATE (cpu
), "Invalid register width for %d (register store ignored)\n", rn
);
868 if (rn
>= FGR_BASE
&& rn
< FGR_BASE
+ NR_FGR
)
870 cpu
->fpr_state
[rn
- FGR_BASE
] = fmt_uninterpreted
;
871 if (cpu
->register_widths
[rn
] == 32)
875 cpu
->fgr
[rn
- FGR_BASE
] =
876 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
881 cpu
->fgr
[rn
- FGR_BASE
] = T2H_4 (*(unsigned32
*)memory
);
889 cpu
->fgr
[rn
- FGR_BASE
] = T2H_8 (*(unsigned64
*)memory
);
894 cpu
->fgr
[rn
- FGR_BASE
] = T2H_4 (*(unsigned32
*)memory
);
900 if (cpu
->register_widths
[rn
] == 32)
905 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
910 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
918 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
923 cpu
->registers
[rn
] = (signed32
) T2H_4(*(unsigned32
*)memory
);
932 mips_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
934 /* NOTE: gdb (the client) stores registers in target byte order
935 while the simulator uses host byte order */
937 if (cpu
->register_widths
[rn
] == 0)
939 sim_io_eprintf (CPU_STATE (cpu
), "Invalid register width for %d (register fetch ignored)\n", rn
);
943 /* Any floating point register */
944 if (rn
>= FGR_BASE
&& rn
< FGR_BASE
+ NR_FGR
)
946 if (cpu
->register_widths
[rn
] == 32)
950 *(unsigned64
*)memory
=
951 H2T_8 ((unsigned32
) (cpu
->fgr
[rn
- FGR_BASE
]));
956 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGR_BASE
]);
964 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGR_BASE
]);
969 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->fgr
[rn
- FGR_BASE
]));
975 if (cpu
->register_widths
[rn
] == 32)
979 *(unsigned64
*)memory
=
980 H2T_8 ((unsigned32
) (cpu
->registers
[rn
]));
985 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
993 *(unsigned64
*)memory
=
994 H2T_8 ((unsigned64
) (cpu
->registers
[rn
]));
999 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
1008 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1009 char * const *argv
, char * const *env
)
1013 #if 0 /* FIXME: doesn't compile */
1014 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1023 /* override PC value set by ColdReset () */
1025 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1027 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1028 sim_cia pc
= bfd_get_start_address (abfd
);
1030 /* The 64-bit BFD sign-extends MIPS addresses to model
1031 32-bit compatibility segments with 64-bit addressing.
1032 These addresses work as is on 64-bit targets but
1033 can be truncated for 32-bit targets. */
1034 if (WITH_TARGET_WORD_BITSIZE
== 32)
1035 pc
= (unsigned32
) pc
;
1037 CPU_PC_SET (cpu
, pc
);
1041 #if 0 /* def DEBUG */
1044 /* We should really place the argv slot values into the argument
1045 registers, and onto the stack as required. However, this
1046 assumes that we have a stack defined, which is not
1047 necessarily true at the moment. */
1049 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1050 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1051 printf("DBG: arg \"%s\"\n",*cptr
);
1058 /*---------------------------------------------------------------------------*/
1059 /*-- Private simulator support interface ------------------------------------*/
1060 /*---------------------------------------------------------------------------*/
1062 /* Read a null terminated string from memory, return in a buffer */
1064 fetch_str (SIM_DESC sd
,
1070 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1072 buf
= NZALLOC (char, nr
+ 1);
1073 sim_read (sd
, addr
, (unsigned char *)buf
, nr
);
1078 /* Implements the "sim firmware" command:
1079 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1080 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1081 defaults to the normal address for that monitor.
1082 sim firmware none --- don't emulate any ROM monitor. Useful
1083 if you need a clean address space. */
1085 sim_firmware_command (SIM_DESC sd
, char *arg
)
1087 int address_present
= 0;
1090 /* Signal occurrence of this option. */
1091 firmware_option_p
= 1;
1093 /* Parse out the address, if present. */
1095 char *p
= strchr (arg
, '@');
1099 address_present
= 1;
1100 p
++; /* skip over @ */
1102 address
= strtoul (p
, &q
, 0);
1105 sim_io_printf (sd
, "Invalid address given to the"
1106 "`sim firmware NAME@ADDRESS' command: %s\n",
1113 address_present
= 0;
1114 address
= -1; /* Dummy value. */
1118 if (! strncmp (arg
, "idt", 3))
1120 idt_monitor_base
= address_present
? address
: 0xBFC00000;
1121 pmon_monitor_base
= 0;
1122 lsipmon_monitor_base
= 0;
1124 else if (! strncmp (arg
, "pmon", 4))
1126 /* pmon uses indirect calls. Hook into implied idt. */
1127 pmon_monitor_base
= address_present
? address
: 0xBFC00500;
1128 idt_monitor_base
= pmon_monitor_base
- 0x500;
1129 lsipmon_monitor_base
= 0;
1131 else if (! strncmp (arg
, "lsipmon", 7))
1133 /* lsipmon uses indirect calls. Hook into implied idt. */
1134 pmon_monitor_base
= 0;
1135 lsipmon_monitor_base
= address_present
? address
: 0xBFC00200;
1136 idt_monitor_base
= lsipmon_monitor_base
- 0x200;
1138 else if (! strncmp (arg
, "none", 4))
1140 if (address_present
)
1143 "The `sim firmware none' command does "
1144 "not take an `ADDRESS' argument.\n");
1147 idt_monitor_base
= 0;
1148 pmon_monitor_base
= 0;
1149 lsipmon_monitor_base
= 0;
1153 sim_io_printf (sd
, "\
1154 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1155 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1163 /* stat structures from MIPS32/64. */
1164 static const char stat32_map
[] =
1165 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1166 ":st_rdev,2:st_size,4:st_atime,4:st_spare1,4:st_mtime,4:st_spare2,4"
1167 ":st_ctime,4:st_spare3,4:st_blksize,4:st_blocks,4:st_spare4,8";
1169 static const char stat64_map
[] =
1170 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1171 ":st_rdev,2:st_size,8:st_atime,8:st_spare1,8:st_mtime,8:st_spare2,8"
1172 ":st_ctime,8:st_spare3,8:st_blksize,8:st_blocks,8:st_spare4,16";
1174 /* Map for calls using the host struct stat. */
1175 static const CB_TARGET_DEFS_MAP CB_stat_map
[] =
1177 { "stat", CB_SYS_stat
, 15 },
1182 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1184 sim_monitor (SIM_DESC sd
,
1187 unsigned int reason
)
1190 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1193 /* The IDT monitor actually allows two instructions per vector
1194 slot. However, the simulator currently causes a trap on each
1195 individual instruction. We cheat, and lose the bottom bit. */
1198 /* The following callback functions are available, however the
1199 monitor we are simulating does not make use of them: get_errno,
1200 isatty, rename, system and time. */
1204 case 6: /* int open(char *path,int flags) */
1206 char *path
= fetch_str (sd
, A0
);
1207 V0
= sim_io_open (sd
, path
, (int)A1
);
1212 case 7: /* int read(int file,char *ptr,int len) */
1216 char *buf
= zalloc (nr
);
1217 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1218 sim_write (sd
, A1
, (unsigned char *)buf
, nr
);
1223 case 8: /* int write(int file,char *ptr,int len) */
1227 char *buf
= zalloc (nr
);
1228 sim_read (sd
, A1
, (unsigned char *)buf
, nr
);
1229 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1231 sim_io_flush_stdout (sd
);
1233 sim_io_flush_stderr (sd
);
1238 case 10: /* int close(int file) */
1240 V0
= sim_io_close (sd
, (int)A0
);
1244 case 2: /* Densan monitor: char inbyte(int waitflag) */
1246 if (A0
== 0) /* waitflag == NOWAIT */
1247 V0
= (unsigned_word
)-1;
1249 /* Drop through to case 11 */
1251 case 11: /* char inbyte(void) */
1254 /* ensure that all output has gone... */
1255 sim_io_flush_stdout (sd
);
1256 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1258 sim_io_error(sd
,"Invalid return from character read");
1259 V0
= (unsigned_word
)-1;
1262 V0
= (unsigned_word
)tmp
;
1266 case 3: /* Densan monitor: void co(char chr) */
1267 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1269 char tmp
= (char)(A0
& 0xFF);
1270 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1274 case 13: /* int unlink(const char *path) */
1276 char *path
= fetch_str (sd
, A0
);
1277 V0
= sim_io_unlink (sd
, path
);
1282 case 14: /* int lseek(int fd, int offset, int whence) */
1284 V0
= sim_io_lseek (sd
, A0
, A1
, A2
);
1288 case 15: /* int stat(const char *path, struct stat *buf); */
1290 /* As long as the infrastructure doesn't cache anything
1291 related to the stat mapping, this trick gets us a dual
1292 "struct stat"-type mapping in the least error-prone way. */
1293 host_callback
*cb
= STATE_CALLBACK (sd
);
1294 const char *saved_map
= cb
->stat_map
;
1295 CB_TARGET_DEFS_MAP
*saved_syscall_map
= cb
->syscall_map
;
1296 bfd
*prog_bfd
= STATE_PROG_BFD (sd
);
1297 int is_elf32bit
= (elf_elfheader(prog_bfd
)->e_ident
[EI_CLASS
] ==
1299 static CB_SYSCALL s
;
1300 CB_SYSCALL_INIT (&s
);
1302 /* Mask out the sign extension part for 64-bit targets because the
1303 MIPS simulator's memory model is still 32-bit. */
1304 s
.arg1
= A0
& 0xFFFFFFFF;
1305 s
.arg2
= A1
& 0xFFFFFFFF;
1308 s
.read_mem
= sim_syscall_read_mem
;
1309 s
.write_mem
= sim_syscall_write_mem
;
1311 cb
->syscall_map
= (CB_TARGET_DEFS_MAP
*) CB_stat_map
;
1312 cb
->stat_map
= is_elf32bit
? stat32_map
: stat64_map
;
1314 if (cb_syscall (cb
, &s
) != CB_RC_OK
)
1315 sim_engine_halt (sd
, cpu
, NULL
, mips_pc_get (cpu
),
1316 sim_stopped
, SIM_SIGILL
);
1319 cb
->stat_map
= saved_map
;
1320 cb
->syscall_map
= saved_syscall_map
;
1324 case 17: /* void _exit() */
1326 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1327 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1328 (unsigned int)(A0
& 0xFFFFFFFF));
1332 case 28: /* PMON flush_cache */
1335 case 55: /* void get_mem_info(unsigned int *ptr) */
1336 /* in: A0 = pointer to three word memory location */
1337 /* out: [A0 + 0] = size */
1338 /* [A0 + 4] = instruction cache size */
1339 /* [A0 + 8] = data cache size */
1342 unsigned_4 zero
= 0;
1343 address_word mem_size
;
1344 sim_memopt
*entry
, *match
= NULL
;
1346 /* Search for memory region mapped to KSEG0 or KSEG1. */
1347 for (entry
= STATE_MEMOPT (sd
);
1349 entry
= entry
->next
)
1351 if ((entry
->addr
== K0BASE
|| entry
->addr
== K1BASE
)
1352 && (!match
|| entry
->level
< match
->level
))
1357 for (alias
= entry
->alias
;
1359 alias
= alias
->next
)
1360 if ((alias
->addr
== K0BASE
|| alias
->addr
== K1BASE
)
1361 && (!match
|| entry
->level
< match
->level
))
1366 /* Get region size, limit to KSEG1 size (512MB). */
1367 SIM_ASSERT (match
!= NULL
);
1368 mem_size
= (match
->modulo
!= 0
1369 ? match
->modulo
: match
->nr_bytes
);
1370 if (mem_size
> K1SIZE
)
1375 sim_write (sd
, A0
+ 0, (unsigned char *)&value
, 4);
1376 sim_write (sd
, A0
+ 4, (unsigned char *)&zero
, 4);
1377 sim_write (sd
, A0
+ 8, (unsigned char *)&zero
, 4);
1378 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1382 case 158: /* PMON printf */
1383 /* in: A0 = pointer to format string */
1384 /* A1 = optional argument 1 */
1385 /* A2 = optional argument 2 */
1386 /* A3 = optional argument 3 */
1388 /* The following is based on the PMON printf source */
1390 address_word s
= A0
;
1392 address_word
*ap
= &A1
; /* 1st argument */
1393 /* This isn't the quickest way, since we call the host print
1394 routine for every character almost. But it does avoid
1395 having to allocate and manage a temporary string buffer. */
1396 /* TODO: Include check that we only use three arguments (A1,
1398 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1403 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1404 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1405 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1407 if (strchr ("dobxXulscefg%", c
))
1422 else if (c
>= '1' && c
<= '9')
1426 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1429 n
= (unsigned int)strtol(tmp
,NULL
,10);
1442 sim_io_printf (sd
, "%%");
1447 address_word p
= *ap
++;
1449 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1450 sim_io_printf(sd
, "%c", ch
);
1453 sim_io_printf(sd
,"(null)");
1456 sim_io_printf (sd
, "%c", (int)*ap
++);
1461 sim_read (sd
, s
++, &c
, 1);
1465 sim_read (sd
, s
++, &c
, 1);
1468 if (strchr ("dobxXu", c
))
1470 word64 lv
= (word64
) *ap
++;
1472 sim_io_printf(sd
,"<binary not supported>");
1475 #define _P(c, fmt64, fmt32) \
1478 sim_io_printf (sd, "%" fmt64, lv); \
1480 sim_io_printf (sd, "%" fmt32, (int)lv); \
1482 #define P(c, fmtc) _P(c, PRI##fmtc##64, PRI##fmtc##32)
1495 else if (strchr ("eEfgG", c
))
1497 double dbl
= *(double*)(ap
++);
1499 #define P(c, fmtc) \
1501 sim_io_printf (sd, "%*.*" #fmtc, width, trunc, dbl); \
1517 sim_io_printf(sd
, "%c", c
);
1523 /* Unknown reason. */
1529 /* Store a word into memory. */
1532 store_word (SIM_DESC sd
,
1538 address_word paddr
= vaddr
;
1540 if ((vaddr
& 3) != 0)
1541 SignalExceptionAddressStore ();
1544 const uword64 mask
= 7;
1548 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1549 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1550 memval
= ((uword64
) val
) << (8 * byte
);
1551 StoreMemory (AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1556 /* Load a word from memory. */
1559 load_word (SIM_DESC sd
,
1564 if ((vaddr
& 3) != 0)
1566 SIM_CORE_SIGNAL (SD
, cpu
, cia
, read_map
, AccessLength_WORD
+1, vaddr
, read_transfer
, sim_core_unaligned_signal
);
1570 address_word paddr
= vaddr
;
1571 const uword64 mask
= 0x7;
1572 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1573 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1577 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1578 LoadMemory (&memval
, NULL
, AccessLength_WORD
, paddr
, vaddr
, isDATA
,
1580 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1581 return EXTEND32 (memval
>> (8 * byte
));
1587 /* Simulate the mips16 entry and exit pseudo-instructions. These
1588 would normally be handled by the reserved instruction exception
1589 code, but for ease of simulation we just handle them directly. */
1592 mips16_entry (SIM_DESC sd
,
1597 int aregs
, sregs
, rreg
;
1600 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1603 aregs
= (insn
& 0x700) >> 8;
1604 sregs
= (insn
& 0x0c0) >> 6;
1605 rreg
= (insn
& 0x020) >> 5;
1607 /* This should be checked by the caller. */
1616 /* This is the entry pseudo-instruction. */
1618 for (i
= 0; i
< aregs
; i
++)
1619 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1627 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1630 for (i
= 0; i
< sregs
; i
++)
1633 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1641 /* This is the exit pseudo-instruction. */
1648 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1651 for (i
= 0; i
< sregs
; i
++)
1654 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1659 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1663 FGR
[0] = WORD64LO (GPR
[4]);
1664 FPR_STATE
[0] = fmt_uninterpreted
;
1666 else if (aregs
== 6)
1668 FGR
[0] = WORD64LO (GPR
[5]);
1669 FGR
[1] = WORD64LO (GPR
[4]);
1670 FPR_STATE
[0] = fmt_uninterpreted
;
1671 FPR_STATE
[1] = fmt_uninterpreted
;
1680 /*-- trace support ----------------------------------------------------------*/
1682 /* The trace support is provided (if required) in the memory accessing
1683 routines. Since we are also providing the architecture specific
1684 features, the architecture simulation code can also deal with
1685 notifying the trace world of cache flushes, etc. Similarly we do
1686 not need to provide profiling support in the simulator engine,
1687 since we can sample in the instruction fetch control loop. By
1688 defining the trace manifest, we add tracing as a run-time
1691 #if WITH_TRACE_ANY_P
1692 /* Tracing by default produces "din" format (as required by
1693 dineroIII). Each line of such a trace file *MUST* have a din label
1694 and address field. The rest of the line is ignored, so comments can
1695 be included if desired. The first field is the label which must be
1696 one of the following values:
1701 3 escape record (treated as unknown access type)
1702 4 escape record (causes cache flush)
1704 The address field is a 32bit (lower-case) hexadecimal address
1705 value. The address should *NOT* be preceded by "0x".
1707 The size of the memory transfer is not important when dealing with
1708 cache lines (as long as no more than a cache line can be
1709 transferred in a single operation :-), however more information
1710 could be given following the dineroIII requirement to allow more
1711 complete memory and cache simulators to provide better
1712 results. i.e. the University of Pisa has a cache simulator that can
1713 also take bus size and speed as (variable) inputs to calculate
1714 complete system performance (a much more useful ability when trying
1715 to construct an end product, rather than a processor). They
1716 currently have an ARM version of their tool called ChARM. */
1720 dotrace (SIM_DESC sd
,
1726 const char *comment
, ...)
1728 if (STATE
& simTRACE
) {
1730 fprintf(tracefh
,"%d %s ; width %d ; ",
1734 va_start(ap
,comment
);
1735 vfprintf(tracefh
,comment
,ap
);
1737 fprintf(tracefh
,"\n");
1739 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1740 we may be generating 64bit ones, we should put the hi-32bits of the
1741 address into the comment field. */
1743 /* TODO: Provide a buffer for the trace lines. We can then avoid
1744 performing writes until the buffer is filled, or the file is
1747 /* NOTE: We could consider adding a comment field to the "din" file
1748 produced using type 3 markers (unknown access). This would then
1749 allow information about the program that the "din" is for, and
1750 the MIPs world that was being simulated, to be placed into the
1755 #endif /* WITH_TRACE_ANY_P */
1757 /*---------------------------------------------------------------------------*/
1758 /*-- simulator engine -------------------------------------------------------*/
1759 /*---------------------------------------------------------------------------*/
1762 ColdReset (SIM_DESC sd
)
1765 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1767 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1768 /* RESET: Fixed PC address: */
1769 PC
= (unsigned_word
) UNSIGNED64 (0xFFFFFFFFBFC00000);
1770 /* The reset vector address is in the unmapped, uncached memory space. */
1772 SR
&= ~(status_SR
| status_TS
| status_RP
);
1773 SR
|= (status_ERL
| status_BEV
);
1775 /* Cheat and allow access to the complete register set immediately */
1776 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1777 && WITH_TARGET_WORD_BITSIZE
== 64)
1778 SR
|= status_FR
; /* 64bit registers */
1780 /* Ensure that any instructions with pending register updates are
1782 PENDING_INVALIDATE();
1784 /* Initialise the FPU registers to the unknown state */
1785 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1788 for (rn
= 0; (rn
< 32); rn
++)
1789 FPR_STATE
[rn
] = fmt_uninterpreted
;
1792 /* Initialise the Config0 register. */
1793 C0_CONFIG
= 0x80000000 /* Config1 present */
1794 | 2; /* KSEG0 uncached */
1795 if (WITH_TARGET_WORD_BITSIZE
== 64)
1797 /* FIXME Currently mips/sim-main.c:address_translation()
1798 truncates all addresses to 32-bits. */
1799 if (0 && WITH_TARGET_ADDRESS_BITSIZE
== 64)
1800 C0_CONFIG
|= (2 << 13); /* MIPS64, 64-bit addresses */
1802 C0_CONFIG
|= (1 << 13); /* MIPS64, 32-bit addresses */
1805 C0_CONFIG
|= 0x00008000; /* Big Endian */
1812 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1813 /* Signal an exception condition. This will result in an exception
1814 that aborts the instruction. The instruction operation pseudocode
1815 will never see a return from this function call. */
1818 signal_exception (SIM_DESC sd
,
1826 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1829 /* Ensure that any active atomic read/modify/write operation will fail: */
1832 /* Save registers before interrupt dispatching */
1833 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1834 SIM_CPU_EXCEPTION_TRIGGER(sd
, cpu
, cia
);
1837 switch (exception
) {
1839 case DebugBreakPoint
:
1840 if (! (Debug
& Debug_DM
))
1846 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1847 DEPC
= cia
- 4; /* reference the branch instruction */
1851 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1855 Debug
|= Debug_DM
; /* in debugging mode */
1856 Debug
|= Debug_DBp
; /* raising a DBp exception */
1858 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1862 case ReservedInstruction
:
1865 unsigned int instruction
;
1866 va_start(ap
,exception
);
1867 instruction
= va_arg(ap
,unsigned int);
1869 /* Provide simple monitor support using ReservedInstruction
1870 exceptions. The following code simulates the fixed vector
1871 entry points into the IDT monitor by causing a simulator
1872 trap, performing the monitor operation, and returning to
1873 the address held in the $ra register (standard PCS return
1874 address). This means we only need to pre-load the vector
1875 space with suitable instruction values. For systems were
1876 actual trap instructions are used, we would not need to
1877 perform this magic. */
1878 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1880 int reason
= (instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
;
1881 if (!sim_monitor (SD
, CPU
, cia
, reason
))
1882 sim_io_error (sd
, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason
, pr_addr (cia
));
1884 /* NOTE: This assumes that a branch-and-link style
1885 instruction was used to enter the vector (which is the
1886 case with the current IDT monitor). */
1887 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1889 /* Look for the mips16 entry and exit instructions, and
1890 simulate a handler for them. */
1891 else if ((cia
& 1) != 0
1892 && (instruction
& 0xf81f) == 0xe809
1893 && (instruction
& 0x0c0) != 0x0c0)
1895 mips16_entry (SD
, CPU
, cia
, instruction
);
1896 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1898 /* else fall through to normal exception processing */
1899 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1903 /* Store exception code into current exception id variable (used
1906 /* TODO: If not simulating exceptions then stop the simulator
1907 execution. At the moment we always stop the simulation. */
1909 #ifdef SUBTARGET_R3900
1910 /* update interrupt-related registers */
1912 /* insert exception code in bits 6:2 */
1913 CAUSE
= LSMASKED32(CAUSE
, 31, 7) | LSINSERTED32(exception
, 6, 2);
1914 /* shift IE/KU history bits left */
1915 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 3, 0), 5, 2);
1917 if (STATE
& simDELAYSLOT
)
1919 STATE
&= ~simDELAYSLOT
;
1921 EPC
= (cia
- 4); /* reference the branch instruction */
1926 if (SR
& status_BEV
)
1927 PC
= (signed)0xBFC00000 + 0x180;
1929 PC
= (signed)0x80000000 + 0x080;
1931 /* See figure 5-17 for an outline of the code below */
1932 if (! (SR
& status_EXL
))
1934 CAUSE
= (exception
<< 2);
1935 if (STATE
& simDELAYSLOT
)
1937 STATE
&= ~simDELAYSLOT
;
1939 EPC
= (cia
- 4); /* reference the branch instruction */
1943 /* FIXME: TLB et.al. */
1944 /* vector = 0x180; */
1948 CAUSE
= (exception
<< 2);
1949 /* vector = 0x180; */
1952 /* Store exception code into current exception id variable (used
1955 if (SR
& status_BEV
)
1956 PC
= (signed)0xBFC00200 + 0x180;
1958 PC
= (signed)0x80000000 + 0x180;
1961 switch ((CAUSE
>> 2) & 0x1F)
1964 /* Interrupts arrive during event processing, no need to
1970 #ifdef SUBTARGET_3900
1971 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1972 PC
= (signed)0xBFC00000;
1973 #endif /* SUBTARGET_3900 */
1976 case TLBModification
:
1981 case InstructionFetch
:
1983 /* The following is so that the simulator will continue from the
1984 exception handler address. */
1985 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1986 sim_stopped
, SIM_SIGBUS
);
1988 case ReservedInstruction
:
1989 case CoProcessorUnusable
:
1991 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1992 sim_stopped
, SIM_SIGILL
);
1994 case IntegerOverflow
:
1996 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1997 sim_stopped
, SIM_SIGFPE
);
2000 sim_engine_halt (SD
, CPU
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
2005 sim_engine_restart (SD
, CPU
, NULL
, PC
);
2010 sim_engine_halt (SD
, CPU
, NULL
, PC
,
2011 sim_stopped
, SIM_SIGTRAP
);
2013 default: /* Unknown internal exception */
2015 sim_engine_halt (SD
, CPU
, NULL
, PC
,
2016 sim_stopped
, SIM_SIGABRT
);
2020 case SimulatorFault
:
2024 va_start(ap
,exception
);
2025 msg
= va_arg(ap
,char *);
2027 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2028 "FATAL: Simulator error \"%s\"\n",msg
);
2037 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2038 "UNPREDICTABLE" behaviour.
2040 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2041 may vary from processor implementation to processor implementation,
2042 instruction to instruction, or as a function of time on the same
2043 implementation or instruction. Software can never depend on results
2044 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2045 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2048 For UNPREDICTABLE behaviour, we print a message, if possible print
2049 the offending instructions mips.igen instruction name (provided by
2050 the caller), and stop the simulator.
2052 XXX FIXME: eventually, stopping the simulator should be made conditional
2053 on a command-line option. */
2055 unpredictable_action(sim_cpu
*cpu
, address_word cia
)
2057 SIM_DESC sd
= CPU_STATE(cpu
);
2059 sim_io_eprintf(sd
, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia
));
2060 sim_engine_halt (SD
, CPU
, NULL
, cia
, sim_stopped
, SIM_SIGABRT
);
2064 /*-- co-processor support routines ------------------------------------------*/
2067 CoProcPresent(unsigned int coproc_number
)
2069 /* Return TRUE if simulator provides a model for the given co-processor number */
2074 cop_lw (SIM_DESC sd
,
2079 unsigned int memword
)
2084 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2087 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2089 StoreFPR(coproc_reg
,fmt_uninterpreted_32
,(uword64
)memword
);
2094 #if 0 /* this should be controlled by a configuration option */
2095 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2104 cop_ld (SIM_DESC sd
,
2113 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num
, coproc_reg
, pr_uword64(memword
), pr_addr(cia
) );
2116 switch (coproc_num
) {
2118 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2120 StoreFPR(coproc_reg
,fmt_uninterpreted_64
,memword
);
2125 #if 0 /* this message should be controlled by a configuration option */
2126 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2138 cop_sw (SIM_DESC sd
,
2144 unsigned int value
= 0;
2149 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2151 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted_32
);
2156 #if 0 /* should be controlled by configuration option */
2157 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2166 cop_sd (SIM_DESC sd
,
2176 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2178 value
= ValueFPR(coproc_reg
,fmt_uninterpreted_64
);
2183 #if 0 /* should be controlled by configuration option */
2184 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2196 decode_coproc (SIM_DESC sd
,
2199 unsigned int instruction
,
2208 case 0: /* standard CPU control and cache registers */
2210 /* R4000 Users Manual (second edition) lists the following CP0
2212 CODE><-RT><RD-><--TAIL--->
2213 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2214 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2215 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2216 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2217 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2218 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2219 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2220 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2221 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2222 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2224 if (((op
== cp0_mfc0
) || (op
== cp0_mtc0
) /* MFC0 / MTC0 */
2225 || (op
== cp0_dmfc0
) || (op
== cp0_dmtc0
)) /* DMFC0 / DMTC0 */
2228 switch (rd
) /* NOTEs: Standard CP0 registers */
2230 /* 0 = Index R4000 VR4100 VR4300 */
2231 /* 1 = Random R4000 VR4100 VR4300 */
2232 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2233 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2234 /* 4 = Context R4000 VR4100 VR4300 */
2235 /* 5 = PageMask R4000 VR4100 VR4300 */
2236 /* 6 = Wired R4000 VR4100 VR4300 */
2237 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2238 /* 9 = Count R4000 VR4100 VR4300 */
2239 /* 10 = EntryHi R4000 VR4100 VR4300 */
2240 /* 11 = Compare R4000 VR4100 VR4300 */
2241 /* 12 = SR R4000 VR4100 VR4300 */
2242 #ifdef SUBTARGET_R3900
2244 /* 3 = Config R3900 */
2246 /* 7 = Cache R3900 */
2248 /* 15 = PRID R3900 */
2254 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2255 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2256 GPR
[rt
] = (signed_word
) (signed_address
) COP0_BADVADDR
;
2258 COP0_BADVADDR
= GPR
[rt
];
2261 #endif /* SUBTARGET_R3900 */
2263 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2268 /* 13 = Cause R4000 VR4100 VR4300 */
2270 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2275 /* 14 = EPC R4000 VR4100 VR4300 */
2277 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2278 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
2282 /* 15 = PRId R4000 VR4100 VR4300 */
2283 #ifdef SUBTARGET_R3900
2286 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2292 /* 16 = Config R4000 VR4100 VR4300 */
2294 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2295 GPR
[rt
] = C0_CONFIG
;
2297 /* only bottom three bits are writable */
2298 C0_CONFIG
= (C0_CONFIG
& ~0x7) | (GPR
[rt
] & 0x7);
2301 #ifdef SUBTARGET_R3900
2304 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2310 /* 17 = LLAddr R4000 VR4100 VR4300 */
2312 /* 18 = WatchLo R4000 VR4100 VR4300 */
2313 /* 19 = WatchHi R4000 VR4100 VR4300 */
2314 /* 20 = XContext R4000 VR4100 VR4300 */
2315 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2316 /* 27 = CacheErr R4000 VR4100 */
2317 /* 28 = TagLo R4000 VR4100 VR4300 */
2318 /* 29 = TagHi R4000 VR4100 VR4300 */
2319 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2320 if (STATE_VERBOSE_P(SD
))
2322 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2323 (unsigned long)cia
);
2324 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
2325 /* CPR[0,rd] = GPR[rt]; */
2327 if (op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2328 GPR
[rt
] = (signed_word
) (signed32
) COP0_GPR
[rd
];
2330 COP0_GPR
[rd
] = GPR
[rt
];
2333 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
2335 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
2339 else if ((op
== cp0_mfc0
|| op
== cp0_dmfc0
)
2342 /* [D]MFC0 RT,C0_CONFIG,SEL */
2350 /* MIPS32 r/o Config1:
2353 /* MIPS16 implemented.
2354 XXX How to check configuration? */
2356 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2357 /* MDMX & FPU implemented */
2361 /* MIPS32 r/o Config2:
2366 /* MIPS32 r/o Config3:
2367 SmartMIPS implemented. */
2373 else if (op
== cp0_eret
&& sel
== 0x18)
2376 if (SR
& status_ERL
)
2378 /* Oops, not yet available */
2379 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
2389 else if (op
== cp0_rfe
&& sel
== 0x10)
2392 #ifdef SUBTARGET_R3900
2393 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2395 /* shift IE/KU history bits right */
2396 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 5, 2), 3, 0);
2398 /* TODO: CACHE register */
2399 #endif /* SUBTARGET_R3900 */
2401 else if (op
== cp0_deret
&& sel
== 0x1F)
2409 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
2410 /* TODO: When executing an ERET or RFE instruction we should
2411 clear LLBIT, to ensure that any out-standing atomic
2412 read/modify/write sequence fails. */
2416 case 2: /* co-processor 2 */
2423 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2424 instruction
,pr_addr(cia
));
2429 case 1: /* should not occur (FPU co-processor) */
2430 case 3: /* should not occur (FPU co-processor) */
2431 SignalException(ReservedInstruction
,instruction
);
2439 /* This code copied from gdb's utils.c. Would like to share this code,
2440 but don't know of a common place where both could get to it. */
2442 /* Temporary storage using circular buffer */
2448 static char buf
[NUMCELLS
][CELLSIZE
];
2450 if (++cell
>=NUMCELLS
) cell
=0;
2454 /* Print routines to handle variable size regs, etc */
2456 /* Eliminate warning from compiler on 32-bit systems */
2457 static int thirty_two
= 32;
2460 pr_addr (SIM_ADDR addr
)
2462 char *paddr_str
=get_cell();
2463 switch (sizeof(addr
))
2466 sprintf(paddr_str
,"%08lx%08lx",
2467 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
2470 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
2473 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
2476 sprintf(paddr_str
,"%x",addr
);
2482 pr_uword64 (uword64 addr
)
2484 char *paddr_str
=get_cell();
2485 sprintf(paddr_str
,"%08lx%08lx",
2486 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
2492 mips_core_signal (SIM_DESC sd
,
2498 transfer_type transfer
,
2499 sim_core_signals sig
)
2501 const char *copy
= (transfer
== read_transfer
? "read" : "write");
2502 address_word ip
= CIA_ADDR (cia
);
2506 case sim_core_unmapped_signal
:
2507 sim_io_eprintf (sd
, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2509 (unsigned long) addr
, (unsigned long) ip
);
2510 COP0_BADVADDR
= addr
;
2511 SignalExceptionDataReference();
2514 case sim_core_unaligned_signal
:
2515 sim_io_eprintf (sd
, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2517 (unsigned long) addr
, (unsigned long) ip
);
2518 COP0_BADVADDR
= addr
;
2519 if(transfer
== read_transfer
)
2520 SignalExceptionAddressLoad();
2522 SignalExceptionAddressStore();
2526 sim_engine_abort (sd
, cpu
, cia
,
2527 "mips_core_signal - internal error - bad switch");
2533 mips_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word cia
)
2535 ASSERT(cpu
!= NULL
);
2537 if(cpu
->exc_suspended
> 0)
2538 sim_io_eprintf(sd
, "Warning, nested exception triggered (%d)\n", cpu
->exc_suspended
);
2541 memcpy(cpu
->exc_trigger_registers
, cpu
->registers
, sizeof(cpu
->exc_trigger_registers
));
2542 cpu
->exc_suspended
= 0;
2546 mips_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
2548 ASSERT(cpu
!= NULL
);
2550 if(cpu
->exc_suspended
> 0)
2551 sim_io_eprintf(sd
, "Warning, nested exception signal (%d then %d)\n",
2552 cpu
->exc_suspended
, exception
);
2554 memcpy(cpu
->exc_suspend_registers
, cpu
->registers
, sizeof(cpu
->exc_suspend_registers
));
2555 memcpy(cpu
->registers
, cpu
->exc_trigger_registers
, sizeof(cpu
->registers
));
2556 cpu
->exc_suspended
= exception
;
2560 mips_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
2562 ASSERT(cpu
!= NULL
);
2564 if(exception
== 0 && cpu
->exc_suspended
> 0)
2566 /* warn not for breakpoints */
2567 if(cpu
->exc_suspended
!= sim_signal_to_host(sd
, SIM_SIGTRAP
))
2568 sim_io_eprintf(sd
, "Warning, resuming but ignoring pending exception signal (%d)\n",
2569 cpu
->exc_suspended
);
2571 else if(exception
!= 0 && cpu
->exc_suspended
> 0)
2573 if(exception
!= cpu
->exc_suspended
)
2574 sim_io_eprintf(sd
, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2575 cpu
->exc_suspended
, exception
);
2577 memcpy(cpu
->registers
, cpu
->exc_suspend_registers
, sizeof(cpu
->registers
));
2579 else if(exception
!= 0 && cpu
->exc_suspended
== 0)
2581 sim_io_eprintf(sd
, "Warning, ignoring spontanous exception signal (%d)\n", exception
);
2583 cpu
->exc_suspended
= 0;
2587 /*---------------------------------------------------------------------------*/
2588 /*> EOF interp.c <*/