2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
41 /* start-sanitize-sky */
45 #include "sky-libvpe.h"
51 /* end-sanitize-sky */
73 #include "libiberty.h"
75 #include "callback.h" /* GDB simulator callback interface */
76 #include "remote-sim.h" /* GDB simulator interface */
84 char* pr_addr
PARAMS ((SIM_ADDR addr
));
85 char* pr_uword64
PARAMS ((uword64 addr
));
88 /* Get the simulator engine description, without including the code: */
95 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
100 /* The following reserved instruction value is used when a simulator
101 trap is required. NOTE: Care must be taken, since this value may be
102 used in later revisions of the MIPS ISA. */
104 #define RSVD_INSTRUCTION (0x00000005)
105 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
107 #define RSVD_INSTRUCTION_ARG_SHIFT 6
108 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
111 /* The following reserved instruction value is used when a simulator
112 halt is required. NOTE: Care must be taken, since this value may
113 be used in later revisions of the MIPS ISA. */
114 #define HALT_INSTRUCTION (0x03ff000d)
115 #define HALT_INSTRUCTION_MASK (0x03FFFFC0)
118 /* Bits in the Debug register */
119 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
120 #define Debug_DM 0x40000000 /* Debug Mode */
121 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
127 /*---------------------------------------------------------------------------*/
128 /*-- GDB simulator interface ------------------------------------------------*/
129 /*---------------------------------------------------------------------------*/
131 static void ColdReset
PARAMS((SIM_DESC sd
));
133 /*---------------------------------------------------------------------------*/
137 #define DELAYSLOT() {\
138 if (STATE & simDELAYSLOT)\
139 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
140 STATE |= simDELAYSLOT;\
143 #define JALDELAYSLOT() {\
145 STATE |= simJALDELAYSLOT;\
149 STATE &= ~simDELAYSLOT;\
150 STATE |= simSKIPNEXT;\
153 #define CANCELDELAYSLOT() {\
155 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
158 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
159 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
161 #define K0BASE (0x80000000)
162 #define K0SIZE (0x20000000)
163 #define K1BASE (0xA0000000)
164 #define K1SIZE (0x20000000)
165 #define MONITOR_BASE (0xBFC00000)
166 #define MONITOR_SIZE (1 << 11)
167 #define MEM_SIZE (2 << 20)
169 /* start-sanitize-sky */
172 #define MEM_SIZE (16 << 20) /* 16 MB */
174 /* end-sanitize-sky */
177 static char *tracefile
= "trace.din"; /* default filename for trace log */
178 FILE *tracefh
= NULL
;
179 static void open_trace
PARAMS((SIM_DESC sd
));
182 static DECLARE_OPTION_HANDLER (mips_option_handler
);
185 OPTION_DINERO_TRACE
= OPTION_START
,
187 /* start-sanitize-sky */
193 /* end-sanitize-sky */
197 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
207 case OPTION_DINERO_TRACE
: /* ??? */
209 /* Eventually the simTRACE flag could be treated as a toggle, to
210 allow external control of the program points being traced
211 (i.e. only from main onwards, excluding the run-time setup,
213 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
215 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
218 else if (strcmp (arg
, "yes") == 0)
220 else if (strcmp (arg
, "no") == 0)
222 else if (strcmp (arg
, "on") == 0)
224 else if (strcmp (arg
, "off") == 0)
228 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
235 Simulator constructed without dinero tracing support (for performance).\n\
236 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
240 case OPTION_DINERO_FILE
:
242 if (optarg
!= NULL
) {
244 tmp
= (char *)malloc(strlen(optarg
) + 1);
247 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
253 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
259 /* start-sanitize-sky */
262 case OPTION_FLOAT_TYPE
:
263 /* Use host (fast) or target (accurate) floating point implementation. */
264 if (arg
&& strcmp (arg
, "host") == 0)
265 STATE_FP_TYPE_OPT (sd
) &= ~STATE_FP_TYPE_OPT_TARGET
;
266 else if (arg
&& strcmp (arg
, "target") == 0)
267 STATE_FP_TYPE_OPT (sd
) |= STATE_FP_TYPE_OPT_TARGET
;
270 fprintf (stderr
, "Unrecognized float-type option `%s'\n", arg
);
273 /*printf ("float-type=0x%08x\n", STATE_FP_TYPE_OPT (sd));*/
277 /* end-sanitize-sky */
283 static const OPTION mips_options
[] =
285 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
286 '\0', "on|off", "Enable dinero tracing",
287 mips_option_handler
},
288 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
289 '\0', "FILE", "Write dinero trace to FILE",
290 mips_option_handler
},
291 /* start-sanitize-sky */
294 { {"float-type", required_argument
, NULL
, OPTION_FLOAT_TYPE
},
295 '\0', "host|target", "Use host (fast) or target (accurate) floating point",
296 mips_option_handler
},
299 /* end-sanitize-sky */
300 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
304 int interrupt_pending
;
307 interrupt_event (SIM_DESC sd
, void *data
)
309 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
312 interrupt_pending
= 0;
313 SignalExceptionInterrupt ();
315 else if (!interrupt_pending
)
316 sim_events_schedule (sd
, 1, interrupt_event
, data
);
320 /*---------------------------------------------------------------------------*/
321 /*-- Device registration hook -----------------------------------------------*/
322 /*---------------------------------------------------------------------------*/
323 static void device_init(SIM_DESC sd
) {
325 extern void register_devices(SIM_DESC
);
326 register_devices(sd
);
330 /*---------------------------------------------------------------------------*/
331 /*-- GDB simulator interface ------------------------------------------------*/
332 /*---------------------------------------------------------------------------*/
335 sim_open (kind
, cb
, abfd
, argv
)
341 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
342 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
344 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
345 /* start-sanitize-sky */
347 #if defined(TARGET_SKY) && defined(SKY_FUNIT)
348 /* Set "--float-type host" as the default. */
349 STATE_FP_TYPE_OPT (sd
) &= ~STATE_FP_TYPE_OPT_TARGET
;
351 /* end-sanitize-sky */
353 /* FIXME: watchpoints code shouldn't need this */
354 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
355 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
356 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
360 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
362 sim_add_option_table (sd
, NULL
, mips_options
);
364 /* Allocate core managed memory */
367 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
368 /* For compatibility with the old code - under this (at level one)
369 are the kernel spaces K0 & K1. Both of these map to a single
370 smaller sub region */
371 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
372 /* start-sanitize-sky */
374 /* end-sanitize-sky */
375 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
377 MEM_SIZE
, /* actual size */
379 /* start-sanitize-sky */
381 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
383 MEM_SIZE
, /* actual size */
385 0); /* add alias at 0x0000 */
387 /* end-sanitize-sky */
391 /* getopt will print the error message so we just have to exit if this fails.
392 FIXME: Hmmm... in the case of gdb we need getopt to call
394 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
396 /* Uninstall the modules to avoid memory leaks,
397 file descriptor leaks, etc. */
398 sim_module_uninstall (sd
);
402 /* check for/establish the a reference program image */
403 if (sim_analyze_program (sd
,
404 (STATE_PROG_ARGV (sd
) != NULL
405 ? *STATE_PROG_ARGV (sd
)
409 sim_module_uninstall (sd
);
413 /* Configure/verify the target byte order and other runtime
414 configuration options */
415 if (sim_config (sd
) != SIM_RC_OK
)
417 sim_module_uninstall (sd
);
421 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
423 /* Uninstall the modules to avoid memory leaks,
424 file descriptor leaks, etc. */
425 sim_module_uninstall (sd
);
429 /* verify assumptions the simulator made about the host type system.
430 This macro does not return if there is a problem */
431 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
432 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
434 /* This is NASTY, in that we are assuming the size of specific
438 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
441 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
442 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
443 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
444 else if ((rn
>= 33) && (rn
<= 37))
445 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
446 else if ((rn
== SRIDX
)
449 || ((rn
>= 72) && (rn
<= 89)))
450 cpu
->register_widths
[rn
] = 32;
452 cpu
->register_widths
[rn
] = 0;
454 /* start-sanitize-r5900 */
456 /* set the 5900 "upper" registers to 64 bits */
457 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
458 cpu
->register_widths
[rn
] = 64;
459 /* end-sanitize-r5900 */
461 /* start-sanitize-sky */
463 /* Now the VU registers */
464 for( rn
= 0; rn
< NUM_VU_INTEGER_REGS
; rn
++ ) {
465 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 16;
466 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 16;
469 for( rn
= NUM_VU_INTEGER_REGS
; rn
< NUM_VU_REGS
; rn
++ ) {
470 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
471 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 32;
474 /* Finally the VIF registers */
475 for( rn
= 2*NUM_VU_REGS
; rn
< 2*NUM_VU_REGS
+ 2*NUM_VIF_REGS
; rn
++ )
476 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
480 /* end-sanitize-sky */
484 if (STATE
& simTRACE
)
488 /* Write an abort sequence into the TRAP (common) exception vector
489 addresses. This is to catch code executing a TRAP (et.al.)
490 instruction without installing a trap handler. */
492 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
493 HALT_INSTRUCTION
/* BREAK */ };
496 sim_write (sd
, 0x80000180, (char *) halt
, sizeof (halt
));
497 sim_write (sd
, 0xBFC00380, (char *) halt
, sizeof (halt
));
501 /* Write the monitor trap address handlers into the monitor (eeprom)
502 address space. This can only be done once the target endianness
503 has been determined. */
506 /* Entry into the IDT monitor is via fixed address vectors, and
507 not using machine instructions. To avoid clashing with use of
508 the MIPS TRAP system, we place our own (simulator specific)
509 "undefined" instructions into the relevant vector slots. */
510 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
512 address_word vaddr
= (MONITOR_BASE
+ loop
);
513 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
515 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
517 /* The PMON monitor uses the same address space, but rather than
518 branching into it the address of a routine is loaded. We can
519 cheat for the moment, and direct the PMON routine to IDT style
520 instructions within the monitor space. This relies on the IDT
521 monitor not using the locations from 0xBFC00500 onwards as its
523 for (loop
= 0; (loop
< 24); loop
++)
525 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
526 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
542 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
544 case 8: /* cliexit */
547 case 11: /* flush_cache */
551 /* FIXME - should monitor_base be SIM_ADDR?? */
552 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
554 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
556 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
558 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
570 tracefh
= fopen(tracefile
,"wb+");
573 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
580 sim_close (sd
, quitting
)
585 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
588 /* "quitting" is non-zero if we cannot hang on errors */
590 /* Ensure that any resources allocated through the callback
591 mechanism are released: */
592 sim_io_shutdown (sd
);
595 if (tracefh
!= NULL
&& tracefh
!= stderr
)
600 /* FIXME - free SD */
607 sim_write (sd
,addr
,buffer
,size
)
610 unsigned char *buffer
;
614 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
616 /* Return the number of bytes written, or zero if error. */
618 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
621 /* We use raw read and write routines, since we do not want to count
622 the GDB memory accesses in our statistics gathering. */
624 for (index
= 0; index
< size
; index
++)
626 address_word vaddr
= (address_word
)addr
+ index
;
629 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
631 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
639 sim_read (sd
,addr
,buffer
,size
)
642 unsigned char *buffer
;
646 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
648 /* Return the number of bytes read, or zero if error. */
650 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
653 for (index
= 0; (index
< size
); index
++)
655 address_word vaddr
= (address_word
)addr
+ index
;
658 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
660 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
668 sim_store_register (sd
,rn
,memory
,length
)
671 unsigned char *memory
;
674 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
675 /* NOTE: gdb (the client) stores registers in target byte order
676 while the simulator uses host byte order */
678 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
681 /* Unfortunately this suffers from the same problem as the register
682 numbering one. We need to know what the width of each logical
683 register number is for the architecture being simulated. */
685 if (cpu
->register_widths
[rn
] == 0)
687 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
691 /* start-sanitize-r5900 */
692 if (rn
>= 90 && rn
< 90 + 32)
694 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
700 SA
= T2H_8(*(unsigned64
*)memory
);
702 case 122: /* FIXME */
703 LO1
= T2H_8(*(unsigned64
*)memory
);
705 case 123: /* FIXME */
706 HI1
= T2H_8(*(unsigned64
*)memory
);
709 /* end-sanitize-r5900 */
711 /* start-sanitize-sky */
713 if (rn
>= NUM_R5900_REGS
)
715 rn
= rn
- NUM_R5900_REGS
;
717 if( rn
< NUM_VU_REGS
)
719 if (rn
< NUM_VU_INTEGER_REGS
)
720 return write_vu_int_reg (&(vu0_device
.regs
), rn
, memory
);
721 else if (rn
>= FIRST_VEC_REG
)
724 return write_vu_vec_reg (&(vu0_device
.regs
), rn
>>2, rn
&3,
727 else switch (rn
- NUM_VU_INTEGER_REGS
)
730 return write_vu_special_reg (&vu0_device
, VU_REG_CIA
,
733 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MR
,
735 case 2: /* VU0 has no P register */
738 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MI
,
741 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MQ
,
744 return write_vu_acc_reg (&(vu0_device
.regs
),
745 rn
- (NUM_VU_INTEGER_REGS
+ 5),
750 rn
= rn
- NUM_VU_REGS
;
752 if (rn
< NUM_VU_REGS
)
754 if (rn
< NUM_VU_INTEGER_REGS
)
755 return write_vu_int_reg (&(vu1_device
.regs
), rn
, memory
);
756 else if (rn
>= FIRST_VEC_REG
)
759 return write_vu_vec_reg (&(vu1_device
.regs
),
760 rn
>> 2, rn
& 3, memory
);
762 else switch (rn
- NUM_VU_INTEGER_REGS
)
765 return write_vu_special_reg (&vu1_device
, VU_REG_CIA
,
768 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MR
,
771 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MP
,
774 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MI
,
777 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MQ
,
780 return write_vu_acc_reg (&(vu1_device
.regs
),
781 rn
- (NUM_VU_INTEGER_REGS
+ 5),
786 rn
-= NUM_VU_REGS
; /* VIF0 registers are next */
788 if (rn
< NUM_VIF_REGS
)
790 if (rn
< NUM_VIF_REGS
-1)
791 return write_pke_reg (&pke0_device
, rn
, memory
);
794 sim_io_eprintf( sd
, "Can't write vif0_pc (store ignored)\n" );
799 rn
-= NUM_VIF_REGS
; /* VIF1 registers are last */
801 if (rn
< NUM_VIF_REGS
)
803 if (rn
< NUM_VIF_REGS
-1)
804 return write_pke_reg (&pke1_device
, rn
, memory
);
807 sim_io_eprintf( sd
, "Can't write vif1_pc (store ignored)\n" );
812 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
816 /* end-sanitize-sky */
818 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
820 if (cpu
->register_widths
[rn
] == 32)
822 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
827 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
832 if (cpu
->register_widths
[rn
] == 32)
834 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
839 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
847 sim_fetch_register (sd
,rn
,memory
,length
)
850 unsigned char *memory
;
853 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
854 /* NOTE: gdb (the client) stores registers in target byte order
855 while the simulator uses host byte order */
857 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
860 if (cpu
->register_widths
[rn
] == 0)
862 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
866 /* start-sanitize-r5900 */
867 if (rn
>= 90 && rn
< 90 + 32)
869 *(unsigned64
*)memory
= GPR1
[rn
- 90];
875 *((unsigned64
*)memory
) = H2T_8(SA
);
877 case 122: /* FIXME */
878 *((unsigned64
*)memory
) = H2T_8(LO1
);
880 case 123: /* FIXME */
881 *((unsigned64
*)memory
) = H2T_8(HI1
);
884 /* end-sanitize-r5900 */
886 /* start-sanitize-sky */
888 if (rn
>= NUM_R5900_REGS
)
890 rn
= rn
- NUM_R5900_REGS
;
892 if (rn
< NUM_VU_REGS
)
894 if (rn
< NUM_VU_INTEGER_REGS
)
895 return read_vu_int_reg (&(vu0_device
.regs
), rn
, memory
);
896 else if (rn
>= FIRST_VEC_REG
)
899 return read_vu_vec_reg (&(vu0_device
.regs
), rn
>>2, rn
& 3,
902 else switch (rn
- NUM_VU_INTEGER_REGS
)
905 return read_vu_special_reg(&vu0_device
, VU_REG_CIA
, memory
);
907 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MR
,
909 case 2: /* VU0 has no P register */
910 *((int *) memory
) = 0;
913 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MI
,
916 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MQ
,
919 return read_vu_acc_reg (&(vu0_device
.regs
),
920 rn
- (NUM_VU_INTEGER_REGS
+ 5),
925 rn
-= NUM_VU_REGS
; /* VU1 registers are next */
927 if (rn
< NUM_VU_REGS
)
929 if (rn
< NUM_VU_INTEGER_REGS
)
930 return read_vu_int_reg (&(vu1_device
.regs
), rn
, memory
);
931 else if (rn
>= FIRST_VEC_REG
)
934 return read_vu_vec_reg (&(vu1_device
.regs
),
935 rn
>> 2, rn
& 3, memory
);
937 else switch (rn
- NUM_VU_INTEGER_REGS
)
940 return read_vu_special_reg(&vu1_device
, VU_REG_CIA
, memory
);
942 return read_vu_misc_reg (&(vu1_device
.regs
),
945 return read_vu_misc_reg (&(vu1_device
.regs
),
948 return read_vu_misc_reg (&(vu1_device
.regs
),
951 return read_vu_misc_reg (&(vu1_device
.regs
),
954 return read_vu_acc_reg (&(vu1_device
.regs
),
955 rn
- (NUM_VU_INTEGER_REGS
+ 5),
960 rn
-= NUM_VU_REGS
; /* VIF0 registers are next */
962 if (rn
< NUM_VIF_REGS
)
964 if (rn
< NUM_VIF_REGS
-1)
965 return read_pke_reg (&pke0_device
, rn
, memory
);
967 return read_pke_pc (&pke0_device
, memory
);
970 rn
-= NUM_VIF_REGS
; /* VIF1 registers are last */
972 if (rn
< NUM_VIF_REGS
)
974 if (rn
< NUM_VIF_REGS
-1)
975 return read_pke_reg (&pke1_device
, rn
, memory
);
977 return read_pke_pc (&pke1_device
, memory
);
980 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
983 /* end-sanitize-sky */
985 /* Any floating point register */
986 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
988 if (cpu
->register_widths
[rn
] == 32)
990 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
995 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
1000 if (cpu
->register_widths
[rn
] == 32)
1002 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
1007 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
1016 sim_create_inferior (sd
, abfd
, argv
,env
)
1024 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1032 /* override PC value set by ColdReset () */
1034 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1036 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1037 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
1041 #if 0 /* def DEBUG */
1044 /* We should really place the argv slot values into the argument
1045 registers, and onto the stack as required. However, this
1046 assumes that we have a stack defined, which is not
1047 necessarily true at the moment. */
1049 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1050 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1051 printf("DBG: arg \"%s\"\n",*cptr
);
1059 sim_do_command (sd
,cmd
)
1063 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
1064 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1068 /*---------------------------------------------------------------------------*/
1069 /*-- Private simulator support interface ------------------------------------*/
1070 /*---------------------------------------------------------------------------*/
1072 /* Read a null terminated string from memory, return in a buffer */
1074 fetch_str (sd
, addr
)
1081 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1083 buf
= NZALLOC (char, nr
+ 1);
1084 sim_read (sd
, addr
, buf
, nr
);
1088 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1090 sim_monitor (SIM_DESC sd
,
1093 unsigned int reason
)
1096 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1099 /* The IDT monitor actually allows two instructions per vector
1100 slot. However, the simulator currently causes a trap on each
1101 individual instruction. We cheat, and lose the bottom bit. */
1104 /* The following callback functions are available, however the
1105 monitor we are simulating does not make use of them: get_errno,
1106 isatty, lseek, rename, system, time and unlink */
1110 case 6: /* int open(char *path,int flags) */
1112 char *path
= fetch_str (sd
, A0
);
1113 V0
= sim_io_open (sd
, path
, (int)A1
);
1118 case 7: /* int read(int file,char *ptr,int len) */
1122 char *buf
= zalloc (nr
);
1123 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1124 sim_write (sd
, A1
, buf
, nr
);
1129 case 8: /* int write(int file,char *ptr,int len) */
1133 char *buf
= zalloc (nr
);
1134 sim_read (sd
, A1
, buf
, nr
);
1135 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1140 case 10: /* int close(int file) */
1142 V0
= sim_io_close (sd
, (int)A0
);
1146 case 2: /* Densan monitor: char inbyte(int waitflag) */
1148 if (A0
== 0) /* waitflag == NOWAIT */
1149 V0
= (unsigned_word
)-1;
1151 /* Drop through to case 11 */
1153 case 11: /* char inbyte(void) */
1156 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1158 sim_io_error(sd
,"Invalid return from character read");
1159 V0
= (unsigned_word
)-1;
1162 V0
= (unsigned_word
)tmp
;
1166 case 3: /* Densan monitor: void co(char chr) */
1167 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1169 char tmp
= (char)(A0
& 0xFF);
1170 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1174 case 17: /* void _exit() */
1176 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1177 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1178 (unsigned int)(A0
& 0xFFFFFFFF));
1182 case 28 : /* PMON flush_cache */
1185 case 55: /* void get_mem_info(unsigned int *ptr) */
1186 /* in: A0 = pointer to three word memory location */
1187 /* out: [A0 + 0] = size */
1188 /* [A0 + 4] = instruction cache size */
1189 /* [A0 + 8] = data cache size */
1191 unsigned_4 value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1192 unsigned_4 zero
= 0;
1194 sim_write (sd
, A0
+ 0, (char *)&value
, 4);
1195 sim_write (sd
, A0
+ 4, (char *)&zero
, 4);
1196 sim_write (sd
, A0
+ 8, (char *)&zero
, 4);
1197 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1201 case 158 : /* PMON printf */
1202 /* in: A0 = pointer to format string */
1203 /* A1 = optional argument 1 */
1204 /* A2 = optional argument 2 */
1205 /* A3 = optional argument 3 */
1207 /* The following is based on the PMON printf source */
1209 address_word s
= A0
;
1211 signed_word
*ap
= &A1
; /* 1st argument */
1212 /* This isn't the quickest way, since we call the host print
1213 routine for every character almost. But it does avoid
1214 having to allocate and manage a temporary string buffer. */
1215 /* TODO: Include check that we only use three arguments (A1,
1217 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1222 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1223 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1224 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1226 if (strchr ("dobxXulscefg%", s
))
1241 else if (c
>= '1' && c
<= '9')
1245 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1248 n
= (unsigned int)strtol(tmp
,NULL
,10);
1261 sim_io_printf (sd
, "%%");
1266 address_word p
= *ap
++;
1268 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1269 sim_io_printf(sd
, "%c", ch
);
1272 sim_io_printf(sd
,"(null)");
1275 sim_io_printf (sd
, "%c", (int)*ap
++);
1280 sim_read (sd
, s
++, &c
, 1);
1284 sim_read (sd
, s
++, &c
, 1);
1287 if (strchr ("dobxXu", c
))
1289 word64 lv
= (word64
) *ap
++;
1291 sim_io_printf(sd
,"<binary not supported>");
1294 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1296 sim_io_printf(sd
, tmp
, lv
);
1298 sim_io_printf(sd
, tmp
, (int)lv
);
1301 else if (strchr ("eEfgG", c
))
1303 double dbl
= *(double*)(ap
++);
1304 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1305 sim_io_printf (sd
, tmp
, dbl
);
1311 sim_io_printf(sd
, "%c", c
);
1317 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1318 reason
, pr_addr(cia
));
1324 /* Store a word into memory. */
1327 store_word (SIM_DESC sd
,
1336 if ((vaddr
& 3) != 0)
1337 SignalExceptionAddressStore ();
1340 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1343 const uword64 mask
= 7;
1347 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1348 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1349 memval
= ((uword64
) val
) << (8 * byte
);
1350 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1356 /* Load a word from memory. */
1359 load_word (SIM_DESC sd
,
1364 if ((vaddr
& 3) != 0)
1365 SignalExceptionAddressLoad ();
1371 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1374 const uword64 mask
= 0x7;
1375 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1376 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1380 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1381 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1383 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1384 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1391 /* Simulate the mips16 entry and exit pseudo-instructions. These
1392 would normally be handled by the reserved instruction exception
1393 code, but for ease of simulation we just handle them directly. */
1396 mips16_entry (SIM_DESC sd
,
1401 int aregs
, sregs
, rreg
;
1404 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1407 aregs
= (insn
& 0x700) >> 8;
1408 sregs
= (insn
& 0x0c0) >> 6;
1409 rreg
= (insn
& 0x020) >> 5;
1411 /* This should be checked by the caller. */
1420 /* This is the entry pseudo-instruction. */
1422 for (i
= 0; i
< aregs
; i
++)
1423 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1431 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1434 for (i
= 0; i
< sregs
; i
++)
1437 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1445 /* This is the exit pseudo-instruction. */
1452 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1455 for (i
= 0; i
< sregs
; i
++)
1458 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1463 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1467 FGR
[0] = WORD64LO (GPR
[4]);
1468 FPR_STATE
[0] = fmt_uninterpreted
;
1470 else if (aregs
== 6)
1472 FGR
[0] = WORD64LO (GPR
[5]);
1473 FGR
[1] = WORD64LO (GPR
[4]);
1474 FPR_STATE
[0] = fmt_uninterpreted
;
1475 FPR_STATE
[1] = fmt_uninterpreted
;
1484 /*-- trace support ----------------------------------------------------------*/
1486 /* The TRACE support is provided (if required) in the memory accessing
1487 routines. Since we are also providing the architecture specific
1488 features, the architecture simulation code can also deal with
1489 notifying the TRACE world of cache flushes, etc. Similarly we do
1490 not need to provide profiling support in the simulator engine,
1491 since we can sample in the instruction fetch control loop. By
1492 defining the TRACE manifest, we add tracing as a run-time
1496 /* Tracing by default produces "din" format (as required by
1497 dineroIII). Each line of such a trace file *MUST* have a din label
1498 and address field. The rest of the line is ignored, so comments can
1499 be included if desired. The first field is the label which must be
1500 one of the following values:
1505 3 escape record (treated as unknown access type)
1506 4 escape record (causes cache flush)
1508 The address field is a 32bit (lower-case) hexadecimal address
1509 value. The address should *NOT* be preceded by "0x".
1511 The size of the memory transfer is not important when dealing with
1512 cache lines (as long as no more than a cache line can be
1513 transferred in a single operation :-), however more information
1514 could be given following the dineroIII requirement to allow more
1515 complete memory and cache simulators to provide better
1516 results. i.e. the University of Pisa has a cache simulator that can
1517 also take bus size and speed as (variable) inputs to calculate
1518 complete system performance (a much more useful ability when trying
1519 to construct an end product, rather than a processor). They
1520 currently have an ARM version of their tool called ChARM. */
1524 dotrace (SIM_DESC sd
,
1532 if (STATE
& simTRACE
) {
1534 fprintf(tracefh
,"%d %s ; width %d ; ",
1538 va_start(ap
,comment
);
1539 vfprintf(tracefh
,comment
,ap
);
1541 fprintf(tracefh
,"\n");
1543 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1544 we may be generating 64bit ones, we should put the hi-32bits of the
1545 address into the comment field. */
1547 /* TODO: Provide a buffer for the trace lines. We can then avoid
1548 performing writes until the buffer is filled, or the file is
1551 /* NOTE: We could consider adding a comment field to the "din" file
1552 produced using type 3 markers (unknown access). This would then
1553 allow information about the program that the "din" is for, and
1554 the MIPs world that was being simulated, to be placed into the
1561 /*---------------------------------------------------------------------------*/
1562 /*-- simulator engine -------------------------------------------------------*/
1563 /*---------------------------------------------------------------------------*/
1566 ColdReset (SIM_DESC sd
)
1569 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1571 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1572 /* RESET: Fixed PC address: */
1573 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1574 /* The reset vector address is in the unmapped, uncached memory space. */
1576 SR
&= ~(status_SR
| status_TS
| status_RP
);
1577 SR
|= (status_ERL
| status_BEV
);
1579 /* Cheat and allow access to the complete register set immediately */
1580 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1581 && WITH_TARGET_WORD_BITSIZE
== 64)
1582 SR
|= status_FR
; /* 64bit registers */
1584 /* Ensure that any instructions with pending register updates are
1586 PENDING_INVALIDATE();
1588 /* Initialise the FPU registers to the unknown state */
1589 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1592 for (rn
= 0; (rn
< 32); rn
++)
1593 FPR_STATE
[rn
] = fmt_uninterpreted
;
1599 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1600 /* Signal an exception condition. This will result in an exception
1601 that aborts the instruction. The instruction operation pseudocode
1602 will never see a return from this function call. */
1605 signal_exception (SIM_DESC sd
,
1613 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1616 /* Ensure that any active atomic read/modify/write operation will fail: */
1619 switch (exception
) {
1624 unsigned int instruction
;
1627 va_start(ap
,exception
);
1628 instruction
= va_arg(ap
,unsigned int);
1631 code
= (instruction
>> 6) & 0xFFFFF;
1633 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1634 code
, pr_addr(cia
));
1638 case DebugBreakPoint
:
1639 if (! (Debug
& Debug_DM
))
1645 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1646 DEPC
= cia
- 4; /* reference the branch instruction */
1650 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1654 Debug
|= Debug_DM
; /* in debugging mode */
1655 Debug
|= Debug_DBp
; /* raising a DBp exception */
1657 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1661 case ReservedInstruction
:
1664 unsigned int instruction
;
1665 va_start(ap
,exception
);
1666 instruction
= va_arg(ap
,unsigned int);
1668 /* Provide simple monitor support using ReservedInstruction
1669 exceptions. The following code simulates the fixed vector
1670 entry points into the IDT monitor by causing a simulator
1671 trap, performing the monitor operation, and returning to
1672 the address held in the $ra register (standard PCS return
1673 address). This means we only need to pre-load the vector
1674 space with suitable instruction values. For systems were
1675 actual trap instructions are used, we would not need to
1676 perform this magic. */
1677 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1679 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1680 /* NOTE: This assumes that a branch-and-link style
1681 instruction was used to enter the vector (which is the
1682 case with the current IDT monitor). */
1683 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1685 /* Look for the mips16 entry and exit instructions, and
1686 simulate a handler for them. */
1687 else if ((cia
& 1) != 0
1688 && (instruction
& 0xf81f) == 0xe809
1689 && (instruction
& 0x0c0) != 0x0c0)
1691 mips16_entry (SD
, CPU
, cia
, instruction
);
1692 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1694 /* else fall through to normal exception processing */
1695 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1700 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1702 /* Keep a copy of the current A0 in-case this is the program exit
1706 unsigned int instruction
;
1707 va_start(ap
, exception
);
1708 instruction
= va_arg(ap
,unsigned int);
1710 /* Check for our special terminating BREAK: */
1711 if ((instruction
& HALT_INSTRUCTION_MASK
)
1712 == (HALT_INSTRUCTION
& HALT_INSTRUCTION_MASK
))
1714 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1715 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1718 if (STATE
& simDELAYSLOT
)
1719 PC
= cia
- 4; /* reference the branch instruction */
1722 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1723 sim_stopped
, SIM_SIGTRAP
);
1726 /* Store exception code into current exception id variable (used
1729 /* TODO: If not simulating exceptions then stop the simulator
1730 execution. At the moment we always stop the simulation. */
1732 /* See figure 5-17 for an outline of the code below */
1733 if (! (SR
& status_EXL
))
1735 CAUSE
= (exception
<< 2);
1736 if (STATE
& simDELAYSLOT
)
1738 STATE
&= ~simDELAYSLOT
;
1740 EPC
= (cia
- 4); /* reference the branch instruction */
1744 /* FIXME: TLB et.al. */
1749 CAUSE
= (exception
<< 2);
1753 /* Store exception code into current exception id variable (used
1755 if (SR
& status_BEV
)
1756 PC
= (signed)0xBFC00200 + 0x180;
1758 PC
= (signed)0x80000000 + 0x180;
1760 switch ((CAUSE
>> 2) & 0x1F)
1763 /* Interrupts arrive during event processing, no need to
1767 case TLBModification
:
1772 case InstructionFetch
:
1774 /* The following is so that the simulator will continue from the
1775 exception address on breakpoint operations. */
1777 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1778 sim_stopped
, SIM_SIGBUS
);
1780 case ReservedInstruction
:
1781 case CoProcessorUnusable
:
1783 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1784 sim_stopped
, SIM_SIGILL
);
1786 case IntegerOverflow
:
1788 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1789 sim_stopped
, SIM_SIGFPE
);
1792 sim_engine_restart (SD
, CPU
, NULL
, PC
);
1798 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1799 sim_stopped
, SIM_SIGTRAP
);
1803 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1804 "FATAL: Should not encounter a breakpoint\n");
1806 default : /* Unknown internal exception */
1808 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1809 sim_stopped
, SIM_SIGABRT
);
1813 case SimulatorFault
:
1817 va_start(ap
,exception
);
1818 msg
= va_arg(ap
,char *);
1820 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1821 "FATAL: Simulator error \"%s\"\n",msg
);
1828 #if defined(WARN_RESULT)
1829 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1830 /* This function indicates that the result of the operation is
1831 undefined. However, this should not affect the instruction
1832 stream. All that is meant to happen is that the destination
1833 register is set to an undefined result. To keep the simulator
1834 simple, we just don't bother updating the destination register, so
1835 the overall result will be undefined. If desired we can stop the
1836 simulator by raising a pseudo-exception. */
1837 #define UndefinedResult() undefined_result (sd,cia)
1839 undefined_result(sd
,cia
)
1843 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1844 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1849 #endif /* WARN_RESULT */
1851 /*-- FPU support routines ---------------------------------------------------*/
1853 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1854 formats conform to ANSI/IEEE Std 754-1985. */
1855 /* SINGLE precision floating:
1856 * seeeeeeeefffffffffffffffffffffff
1858 * e = 8bits = exponent
1859 * f = 23bits = fraction
1861 /* SINGLE precision fixed:
1862 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1864 * i = 31bits = integer
1866 /* DOUBLE precision floating:
1867 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1869 * e = 11bits = exponent
1870 * f = 52bits = fraction
1872 /* DOUBLE precision fixed:
1873 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1875 * i = 63bits = integer
1878 /* Extract sign-bit: */
1879 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1880 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1881 /* Extract biased exponent: */
1882 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1883 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1884 /* Extract unbiased Exponent: */
1885 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1886 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1887 /* Extract complete fraction field: */
1888 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1889 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1890 /* Extract numbered fraction bit: */
1891 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1892 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1894 /* Explicit QNaN values used when value required: */
1895 #define FPQNaN_SINGLE (0x7FBFFFFF)
1896 #define FPQNaN_WORD (0x7FFFFFFF)
1897 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1898 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1900 /* Explicit Infinity values used when required: */
1901 #define FPINF_SINGLE (0x7F800000)
1902 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1904 #if 1 /* def DEBUG */
1905 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1906 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1910 value_fpr (SIM_DESC sd
,
1919 /* Treat unused register values, as fixed-point 64bit values: */
1920 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1922 /* If request to read data as "uninterpreted", then use the current
1924 fmt
= FPR_STATE
[fpr
];
1929 /* For values not yet accessed, set to the desired format: */
1930 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1931 FPR_STATE
[fpr
] = fmt
;
1933 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1936 if (fmt
!= FPR_STATE
[fpr
]) {
1937 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1938 FPR_STATE
[fpr
] = fmt_unknown
;
1941 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1942 /* Set QNaN value: */
1945 value
= FPQNaN_SINGLE
;
1949 value
= FPQNaN_DOUBLE
;
1953 value
= FPQNaN_WORD
;
1957 value
= FPQNaN_LONG
;
1964 } else if (SizeFGR() == 64) {
1968 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1971 case fmt_uninterpreted
:
1985 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1988 case fmt_uninterpreted
:
1991 if ((fpr
& 1) == 0) { /* even registers only */
1992 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
1994 SignalException(ReservedInstruction
,0);
2005 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2008 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2015 store_fpr (SIM_DESC sd
,
2025 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2028 if (SizeFGR() == 64) {
2030 case fmt_uninterpreted_32
:
2031 fmt
= fmt_uninterpreted
;
2034 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2035 FPR_STATE
[fpr
] = fmt
;
2038 case fmt_uninterpreted_64
:
2039 fmt
= fmt_uninterpreted
;
2040 case fmt_uninterpreted
:
2044 FPR_STATE
[fpr
] = fmt
;
2048 FPR_STATE
[fpr
] = fmt_unknown
;
2054 case fmt_uninterpreted_32
:
2055 fmt
= fmt_uninterpreted
;
2058 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2059 FPR_STATE
[fpr
] = fmt
;
2062 case fmt_uninterpreted_64
:
2063 fmt
= fmt_uninterpreted
;
2064 case fmt_uninterpreted
:
2067 if ((fpr
& 1) == 0) { /* even register number only */
2068 FGR
[fpr
+1] = (value
>> 32);
2069 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2070 FPR_STATE
[fpr
+ 1] = fmt
;
2071 FPR_STATE
[fpr
] = fmt
;
2073 FPR_STATE
[fpr
] = fmt_unknown
;
2074 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2075 SignalException(ReservedInstruction
,0);
2080 FPR_STATE
[fpr
] = fmt_unknown
;
2085 #if defined(WARN_RESULT)
2088 #endif /* WARN_RESULT */
2091 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2094 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2111 sim_fpu_32to (&wop
, op
);
2112 boolean
= sim_fpu_is_nan (&wop
);
2119 sim_fpu_64to (&wop
, op
);
2120 boolean
= sim_fpu_is_nan (&wop
);
2124 fprintf (stderr
, "Bad switch\n");
2129 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2143 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2150 sim_fpu_32to (&wop
, op
);
2151 boolean
= sim_fpu_is_infinity (&wop
);
2157 sim_fpu_64to (&wop
, op
);
2158 boolean
= sim_fpu_is_infinity (&wop
);
2162 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2167 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2181 /* Argument checking already performed by the FPCOMPARE code */
2184 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2187 /* The format type should already have been checked: */
2193 sim_fpu_32to (&wop1
, op1
);
2194 sim_fpu_32to (&wop2
, op2
);
2195 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2202 sim_fpu_64to (&wop1
, op1
);
2203 sim_fpu_64to (&wop2
, op2
);
2204 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2208 fprintf (stderr
, "Bad switch\n");
2213 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2227 /* Argument checking already performed by the FPCOMPARE code */
2230 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2233 /* The format type should already have been checked: */
2239 sim_fpu_32to (&wop1
, op1
);
2240 sim_fpu_32to (&wop2
, op2
);
2241 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2248 sim_fpu_64to (&wop1
, op1
);
2249 sim_fpu_64to (&wop2
, op2
);
2250 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2254 fprintf (stderr
, "Bad switch\n");
2259 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2266 AbsoluteValue(op
,fmt
)
2273 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2276 /* The format type should already have been checked: */
2282 sim_fpu_32to (&wop
, op
);
2283 sim_fpu_abs (&wop
, &wop
);
2284 sim_fpu_to32 (&ans
, &wop
);
2292 sim_fpu_64to (&wop
, op
);
2293 sim_fpu_abs (&wop
, &wop
);
2294 sim_fpu_to64 (&ans
, &wop
);
2299 fprintf (stderr
, "Bad switch\n");
2314 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2317 /* The format type should already have been checked: */
2323 sim_fpu_32to (&wop
, op
);
2324 sim_fpu_neg (&wop
, &wop
);
2325 sim_fpu_to32 (&ans
, &wop
);
2333 sim_fpu_64to (&wop
, op
);
2334 sim_fpu_neg (&wop
, &wop
);
2335 sim_fpu_to64 (&ans
, &wop
);
2340 fprintf (stderr
, "Bad switch\n");
2356 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2359 /* The registers must specify FPRs valid for operands of type
2360 "fmt". If they are not valid, the result is undefined. */
2362 /* The format type should already have been checked: */
2370 sim_fpu_32to (&wop1
, op1
);
2371 sim_fpu_32to (&wop2
, op2
);
2372 sim_fpu_add (&ans
, &wop1
, &wop2
);
2373 sim_fpu_to32 (&res
, &ans
);
2383 sim_fpu_64to (&wop1
, op1
);
2384 sim_fpu_64to (&wop2
, op2
);
2385 sim_fpu_add (&ans
, &wop1
, &wop2
);
2386 sim_fpu_to64 (&res
, &ans
);
2391 fprintf (stderr
, "Bad switch\n");
2396 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2411 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2414 /* The registers must specify FPRs valid for operands of type
2415 "fmt". If they are not valid, the result is undefined. */
2417 /* The format type should already have been checked: */
2425 sim_fpu_32to (&wop1
, op1
);
2426 sim_fpu_32to (&wop2
, op2
);
2427 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2428 sim_fpu_to32 (&res
, &ans
);
2438 sim_fpu_64to (&wop1
, op1
);
2439 sim_fpu_64to (&wop2
, op2
);
2440 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2441 sim_fpu_to64 (&res
, &ans
);
2446 fprintf (stderr
, "Bad switch\n");
2451 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2458 Multiply(op1
,op2
,fmt
)
2466 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2469 /* The registers must specify FPRs valid for operands of type
2470 "fmt". If they are not valid, the result is undefined. */
2472 /* The format type should already have been checked: */
2480 sim_fpu_32to (&wop1
, op1
);
2481 sim_fpu_32to (&wop2
, op2
);
2482 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2483 sim_fpu_to32 (&res
, &ans
);
2493 sim_fpu_64to (&wop1
, op1
);
2494 sim_fpu_64to (&wop2
, op2
);
2495 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2496 sim_fpu_to64 (&res
, &ans
);
2501 fprintf (stderr
, "Bad switch\n");
2506 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2521 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2524 /* The registers must specify FPRs valid for operands of type
2525 "fmt". If they are not valid, the result is undefined. */
2527 /* The format type should already have been checked: */
2535 sim_fpu_32to (&wop1
, op1
);
2536 sim_fpu_32to (&wop2
, op2
);
2537 sim_fpu_div (&ans
, &wop1
, &wop2
);
2538 sim_fpu_to32 (&res
, &ans
);
2548 sim_fpu_64to (&wop1
, op1
);
2549 sim_fpu_64to (&wop2
, op2
);
2550 sim_fpu_div (&ans
, &wop1
, &wop2
);
2551 sim_fpu_to64 (&res
, &ans
);
2556 fprintf (stderr
, "Bad switch\n");
2561 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2575 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2578 /* The registers must specify FPRs valid for operands of type
2579 "fmt". If they are not valid, the result is undefined. */
2581 /* The format type should already have been checked: */
2588 sim_fpu_32to (&wop
, op
);
2589 sim_fpu_inv (&ans
, &wop
);
2590 sim_fpu_to32 (&res
, &ans
);
2599 sim_fpu_64to (&wop
, op
);
2600 sim_fpu_inv (&ans
, &wop
);
2601 sim_fpu_to64 (&res
, &ans
);
2606 fprintf (stderr
, "Bad switch\n");
2611 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2625 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2628 /* The registers must specify FPRs valid for operands of type
2629 "fmt". If they are not valid, the result is undefined. */
2631 /* The format type should already have been checked: */
2638 sim_fpu_32to (&wop
, op
);
2639 sim_fpu_sqrt (&ans
, &wop
);
2640 sim_fpu_to32 (&res
, &ans
);
2649 sim_fpu_64to (&wop
, op
);
2650 sim_fpu_sqrt (&ans
, &wop
);
2651 sim_fpu_to64 (&res
, &ans
);
2656 fprintf (stderr
, "Bad switch\n");
2661 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2677 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2680 /* The registers must specify FPRs valid for operands of type
2681 "fmt". If they are not valid, the result is undefined. */
2683 /* The format type should already have been checked: */
2690 sim_fpu_32to (&wop1
, op1
);
2691 sim_fpu_32to (&wop2
, op2
);
2692 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2699 sim_fpu_64to (&wop1
, op1
);
2700 sim_fpu_64to (&wop2
, op2
);
2701 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2705 fprintf (stderr
, "Bad switch\n");
2711 case SIM_FPU_IS_SNAN
:
2712 case SIM_FPU_IS_QNAN
:
2714 case SIM_FPU_IS_NINF
:
2715 case SIM_FPU_IS_NNUMBER
:
2716 case SIM_FPU_IS_NDENORM
:
2717 case SIM_FPU_IS_NZERO
:
2718 result
= op2
; /* op1 - op2 < 0 */
2719 case SIM_FPU_IS_PINF
:
2720 case SIM_FPU_IS_PNUMBER
:
2721 case SIM_FPU_IS_PDENORM
:
2722 case SIM_FPU_IS_PZERO
:
2723 result
= op1
; /* op1 - op2 > 0 */
2725 fprintf (stderr
, "Bad switch\n");
2730 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2747 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2750 /* The registers must specify FPRs valid for operands of type
2751 "fmt". If they are not valid, the result is undefined. */
2753 /* The format type should already have been checked: */
2760 sim_fpu_32to (&wop1
, op1
);
2761 sim_fpu_32to (&wop2
, op2
);
2762 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2769 sim_fpu_64to (&wop1
, op1
);
2770 sim_fpu_64to (&wop2
, op2
);
2771 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2775 fprintf (stderr
, "Bad switch\n");
2781 case SIM_FPU_IS_SNAN
:
2782 case SIM_FPU_IS_QNAN
:
2784 case SIM_FPU_IS_NINF
:
2785 case SIM_FPU_IS_NNUMBER
:
2786 case SIM_FPU_IS_NDENORM
:
2787 case SIM_FPU_IS_NZERO
:
2788 result
= op1
; /* op1 - op2 < 0 */
2789 case SIM_FPU_IS_PINF
:
2790 case SIM_FPU_IS_PNUMBER
:
2791 case SIM_FPU_IS_PDENORM
:
2792 case SIM_FPU_IS_PZERO
:
2793 result
= op2
; /* op1 - op2 > 0 */
2795 fprintf (stderr
, "Bad switch\n");
2800 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2808 convert (SIM_DESC sd
,
2817 sim_fpu_round round
;
2818 unsigned32 result32
;
2819 unsigned64 result64
;
2822 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2828 /* Round result to nearest representable value. When two
2829 representable values are equally near, round to the value
2830 that has a least significant bit of zero (i.e. is even). */
2831 round
= sim_fpu_round_near
;
2834 /* Round result to the value closest to, and not greater in
2835 magnitude than, the result. */
2836 round
= sim_fpu_round_zero
;
2839 /* Round result to the value closest to, and not less than,
2841 round
= sim_fpu_round_up
;
2845 /* Round result to the value closest to, and not greater than,
2847 round
= sim_fpu_round_down
;
2851 fprintf (stderr
, "Bad switch\n");
2855 /* Convert the input to sim_fpu internal format */
2859 sim_fpu_64to (&wop
, op
);
2862 sim_fpu_32to (&wop
, op
);
2865 sim_fpu_i32to (&wop
, op
, round
);
2868 sim_fpu_i64to (&wop
, op
, round
);
2871 fprintf (stderr
, "Bad switch\n");
2875 /* Convert sim_fpu format into the output */
2876 /* The value WOP is converted to the destination format, rounding
2877 using mode RM. When the destination is a fixed-point format, then
2878 a source value of Infinity, NaN or one which would round to an
2879 integer outside the fixed point range then an IEEE Invalid
2880 Operation condition is raised. */
2884 sim_fpu_round_32 (&wop
, round
, 0);
2885 sim_fpu_to32 (&result32
, &wop
);
2886 result64
= result32
;
2889 sim_fpu_round_64 (&wop
, round
, 0);
2890 sim_fpu_to64 (&result64
, &wop
);
2893 sim_fpu_to32i (&result32
, &wop
, round
);
2894 result64
= result32
;
2897 sim_fpu_to64i (&result64
, &wop
, round
);
2901 fprintf (stderr
, "Bad switch\n");
2906 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2913 /*-- co-processor support routines ------------------------------------------*/
2916 CoProcPresent(coproc_number
)
2917 unsigned int coproc_number
;
2919 /* Return TRUE if simulator provides a model for the given co-processor number */
2924 cop_lw (SIM_DESC sd
,
2929 unsigned int memword
)
2934 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2937 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2939 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2940 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2945 #if 0 /* this should be controlled by a configuration option */
2946 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2955 cop_ld (SIM_DESC sd
,
2962 switch (coproc_num
) {
2964 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2966 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2971 #if 0 /* this message should be controlled by a configuration option */
2972 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2981 /* start-sanitize-sky */
2984 cop_lq (SIM_DESC sd
,
2989 unsigned128 memword
)
3000 /* one word at a time, argh! */
3004 value
= H2T_4(*A4_16(& memword
, 3-i
));
3005 write_vu_vec_reg(&(vu0_device
.regs
), coproc_reg
, i
, & value
);
3011 sim_io_printf(sd
,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3012 coproc_num
,coproc_reg
,pr_addr(cia
));
3018 #endif /* TARGET_SKY */
3019 /* end-sanitize-sky */
3023 cop_sw (SIM_DESC sd
,
3029 unsigned int value
= 0;
3034 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3037 hold
= FPR_STATE
[coproc_reg
];
3038 FPR_STATE
[coproc_reg
] = fmt_word
;
3039 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3040 FPR_STATE
[coproc_reg
] = hold
;
3045 #if 0 /* should be controlled by configuration option */
3046 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3055 cop_sd (SIM_DESC sd
,
3065 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3067 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3072 #if 0 /* should be controlled by configuration option */
3073 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3082 /* start-sanitize-sky */
3085 cop_sq (SIM_DESC sd
,
3091 unsigned128 value
= U16_8(0, 0);
3102 /* one word at a time, argh! */
3106 read_vu_vec_reg(&(vu0_device
.regs
), coproc_reg
, i
, & value
);
3107 *A4_16(& xyzw
, 3-i
) = T2H_4(value
);
3114 sim_io_printf(sd
,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3115 coproc_num
,coproc_reg
,pr_addr(cia
));
3121 #endif /* TARGET_SKY */
3122 /* end-sanitize-sky */
3126 decode_coproc (SIM_DESC sd
,
3129 unsigned int instruction
)
3131 int coprocnum
= ((instruction
>> 26) & 3);
3135 case 0: /* standard CPU control and cache registers */
3137 int code
= ((instruction
>> 21) & 0x1F);
3138 /* R4000 Users Manual (second edition) lists the following CP0
3140 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3141 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3142 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3143 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3144 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3145 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3146 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3147 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3148 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3149 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3151 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3153 int rt
= ((instruction
>> 16) & 0x1F);
3154 int rd
= ((instruction
>> 11) & 0x1F);
3156 switch (rd
) /* NOTEs: Standard CP0 registers */
3158 /* 0 = Index R4000 VR4100 VR4300 */
3159 /* 1 = Random R4000 VR4100 VR4300 */
3160 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3161 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3162 /* 4 = Context R4000 VR4100 VR4300 */
3163 /* 5 = PageMask R4000 VR4100 VR4300 */
3164 /* 6 = Wired R4000 VR4100 VR4300 */
3165 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3166 /* 9 = Count R4000 VR4100 VR4300 */
3167 /* 10 = EntryHi R4000 VR4100 VR4300 */
3168 /* 11 = Compare R4000 VR4100 VR4300 */
3169 /* 12 = SR R4000 VR4100 VR4300 */
3176 /* 13 = Cause R4000 VR4100 VR4300 */
3183 /* 14 = EPC R4000 VR4100 VR4300 */
3186 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
3190 /* 15 = PRId R4000 VR4100 VR4300 */
3191 #ifdef SUBTARGET_R3900
3200 /* 16 = Config R4000 VR4100 VR4300 */
3203 GPR
[rt
] = C0_CONFIG
;
3205 C0_CONFIG
= GPR
[rt
];
3208 #ifdef SUBTARGET_R3900
3217 /* 17 = LLAddr R4000 VR4100 VR4300 */
3219 /* 18 = WatchLo R4000 VR4100 VR4300 */
3220 /* 19 = WatchHi R4000 VR4100 VR4300 */
3221 /* 20 = XContext R4000 VR4100 VR4300 */
3222 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3223 /* 27 = CacheErr R4000 VR4100 */
3224 /* 28 = TagLo R4000 VR4100 VR4300 */
3225 /* 29 = TagHi R4000 VR4100 VR4300 */
3226 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3227 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3228 /* CPR[0,rd] = GPR[rt]; */
3231 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3233 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3236 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3239 if (SR
& status_ERL
)
3241 /* Oops, not yet available */
3242 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3252 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3256 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3264 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3265 /* TODO: When executing an ERET or RFE instruction we should
3266 clear LLBIT, to ensure that any out-standing atomic
3267 read/modify/write sequence fails. */
3271 case 2: /* co-processor 2 */
3275 /* start-sanitize-sky */
3277 /* On the R5900, this refers to a "VU" vector co-processor. */
3279 int i_25_21
= (instruction
>> 21) & 0x1f;
3280 int i_20_16
= (instruction
>> 16) & 0x1f;
3281 int i_20_6
= (instruction
>> 6) & 0x7fff;
3282 int i_15_11
= (instruction
>> 11) & 0x1f;
3283 int i_15_0
= instruction
& 0xffff;
3284 int i_10_1
= (instruction
>> 1) & 0x3ff;
3285 int i_10_0
= instruction
& 0x7ff;
3286 int i_10_6
= (instruction
>> 6) & 0x1f;
3287 int i_5_0
= instruction
& 0x03f;
3288 int interlock
= instruction
& 0x01;
3289 /* setup for semantic.c-like actions below */
3290 typedef unsigned_4 instruction_word
;
3296 /* test COP2 usability */
3297 if(! (SR
& status_CU2
))
3299 SignalException(CoProcessorUnusable
,instruction
);
3303 #define MY_INDEX itable_COPz_NORMAL
3304 #define MY_PREFIX COPz_NORMAL
3305 #define MY_NAME "COPz_NORMAL"
3307 /* classify & execute basic COP2 instructions */
3308 if(i_25_21
== 0x08 && i_20_16
== 0x00) /* BC2F */
3310 address_word offset
= EXTEND16(i_15_0
) << 2;
3311 if(! vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3313 else if(i_25_21
== 0x08 && i_20_16
==0x02) /* BC2FL */
3315 address_word offset
= EXTEND16(i_15_0
) << 2;
3316 if(! vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3317 else NULLIFY_NEXT_INSTRUCTION();
3319 else if(i_25_21
== 0x08 && i_20_16
== 0x01) /* BC2T */
3321 address_word offset
= EXTEND16(i_15_0
) << 2;
3322 if(vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3324 else if(i_25_21
== 0x08 && i_20_16
== 0x03) /* BC2TL */
3326 address_word offset
= EXTEND16(i_15_0
) << 2;
3327 if(vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3328 else NULLIFY_NEXT_INSTRUCTION();
3330 else if((i_25_21
== 0x02 && i_10_1
== 0x000) || /* CFC2 */
3331 (i_25_21
== 0x01)) /* QMFC2 */
3336 /* interlock checking */
3337 /* POLICY: never busy in macro mode */
3338 while(vu0_busy() && interlock
)
3341 /* perform VU register address */
3342 if(i_25_21
== 0x01) /* QMFC2 */
3345 /* one word at a time, argh! */
3346 read_vu_vec_reg(&(vu0_device
.regs
), id
, 0, A4_16(& xyzw
, 3));
3347 read_vu_vec_reg(&(vu0_device
.regs
), id
, 1, A4_16(& xyzw
, 2));
3348 read_vu_vec_reg(&(vu0_device
.regs
), id
, 2, A4_16(& xyzw
, 1));
3349 read_vu_vec_reg(&(vu0_device
.regs
), id
, 3, A4_16(& xyzw
, 0));
3350 GPR
[rt
] = T2H_8(* A8_16(& xyzw
, 1));
3351 GPR1
[rt
] = T2H_8(* A8_16(& xyzw
, 0));
3356 /* enum + int calculation, argh! */
3357 id
= VU_REG_MST
+ 16 * id
;
3358 read_vu_misc_reg(&(vu0_device
.regs
), id
, & data
);
3359 GPR
[rt
] = EXTEND32(T2H_4(data
));
3362 else if((i_25_21
== 0x06 && i_10_1
== 0x000) || /* CTC2 */
3363 (i_25_21
== 0x05)) /* QMTC2 */
3368 /* interlock checking: wait until M or E bits set */
3369 /* POLICY: never busy in macro mode */
3370 while(vu0_busy() && interlock
)
3372 if(vu0_micro_interlock_released())
3374 vu0_micro_interlock_clear();
3381 /* perform VU register address */
3382 if(i_25_21
== 0x05) /* QMTC2 */
3384 unsigned_16 xyzw
= U16_8(GPR1
[rt
], GPR
[rt
]);
3386 xyzw
= H2T_16(xyzw
);
3387 /* one word at a time, argh! */
3388 write_vu_vec_reg(&(vu0_device
.regs
), id
, 0, A4_16(& xyzw
, 3));
3389 write_vu_vec_reg(&(vu0_device
.regs
), id
, 1, A4_16(& xyzw
, 2));
3390 write_vu_vec_reg(&(vu0_device
.regs
), id
, 2, A4_16(& xyzw
, 1));
3391 write_vu_vec_reg(&(vu0_device
.regs
), id
, 3, A4_16(& xyzw
, 0));
3395 unsigned_4 data
= H2T_4(GPR
[rt
]);
3396 /* enum + int calculation, argh! */
3397 id
= VU_REG_MST
+ 16 * id
;
3398 write_vu_misc_reg(&(vu0_device
.regs
), id
, & data
);
3401 else if(i_10_0
== 0x3bf) /* VWAITQ */
3406 else if(i_5_0
== 0x38) /* VCALLMS */
3408 unsigned_4 data
= H2T_2(i_20_6
);
3413 /* write to reserved CIA register to get VU0 moving */
3414 write_vu_special_reg(& vu0_device
, VU_REG_CIA
, & data
);
3418 else if(i_5_0
== 0x39) /* VCALLMSR */
3425 read_vu_special_reg(& vu0_device
, VU_REG_CMSAR0
, & data
);
3426 /* write to reserved CIA register to get VU0 moving */
3427 write_vu_special_reg(& vu0_device
, VU_REG_CIA
, & data
);
3431 /* handle all remaining UPPER VU instructions in one block */
3432 else if((i_5_0
< 0x30) || /* VADDx .. VMINI */
3433 (i_5_0
>= 0x3c && i_10_6
< 0x0c)) /* VADDAx .. VNOP */
3435 unsigned_4 vu_upper
, vu_lower
;
3437 0x00000000 | /* bits 31 .. 25 */
3438 (instruction
& 0x01ffffff); /* bits 24 .. 0 */
3439 vu_lower
= 0x8000033c; /* NOP */
3441 /* POLICY: never busy in macro mode */
3445 vu0_macro_issue(vu_upper
, vu_lower
);
3447 /* POLICY: wait for completion of macro-instruction */
3451 /* handle all remaining LOWER VU instructions in one block */
3452 else if((i_5_0
>= 0x30 && i_5_0
<= 0x35) || /* VIADD .. VIOR */
3453 (i_5_0
>= 0x3c && i_10_6
>= 0x0c)) /* VMOVE .. VRXOR */
3454 { /* N.B.: VWAITQ already covered by prior case */
3455 unsigned_4 vu_upper
, vu_lower
;
3456 vu_upper
= 0x000002ff; /* NOP/NOP */
3458 0x80000000 | /* bits 31 .. 25 */
3459 (instruction
& 0x01ffffff); /* bits 24 .. 0 */
3461 /* POLICY: never busy in macro mode */
3465 vu0_macro_issue(vu_upper
, vu_lower
);
3467 /* POLICY: wait for completion of macro-instruction */
3471 /* ... no other COP2 instructions ... */
3474 SignalException(ReservedInstruction
, instruction
);
3478 /* cleanup for semantic.c-like actions above */
3485 #endif /* TARGET_SKY */
3486 /* end-sanitize-sky */
3490 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3491 instruction
,pr_addr(cia
));
3496 case 1: /* should not occur (FPU co-processor) */
3497 case 3: /* should not occur (FPU co-processor) */
3498 SignalException(ReservedInstruction
,instruction
);
3506 /*-- instruction simulation -------------------------------------------------*/
3508 /* When the IGEN simulator is being built, the function below is be
3509 replaced by a generated version. However, WITH_IGEN == 2 indicates
3510 that the fubction below should be compiled but under a different
3511 name (to allow backward compatibility) */
3513 #if (WITH_IGEN != 1)
3515 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3517 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3520 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3523 int next_cpu_nr
; /* ignore */
3524 int nr_cpus
; /* ignore */
3525 int siggnal
; /* ignore */
3527 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3528 #if !defined(FASTSIM)
3529 unsigned int pipeline_count
= 1;
3533 if (STATE_MEMORY (sd
) == NULL
) {
3534 printf("DBG: simulate() entered with no memory\n");
3539 #if 0 /* Disabled to check that everything works OK */
3540 /* The VR4300 seems to sign-extend the PC on its first
3541 access. However, this may just be because it is currently
3542 configured in 32bit mode. However... */
3543 PC
= SIGNEXTEND(PC
,32);
3546 /* main controlling loop */
3548 /* vaddr is slowly being replaced with cia - current instruction
3550 address_word cia
= (uword64
)PC
;
3551 address_word vaddr
= cia
;
3554 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3558 printf("DBG: state = 0x%08X :",state
);
3559 if (state
& simHALTEX
) printf(" simHALTEX");
3560 if (state
& simHALTIN
) printf(" simHALTIN");
3565 DSSTATE
= (STATE
& simDELAYSLOT
);
3568 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3571 /* Fetch the next instruction from the simulator memory: */
3572 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3573 if ((vaddr
& 1) == 0) {
3574 /* Copy the action of the LW instruction */
3575 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3576 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3579 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3580 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3581 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3582 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3584 /* Copy the action of the LH instruction */
3585 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3586 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3589 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3590 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3591 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3592 paddr
& ~ (uword64
) 1,
3593 vaddr
, isINSTRUCTION
, isREAL
);
3594 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3595 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3598 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3603 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3606 /* This is required by exception processing, to ensure that we can
3607 cope with exceptions in the delay slots of branches that may
3608 already have changed the PC. */
3609 if ((vaddr
& 1) == 0)
3610 PC
+= 4; /* increment ready for the next fetch */
3613 /* NOTE: If we perform a delay slot change to the PC, this
3614 increment is not requuired. However, it would make the
3615 simulator more complicated to try and avoid this small hit. */
3617 /* Currently this code provides a simple model. For more
3618 complicated models we could perform exception status checks at
3619 this point, and set the simSTOP state as required. This could
3620 also include processing any hardware interrupts raised by any
3621 I/O model attached to the simulator context.
3623 Support for "asynchronous" I/O events within the simulated world
3624 could be providing by managing a counter, and calling a I/O
3625 specific handler when a particular threshold is reached. On most
3626 architectures a decrement and check for zero operation is
3627 usually quicker than an increment and compare. However, the
3628 process of managing a known value decrement to zero, is higher
3629 than the cost of using an explicit value UINT_MAX into the
3630 future. Which system is used will depend on how complicated the
3631 I/O model is, and how much it is likely to affect the simulator
3634 If events need to be scheduled further in the future than
3635 UINT_MAX event ticks, then the I/O model should just provide its
3636 own counter, triggered from the event system. */
3638 /* MIPS pipeline ticks. To allow for future support where the
3639 pipeline hit of individual instructions is known, this control
3640 loop manages a "pipeline_count" variable. It is initialised to
3641 1 (one), and will only be changed by the simulator engine when
3642 executing an instruction. If the engine does not have access to
3643 pipeline cycle count information then all instructions will be
3644 treated as using a single cycle. NOTE: A standard system is not
3645 provided by the default simulator because different MIPS
3646 architectures have different cycle counts for the same
3649 [NOTE: pipeline_count has been replaced the event queue] */
3651 /* shuffle the floating point status pipeline state */
3652 ENGINE_ISSUE_PREFIX_HOOK();
3654 /* NOTE: For multi-context simulation environments the "instruction"
3655 variable should be local to this routine. */
3657 /* Shorthand accesses for engine. Note: If we wanted to use global
3658 variables (and a single-threaded simulator engine), then we can
3659 create the actual variables with these names. */
3661 if (!(STATE
& simSKIPNEXT
)) {
3662 /* Include the simulator engine */
3663 #include "oengine.c"
3664 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3665 #error "Mismatch between run-time simulator code and simulation engine"
3667 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3668 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3670 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3671 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3674 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3675 should check for it being changed. It is better doing it here,
3676 than within the simulator, since it will help keep the simulator
3679 #if defined(WARN_ZERO)
3680 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3681 #endif /* WARN_ZERO */
3682 ZERO
= 0; /* reset back to zero before next instruction */
3684 } else /* simSKIPNEXT check */
3685 STATE
&= ~simSKIPNEXT
;
3687 /* If the delay slot was active before the instruction is
3688 executed, then update the PC to its new value: */
3691 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3700 #if !defined(FASTSIM)
3701 if (sim_events_tickn (sd
, pipeline_count
))
3703 /* cpu->cia = cia; */
3704 sim_events_process (sd
);
3707 if (sim_events_tick (sd
))
3709 /* cpu->cia = cia; */
3710 sim_events_process (sd
);
3712 #endif /* FASTSIM */
3718 /* This code copied from gdb's utils.c. Would like to share this code,
3719 but don't know of a common place where both could get to it. */
3721 /* Temporary storage using circular buffer */
3727 static char buf
[NUMCELLS
][CELLSIZE
];
3729 if (++cell
>=NUMCELLS
) cell
=0;
3733 /* Print routines to handle variable size regs, etc */
3735 /* Eliminate warning from compiler on 32-bit systems */
3736 static int thirty_two
= 32;
3742 char *paddr_str
=get_cell();
3743 switch (sizeof(addr
))
3746 sprintf(paddr_str
,"%08lx%08lx",
3747 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3750 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3753 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3756 sprintf(paddr_str
,"%x",addr
);
3765 char *paddr_str
=get_cell();
3766 sprintf(paddr_str
,"%08lx%08lx",
3767 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3773 /*---------------------------------------------------------------------------*/
3774 /*> EOF interp.c <*/