2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
83 /* The following reserved instruction value is used when a simulator
84 trap is required. NOTE: Care must be taken, since this value may be
85 used in later revisions of the MIPS ISA. */
86 #define RSVD_INSTRUCTION (0x00000005)
87 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
89 #define RSVD_INSTRUCTION_ARG_SHIFT 6
90 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
93 /* Bits in the Debug register */
94 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
95 #define Debug_DM 0x40000000 /* Debug Mode */
96 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
102 /*---------------------------------------------------------------------------*/
103 /*-- GDB simulator interface ------------------------------------------------*/
104 /*---------------------------------------------------------------------------*/
106 static void ColdReset
PARAMS((SIM_DESC sd
));
108 /*---------------------------------------------------------------------------*/
112 #define DELAYSLOT() {\
113 if (STATE & simDELAYSLOT)\
114 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
115 STATE |= simDELAYSLOT;\
118 #define JALDELAYSLOT() {\
120 STATE |= simJALDELAYSLOT;\
124 STATE &= ~simDELAYSLOT;\
125 STATE |= simSKIPNEXT;\
128 #define CANCELDELAYSLOT() {\
130 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
133 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
134 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
136 #define K0BASE (0x80000000)
137 #define K0SIZE (0x20000000)
138 #define K1BASE (0xA0000000)
139 #define K1SIZE (0x20000000)
140 #define MONITOR_BASE (0xBFC00000)
141 #define MONITOR_SIZE (1 << 11)
142 #define MEM_SIZE (2 << 20)
145 static char *tracefile
= "trace.din"; /* default filename for trace log */
146 FILE *tracefh
= NULL
;
147 static void open_trace
PARAMS((SIM_DESC sd
));
150 #define OPTION_DINERO_TRACE 200
151 #define OPTION_DINERO_FILE 201
154 mips_option_handler (sd
, opt
, arg
)
161 case OPTION_DINERO_TRACE
: /* ??? */
163 /* Eventually the simTRACE flag could be treated as a toggle, to
164 allow external control of the program points being traced
165 (i.e. only from main onwards, excluding the run-time setup,
169 else if (strcmp (arg
, "yes") == 0)
171 else if (strcmp (arg
, "no") == 0)
173 else if (strcmp (arg
, "on") == 0)
175 else if (strcmp (arg
, "off") == 0)
179 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
185 Simulator constructed without dinero tracing support (for performance).\n\
186 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
190 case OPTION_DINERO_FILE
:
192 if (optarg
!= NULL
) {
194 tmp
= (char *)malloc(strlen(optarg
) + 1);
197 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
203 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
214 static const OPTION mips_options
[] =
216 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
217 '\0', "on|off", "Enable dinero tracing",
218 mips_option_handler
},
219 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
220 '\0', "FILE", "Write dinero trace to FILE",
221 mips_option_handler
},
222 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
226 int interrupt_pending
;
229 interrupt_event (SIM_DESC sd
, void *data
)
233 interrupt_pending
= 0;
234 SignalExceptionInterrupt ();
236 else if (!interrupt_pending
)
237 sim_events_schedule (sd
, 1, interrupt_event
, data
);
242 /*---------------------------------------------------------------------------*/
243 /*-- GDB simulator interface ------------------------------------------------*/
244 /*---------------------------------------------------------------------------*/
247 sim_open (kind
, cb
, abfd
, argv
)
253 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
254 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
256 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
258 /* FIXME: watchpoints code shouldn't need this */
259 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
260 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
261 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
265 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
267 sim_add_option_table (sd
, mips_options
);
269 /* Allocate core managed memory */
272 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
273 /* For compatibility with the old code - under this (at level one)
274 are the kernel spaces K0 & K1. Both of these map to a single
275 smaller sub region */
276 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
278 MEM_SIZE
, /* actual size */
281 /* getopt will print the error message so we just have to exit if this fails.
282 FIXME: Hmmm... in the case of gdb we need getopt to call
284 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
286 /* Uninstall the modules to avoid memory leaks,
287 file descriptor leaks, etc. */
288 sim_module_uninstall (sd
);
292 /* check for/establish the a reference program image */
293 if (sim_analyze_program (sd
,
294 (STATE_PROG_ARGV (sd
) != NULL
295 ? *STATE_PROG_ARGV (sd
)
299 sim_module_uninstall (sd
);
303 /* Configure/verify the target byte order and other runtime
304 configuration options */
305 if (sim_config (sd
) != SIM_RC_OK
)
307 sim_module_uninstall (sd
);
311 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
313 /* Uninstall the modules to avoid memory leaks,
314 file descriptor leaks, etc. */
315 sim_module_uninstall (sd
);
319 /* verify assumptions the simulator made about the host type system.
320 This macro does not return if there is a problem */
321 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
322 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
325 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
326 and DOUBLE binary formats. This is a bit nasty, requiring that we
327 trust the explicit manifests held in the source: */
328 /* TODO: We need to cope with the simulated target and the host not
329 having the same endianness. This will require the high and low
330 words of a (double) to be swapped when converting between the
331 host and the simulated target. */
339 s
.d
= (double)523.2939453125;
341 if ((s
.i
[0] == 0 && (s
.f
[1] != (float)4.01102924346923828125
342 || s
.i
[1] != 0x40805A5A))
343 || (s
.i
[1] == 0 && (s
.f
[0] != (float)4.01102924346923828125
344 || s
.i
[0] != 0x40805A5A)))
346 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
352 /* This is NASTY, in that we are assuming the size of specific
356 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
358 cpu
->register_widths
[rn
] = GPRLEN
;
359 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
360 cpu
->register_widths
[rn
] = GPRLEN
;
361 else if ((rn
>= 33) && (rn
<= 37))
362 cpu
->register_widths
[rn
] = GPRLEN
;
363 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
364 cpu
->register_widths
[rn
] = 32;
366 cpu
->register_widths
[rn
] = 0;
368 /* start-sanitize-r5900 */
370 /* set the 5900 "upper" registers to 64 bits */
371 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
372 cpu
->register_widths
[rn
] = 64;
373 /* end-sanitize-r5900 */
377 if (STATE
& simTRACE
)
381 /* Write the monitor trap address handlers into the monitor (eeprom)
382 address space. This can only be done once the target endianness
383 has been determined. */
386 /* Entry into the IDT monitor is via fixed address vectors, and
387 not using machine instructions. To avoid clashing with use of
388 the MIPS TRAP system, we place our own (simulator specific)
389 "undefined" instructions into the relevant vector slots. */
390 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
392 address_word vaddr
= (MONITOR_BASE
+ loop
);
393 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
395 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
397 /* The PMON monitor uses the same address space, but rather than
398 branching into it the address of a routine is loaded. We can
399 cheat for the moment, and direct the PMON routine to IDT style
400 instructions within the monitor space. This relies on the IDT
401 monitor not using the locations from 0xBFC00500 onwards as its
403 for (loop
= 0; (loop
< 24); loop
++)
405 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
406 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
422 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
424 case 8: /* cliexit */
427 case 11: /* flush_cache */
431 /* FIXME - should monitor_base be SIM_ADDR?? */
432 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
434 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
436 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
438 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
450 tracefh
= fopen(tracefile
,"wb+");
453 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
460 sim_close (sd
, quitting
)
465 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
468 /* "quitting" is non-zero if we cannot hang on errors */
470 /* Ensure that any resources allocated through the callback
471 mechanism are released: */
472 sim_io_shutdown (sd
);
475 if (tracefh
!= NULL
&& tracefh
!= stderr
)
486 sim_write (sd
,addr
,buffer
,size
)
489 unsigned char *buffer
;
494 /* Return the number of bytes written, or zero if error. */
496 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
499 /* We use raw read and write routines, since we do not want to count
500 the GDB memory accesses in our statistics gathering. */
502 for (index
= 0; index
< size
; index
++)
504 address_word vaddr
= (address_word
)addr
+ index
;
507 if (!address_translation (sd
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
509 if (sim_core_write_buffer (sd
, NULL
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
517 sim_read (sd
,addr
,buffer
,size
)
520 unsigned char *buffer
;
525 /* Return the number of bytes read, or zero if error. */
527 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
530 for (index
= 0; (index
< size
); index
++)
532 address_word vaddr
= (address_word
)addr
+ index
;
535 if (!address_translation (sd
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
537 if (sim_core_read_buffer (sd
, NULL
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
545 sim_store_register (sd
,rn
,memory
)
548 unsigned char *memory
;
550 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
551 /* NOTE: gdb (the client) stores registers in target byte order
552 while the simulator uses host byte order */
554 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
557 /* Unfortunately this suffers from the same problem as the register
558 numbering one. We need to know what the width of each logical
559 register number is for the architecture being simulated. */
561 if (cpu
->register_widths
[rn
] == 0)
562 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
563 /* start-sanitize-r5900 */
564 else if (rn
== REGISTER_SA
)
565 SA
= T2H_8(*(uword64
*)memory
);
566 else if (rn
> LAST_EMBED_REGNUM
)
567 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(uword64
*)memory
);
568 /* end-sanitize-r5900 */
569 else if (cpu
->register_widths
[rn
] == 32)
570 cpu
->registers
[rn
] = T2H_4 (*(unsigned int*)memory
);
572 cpu
->registers
[rn
] = T2H_8 (*(uword64
*)memory
);
578 sim_fetch_register (sd
,rn
,memory
)
581 unsigned char *memory
;
583 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
584 /* NOTE: gdb (the client) stores registers in target byte order
585 while the simulator uses host byte order */
587 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
590 if (cpu
->register_widths
[rn
] == 0)
591 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
592 /* start-sanitize-r5900 */
593 else if (rn
== REGISTER_SA
)
594 *((uword64
*)memory
) = H2T_8(SA
);
595 else if (rn
> LAST_EMBED_REGNUM
)
596 *((uword64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
597 /* end-sanitize-r5900 */
598 else if (cpu
->register_widths
[rn
] == 32)
599 *((unsigned int *)memory
) = H2T_4 ((unsigned int)(cpu
->registers
[rn
] & 0xFFFFFFFF));
600 else /* 64bit register */
601 *((uword64
*)memory
) = H2T_8 (cpu
->registers
[rn
]);
608 sim_info (sd
,verbose
)
612 /* Accessed from the GDB "info files" command: */
613 if (STATE_VERBOSE_P (sd
) || verbose
)
616 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
617 (PROCESSOR_64BIT
? 64 : 32),
618 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
620 #if !defined(FASTSIM)
621 /* It would be a useful feature, if when performing multi-cycle
622 simulations (rather than single-stepping) we keep the start and
623 end times of the execution, so that we can give a performance
624 figure for the simulator. */
625 #endif /* !FASTSIM */
626 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
627 (long) sim_events_time (sd
));
629 /* print information pertaining to MIPS ISA and architecture being simulated */
630 /* things that may be interesting */
631 /* instructions executed - if available */
632 /* cycles executed - if available */
633 /* pipeline stalls - if available */
634 /* virtual time taken */
636 /* profiling frequency */
640 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
645 sim_create_inferior (sd
, abfd
, argv
,env
)
653 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
660 /* override PC value set by ColdReset () */
661 PC
= (unsigned64
) bfd_get_start_address (abfd
);
663 #if 0 /* def DEBUG */
666 /* We should really place the argv slot values into the argument
667 registers, and onto the stack as required. However, this
668 assumes that we have a stack defined, which is not
669 necessarily true at the moment. */
671 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
672 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
673 printf("DBG: arg \"%s\"\n",*cptr
);
681 sim_do_command (sd
,cmd
)
685 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
686 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
690 /*---------------------------------------------------------------------------*/
691 /*-- Private simulator support interface ------------------------------------*/
692 /*---------------------------------------------------------------------------*/
694 /* Read a null terminated string from memory, return in a buffer */
703 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
705 buf
= NZALLOC (char, nr
+ 1);
706 sim_read (sd
, addr
, buf
, nr
);
710 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
712 sim_monitor(sd
,cia
,reason
)
718 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
721 /* The IDT monitor actually allows two instructions per vector
722 slot. However, the simulator currently causes a trap on each
723 individual instruction. We cheat, and lose the bottom bit. */
726 /* The following callback functions are available, however the
727 monitor we are simulating does not make use of them: get_errno,
728 isatty, lseek, rename, system, time and unlink */
732 case 6: /* int open(char *path,int flags) */
734 char *path
= fetch_str (sd
, A0
);
735 V0
= sim_io_open (sd
, path
, (int)A1
);
740 case 7: /* int read(int file,char *ptr,int len) */
744 char *buf
= zalloc (nr
);
745 V0
= sim_io_read (sd
, fd
, buf
, nr
);
746 sim_write (sd
, A1
, buf
, nr
);
751 case 8: /* int write(int file,char *ptr,int len) */
755 char *buf
= zalloc (nr
);
756 sim_read (sd
, A1
, buf
, nr
);
757 V0
= sim_io_write (sd
, fd
, buf
, nr
);
762 case 10: /* int close(int file) */
764 V0
= sim_io_close (sd
, (int)A0
);
768 case 2: /* Densan monitor: char inbyte(int waitflag) */
770 if (A0
== 0) /* waitflag == NOWAIT */
773 /* Drop through to case 11 */
775 case 11: /* char inbyte(void) */
778 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
780 sim_io_error(sd
,"Invalid return from character read");
788 case 3: /* Densan monitor: void co(char chr) */
789 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
791 char tmp
= (char)(A0
& 0xFF);
792 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
796 case 17: /* void _exit() */
798 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
799 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
, sim_exited
,
800 (unsigned int)(A0
& 0xFFFFFFFF));
804 case 28 : /* PMON flush_cache */
807 case 55: /* void get_mem_info(unsigned int *ptr) */
808 /* in: A0 = pointer to three word memory location */
809 /* out: [A0 + 0] = size */
810 /* [A0 + 4] = instruction cache size */
811 /* [A0 + 8] = data cache size */
813 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
815 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
816 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
820 case 158 : /* PMON printf */
821 /* in: A0 = pointer to format string */
822 /* A1 = optional argument 1 */
823 /* A2 = optional argument 2 */
824 /* A3 = optional argument 3 */
826 /* The following is based on the PMON printf source */
830 signed_word
*ap
= &A1
; /* 1st argument */
831 /* This isn't the quickest way, since we call the host print
832 routine for every character almost. But it does avoid
833 having to allocate and manage a temporary string buffer. */
834 /* TODO: Include check that we only use three arguments (A1,
836 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
841 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
842 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
843 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
845 if (strchr ("dobxXulscefg%", s
))
860 else if (c
>= '1' && c
<= '9')
864 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
867 n
= (unsigned int)strtol(tmp
,NULL
,10);
880 sim_io_printf (sd
, "%%");
885 address_word p
= *ap
++;
887 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
888 sim_io_printf(sd
, "%c", ch
);
891 sim_io_printf(sd
,"(null)");
894 sim_io_printf (sd
, "%c", (int)*ap
++);
899 sim_read (sd
, s
++, &c
, 1);
903 sim_read (sd
, s
++, &c
, 1);
906 if (strchr ("dobxXu", c
))
908 word64 lv
= (word64
) *ap
++;
910 sim_io_printf(sd
,"<binary not supported>");
913 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
915 sim_io_printf(sd
, tmp
, lv
);
917 sim_io_printf(sd
, tmp
, (int)lv
);
920 else if (strchr ("eEfgG", c
))
922 double dbl
= *(double*)(ap
++);
923 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
924 sim_io_printf (sd
, tmp
, dbl
);
930 sim_io_printf(sd
, "%c", c
);
936 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
937 reason
, pr_addr(cia
));
943 /* Store a word into memory. */
946 store_word (sd
, cia
, vaddr
, val
)
955 if ((vaddr
& 3) != 0)
956 SignalExceptionAddressStore ();
959 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
962 const uword64 mask
= 7;
966 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
967 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
968 memval
= ((uword64
) val
) << (8 * byte
);
969 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
975 /* Load a word from memory. */
978 load_word (sd
, cia
, vaddr
)
983 if ((vaddr
& 3) != 0)
984 SignalExceptionAddressLoad ();
990 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
993 const uword64 mask
= 0x7;
994 const unsigned int reverse
= ReverseEndian
? 1 : 0;
995 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
999 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1000 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1002 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1003 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1010 /* Simulate the mips16 entry and exit pseudo-instructions. These
1011 would normally be handled by the reserved instruction exception
1012 code, but for ease of simulation we just handle them directly. */
1015 mips16_entry (sd
,insn
)
1019 int aregs
, sregs
, rreg
;
1022 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1025 aregs
= (insn
& 0x700) >> 8;
1026 sregs
= (insn
& 0x0c0) >> 6;
1027 rreg
= (insn
& 0x020) >> 5;
1029 /* This should be checked by the caller. */
1038 /* This is the entry pseudo-instruction. */
1040 for (i
= 0; i
< aregs
; i
++)
1041 store_word ((uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1049 store_word ((uword64
) tsp
, RA
);
1052 for (i
= 0; i
< sregs
; i
++)
1055 store_word ((uword64
) tsp
, GPR
[16 + i
]);
1063 /* This is the exit pseudo-instruction. */
1070 RA
= load_word ((uword64
) tsp
);
1073 for (i
= 0; i
< sregs
; i
++)
1076 GPR
[i
+ 16] = load_word ((uword64
) tsp
);
1084 FGR
[0] = WORD64LO (GPR
[4]);
1085 FPR_STATE
[0] = fmt_uninterpreted
;
1087 else if (aregs
== 6)
1089 FGR
[0] = WORD64LO (GPR
[5]);
1090 FGR
[1] = WORD64LO (GPR
[4]);
1091 FPR_STATE
[0] = fmt_uninterpreted
;
1092 FPR_STATE
[1] = fmt_uninterpreted
;
1094 #endif /* defined(HASFPU) */
1100 /*-- trace support ----------------------------------------------------------*/
1102 /* The TRACE support is provided (if required) in the memory accessing
1103 routines. Since we are also providing the architecture specific
1104 features, the architecture simulation code can also deal with
1105 notifying the TRACE world of cache flushes, etc. Similarly we do
1106 not need to provide profiling support in the simulator engine,
1107 since we can sample in the instruction fetch control loop. By
1108 defining the TRACE manifest, we add tracing as a run-time
1112 /* Tracing by default produces "din" format (as required by
1113 dineroIII). Each line of such a trace file *MUST* have a din label
1114 and address field. The rest of the line is ignored, so comments can
1115 be included if desired. The first field is the label which must be
1116 one of the following values:
1121 3 escape record (treated as unknown access type)
1122 4 escape record (causes cache flush)
1124 The address field is a 32bit (lower-case) hexadecimal address
1125 value. The address should *NOT* be preceded by "0x".
1127 The size of the memory transfer is not important when dealing with
1128 cache lines (as long as no more than a cache line can be
1129 transferred in a single operation :-), however more information
1130 could be given following the dineroIII requirement to allow more
1131 complete memory and cache simulators to provide better
1132 results. i.e. the University of Pisa has a cache simulator that can
1133 also take bus size and speed as (variable) inputs to calculate
1134 complete system performance (a much more useful ability when trying
1135 to construct an end product, rather than a processor). They
1136 currently have an ARM version of their tool called ChARM. */
1140 dotrace (SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...)
1142 if (STATE
& simTRACE
) {
1144 fprintf(tracefh
,"%d %s ; width %d ; ",
1148 va_start(ap
,comment
);
1149 vfprintf(tracefh
,comment
,ap
);
1151 fprintf(tracefh
,"\n");
1153 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1154 we may be generating 64bit ones, we should put the hi-32bits of the
1155 address into the comment field. */
1157 /* TODO: Provide a buffer for the trace lines. We can then avoid
1158 performing writes until the buffer is filled, or the file is
1161 /* NOTE: We could consider adding a comment field to the "din" file
1162 produced using type 3 markers (unknown access). This would then
1163 allow information about the program that the "din" is for, and
1164 the MIPs world that was being simulated, to be placed into the
1171 /*---------------------------------------------------------------------------*/
1172 /*-- simulator engine -------------------------------------------------------*/
1173 /*---------------------------------------------------------------------------*/
1179 /* RESET: Fixed PC address: */
1180 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1181 /* The reset vector address is in the unmapped, uncached memory space. */
1183 SR
&= ~(status_SR
| status_TS
| status_RP
);
1184 SR
|= (status_ERL
| status_BEV
);
1186 /* Cheat and allow access to the complete register set immediately */
1187 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1188 && WITH_TARGET_WORD_BITSIZE
== 64)
1189 SR
|= status_FR
; /* 64bit registers */
1191 /* Ensure that any instructions with pending register updates are
1195 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1196 PENDING_SLOT_REG
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1197 PENDING_IN
= PENDING_OUT
= PENDING_TOTAL
= 0;
1200 /* Initialise the FPU registers to the unknown state */
1201 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1204 for (rn
= 0; (rn
< 32); rn
++)
1205 FPR_STATE
[rn
] = fmt_uninterpreted
;
1211 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1213 /* Translate a virtual address to a physical address and cache
1214 coherence algorithm describing the mechanism used to resolve the
1215 memory reference. Given the virtual address vAddr, and whether the
1216 reference is to Instructions ot Data (IorD), find the corresponding
1217 physical address (pAddr) and the cache coherence algorithm (CCA)
1218 used to resolve the reference. If the virtual address is in one of
1219 the unmapped address spaces the physical address and the CCA are
1220 determined directly by the virtual address. If the virtual address
1221 is in one of the mapped address spaces then the TLB is used to
1222 determine the physical address and access type; if the required
1223 translation is not present in the TLB or the desired access is not
1224 permitted the function fails and an exception is taken.
1226 NOTE: Normally (RAW == 0), when address translation fails, this
1227 function raises an exception and does not return. */
1230 address_translation(sd
,cia
,vAddr
,IorD
,LorS
,pAddr
,CCA
,raw
)
1236 address_word
*pAddr
;
1240 int res
= -1; /* TRUE : Assume good return */
1243 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1246 /* Check that the address is valid for this memory model */
1248 /* For a simple (flat) memory model, we simply pass virtual
1249 addressess through (mostly) unchanged. */
1250 vAddr
&= 0xFFFFFFFF;
1252 *pAddr
= vAddr
; /* default for isTARGET */
1253 *CCA
= Uncached
; /* not used for isHOST */
1258 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1260 /* Prefetch data from memory. Prefetch is an advisory instruction for
1261 which an implementation specific action is taken. The action taken
1262 may increase performance, but must not change the meaning of the
1263 program, or alter architecturally-visible state. */
1266 prefetch(sd
,cia
,CCA
,pAddr
,vAddr
,DATA
,hint
)
1276 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1279 /* For our simple memory model we do nothing */
1283 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1285 /* Load a value from memory. Use the cache and main memory as
1286 specified in the Cache Coherence Algorithm (CCA) and the sort of
1287 access (IorD) to find the contents of AccessLength memory bytes
1288 starting at physical location pAddr. The data is returned in the
1289 fixed width naturally-aligned memory element (MemElem). The
1290 low-order two (or three) bits of the address and the AccessLength
1291 indicate which of the bytes within MemElem needs to be given to the
1292 processor. If the memory access type of the reference is uncached
1293 then only the referenced bytes are read from memory and valid
1294 within the memory element. If the access type is cached, and the
1295 data is not present in cache, an implementation specific size and
1296 alignment block of memory is read and loaded into the cache to
1297 satisfy a load reference. At a minimum, the block is the entire
1300 load_memory(sd
,cia
,memvalp
,memval1p
,CCA
,AccessLength
,pAddr
,vAddr
,IorD
)
1315 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1318 #if defined(WARN_MEM)
1319 if (CCA
!= uncached
)
1320 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1321 #endif /* WARN_MEM */
1323 /* If instruction fetch then we need to check that the two lo-order
1324 bits are zero, otherwise raise a InstructionFetch exception: */
1325 if ((IorD
== isINSTRUCTION
)
1326 && ((pAddr
& 0x3) != 0)
1327 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1328 SignalExceptionInstructionFetch ();
1330 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1332 /* In reality this should be a Bus Error */
1333 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1335 (LOADDRMASK
+ 1) << 2,
1340 dotrace(sd
,tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1343 /* Read the specified number of bytes from memory. Adjust for
1344 host/target byte ordering/ Align the least significant byte
1347 switch (AccessLength
)
1349 case AccessLength_QUADWORD
:
1351 unsigned_16 val
= sim_core_read_aligned_16 (STATE_CPU (sd
, 0), NULL_CIA
,
1352 sim_core_read_map
, pAddr
);
1353 value1
= VH8_16 (val
);
1354 value
= VL8_16 (val
);
1357 case AccessLength_DOUBLEWORD
:
1358 value
= sim_core_read_aligned_8 (STATE_CPU (sd
, 0), NULL_CIA
,
1359 sim_core_read_map
, pAddr
);
1361 case AccessLength_SEPTIBYTE
:
1362 value
= sim_core_read_misaligned_7 (STATE_CPU (sd
, 0), NULL_CIA
,
1363 sim_core_read_map
, pAddr
);
1364 case AccessLength_SEXTIBYTE
:
1365 value
= sim_core_read_misaligned_6 (STATE_CPU (sd
, 0), NULL_CIA
,
1366 sim_core_read_map
, pAddr
);
1367 case AccessLength_QUINTIBYTE
:
1368 value
= sim_core_read_misaligned_5 (STATE_CPU (sd
, 0), NULL_CIA
,
1369 sim_core_read_map
, pAddr
);
1370 case AccessLength_WORD
:
1371 value
= sim_core_read_aligned_4 (STATE_CPU (sd
, 0), NULL_CIA
,
1372 sim_core_read_map
, pAddr
);
1374 case AccessLength_TRIPLEBYTE
:
1375 value
= sim_core_read_misaligned_3 (STATE_CPU (sd
, 0), NULL_CIA
,
1376 sim_core_read_map
, pAddr
);
1377 case AccessLength_HALFWORD
:
1378 value
= sim_core_read_aligned_2 (STATE_CPU (sd
, 0), NULL_CIA
,
1379 sim_core_read_map
, pAddr
);
1381 case AccessLength_BYTE
:
1382 value
= sim_core_read_aligned_1 (STATE_CPU (sd
, 0), NULL_CIA
,
1383 sim_core_read_map
, pAddr
);
1390 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1391 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1394 /* See also store_memory. */
1395 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1398 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1399 shifted to the most significant byte position. */
1400 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1402 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1403 is already in the correct postition. */
1404 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1408 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1409 pr_uword64(value1
),pr_uword64(value
));
1413 if (memval1p
) *memval1p
= value1
;
1417 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1419 /* Store a value to memory. The specified data is stored into the
1420 physical location pAddr using the memory hierarchy (data caches and
1421 main memory) as specified by the Cache Coherence Algorithm
1422 (CCA). The MemElem contains the data for an aligned, fixed-width
1423 memory element (word for 32-bit processors, doubleword for 64-bit
1424 processors), though only the bytes that will actually be stored to
1425 memory need to be valid. The low-order two (or three) bits of pAddr
1426 and the AccessLength field indicates which of the bytes within the
1427 MemElem data should actually be stored; only these bytes in memory
1431 store_memory(sd
,cia
,CCA
,AccessLength
,MemElem
,MemElem1
,pAddr
,vAddr
)
1437 uword64 MemElem1
; /* High order 64 bits */
1442 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1445 #if defined(WARN_MEM)
1446 if (CCA
!= uncached
)
1447 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1448 #endif /* WARN_MEM */
1450 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1451 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1454 dotrace(sd
,tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1458 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1461 /* See also load_memory */
1462 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1465 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1466 shifted to the most significant byte position. */
1467 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1469 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1470 is already in the correct postition. */
1471 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1475 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1478 switch (AccessLength
)
1480 case AccessLength_QUADWORD
:
1482 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1483 sim_core_write_aligned_16 (STATE_CPU (sd
, 0), NULL_CIA
,
1484 sim_core_write_map
, pAddr
, val
);
1487 case AccessLength_DOUBLEWORD
:
1488 sim_core_write_aligned_8 (STATE_CPU (sd
, 0), NULL_CIA
,
1489 sim_core_write_map
, pAddr
, MemElem
);
1491 case AccessLength_SEPTIBYTE
:
1492 sim_core_write_misaligned_7 (STATE_CPU (sd
, 0), NULL_CIA
,
1493 sim_core_write_map
, pAddr
, MemElem
);
1495 case AccessLength_SEXTIBYTE
:
1496 sim_core_write_misaligned_6 (STATE_CPU (sd
, 0), NULL_CIA
,
1497 sim_core_write_map
, pAddr
, MemElem
);
1499 case AccessLength_QUINTIBYTE
:
1500 sim_core_write_misaligned_5 (STATE_CPU (sd
, 0), NULL_CIA
,
1501 sim_core_write_map
, pAddr
, MemElem
);
1503 case AccessLength_WORD
:
1504 sim_core_write_aligned_4 (STATE_CPU (sd
, 0), NULL_CIA
,
1505 sim_core_write_map
, pAddr
, MemElem
);
1507 case AccessLength_TRIPLEBYTE
:
1508 sim_core_write_misaligned_3 (STATE_CPU (sd
, 0), NULL_CIA
,
1509 sim_core_write_map
, pAddr
, MemElem
);
1511 case AccessLength_HALFWORD
:
1512 sim_core_write_aligned_2 (STATE_CPU (sd
, 0), NULL_CIA
,
1513 sim_core_write_map
, pAddr
, MemElem
);
1515 case AccessLength_BYTE
:
1516 sim_core_write_aligned_1 (STATE_CPU (sd
, 0), NULL_CIA
,
1517 sim_core_write_map
, pAddr
, MemElem
);
1528 ifetch32 (SIM_DESC sd
,
1532 /* Copy the action of the LW instruction */
1533 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1534 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1537 unsigned32 instruction
;
1540 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1541 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1542 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1543 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1544 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1549 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1550 /* Order loads and stores to synchronise shared memory. Perform the
1551 action necessary to make the effects of groups of synchronizable
1552 loads and stores indicated by stype occur in the same order for all
1555 sync_operation(sd
,cia
,stype
)
1561 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1566 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1567 /* Signal an exception condition. This will result in an exception
1568 that aborts the instruction. The instruction operation pseudocode
1569 will never see a return from this function call. */
1572 signal_exception (SIM_DESC sd
,
1579 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1582 /* Ensure that any active atomic read/modify/write operation will fail: */
1585 switch (exception
) {
1586 /* TODO: For testing purposes I have been ignoring TRAPs. In
1587 reality we should either simulate them, or allow the user to
1588 ignore them at run-time.
1591 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1597 unsigned int instruction
;
1600 va_start(ap
,exception
);
1601 instruction
= va_arg(ap
,unsigned int);
1604 code
= (instruction
>> 6) & 0xFFFFF;
1606 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1607 code
, pr_addr(cia
));
1611 case DebugBreakPoint
:
1612 if (! (Debug
& Debug_DM
))
1618 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1619 DEPC
= cia
- 4; /* reference the branch instruction */
1623 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1627 Debug
|= Debug_DM
; /* in debugging mode */
1628 Debug
|= Debug_DBp
; /* raising a DBp exception */
1630 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
1634 case ReservedInstruction
:
1637 unsigned int instruction
;
1638 va_start(ap
,exception
);
1639 instruction
= va_arg(ap
,unsigned int);
1641 /* Provide simple monitor support using ReservedInstruction
1642 exceptions. The following code simulates the fixed vector
1643 entry points into the IDT monitor by causing a simulator
1644 trap, performing the monitor operation, and returning to
1645 the address held in the $ra register (standard PCS return
1646 address). This means we only need to pre-load the vector
1647 space with suitable instruction values. For systems were
1648 actual trap instructions are used, we would not need to
1649 perform this magic. */
1650 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1652 sim_monitor(sd
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1653 /* NOTE: This assumes that a branch-and-link style
1654 instruction was used to enter the vector (which is the
1655 case with the current IDT monitor). */
1656 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, RA
);
1658 /* Look for the mips16 entry and exit instructions, and
1659 simulate a handler for them. */
1660 else if ((cia
& 1) != 0
1661 && (instruction
& 0xf81f) == 0xe809
1662 && (instruction
& 0x0c0) != 0x0c0)
1664 mips16_entry (instruction
);
1665 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1667 /* else fall through to normal exception processing */
1668 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1673 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1675 /* Keep a copy of the current A0 in-case this is the program exit
1679 unsigned int instruction
;
1680 va_start(ap
,exception
);
1681 instruction
= va_arg(ap
,unsigned int);
1683 /* Check for our special terminating BREAK: */
1684 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1685 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, cia
,
1686 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1689 if (STATE
& simDELAYSLOT
)
1690 PC
= cia
- 4; /* reference the branch instruction */
1693 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, cia
,
1694 sim_stopped
, SIM_SIGTRAP
);
1697 /* Store exception code into current exception id variable (used
1700 /* TODO: If not simulating exceptions then stop the simulator
1701 execution. At the moment we always stop the simulation. */
1703 /* See figure 5-17 for an outline of the code below */
1704 if (! (SR
& status_EXL
))
1706 CAUSE
= (exception
<< 2);
1707 if (STATE
& simDELAYSLOT
)
1709 STATE
&= ~simDELAYSLOT
;
1711 EPC
= (cia
- 4); /* reference the branch instruction */
1715 /* FIXME: TLB et.al. */
1720 CAUSE
= (exception
<< 2);
1724 /* Store exception code into current exception id variable (used
1726 if (SR
& status_BEV
)
1727 PC
= (signed)0xBFC00200 + 0x180;
1729 PC
= (signed)0x80000000 + 0x180;
1731 switch ((CAUSE
>> 2) & 0x1F)
1734 /* Interrupts arrive during event processing, no need to
1738 case TLBModification
:
1743 case InstructionFetch
:
1745 /* The following is so that the simulator will continue from the
1746 exception address on breakpoint operations. */
1748 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1749 sim_stopped
, SIM_SIGBUS
);
1751 case ReservedInstruction
:
1752 case CoProcessorUnusable
:
1754 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1755 sim_stopped
, SIM_SIGILL
);
1757 case IntegerOverflow
:
1759 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1760 sim_stopped
, SIM_SIGFPE
);
1766 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1767 sim_stopped
, SIM_SIGTRAP
);
1771 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
1772 "FATAL: Should not encounter a breakpoint\n");
1774 default : /* Unknown internal exception */
1776 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1777 sim_stopped
, SIM_SIGABRT
);
1781 case SimulatorFault
:
1785 va_start(ap
,exception
);
1786 msg
= va_arg(ap
,char *);
1788 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
1789 "FATAL: Simulator error \"%s\"\n",msg
);
1796 #if defined(WARN_RESULT)
1797 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1798 /* This function indicates that the result of the operation is
1799 undefined. However, this should not affect the instruction
1800 stream. All that is meant to happen is that the destination
1801 register is set to an undefined result. To keep the simulator
1802 simple, we just don't bother updating the destination register, so
1803 the overall result will be undefined. If desired we can stop the
1804 simulator by raising a pseudo-exception. */
1805 #define UndefinedResult() undefined_result (sd,cia)
1807 undefined_result(sd
,cia
)
1811 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1812 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1817 #endif /* WARN_RESULT */
1820 cache_op(sd
,cia
,op
,pAddr
,vAddr
,instruction
)
1826 unsigned int instruction
;
1828 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1829 static int icache_warning
= 1;
1830 static int dcache_warning
= 1;
1832 static int icache_warning
= 0;
1833 static int dcache_warning
= 0;
1836 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1837 enable bit in the Status Register is clear - a coprocessor
1838 unusable exception is taken. */
1840 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
1844 case 0: /* instruction cache */
1846 case 0: /* Index Invalidate */
1847 case 1: /* Index Load Tag */
1848 case 2: /* Index Store Tag */
1849 case 4: /* Hit Invalidate */
1851 case 6: /* Hit Writeback */
1852 if (!icache_warning
)
1854 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
1860 SignalException(ReservedInstruction
,instruction
);
1865 case 1: /* data cache */
1867 case 0: /* Index Writeback Invalidate */
1868 case 1: /* Index Load Tag */
1869 case 2: /* Index Store Tag */
1870 case 3: /* Create Dirty */
1871 case 4: /* Hit Invalidate */
1872 case 5: /* Hit Writeback Invalidate */
1873 case 6: /* Hit Writeback */
1874 if (!dcache_warning
)
1876 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
1882 SignalException(ReservedInstruction
,instruction
);
1887 default: /* unrecognised cache ID */
1888 SignalException(ReservedInstruction
,instruction
);
1895 /*-- FPU support routines ---------------------------------------------------*/
1897 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
1899 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1900 formats conform to ANSI/IEEE Std 754-1985. */
1901 /* SINGLE precision floating:
1902 * seeeeeeeefffffffffffffffffffffff
1904 * e = 8bits = exponent
1905 * f = 23bits = fraction
1907 /* SINGLE precision fixed:
1908 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1910 * i = 31bits = integer
1912 /* DOUBLE precision floating:
1913 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1915 * e = 11bits = exponent
1916 * f = 52bits = fraction
1918 /* DOUBLE precision fixed:
1919 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1921 * i = 63bits = integer
1924 /* Extract sign-bit: */
1925 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1926 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1927 /* Extract biased exponent: */
1928 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1929 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1930 /* Extract unbiased Exponent: */
1931 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1932 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1933 /* Extract complete fraction field: */
1934 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1935 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1936 /* Extract numbered fraction bit: */
1937 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1938 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1940 /* Explicit QNaN values used when value required: */
1941 #define FPQNaN_SINGLE (0x7FBFFFFF)
1942 #define FPQNaN_WORD (0x7FFFFFFF)
1943 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1944 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1946 /* Explicit Infinity values used when required: */
1947 #define FPINF_SINGLE (0x7F800000)
1948 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1950 #if 1 /* def DEBUG */
1951 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1952 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1956 value_fpr(sd
,cia
,fpr
,fmt
)
1965 /* Treat unused register values, as fixed-point 64bit values: */
1966 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1968 /* If request to read data as "uninterpreted", then use the current
1970 fmt
= FPR_STATE
[fpr
];
1975 /* For values not yet accessed, set to the desired format: */
1976 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1977 FPR_STATE
[fpr
] = fmt
;
1979 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1982 if (fmt
!= FPR_STATE
[fpr
]) {
1983 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1984 FPR_STATE
[fpr
] = fmt_unknown
;
1987 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1988 /* Set QNaN value: */
1991 value
= FPQNaN_SINGLE
;
1995 value
= FPQNaN_DOUBLE
;
1999 value
= FPQNaN_WORD
;
2003 value
= FPQNaN_LONG
;
2010 } else if (SizeFGR() == 64) {
2014 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2017 case fmt_uninterpreted
:
2031 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2034 case fmt_uninterpreted
:
2037 if ((fpr
& 1) == 0) { /* even registers only */
2038 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2040 SignalException(ReservedInstruction
,0);
2051 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2054 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2061 store_fpr(sd
,cia
,fpr
,fmt
,value
)
2071 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2074 if (SizeFGR() == 64) {
2076 case fmt_uninterpreted_32
:
2077 fmt
= fmt_uninterpreted
;
2080 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2081 FPR_STATE
[fpr
] = fmt
;
2084 case fmt_uninterpreted_64
:
2085 fmt
= fmt_uninterpreted
;
2086 case fmt_uninterpreted
:
2090 FPR_STATE
[fpr
] = fmt
;
2094 FPR_STATE
[fpr
] = fmt_unknown
;
2100 case fmt_uninterpreted_32
:
2101 fmt
= fmt_uninterpreted
;
2104 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2105 FPR_STATE
[fpr
] = fmt
;
2108 case fmt_uninterpreted_64
:
2109 fmt
= fmt_uninterpreted
;
2110 case fmt_uninterpreted
:
2113 if ((fpr
& 1) == 0) { /* even register number only */
2114 FGR
[fpr
+1] = (value
>> 32);
2115 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2116 FPR_STATE
[fpr
+ 1] = fmt
;
2117 FPR_STATE
[fpr
] = fmt
;
2119 FPR_STATE
[fpr
] = fmt_unknown
;
2120 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2121 SignalException(ReservedInstruction
,0);
2126 FPR_STATE
[fpr
] = fmt_unknown
;
2131 #if defined(WARN_RESULT)
2134 #endif /* WARN_RESULT */
2137 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2140 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2157 sim_fpu_32to (&wop
, op
);
2158 boolean
= sim_fpu_is_nan (&wop
);
2165 sim_fpu_64to (&wop
, op
);
2166 boolean
= sim_fpu_is_nan (&wop
);
2170 fprintf (stderr
, "Bad switch\n");
2175 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2189 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2196 sim_fpu_32to (&wop
, op
);
2197 boolean
= sim_fpu_is_infinity (&wop
);
2203 sim_fpu_64to (&wop
, op
);
2204 boolean
= sim_fpu_is_infinity (&wop
);
2208 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2213 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2227 /* Argument checking already performed by the FPCOMPARE code */
2230 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2233 /* The format type should already have been checked: */
2239 sim_fpu_32to (&wop1
, op1
);
2240 sim_fpu_32to (&wop2
, op2
);
2241 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2248 sim_fpu_64to (&wop1
, op1
);
2249 sim_fpu_64to (&wop2
, op2
);
2250 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2254 fprintf (stderr
, "Bad switch\n");
2259 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2273 /* Argument checking already performed by the FPCOMPARE code */
2276 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2279 /* The format type should already have been checked: */
2285 sim_fpu_32to (&wop1
, op1
);
2286 sim_fpu_32to (&wop2
, op2
);
2287 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2294 sim_fpu_64to (&wop1
, op1
);
2295 sim_fpu_64to (&wop2
, op2
);
2296 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2300 fprintf (stderr
, "Bad switch\n");
2305 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2312 AbsoluteValue(op
,fmt
)
2319 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2322 /* The format type should already have been checked: */
2328 sim_fpu_32to (&wop
, op
);
2329 sim_fpu_abs (&wop
, &wop
);
2330 sim_fpu_to32 (&ans
, &wop
);
2338 sim_fpu_64to (&wop
, op
);
2339 sim_fpu_abs (&wop
, &wop
);
2340 sim_fpu_to64 (&ans
, &wop
);
2345 fprintf (stderr
, "Bad switch\n");
2360 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2363 /* The format type should already have been checked: */
2369 sim_fpu_32to (&wop
, op
);
2370 sim_fpu_neg (&wop
, &wop
);
2371 sim_fpu_to32 (&ans
, &wop
);
2379 sim_fpu_64to (&wop
, op
);
2380 sim_fpu_neg (&wop
, &wop
);
2381 sim_fpu_to64 (&ans
, &wop
);
2386 fprintf (stderr
, "Bad switch\n");
2402 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2405 /* The registers must specify FPRs valid for operands of type
2406 "fmt". If they are not valid, the result is undefined. */
2408 /* The format type should already have been checked: */
2416 sim_fpu_32to (&wop1
, op1
);
2417 sim_fpu_32to (&wop2
, op2
);
2418 sim_fpu_add (&ans
, &wop1
, &wop2
);
2419 sim_fpu_to32 (&res
, &ans
);
2429 sim_fpu_64to (&wop1
, op1
);
2430 sim_fpu_64to (&wop2
, op2
);
2431 sim_fpu_add (&ans
, &wop1
, &wop2
);
2432 sim_fpu_to64 (&res
, &ans
);
2437 fprintf (stderr
, "Bad switch\n");
2442 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2457 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2460 /* The registers must specify FPRs valid for operands of type
2461 "fmt". If they are not valid, the result is undefined. */
2463 /* The format type should already have been checked: */
2471 sim_fpu_32to (&wop1
, op1
);
2472 sim_fpu_32to (&wop2
, op2
);
2473 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2474 sim_fpu_to32 (&res
, &ans
);
2484 sim_fpu_64to (&wop1
, op1
);
2485 sim_fpu_64to (&wop2
, op2
);
2486 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2487 sim_fpu_to64 (&res
, &ans
);
2492 fprintf (stderr
, "Bad switch\n");
2497 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2504 Multiply(op1
,op2
,fmt
)
2512 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2515 /* The registers must specify FPRs valid for operands of type
2516 "fmt". If they are not valid, the result is undefined. */
2518 /* The format type should already have been checked: */
2526 sim_fpu_32to (&wop1
, op1
);
2527 sim_fpu_32to (&wop2
, op2
);
2528 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2529 sim_fpu_to32 (&res
, &ans
);
2539 sim_fpu_64to (&wop1
, op1
);
2540 sim_fpu_64to (&wop2
, op2
);
2541 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2542 sim_fpu_to64 (&res
, &ans
);
2547 fprintf (stderr
, "Bad switch\n");
2552 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2567 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2570 /* The registers must specify FPRs valid for operands of type
2571 "fmt". If they are not valid, the result is undefined. */
2573 /* The format type should already have been checked: */
2581 sim_fpu_32to (&wop1
, op1
);
2582 sim_fpu_32to (&wop2
, op2
);
2583 sim_fpu_div (&ans
, &wop1
, &wop2
);
2584 sim_fpu_to32 (&res
, &ans
);
2594 sim_fpu_64to (&wop1
, op1
);
2595 sim_fpu_64to (&wop2
, op2
);
2596 sim_fpu_div (&ans
, &wop1
, &wop2
);
2597 sim_fpu_to64 (&res
, &ans
);
2602 fprintf (stderr
, "Bad switch\n");
2607 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2621 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2624 /* The registers must specify FPRs valid for operands of type
2625 "fmt". If they are not valid, the result is undefined. */
2627 /* The format type should already have been checked: */
2634 sim_fpu_32to (&wop
, op
);
2635 sim_fpu_inv (&ans
, &wop
);
2636 sim_fpu_to32 (&res
, &ans
);
2645 sim_fpu_64to (&wop
, op
);
2646 sim_fpu_inv (&ans
, &wop
);
2647 sim_fpu_to64 (&res
, &ans
);
2652 fprintf (stderr
, "Bad switch\n");
2657 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2671 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2674 /* The registers must specify FPRs valid for operands of type
2675 "fmt". If they are not valid, the result is undefined. */
2677 /* The format type should already have been checked: */
2684 sim_fpu_32to (&wop
, op
);
2685 sim_fpu_sqrt (&ans
, &wop
);
2686 sim_fpu_to32 (&res
, &ans
);
2695 sim_fpu_64to (&wop
, op
);
2696 sim_fpu_sqrt (&ans
, &wop
);
2697 sim_fpu_to64 (&res
, &ans
);
2702 fprintf (stderr
, "Bad switch\n");
2707 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2714 convert(sd
,cia
,rm
,op
,from
,to
)
2723 sim_fpu_round round
;
2724 unsigned32 result32
;
2725 unsigned64 result64
;
2728 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2734 /* Round result to nearest representable value. When two
2735 representable values are equally near, round to the value
2736 that has a least significant bit of zero (i.e. is even). */
2737 round
= sim_fpu_round_near
;
2740 /* Round result to the value closest to, and not greater in
2741 magnitude than, the result. */
2742 round
= sim_fpu_round_zero
;
2745 /* Round result to the value closest to, and not less than,
2747 round
= sim_fpu_round_up
;
2751 /* Round result to the value closest to, and not greater than,
2753 round
= sim_fpu_round_down
;
2757 fprintf (stderr
, "Bad switch\n");
2761 /* Convert the input to sim_fpu internal format */
2765 sim_fpu_64to (&wop
, op
);
2768 sim_fpu_32to (&wop
, op
);
2771 sim_fpu_i32to (&wop
, op
, round
);
2774 sim_fpu_i64to (&wop
, op
, round
);
2777 fprintf (stderr
, "Bad switch\n");
2781 /* Convert sim_fpu format into the output */
2782 /* The value WOP is converted to the destination format, rounding
2783 using mode RM. When the destination is a fixed-point format, then
2784 a source value of Infinity, NaN or one which would round to an
2785 integer outside the fixed point range then an IEEE Invalid
2786 Operation condition is raised. */
2790 sim_fpu_round_32 (&wop
, round
, 0);
2791 sim_fpu_to32 (&result32
, &wop
);
2792 result64
= result32
;
2795 sim_fpu_round_64 (&wop
, round
, 0);
2796 sim_fpu_to64 (&result64
, &wop
);
2799 sim_fpu_to32i (&result32
, &wop
, round
);
2800 result64
= result32
;
2803 sim_fpu_to64i (&result64
, &wop
, round
);
2807 fprintf (stderr
, "Bad switch\n");
2812 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2820 /*-- co-processor support routines ------------------------------------------*/
2823 CoProcPresent(coproc_number
)
2824 unsigned int coproc_number
;
2826 /* Return TRUE if simulator provides a model for the given co-processor number */
2831 cop_lw(sd
,cia
,coproc_num
,coproc_reg
,memword
)
2834 int coproc_num
, coproc_reg
;
2835 unsigned int memword
;
2837 switch (coproc_num
) {
2841 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2843 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2844 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2849 #if 0 /* this should be controlled by a configuration option */
2850 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2859 cop_ld(sd
,cia
,coproc_num
,coproc_reg
,memword
)
2862 int coproc_num
, coproc_reg
;
2865 switch (coproc_num
) {
2868 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2873 #if 0 /* this message should be controlled by a configuration option */
2874 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2883 cop_sw(sd
,cia
,coproc_num
,coproc_reg
)
2886 int coproc_num
, coproc_reg
;
2888 unsigned int value
= 0;
2890 switch (coproc_num
) {
2896 hold
= FPR_STATE
[coproc_reg
];
2897 FPR_STATE
[coproc_reg
] = fmt_word
;
2898 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
2899 FPR_STATE
[coproc_reg
] = hold
;
2903 value
= (unsigned int)ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
2906 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE
[coproc_reg
]));
2908 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
2915 #if 0 /* should be controlled by configuration option */
2916 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2925 cop_sd(sd
,cia
,coproc_num
,coproc_reg
)
2928 int coproc_num
, coproc_reg
;
2931 switch (coproc_num
) {
2935 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
2938 value
= ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
2941 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE
[coproc_reg
]));
2943 value
= ValueFPR(coproc_reg
,fmt_double
);
2950 #if 0 /* should be controlled by configuration option */
2951 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2960 decode_coproc(sd
,cia
,instruction
)
2963 unsigned int instruction
;
2965 int coprocnum
= ((instruction
>> 26) & 3);
2969 case 0: /* standard CPU control and cache registers */
2971 int code
= ((instruction
>> 21) & 0x1F);
2972 /* R4000 Users Manual (second edition) lists the following CP0
2974 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2975 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2976 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2977 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2978 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2979 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2980 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2981 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2982 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2983 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2985 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
2987 int rt
= ((instruction
>> 16) & 0x1F);
2988 int rd
= ((instruction
>> 11) & 0x1F);
2990 switch (rd
) /* NOTEs: Standard CP0 registers */
2992 /* 0 = Index R4000 VR4100 VR4300 */
2993 /* 1 = Random R4000 VR4100 VR4300 */
2994 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2995 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2996 /* 4 = Context R4000 VR4100 VR4300 */
2997 /* 5 = PageMask R4000 VR4100 VR4300 */
2998 /* 6 = Wired R4000 VR4100 VR4300 */
2999 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3000 /* 9 = Count R4000 VR4100 VR4300 */
3001 /* 10 = EntryHi R4000 VR4100 VR4300 */
3002 /* 11 = Compare R4000 VR4100 VR4300 */
3003 /* 12 = SR R4000 VR4100 VR4300 */
3010 /* 13 = Cause R4000 VR4100 VR4300 */
3017 /* 14 = EPC R4000 VR4100 VR4300 */
3018 /* 15 = PRId R4000 VR4100 VR4300 */
3019 #ifdef SUBTARGET_R3900
3028 /* 16 = Config R4000 VR4100 VR4300 */
3031 GPR
[rt
] = C0_CONFIG
;
3033 C0_CONFIG
= GPR
[rt
];
3036 #ifdef SUBTARGET_R3900
3045 /* 17 = LLAddr R4000 VR4100 VR4300 */
3047 /* 18 = WatchLo R4000 VR4100 VR4300 */
3048 /* 19 = WatchHi R4000 VR4100 VR4300 */
3049 /* 20 = XContext R4000 VR4100 VR4300 */
3050 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3051 /* 27 = CacheErr R4000 VR4100 */
3052 /* 28 = TagLo R4000 VR4100 VR4300 */
3053 /* 29 = TagHi R4000 VR4100 VR4300 */
3054 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3055 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3056 /* CPR[0,rd] = GPR[rt]; */
3059 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3061 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3064 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3067 if (SR
& status_ERL
)
3069 /* Oops, not yet available */
3070 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3080 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3084 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3092 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3093 /* TODO: When executing an ERET or RFE instruction we should
3094 clear LLBIT, to ensure that any out-standing atomic
3095 read/modify/write sequence fails. */
3099 case 2: /* undefined co-processor */
3100 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3103 case 1: /* should not occur (FPU co-processor) */
3104 case 3: /* should not occur (FPU co-processor) */
3105 SignalException(ReservedInstruction
,instruction
);
3112 /*-- instruction simulation -------------------------------------------------*/
3114 /* When the IGEN simulator is being built, the function below is be
3115 replaced by a generated version. However, WITH_IGEN == 2 indicates
3116 that the fubction below should be compiled but under a different
3117 name (to allow backward compatibility) */
3119 #if (WITH_IGEN != 1)
3121 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3123 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3126 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3129 int next_cpu_nr
; /* ignore */
3130 int nr_cpus
; /* ignore */
3131 int siggnal
; /* ignore */
3133 #if !defined(FASTSIM)
3134 unsigned int pipeline_count
= 1;
3138 if (STATE_MEMORY (sd
) == NULL
) {
3139 printf("DBG: simulate() entered with no memory\n");
3144 #if 0 /* Disabled to check that everything works OK */
3145 /* The VR4300 seems to sign-extend the PC on its first
3146 access. However, this may just be because it is currently
3147 configured in 32bit mode. However... */
3148 PC
= SIGNEXTEND(PC
,32);
3151 /* main controlling loop */
3153 /* vaddr is slowly being replaced with cia - current instruction
3155 address_word cia
= (uword64
)PC
;
3156 address_word vaddr
= cia
;
3159 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3163 printf("DBG: state = 0x%08X :",state
);
3164 if (state
& simHALTEX
) printf(" simHALTEX");
3165 if (state
& simHALTIN
) printf(" simHALTIN");
3170 DSSTATE
= (STATE
& simDELAYSLOT
);
3173 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3176 /* Fetch the next instruction from the simulator memory: */
3177 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3178 if ((vaddr
& 1) == 0) {
3179 /* Copy the action of the LW instruction */
3180 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3181 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3184 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3185 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3186 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3187 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3189 /* Copy the action of the LH instruction */
3190 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3191 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3194 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3195 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3196 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3197 paddr
& ~ (uword64
) 1,
3198 vaddr
, isINSTRUCTION
, isREAL
);
3199 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3200 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3203 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3208 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3211 /* This is required by exception processing, to ensure that we can
3212 cope with exceptions in the delay slots of branches that may
3213 already have changed the PC. */
3214 if ((vaddr
& 1) == 0)
3215 PC
+= 4; /* increment ready for the next fetch */
3218 /* NOTE: If we perform a delay slot change to the PC, this
3219 increment is not requuired. However, it would make the
3220 simulator more complicated to try and avoid this small hit. */
3222 /* Currently this code provides a simple model. For more
3223 complicated models we could perform exception status checks at
3224 this point, and set the simSTOP state as required. This could
3225 also include processing any hardware interrupts raised by any
3226 I/O model attached to the simulator context.
3228 Support for "asynchronous" I/O events within the simulated world
3229 could be providing by managing a counter, and calling a I/O
3230 specific handler when a particular threshold is reached. On most
3231 architectures a decrement and check for zero operation is
3232 usually quicker than an increment and compare. However, the
3233 process of managing a known value decrement to zero, is higher
3234 than the cost of using an explicit value UINT_MAX into the
3235 future. Which system is used will depend on how complicated the
3236 I/O model is, and how much it is likely to affect the simulator
3239 If events need to be scheduled further in the future than
3240 UINT_MAX event ticks, then the I/O model should just provide its
3241 own counter, triggered from the event system. */
3243 /* MIPS pipeline ticks. To allow for future support where the
3244 pipeline hit of individual instructions is known, this control
3245 loop manages a "pipeline_count" variable. It is initialised to
3246 1 (one), and will only be changed by the simulator engine when
3247 executing an instruction. If the engine does not have access to
3248 pipeline cycle count information then all instructions will be
3249 treated as using a single cycle. NOTE: A standard system is not
3250 provided by the default simulator because different MIPS
3251 architectures have different cycle counts for the same
3254 [NOTE: pipeline_count has been replaced the event queue] */
3256 /* shuffle the floating point status pipeline state */
3257 ENGINE_ISSUE_PREFIX_HOOK();
3259 /* NOTE: For multi-context simulation environments the "instruction"
3260 variable should be local to this routine. */
3262 /* Shorthand accesses for engine. Note: If we wanted to use global
3263 variables (and a single-threaded simulator engine), then we can
3264 create the actual variables with these names. */
3266 if (!(STATE
& simSKIPNEXT
)) {
3267 /* Include the simulator engine */
3268 #include "oengine.c"
3269 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3270 #error "Mismatch between run-time simulator code and simulation engine"
3272 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3273 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3275 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3276 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3279 #if defined(WARN_LOHI)
3280 /* Decrement the HI/LO validity ticks */
3285 /* start-sanitize-r5900 */
3290 /* end-sanitize-r5900 */
3291 #endif /* WARN_LOHI */
3293 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3294 should check for it being changed. It is better doing it here,
3295 than within the simulator, since it will help keep the simulator
3298 #if defined(WARN_ZERO)
3299 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3300 #endif /* WARN_ZERO */
3301 ZERO
= 0; /* reset back to zero before next instruction */
3303 } else /* simSKIPNEXT check */
3304 STATE
&= ~simSKIPNEXT
;
3306 /* If the delay slot was active before the instruction is
3307 executed, then update the PC to its new value: */
3310 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3316 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3317 /* Deal with pending register updates: */
3319 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3321 if (PENDING_OUT
!= PENDING_IN
) {
3323 int index
= PENDING_OUT
;
3324 int total
= PENDING_TOTAL
;
3325 if (PENDING_TOTAL
== 0) {
3326 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3329 for (loop
= 0; (loop
< total
); loop
++) {
3331 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3333 if (PENDING_SLOT_REG
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3335 printf("pending_slot_count[%d] = %d\n",index
,PENDING_SLOT_COUNT
[index
]);
3337 if (--(PENDING_SLOT_COUNT
[index
]) == 0) {
3339 printf("pending_slot_reg[%d] = %d\n",index
,PENDING_SLOT_REG
[index
]);
3340 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(PENDING_SLOT_VALUE
[index
]));
3342 if (PENDING_SLOT_REG
[index
] == COCIDX
) {
3344 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3349 REGISTERS
[PENDING_SLOT_REG
[index
]] = PENDING_SLOT_VALUE
[index
];
3351 /* The only time we have PENDING updates to FPU
3352 registers, is when performing binary transfers. This
3353 means we should update the register type field. */
3354 if ((PENDING_SLOT_REG
[index
] >= FGRIDX
) && (PENDING_SLOT_REG
[index
] < (FGRIDX
+ 32)))
3355 FPR_STATE
[PENDING_SLOT_REG
[index
] - FGRIDX
] = fmt_uninterpreted
;
3359 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG
[index
],pr_addr(REGISTERS
[PENDING_SLOT_REG
[index
]]));
3361 PENDING_SLOT_REG
[index
] = (LAST_EMBED_REGNUM
+ 1);
3363 if (PENDING_OUT
== PSLOTS
)
3369 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3372 if (index
== PSLOTS
)
3377 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN
,PENDING_OUT
,PENDING_TOTAL
);
3381 #if !defined(FASTSIM)
3382 if (sim_events_tickn (sd
, pipeline_count
))
3384 /* cpu->cia = cia; */
3385 sim_events_process (sd
);
3388 if (sim_events_tick (sd
))
3390 /* cpu->cia = cia; */
3391 sim_events_process (sd
);
3393 #endif /* FASTSIM */
3399 /* This code copied from gdb's utils.c. Would like to share this code,
3400 but don't know of a common place where both could get to it. */
3402 /* Temporary storage using circular buffer */
3408 static char buf
[NUMCELLS
][CELLSIZE
];
3410 if (++cell
>=NUMCELLS
) cell
=0;
3414 /* Print routines to handle variable size regs, etc */
3416 /* Eliminate warning from compiler on 32-bit systems */
3417 static int thirty_two
= 32;
3423 char *paddr_str
=get_cell();
3424 switch (sizeof(addr
))
3427 sprintf(paddr_str
,"%08lx%08lx",
3428 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3431 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3434 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3437 sprintf(paddr_str
,"%x",addr
);
3446 char *paddr_str
=get_cell();
3447 sprintf(paddr_str
,"%08lx%08lx",
3448 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3453 /*---------------------------------------------------------------------------*/
3454 /*> EOF interp.c <*/