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Add support for Thumb target.
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
18 $Date$
19
20 NOTEs:
21
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 code on the hardware.
26
27 */
28
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
33 #define TRACE (1)
34 #endif
35
36 #include "bfd.h"
37 #include "sim-main.h"
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
41
42 #include "config.h"
43
44 #include <stdio.h>
45 #include <stdarg.h>
46 #include <ansidecl.h>
47 #include <ctype.h>
48 #include <limits.h>
49 #include <math.h>
50 #ifdef HAVE_STDLIB_H
51 #include <stdlib.h>
52 #endif
53 #ifdef HAVE_STRING_H
54 #include <string.h>
55 #else
56 #ifdef HAVE_STRINGS_H
57 #include <strings.h>
58 #endif
59 #endif
60
61 #include "getopt.h"
62 #include "libiberty.h"
63 #include "bfd.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
66
67 #include "sysdep.h"
68
69 #ifndef PARAMS
70 #define PARAMS(x)
71 #endif
72
73 char* pr_addr PARAMS ((SIM_ADDR addr));
74 char* pr_uword64 PARAMS ((uword64 addr));
75
76
77 /* Get the simulator engine description, without including the code: */
78 #define SIM_MANIFESTS
79 #include "oengine.c"
80 #undef SIM_MANIFESTS
81
82
83 /* The following reserved instruction value is used when a simulator
84 trap is required. NOTE: Care must be taken, since this value may be
85 used in later revisions of the MIPS ISA. */
86 #define RSVD_INSTRUCTION (0x00000005)
87 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
88
89 #define RSVD_INSTRUCTION_ARG_SHIFT 6
90 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
91
92
93 /* Bits in the Debug register */
94 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
95 #define Debug_DM 0x40000000 /* Debug Mode */
96 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
97
98
99
100
101
102 /*---------------------------------------------------------------------------*/
103 /*-- GDB simulator interface ------------------------------------------------*/
104 /*---------------------------------------------------------------------------*/
105
106 static void ColdReset PARAMS((SIM_DESC sd));
107
108 /*---------------------------------------------------------------------------*/
109
110
111
112 #define DELAYSLOT() {\
113 if (STATE & simDELAYSLOT)\
114 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
115 STATE |= simDELAYSLOT;\
116 }
117
118 #define JALDELAYSLOT() {\
119 DELAYSLOT ();\
120 STATE |= simJALDELAYSLOT;\
121 }
122
123 #define NULLIFY() {\
124 STATE &= ~simDELAYSLOT;\
125 STATE |= simSKIPNEXT;\
126 }
127
128 #define CANCELDELAYSLOT() {\
129 DSSTATE = 0;\
130 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
131 }
132
133 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
134 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
135
136 #define K0BASE (0x80000000)
137 #define K0SIZE (0x20000000)
138 #define K1BASE (0xA0000000)
139 #define K1SIZE (0x20000000)
140 #define MONITOR_BASE (0xBFC00000)
141 #define MONITOR_SIZE (1 << 11)
142 #define MEM_SIZE (2 << 20)
143
144 #if defined(TRACE)
145 static char *tracefile = "trace.din"; /* default filename for trace log */
146 FILE *tracefh = NULL;
147 static void open_trace PARAMS((SIM_DESC sd));
148 #endif /* TRACE */
149
150 #define OPTION_DINERO_TRACE 200
151 #define OPTION_DINERO_FILE 201
152
153 static SIM_RC
154 mips_option_handler (sd, opt, arg)
155 SIM_DESC sd;
156 int opt;
157 char *arg;
158 {
159 switch (opt)
160 {
161 case OPTION_DINERO_TRACE: /* ??? */
162 #if defined(TRACE)
163 /* Eventually the simTRACE flag could be treated as a toggle, to
164 allow external control of the program points being traced
165 (i.e. only from main onwards, excluding the run-time setup,
166 etc.). */
167 if (arg == NULL)
168 STATE |= simTRACE;
169 else if (strcmp (arg, "yes") == 0)
170 STATE |= simTRACE;
171 else if (strcmp (arg, "no") == 0)
172 STATE &= ~simTRACE;
173 else if (strcmp (arg, "on") == 0)
174 STATE |= simTRACE;
175 else if (strcmp (arg, "off") == 0)
176 STATE &= ~simTRACE;
177 else
178 {
179 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
180 return SIM_RC_FAIL;
181 }
182 return SIM_RC_OK;
183 #else /* !TRACE */
184 fprintf(stderr,"\
185 Simulator constructed without dinero tracing support (for performance).\n\
186 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
187 return SIM_RC_FAIL;
188 #endif /* !TRACE */
189
190 case OPTION_DINERO_FILE:
191 #if defined(TRACE)
192 if (optarg != NULL) {
193 char *tmp;
194 tmp = (char *)malloc(strlen(optarg) + 1);
195 if (tmp == NULL)
196 {
197 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
198 return SIM_RC_FAIL;
199 }
200 else {
201 strcpy(tmp,optarg);
202 tracefile = tmp;
203 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
204 }
205 }
206 #endif /* TRACE */
207 return SIM_RC_OK;
208
209 }
210
211 return SIM_RC_OK;
212 }
213
214 static const OPTION mips_options[] =
215 {
216 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
217 '\0', "on|off", "Enable dinero tracing",
218 mips_option_handler },
219 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
220 '\0', "FILE", "Write dinero trace to FILE",
221 mips_option_handler },
222 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
223 };
224
225
226 int interrupt_pending;
227
228 static void
229 interrupt_event (SIM_DESC sd, void *data)
230 {
231 if (SR & status_IE)
232 {
233 interrupt_pending = 0;
234 SignalExceptionInterrupt ();
235 }
236 else if (!interrupt_pending)
237 sim_events_schedule (sd, 1, interrupt_event, data);
238 }
239
240
241
242 /*---------------------------------------------------------------------------*/
243 /*-- GDB simulator interface ------------------------------------------------*/
244 /*---------------------------------------------------------------------------*/
245
246 SIM_DESC
247 sim_open (kind, cb, abfd, argv)
248 SIM_OPEN_KIND kind;
249 host_callback *cb;
250 struct _bfd *abfd;
251 char **argv;
252 {
253 SIM_DESC sd = sim_state_alloc (kind, cb);
254 sim_cpu *cpu = STATE_CPU (sd, 0);
255
256 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
257
258 /* FIXME: watchpoints code shouldn't need this */
259 STATE_WATCHPOINTS (sd)->pc = &(PC);
260 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
261 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
262
263 STATE = 0;
264
265 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
266 return 0;
267 sim_add_option_table (sd, mips_options);
268
269 /* Allocate core managed memory */
270
271 /* the monitor */
272 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
273 /* For compatibility with the old code - under this (at level one)
274 are the kernel spaces K0 & K1. Both of these map to a single
275 smaller sub region */
276 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
277 K1BASE, K0SIZE,
278 MEM_SIZE, /* actual size */
279 K0BASE);
280
281 /* getopt will print the error message so we just have to exit if this fails.
282 FIXME: Hmmm... in the case of gdb we need getopt to call
283 print_filtered. */
284 if (sim_parse_args (sd, argv) != SIM_RC_OK)
285 {
286 /* Uninstall the modules to avoid memory leaks,
287 file descriptor leaks, etc. */
288 sim_module_uninstall (sd);
289 return 0;
290 }
291
292 /* check for/establish the a reference program image */
293 if (sim_analyze_program (sd,
294 (STATE_PROG_ARGV (sd) != NULL
295 ? *STATE_PROG_ARGV (sd)
296 : NULL),
297 abfd) != SIM_RC_OK)
298 {
299 sim_module_uninstall (sd);
300 return 0;
301 }
302
303 /* Configure/verify the target byte order and other runtime
304 configuration options */
305 if (sim_config (sd) != SIM_RC_OK)
306 {
307 sim_module_uninstall (sd);
308 return 0;
309 }
310
311 if (sim_post_argv_init (sd) != SIM_RC_OK)
312 {
313 /* Uninstall the modules to avoid memory leaks,
314 file descriptor leaks, etc. */
315 sim_module_uninstall (sd);
316 return 0;
317 }
318
319 /* verify assumptions the simulator made about the host type system.
320 This macro does not return if there is a problem */
321 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
322 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
323
324 #if defined(HASFPU)
325 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
326 and DOUBLE binary formats. This is a bit nasty, requiring that we
327 trust the explicit manifests held in the source: */
328 /* TODO: We need to cope with the simulated target and the host not
329 having the same endianness. This will require the high and low
330 words of a (double) to be swapped when converting between the
331 host and the simulated target. */
332 {
333 union {
334 unsigned int i[2];
335 double d;
336 float f[2];
337 } s;
338
339 s.d = (double)523.2939453125;
340
341 if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
342 || s.i[1] != 0x40805A5A))
343 || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
344 || s.i[0] != 0x40805A5A)))
345 {
346 fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
347 return 0;
348 }
349 }
350 #endif /* HASFPU */
351
352 /* This is NASTY, in that we are assuming the size of specific
353 registers: */
354 {
355 int rn;
356 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
357 if (rn < 32)
358 cpu->register_widths[rn] = GPRLEN;
359 else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
360 cpu->register_widths[rn] = GPRLEN;
361 else if ((rn >= 33) && (rn <= 37))
362 cpu->register_widths[rn] = GPRLEN;
363 else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
364 cpu->register_widths[rn] = 32;
365 else
366 cpu->register_widths[rn] = 0;
367 }
368 /* start-sanitize-r5900 */
369
370 /* set the 5900 "upper" registers to 64 bits */
371 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
372 cpu->register_widths[rn] = 64;
373 /* end-sanitize-r5900 */
374 }
375
376 #if defined(TRACE)
377 if (STATE & simTRACE)
378 open_trace(sd);
379 #endif /* TRACE */
380
381 /* Write the monitor trap address handlers into the monitor (eeprom)
382 address space. This can only be done once the target endianness
383 has been determined. */
384 {
385 unsigned loop;
386 /* Entry into the IDT monitor is via fixed address vectors, and
387 not using machine instructions. To avoid clashing with use of
388 the MIPS TRAP system, we place our own (simulator specific)
389 "undefined" instructions into the relevant vector slots. */
390 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
391 {
392 address_word vaddr = (MONITOR_BASE + loop);
393 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
394 H2T (insn);
395 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
396 }
397 /* The PMON monitor uses the same address space, but rather than
398 branching into it the address of a routine is loaded. We can
399 cheat for the moment, and direct the PMON routine to IDT style
400 instructions within the monitor space. This relies on the IDT
401 monitor not using the locations from 0xBFC00500 onwards as its
402 entry points.*/
403 for (loop = 0; (loop < 24); loop++)
404 {
405 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
406 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
407 switch (loop)
408 {
409 case 0: /* read */
410 value = 7;
411 break;
412 case 1: /* write */
413 value = 8;
414 break;
415 case 2: /* open */
416 value = 6;
417 break;
418 case 3: /* close */
419 value = 10;
420 break;
421 case 5: /* printf */
422 value = ((0x500 - 16) / 8); /* not an IDT reason code */
423 break;
424 case 8: /* cliexit */
425 value = 17;
426 break;
427 case 11: /* flush_cache */
428 value = 28;
429 break;
430 }
431 /* FIXME - should monitor_base be SIM_ADDR?? */
432 value = ((unsigned int)MONITOR_BASE + (value * 8));
433 H2T (value);
434 sim_write (sd, vaddr, (char *)&value, sizeof (value));
435
436 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
437 vaddr -= 0x300;
438 sim_write (sd, vaddr, (char *)&value, sizeof (value));
439 }
440 }
441
442 return sd;
443 }
444
445 #if defined(TRACE)
446 static void
447 open_trace(sd)
448 SIM_DESC sd;
449 {
450 tracefh = fopen(tracefile,"wb+");
451 if (tracefh == NULL)
452 {
453 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
454 tracefh = stderr;
455 }
456 }
457 #endif /* TRACE */
458
459 void
460 sim_close (sd, quitting)
461 SIM_DESC sd;
462 int quitting;
463 {
464 #ifdef DEBUG
465 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
466 #endif
467
468 /* "quitting" is non-zero if we cannot hang on errors */
469
470 /* Ensure that any resources allocated through the callback
471 mechanism are released: */
472 sim_io_shutdown (sd);
473
474 #if defined(TRACE)
475 if (tracefh != NULL && tracefh != stderr)
476 fclose(tracefh);
477 tracefh = NULL;
478 STATE &= ~simTRACE;
479 #endif /* TRACE */
480
481 return;
482 }
483
484
485 int
486 sim_write (sd,addr,buffer,size)
487 SIM_DESC sd;
488 SIM_ADDR addr;
489 unsigned char *buffer;
490 int size;
491 {
492 int index;
493
494 /* Return the number of bytes written, or zero if error. */
495 #ifdef DEBUG
496 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
497 #endif
498
499 /* We use raw read and write routines, since we do not want to count
500 the GDB memory accesses in our statistics gathering. */
501
502 for (index = 0; index < size; index++)
503 {
504 address_word vaddr = (address_word)addr + index;
505 address_word paddr;
506 int cca;
507 if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
508 break;
509 if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
510 break;
511 }
512
513 return(index);
514 }
515
516 int
517 sim_read (sd,addr,buffer,size)
518 SIM_DESC sd;
519 SIM_ADDR addr;
520 unsigned char *buffer;
521 int size;
522 {
523 int index;
524
525 /* Return the number of bytes read, or zero if error. */
526 #ifdef DEBUG
527 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
528 #endif /* DEBUG */
529
530 for (index = 0; (index < size); index++)
531 {
532 address_word vaddr = (address_word)addr + index;
533 address_word paddr;
534 int cca;
535 if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
536 break;
537 if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
538 break;
539 }
540
541 return(index);
542 }
543
544 void
545 sim_store_register (sd,rn,memory)
546 SIM_DESC sd;
547 int rn;
548 unsigned char *memory;
549 {
550 sim_cpu *cpu = STATE_CPU (sd, 0);
551 /* NOTE: gdb (the client) stores registers in target byte order
552 while the simulator uses host byte order */
553 #ifdef DEBUG
554 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
555 #endif /* DEBUG */
556
557 /* Unfortunately this suffers from the same problem as the register
558 numbering one. We need to know what the width of each logical
559 register number is for the architecture being simulated. */
560
561 if (cpu->register_widths[rn] == 0)
562 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
563 /* start-sanitize-r5900 */
564 else if (rn == REGISTER_SA)
565 SA = T2H_8(*(uword64*)memory);
566 else if (rn > LAST_EMBED_REGNUM)
567 cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
568 /* end-sanitize-r5900 */
569 else if (cpu->register_widths[rn] == 32)
570 cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
571 else
572 cpu->registers[rn] = T2H_8 (*(uword64*)memory);
573
574 return;
575 }
576
577 void
578 sim_fetch_register (sd,rn,memory)
579 SIM_DESC sd;
580 int rn;
581 unsigned char *memory;
582 {
583 sim_cpu *cpu = STATE_CPU (sd, 0);
584 /* NOTE: gdb (the client) stores registers in target byte order
585 while the simulator uses host byte order */
586 #ifdef DEBUG
587 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
588 #endif /* DEBUG */
589
590 if (cpu->register_widths[rn] == 0)
591 sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
592 /* start-sanitize-r5900 */
593 else if (rn == REGISTER_SA)
594 *((uword64 *)memory) = H2T_8(SA);
595 else if (rn > LAST_EMBED_REGNUM)
596 *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
597 /* end-sanitize-r5900 */
598 else if (cpu->register_widths[rn] == 32)
599 *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
600 else /* 64bit register */
601 *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
602
603 return;
604 }
605
606
607 void
608 sim_info (sd,verbose)
609 SIM_DESC sd;
610 int verbose;
611 {
612 /* Accessed from the GDB "info files" command: */
613 if (STATE_VERBOSE_P (sd) || verbose)
614 {
615
616 sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
617 (PROCESSOR_64BIT ? 64 : 32),
618 (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
619
620 #if !defined(FASTSIM)
621 /* It would be a useful feature, if when performing multi-cycle
622 simulations (rather than single-stepping) we keep the start and
623 end times of the execution, so that we can give a performance
624 figure for the simulator. */
625 #endif /* !FASTSIM */
626 sim_io_printf (sd, "Number of execution cycles = %ld\n",
627 (long) sim_events_time (sd));
628
629 /* print information pertaining to MIPS ISA and architecture being simulated */
630 /* things that may be interesting */
631 /* instructions executed - if available */
632 /* cycles executed - if available */
633 /* pipeline stalls - if available */
634 /* virtual time taken */
635 /* profiling size */
636 /* profiling frequency */
637 /* profile minpc */
638 /* profile maxpc */
639 }
640 profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL);
641 }
642
643
644 SIM_RC
645 sim_create_inferior (sd, abfd, argv,env)
646 SIM_DESC sd;
647 struct _bfd *abfd;
648 char **argv;
649 char **env;
650 {
651
652 #ifdef DEBUG
653 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
654 pr_addr(PC));
655 #endif /* DEBUG */
656
657 ColdReset(sd);
658
659 if (abfd != NULL)
660 /* override PC value set by ColdReset () */
661 PC = (unsigned64) bfd_get_start_address (abfd);
662
663 #if 0 /* def DEBUG */
664 if (argv || env)
665 {
666 /* We should really place the argv slot values into the argument
667 registers, and onto the stack as required. However, this
668 assumes that we have a stack defined, which is not
669 necessarily true at the moment. */
670 char **cptr;
671 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
672 for (cptr = argv; (cptr && *cptr); cptr++)
673 printf("DBG: arg \"%s\"\n",*cptr);
674 }
675 #endif /* DEBUG */
676
677 return SIM_RC_OK;
678 }
679
680 void
681 sim_do_command (sd,cmd)
682 SIM_DESC sd;
683 char *cmd;
684 {
685 if (sim_args_command (sd, cmd) != SIM_RC_OK)
686 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
687 cmd);
688 }
689
690 /*---------------------------------------------------------------------------*/
691 /*-- Private simulator support interface ------------------------------------*/
692 /*---------------------------------------------------------------------------*/
693
694 /* Read a null terminated string from memory, return in a buffer */
695 static char *
696 fetch_str (sd, addr)
697 SIM_DESC sd;
698 address_word addr;
699 {
700 char *buf;
701 int nr = 0;
702 char null;
703 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
704 nr++;
705 buf = NZALLOC (char, nr + 1);
706 sim_read (sd, addr, buf, nr);
707 return buf;
708 }
709
710 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
711 static void
712 sim_monitor(sd,cia,reason)
713 SIM_DESC sd;
714 address_word cia;
715 unsigned int reason;
716 {
717 #ifdef DEBUG
718 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
719 #endif /* DEBUG */
720
721 /* The IDT monitor actually allows two instructions per vector
722 slot. However, the simulator currently causes a trap on each
723 individual instruction. We cheat, and lose the bottom bit. */
724 reason >>= 1;
725
726 /* The following callback functions are available, however the
727 monitor we are simulating does not make use of them: get_errno,
728 isatty, lseek, rename, system, time and unlink */
729 switch (reason)
730 {
731
732 case 6: /* int open(char *path,int flags) */
733 {
734 char *path = fetch_str (sd, A0);
735 V0 = sim_io_open (sd, path, (int)A1);
736 zfree (path);
737 break;
738 }
739
740 case 7: /* int read(int file,char *ptr,int len) */
741 {
742 int fd = A0;
743 int nr = A2;
744 char *buf = zalloc (nr);
745 V0 = sim_io_read (sd, fd, buf, nr);
746 sim_write (sd, A1, buf, nr);
747 zfree (buf);
748 }
749 break;
750
751 case 8: /* int write(int file,char *ptr,int len) */
752 {
753 int fd = A0;
754 int nr = A2;
755 char *buf = zalloc (nr);
756 sim_read (sd, A1, buf, nr);
757 V0 = sim_io_write (sd, fd, buf, nr);
758 zfree (buf);
759 break;
760 }
761
762 case 10: /* int close(int file) */
763 {
764 V0 = sim_io_close (sd, (int)A0);
765 break;
766 }
767
768 case 11: /* char inbyte(void) */
769 {
770 char tmp;
771 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
772 {
773 sim_io_error(sd,"Invalid return from character read");
774 V0 = (ut_reg)-1;
775 }
776 else
777 V0 = (ut_reg)tmp;
778 break;
779 }
780
781 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
782 {
783 char tmp = (char)(A0 & 0xFF);
784 sim_io_write_stdout (sd, &tmp, sizeof(char));
785 break;
786 }
787
788 case 17: /* void _exit() */
789 {
790 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
791 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited,
792 (unsigned int)(A0 & 0xFFFFFFFF));
793 break;
794 }
795
796 case 28 : /* PMON flush_cache */
797 break;
798
799 case 55: /* void get_mem_info(unsigned int *ptr) */
800 /* in: A0 = pointer to three word memory location */
801 /* out: [A0 + 0] = size */
802 /* [A0 + 4] = instruction cache size */
803 /* [A0 + 8] = data cache size */
804 {
805 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
806 H2T (value);
807 sim_write (sd, A0, (char *)&value, sizeof (value));
808 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
809 break;
810 }
811
812 case 158 : /* PMON printf */
813 /* in: A0 = pointer to format string */
814 /* A1 = optional argument 1 */
815 /* A2 = optional argument 2 */
816 /* A3 = optional argument 3 */
817 /* out: void */
818 /* The following is based on the PMON printf source */
819 {
820 address_word s = A0;
821 char c;
822 signed_word *ap = &A1; /* 1st argument */
823 /* This isn't the quickest way, since we call the host print
824 routine for every character almost. But it does avoid
825 having to allocate and manage a temporary string buffer. */
826 /* TODO: Include check that we only use three arguments (A1,
827 A2 and A3) */
828 while (sim_read (sd, s++, &c, 1) && c != '\0')
829 {
830 if (c == '%')
831 {
832 char tmp[40];
833 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
834 int width = 0, trunc = 0, haddot = 0, longlong = 0;
835 while (sim_read (sd, s++, &c, 1) && c != '\0')
836 {
837 if (strchr ("dobxXulscefg%", s))
838 break;
839 else if (c == '-')
840 fmt = FMT_LJUST;
841 else if (c == '0')
842 fmt = FMT_RJUST0;
843 else if (c == '~')
844 fmt = FMT_CENTER;
845 else if (c == '*')
846 {
847 if (haddot)
848 trunc = (int)*ap++;
849 else
850 width = (int)*ap++;
851 }
852 else if (c >= '1' && c <= '9')
853 {
854 address_word t = s;
855 unsigned int n;
856 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
857 tmp[s - t] = c;
858 tmp[s - t] = '\0';
859 n = (unsigned int)strtol(tmp,NULL,10);
860 if (haddot)
861 trunc = n;
862 else
863 width = n;
864 s--;
865 }
866 else if (c == '.')
867 haddot = 1;
868 }
869 switch (c)
870 {
871 case '%':
872 sim_io_printf (sd, "%%");
873 break;
874 case 's':
875 if ((int)*ap != 0)
876 {
877 address_word p = *ap++;
878 char ch;
879 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
880 sim_io_printf(sd, "%c", ch);
881 }
882 else
883 sim_io_printf(sd,"(null)");
884 break;
885 case 'c':
886 sim_io_printf (sd, "%c", (int)*ap++);
887 break;
888 default:
889 if (c == 'l')
890 {
891 sim_read (sd, s++, &c, 1);
892 if (c == 'l')
893 {
894 longlong = 1;
895 sim_read (sd, s++, &c, 1);
896 }
897 }
898 if (strchr ("dobxXu", c))
899 {
900 word64 lv = (word64) *ap++;
901 if (c == 'b')
902 sim_io_printf(sd,"<binary not supported>");
903 else
904 {
905 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
906 if (longlong)
907 sim_io_printf(sd, tmp, lv);
908 else
909 sim_io_printf(sd, tmp, (int)lv);
910 }
911 }
912 else if (strchr ("eEfgG", c))
913 {
914 double dbl = *(double*)(ap++);
915 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
916 sim_io_printf (sd, tmp, dbl);
917 trunc = 0;
918 }
919 }
920 }
921 else
922 sim_io_printf(sd, "%c", c);
923 }
924 break;
925 }
926
927 default:
928 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
929 reason, pr_addr(cia));
930 break;
931 }
932 return;
933 }
934
935 /* Store a word into memory. */
936
937 static void
938 store_word (sd, cia, vaddr, val)
939 SIM_DESC sd;
940 address_word cia;
941 uword64 vaddr;
942 t_reg val;
943 {
944 address_word paddr;
945 int uncached;
946
947 if ((vaddr & 3) != 0)
948 SignalExceptionAddressStore ();
949 else
950 {
951 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
952 isTARGET, isREAL))
953 {
954 const uword64 mask = 7;
955 uword64 memval;
956 unsigned int byte;
957
958 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
959 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
960 memval = ((uword64) val) << (8 * byte);
961 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
962 isREAL);
963 }
964 }
965 }
966
967 /* Load a word from memory. */
968
969 static t_reg
970 load_word (sd, cia, vaddr)
971 SIM_DESC sd;
972 address_word cia;
973 uword64 vaddr;
974 {
975 if ((vaddr & 3) != 0)
976 SignalExceptionAddressLoad ();
977 else
978 {
979 address_word paddr;
980 int uncached;
981
982 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
983 isTARGET, isREAL))
984 {
985 const uword64 mask = 0x7;
986 const unsigned int reverse = ReverseEndian ? 1 : 0;
987 const unsigned int bigend = BigEndianCPU ? 1 : 0;
988 uword64 memval;
989 unsigned int byte;
990
991 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
992 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
993 isDATA, isREAL);
994 byte = (vaddr & mask) ^ (bigend << 2);
995 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
996 }
997 }
998
999 return 0;
1000 }
1001
1002 /* Simulate the mips16 entry and exit pseudo-instructions. These
1003 would normally be handled by the reserved instruction exception
1004 code, but for ease of simulation we just handle them directly. */
1005
1006 static void
1007 mips16_entry (sd,insn)
1008 SIM_DESC sd;
1009 unsigned int insn;
1010 {
1011 int aregs, sregs, rreg;
1012
1013 #ifdef DEBUG
1014 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1015 #endif /* DEBUG */
1016
1017 aregs = (insn & 0x700) >> 8;
1018 sregs = (insn & 0x0c0) >> 6;
1019 rreg = (insn & 0x020) >> 5;
1020
1021 /* This should be checked by the caller. */
1022 if (sregs == 3)
1023 abort ();
1024
1025 if (aregs < 5)
1026 {
1027 int i;
1028 t_reg tsp;
1029
1030 /* This is the entry pseudo-instruction. */
1031
1032 for (i = 0; i < aregs; i++)
1033 store_word ((uword64) (SP + 4 * i), GPR[i + 4]);
1034
1035 tsp = SP;
1036 SP -= 32;
1037
1038 if (rreg)
1039 {
1040 tsp -= 4;
1041 store_word ((uword64) tsp, RA);
1042 }
1043
1044 for (i = 0; i < sregs; i++)
1045 {
1046 tsp -= 4;
1047 store_word ((uword64) tsp, GPR[16 + i]);
1048 }
1049 }
1050 else
1051 {
1052 int i;
1053 t_reg tsp;
1054
1055 /* This is the exit pseudo-instruction. */
1056
1057 tsp = SP + 32;
1058
1059 if (rreg)
1060 {
1061 tsp -= 4;
1062 RA = load_word ((uword64) tsp);
1063 }
1064
1065 for (i = 0; i < sregs; i++)
1066 {
1067 tsp -= 4;
1068 GPR[i + 16] = load_word ((uword64) tsp);
1069 }
1070
1071 SP += 32;
1072
1073 #if defined(HASFPU)
1074 if (aregs == 5)
1075 {
1076 FGR[0] = WORD64LO (GPR[4]);
1077 FPR_STATE[0] = fmt_uninterpreted;
1078 }
1079 else if (aregs == 6)
1080 {
1081 FGR[0] = WORD64LO (GPR[5]);
1082 FGR[1] = WORD64LO (GPR[4]);
1083 FPR_STATE[0] = fmt_uninterpreted;
1084 FPR_STATE[1] = fmt_uninterpreted;
1085 }
1086 #endif /* defined(HASFPU) */
1087
1088 PC = RA;
1089 }
1090 }
1091
1092 /*-- trace support ----------------------------------------------------------*/
1093
1094 /* The TRACE support is provided (if required) in the memory accessing
1095 routines. Since we are also providing the architecture specific
1096 features, the architecture simulation code can also deal with
1097 notifying the TRACE world of cache flushes, etc. Similarly we do
1098 not need to provide profiling support in the simulator engine,
1099 since we can sample in the instruction fetch control loop. By
1100 defining the TRACE manifest, we add tracing as a run-time
1101 option. */
1102
1103 #if defined(TRACE)
1104 /* Tracing by default produces "din" format (as required by
1105 dineroIII). Each line of such a trace file *MUST* have a din label
1106 and address field. The rest of the line is ignored, so comments can
1107 be included if desired. The first field is the label which must be
1108 one of the following values:
1109
1110 0 read data
1111 1 write data
1112 2 instruction fetch
1113 3 escape record (treated as unknown access type)
1114 4 escape record (causes cache flush)
1115
1116 The address field is a 32bit (lower-case) hexadecimal address
1117 value. The address should *NOT* be preceded by "0x".
1118
1119 The size of the memory transfer is not important when dealing with
1120 cache lines (as long as no more than a cache line can be
1121 transferred in a single operation :-), however more information
1122 could be given following the dineroIII requirement to allow more
1123 complete memory and cache simulators to provide better
1124 results. i.e. the University of Pisa has a cache simulator that can
1125 also take bus size and speed as (variable) inputs to calculate
1126 complete system performance (a much more useful ability when trying
1127 to construct an end product, rather than a processor). They
1128 currently have an ARM version of their tool called ChARM. */
1129
1130
1131 void
1132 dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
1133 {
1134 if (STATE & simTRACE) {
1135 va_list ap;
1136 fprintf(tracefh,"%d %s ; width %d ; ",
1137 type,
1138 pr_addr(address),
1139 width);
1140 va_start(ap,comment);
1141 vfprintf(tracefh,comment,ap);
1142 va_end(ap);
1143 fprintf(tracefh,"\n");
1144 }
1145 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1146 we may be generating 64bit ones, we should put the hi-32bits of the
1147 address into the comment field. */
1148
1149 /* TODO: Provide a buffer for the trace lines. We can then avoid
1150 performing writes until the buffer is filled, or the file is
1151 being closed. */
1152
1153 /* NOTE: We could consider adding a comment field to the "din" file
1154 produced using type 3 markers (unknown access). This would then
1155 allow information about the program that the "din" is for, and
1156 the MIPs world that was being simulated, to be placed into the
1157 trace file. */
1158
1159 return;
1160 }
1161 #endif /* TRACE */
1162
1163 /*---------------------------------------------------------------------------*/
1164 /*-- simulator engine -------------------------------------------------------*/
1165 /*---------------------------------------------------------------------------*/
1166
1167 static void
1168 ColdReset (sd)
1169 SIM_DESC sd;
1170 {
1171 /* RESET: Fixed PC address: */
1172 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
1173 /* The reset vector address is in the unmapped, uncached memory space. */
1174
1175 SR &= ~(status_SR | status_TS | status_RP);
1176 SR |= (status_ERL | status_BEV);
1177
1178 /* Cheat and allow access to the complete register set immediately */
1179 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1180 && WITH_TARGET_WORD_BITSIZE == 64)
1181 SR |= status_FR; /* 64bit registers */
1182
1183 /* Ensure that any instructions with pending register updates are
1184 cleared: */
1185 {
1186 int loop;
1187 for (loop = 0; (loop < PSLOTS); loop++)
1188 PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
1189 PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
1190 }
1191
1192 /* Initialise the FPU registers to the unknown state */
1193 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1194 {
1195 int rn;
1196 for (rn = 0; (rn < 32); rn++)
1197 FPR_STATE[rn] = fmt_uninterpreted;
1198 }
1199
1200 return;
1201 }
1202
1203 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1204 (revision 3.1) */
1205 /* Translate a virtual address to a physical address and cache
1206 coherence algorithm describing the mechanism used to resolve the
1207 memory reference. Given the virtual address vAddr, and whether the
1208 reference is to Instructions ot Data (IorD), find the corresponding
1209 physical address (pAddr) and the cache coherence algorithm (CCA)
1210 used to resolve the reference. If the virtual address is in one of
1211 the unmapped address spaces the physical address and the CCA are
1212 determined directly by the virtual address. If the virtual address
1213 is in one of the mapped address spaces then the TLB is used to
1214 determine the physical address and access type; if the required
1215 translation is not present in the TLB or the desired access is not
1216 permitted the function fails and an exception is taken.
1217
1218 NOTE: Normally (RAW == 0), when address translation fails, this
1219 function raises an exception and does not return. */
1220
1221 int
1222 address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
1223 SIM_DESC sd;
1224 address_word cia;
1225 address_word vAddr;
1226 int IorD;
1227 int LorS;
1228 address_word *pAddr;
1229 int *CCA;
1230 int raw;
1231 {
1232 int res = -1; /* TRUE : Assume good return */
1233
1234 #ifdef DEBUG
1235 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
1236 #endif
1237
1238 /* Check that the address is valid for this memory model */
1239
1240 /* For a simple (flat) memory model, we simply pass virtual
1241 addressess through (mostly) unchanged. */
1242 vAddr &= 0xFFFFFFFF;
1243
1244 *pAddr = vAddr; /* default for isTARGET */
1245 *CCA = Uncached; /* not used for isHOST */
1246
1247 return(res);
1248 }
1249
1250 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1251 (revision 3.1) */
1252 /* Prefetch data from memory. Prefetch is an advisory instruction for
1253 which an implementation specific action is taken. The action taken
1254 may increase performance, but must not change the meaning of the
1255 program, or alter architecturally-visible state. */
1256
1257 void
1258 prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
1259 SIM_DESC sd;
1260 address_word cia;
1261 int CCA;
1262 address_word pAddr;
1263 address_word vAddr;
1264 int DATA;
1265 int hint;
1266 {
1267 #ifdef DEBUG
1268 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
1269 #endif /* DEBUG */
1270
1271 /* For our simple memory model we do nothing */
1272 return;
1273 }
1274
1275 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1276 (revision 3.1) */
1277 /* Load a value from memory. Use the cache and main memory as
1278 specified in the Cache Coherence Algorithm (CCA) and the sort of
1279 access (IorD) to find the contents of AccessLength memory bytes
1280 starting at physical location pAddr. The data is returned in the
1281 fixed width naturally-aligned memory element (MemElem). The
1282 low-order two (or three) bits of the address and the AccessLength
1283 indicate which of the bytes within MemElem needs to be given to the
1284 processor. If the memory access type of the reference is uncached
1285 then only the referenced bytes are read from memory and valid
1286 within the memory element. If the access type is cached, and the
1287 data is not present in cache, an implementation specific size and
1288 alignment block of memory is read and loaded into the cache to
1289 satisfy a load reference. At a minimum, the block is the entire
1290 memory element. */
1291 void
1292 load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
1293 SIM_DESC sd;
1294 address_word cia;
1295 uword64* memvalp;
1296 uword64* memval1p;
1297 int CCA;
1298 int AccessLength;
1299 address_word pAddr;
1300 address_word vAddr;
1301 int IorD;
1302 {
1303 uword64 value = 0;
1304 uword64 value1 = 0;
1305
1306 #ifdef DEBUG
1307 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
1308 #endif /* DEBUG */
1309
1310 #if defined(WARN_MEM)
1311 if (CCA != uncached)
1312 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1313 #endif /* WARN_MEM */
1314
1315 /* If instruction fetch then we need to check that the two lo-order
1316 bits are zero, otherwise raise a InstructionFetch exception: */
1317 if ((IorD == isINSTRUCTION)
1318 && ((pAddr & 0x3) != 0)
1319 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
1320 SignalExceptionInstructionFetch ();
1321
1322 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1323 {
1324 /* In reality this should be a Bus Error */
1325 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1326 AccessLength,
1327 (LOADDRMASK + 1) << 2,
1328 pr_addr (pAddr));
1329 }
1330
1331 #if defined(TRACE)
1332 dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
1333 #endif /* TRACE */
1334
1335 /* Read the specified number of bytes from memory. Adjust for
1336 host/target byte ordering/ Align the least significant byte
1337 read. */
1338
1339 switch (AccessLength)
1340 {
1341 case AccessLength_QUADWORD :
1342 {
1343 unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
1344 sim_core_read_map, pAddr);
1345 value1 = VH8_16 (val);
1346 value = VL8_16 (val);
1347 break;
1348 }
1349 case AccessLength_DOUBLEWORD :
1350 value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
1351 sim_core_read_map, pAddr);
1352 break;
1353 case AccessLength_SEPTIBYTE :
1354 value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
1355 sim_core_read_map, pAddr);
1356 case AccessLength_SEXTIBYTE :
1357 value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
1358 sim_core_read_map, pAddr);
1359 case AccessLength_QUINTIBYTE :
1360 value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
1361 sim_core_read_map, pAddr);
1362 case AccessLength_WORD :
1363 value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
1364 sim_core_read_map, pAddr);
1365 break;
1366 case AccessLength_TRIPLEBYTE :
1367 value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
1368 sim_core_read_map, pAddr);
1369 case AccessLength_HALFWORD :
1370 value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
1371 sim_core_read_map, pAddr);
1372 break;
1373 case AccessLength_BYTE :
1374 value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
1375 sim_core_read_map, pAddr);
1376 break;
1377 default:
1378 abort ();
1379 }
1380
1381 #ifdef DEBUG
1382 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1383 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
1384 #endif /* DEBUG */
1385
1386 /* See also store_memory. */
1387 if (AccessLength <= AccessLength_DOUBLEWORD)
1388 {
1389 if (BigEndianMem)
1390 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1391 shifted to the most significant byte position. */
1392 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1393 else
1394 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1395 is already in the correct postition. */
1396 value <<= ((pAddr & LOADDRMASK) * 8);
1397 }
1398
1399 #ifdef DEBUG
1400 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1401 pr_uword64(value1),pr_uword64(value));
1402 #endif /* DEBUG */
1403
1404 *memvalp = value;
1405 if (memval1p) *memval1p = value1;
1406 }
1407
1408
1409 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1410 (revision 3.1) */
1411 /* Store a value to memory. The specified data is stored into the
1412 physical location pAddr using the memory hierarchy (data caches and
1413 main memory) as specified by the Cache Coherence Algorithm
1414 (CCA). The MemElem contains the data for an aligned, fixed-width
1415 memory element (word for 32-bit processors, doubleword for 64-bit
1416 processors), though only the bytes that will actually be stored to
1417 memory need to be valid. The low-order two (or three) bits of pAddr
1418 and the AccessLength field indicates which of the bytes within the
1419 MemElem data should actually be stored; only these bytes in memory
1420 will be changed. */
1421
1422 void
1423 store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
1424 SIM_DESC sd;
1425 address_word cia;
1426 int CCA;
1427 int AccessLength;
1428 uword64 MemElem;
1429 uword64 MemElem1; /* High order 64 bits */
1430 address_word pAddr;
1431 address_word vAddr;
1432 {
1433 #ifdef DEBUG
1434 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
1435 #endif /* DEBUG */
1436
1437 #if defined(WARN_MEM)
1438 if (CCA != uncached)
1439 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1440 #endif /* WARN_MEM */
1441
1442 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1443 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1444
1445 #if defined(TRACE)
1446 dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
1447 #endif /* TRACE */
1448
1449 #ifdef DEBUG
1450 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
1451 #endif /* DEBUG */
1452
1453 /* See also load_memory */
1454 if (AccessLength <= AccessLength_DOUBLEWORD)
1455 {
1456 if (BigEndianMem)
1457 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1458 shifted to the most significant byte position. */
1459 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1460 else
1461 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1462 is already in the correct postition. */
1463 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1464 }
1465
1466 #ifdef DEBUG
1467 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
1468 #endif /* DEBUG */
1469
1470 switch (AccessLength)
1471 {
1472 case AccessLength_QUADWORD :
1473 {
1474 unsigned_16 val = U16_8 (MemElem1, MemElem);
1475 sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
1476 sim_core_write_map, pAddr, val);
1477 break;
1478 }
1479 case AccessLength_DOUBLEWORD :
1480 sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
1481 sim_core_write_map, pAddr, MemElem);
1482 break;
1483 case AccessLength_SEPTIBYTE :
1484 sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
1485 sim_core_write_map, pAddr, MemElem);
1486 break;
1487 case AccessLength_SEXTIBYTE :
1488 sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
1489 sim_core_write_map, pAddr, MemElem);
1490 break;
1491 case AccessLength_QUINTIBYTE :
1492 sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
1493 sim_core_write_map, pAddr, MemElem);
1494 break;
1495 case AccessLength_WORD :
1496 sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
1497 sim_core_write_map, pAddr, MemElem);
1498 break;
1499 case AccessLength_TRIPLEBYTE :
1500 sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
1501 sim_core_write_map, pAddr, MemElem);
1502 break;
1503 case AccessLength_HALFWORD :
1504 sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
1505 sim_core_write_map, pAddr, MemElem);
1506 break;
1507 case AccessLength_BYTE :
1508 sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
1509 sim_core_write_map, pAddr, MemElem);
1510 break;
1511 default:
1512 abort ();
1513 }
1514
1515 return;
1516 }
1517
1518
1519 unsigned32
1520 ifetch32 (SIM_DESC sd,
1521 address_word cia,
1522 address_word vaddr)
1523 {
1524 /* Copy the action of the LW instruction */
1525 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1526 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1527 unsigned64 value;
1528 address_word paddr;
1529 unsigned32 instruction;
1530 unsigned byte;
1531 int cca;
1532 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1533 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1534 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1535 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1536 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1537 return instruction;
1538 }
1539
1540
1541 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1542 /* Order loads and stores to synchronise shared memory. Perform the
1543 action necessary to make the effects of groups of synchronizable
1544 loads and stores indicated by stype occur in the same order for all
1545 processors. */
1546 void
1547 sync_operation(sd,cia,stype)
1548 SIM_DESC sd;
1549 address_word cia;
1550 int stype;
1551 {
1552 #ifdef DEBUG
1553 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
1554 #endif /* DEBUG */
1555 return;
1556 }
1557
1558 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1559 /* Signal an exception condition. This will result in an exception
1560 that aborts the instruction. The instruction operation pseudocode
1561 will never see a return from this function call. */
1562
1563 void
1564 signal_exception (SIM_DESC sd,
1565 address_word cia,
1566 int exception,...)
1567 {
1568 int vector;
1569
1570 #ifdef DEBUG
1571 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1572 #endif /* DEBUG */
1573
1574 /* Ensure that any active atomic read/modify/write operation will fail: */
1575 LLBIT = 0;
1576
1577 switch (exception) {
1578 /* TODO: For testing purposes I have been ignoring TRAPs. In
1579 reality we should either simulate them, or allow the user to
1580 ignore them at run-time.
1581 Same for SYSCALL */
1582 case Trap :
1583 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
1584 break;
1585
1586 case SystemCall :
1587 {
1588 va_list ap;
1589 unsigned int instruction;
1590 unsigned int code;
1591
1592 va_start(ap,exception);
1593 instruction = va_arg(ap,unsigned int);
1594 va_end(ap);
1595
1596 code = (instruction >> 6) & 0xFFFFF;
1597
1598 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1599 code, pr_addr(cia));
1600 }
1601 break;
1602
1603 case DebugBreakPoint :
1604 if (! (Debug & Debug_DM))
1605 {
1606 if (INDELAYSLOT())
1607 {
1608 CANCELDELAYSLOT();
1609
1610 Debug |= Debug_DBD; /* signaled from within in delay slot */
1611 DEPC = cia - 4; /* reference the branch instruction */
1612 }
1613 else
1614 {
1615 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1616 DEPC = cia;
1617 }
1618
1619 Debug |= Debug_DM; /* in debugging mode */
1620 Debug |= Debug_DBp; /* raising a DBp exception */
1621 PC = 0xBFC00200;
1622 sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
1623 }
1624 break;
1625
1626 case ReservedInstruction :
1627 {
1628 va_list ap;
1629 unsigned int instruction;
1630 va_start(ap,exception);
1631 instruction = va_arg(ap,unsigned int);
1632 va_end(ap);
1633 /* Provide simple monitor support using ReservedInstruction
1634 exceptions. The following code simulates the fixed vector
1635 entry points into the IDT monitor by causing a simulator
1636 trap, performing the monitor operation, and returning to
1637 the address held in the $ra register (standard PCS return
1638 address). This means we only need to pre-load the vector
1639 space with suitable instruction values. For systems were
1640 actual trap instructions are used, we would not need to
1641 perform this magic. */
1642 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1643 {
1644 sim_monitor(sd, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1645 /* NOTE: This assumes that a branch-and-link style
1646 instruction was used to enter the vector (which is the
1647 case with the current IDT monitor). */
1648 sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA);
1649 }
1650 /* Look for the mips16 entry and exit instructions, and
1651 simulate a handler for them. */
1652 else if ((cia & 1) != 0
1653 && (instruction & 0xf81f) == 0xe809
1654 && (instruction & 0x0c0) != 0x0c0)
1655 {
1656 mips16_entry (instruction);
1657 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1658 }
1659 /* else fall through to normal exception processing */
1660 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
1661 }
1662
1663 case BreakPoint:
1664 #ifdef DEBUG
1665 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1666 #endif /* DEBUG */
1667 /* Keep a copy of the current A0 in-case this is the program exit
1668 breakpoint: */
1669 {
1670 va_list ap;
1671 unsigned int instruction;
1672 va_start(ap,exception);
1673 instruction = va_arg(ap,unsigned int);
1674 va_end(ap);
1675 /* Check for our special terminating BREAK: */
1676 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
1677 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
1678 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1679 }
1680 }
1681 if (STATE & simDELAYSLOT)
1682 PC = cia - 4; /* reference the branch instruction */
1683 else
1684 PC = cia;
1685 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
1686 sim_stopped, SIM_SIGTRAP);
1687
1688 default:
1689 /* Store exception code into current exception id variable (used
1690 by exit code): */
1691
1692 /* TODO: If not simulating exceptions then stop the simulator
1693 execution. At the moment we always stop the simulation. */
1694
1695 /* See figure 5-17 for an outline of the code below */
1696 if (! (SR & status_EXL))
1697 {
1698 CAUSE = (exception << 2);
1699 if (STATE & simDELAYSLOT)
1700 {
1701 STATE &= ~simDELAYSLOT;
1702 CAUSE |= cause_BD;
1703 EPC = (cia - 4); /* reference the branch instruction */
1704 }
1705 else
1706 EPC = cia;
1707 /* FIXME: TLB et.al. */
1708 vector = 0x180;
1709 }
1710 else
1711 {
1712 CAUSE = (exception << 2);
1713 vector = 0x180;
1714 }
1715 SR |= status_EXL;
1716 /* Store exception code into current exception id variable (used
1717 by exit code): */
1718 if (SR & status_BEV)
1719 PC = (signed)0xBFC00200 + 0x180;
1720 else
1721 PC = (signed)0x80000000 + 0x180;
1722
1723 switch ((CAUSE >> 2) & 0x1F)
1724 {
1725 case Interrupt:
1726 /* Interrupts arrive during event processing, no need to
1727 restart */
1728 return;
1729
1730 case TLBModification:
1731 case TLBLoad:
1732 case TLBStore:
1733 case AddressLoad:
1734 case AddressStore:
1735 case InstructionFetch:
1736 case DataReference:
1737 /* The following is so that the simulator will continue from the
1738 exception address on breakpoint operations. */
1739 PC = EPC;
1740 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1741 sim_stopped, SIM_SIGBUS);
1742
1743 case ReservedInstruction:
1744 case CoProcessorUnusable:
1745 PC = EPC;
1746 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1747 sim_stopped, SIM_SIGILL);
1748
1749 case IntegerOverflow:
1750 case FPE:
1751 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1752 sim_stopped, SIM_SIGFPE);
1753
1754 case Trap:
1755 case Watch:
1756 case SystemCall:
1757 PC = EPC;
1758 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1759 sim_stopped, SIM_SIGTRAP);
1760
1761 case BreakPoint:
1762 PC = EPC;
1763 sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
1764 "FATAL: Should not encounter a breakpoint\n");
1765
1766 default : /* Unknown internal exception */
1767 PC = EPC;
1768 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1769 sim_stopped, SIM_SIGABRT);
1770
1771 }
1772
1773 case SimulatorFault:
1774 {
1775 va_list ap;
1776 char *msg;
1777 va_start(ap,exception);
1778 msg = va_arg(ap,char *);
1779 va_end(ap);
1780 sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
1781 "FATAL: Simulator error \"%s\"\n",msg);
1782 }
1783 }
1784
1785 return;
1786 }
1787
1788 #if defined(WARN_RESULT)
1789 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1790 /* This function indicates that the result of the operation is
1791 undefined. However, this should not affect the instruction
1792 stream. All that is meant to happen is that the destination
1793 register is set to an undefined result. To keep the simulator
1794 simple, we just don't bother updating the destination register, so
1795 the overall result will be undefined. If desired we can stop the
1796 simulator by raising a pseudo-exception. */
1797 #define UndefinedResult() undefined_result (sd,cia)
1798 static void
1799 undefined_result(sd,cia)
1800 SIM_DESC sd;
1801 address_word cia;
1802 {
1803 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
1804 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1805 state |= simSTOP;
1806 #endif
1807 return;
1808 }
1809 #endif /* WARN_RESULT */
1810
1811 void
1812 cache_op(sd,cia,op,pAddr,vAddr,instruction)
1813 SIM_DESC sd;
1814 address_word cia;
1815 int op;
1816 address_word pAddr;
1817 address_word vAddr;
1818 unsigned int instruction;
1819 {
1820 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1821 static int icache_warning = 1;
1822 static int dcache_warning = 1;
1823 #else
1824 static int icache_warning = 0;
1825 static int dcache_warning = 0;
1826 #endif
1827
1828 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1829 enable bit in the Status Register is clear - a coprocessor
1830 unusable exception is taken. */
1831 #if 0
1832 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
1833 #endif
1834
1835 switch (op & 0x3) {
1836 case 0: /* instruction cache */
1837 switch (op >> 2) {
1838 case 0: /* Index Invalidate */
1839 case 1: /* Index Load Tag */
1840 case 2: /* Index Store Tag */
1841 case 4: /* Hit Invalidate */
1842 case 5: /* Fill */
1843 case 6: /* Hit Writeback */
1844 if (!icache_warning)
1845 {
1846 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
1847 icache_warning = 1;
1848 }
1849 break;
1850
1851 default:
1852 SignalException(ReservedInstruction,instruction);
1853 break;
1854 }
1855 break;
1856
1857 case 1: /* data cache */
1858 switch (op >> 2) {
1859 case 0: /* Index Writeback Invalidate */
1860 case 1: /* Index Load Tag */
1861 case 2: /* Index Store Tag */
1862 case 3: /* Create Dirty */
1863 case 4: /* Hit Invalidate */
1864 case 5: /* Hit Writeback Invalidate */
1865 case 6: /* Hit Writeback */
1866 if (!dcache_warning)
1867 {
1868 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
1869 dcache_warning = 1;
1870 }
1871 break;
1872
1873 default:
1874 SignalException(ReservedInstruction,instruction);
1875 break;
1876 }
1877 break;
1878
1879 default: /* unrecognised cache ID */
1880 SignalException(ReservedInstruction,instruction);
1881 break;
1882 }
1883
1884 return;
1885 }
1886
1887 /*-- FPU support routines ---------------------------------------------------*/
1888
1889 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
1890
1891 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1892 formats conform to ANSI/IEEE Std 754-1985. */
1893 /* SINGLE precision floating:
1894 * seeeeeeeefffffffffffffffffffffff
1895 * s = 1bit = sign
1896 * e = 8bits = exponent
1897 * f = 23bits = fraction
1898 */
1899 /* SINGLE precision fixed:
1900 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1901 * s = 1bit = sign
1902 * i = 31bits = integer
1903 */
1904 /* DOUBLE precision floating:
1905 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1906 * s = 1bit = sign
1907 * e = 11bits = exponent
1908 * f = 52bits = fraction
1909 */
1910 /* DOUBLE precision fixed:
1911 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1912 * s = 1bit = sign
1913 * i = 63bits = integer
1914 */
1915
1916 /* Extract sign-bit: */
1917 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1918 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1919 /* Extract biased exponent: */
1920 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1921 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1922 /* Extract unbiased Exponent: */
1923 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1924 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1925 /* Extract complete fraction field: */
1926 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1927 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1928 /* Extract numbered fraction bit: */
1929 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1930 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1931
1932 /* Explicit QNaN values used when value required: */
1933 #define FPQNaN_SINGLE (0x7FBFFFFF)
1934 #define FPQNaN_WORD (0x7FFFFFFF)
1935 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1936 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1937
1938 /* Explicit Infinity values used when required: */
1939 #define FPINF_SINGLE (0x7F800000)
1940 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1941
1942 #if 1 /* def DEBUG */
1943 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1944 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1945 #endif /* DEBUG */
1946
1947 uword64
1948 value_fpr(sd,cia,fpr,fmt)
1949 SIM_DESC sd;
1950 address_word cia;
1951 int fpr;
1952 FP_formats fmt;
1953 {
1954 uword64 value = 0;
1955 int err = 0;
1956
1957 /* Treat unused register values, as fixed-point 64bit values: */
1958 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
1959 #if 1
1960 /* If request to read data as "uninterpreted", then use the current
1961 encoding: */
1962 fmt = FPR_STATE[fpr];
1963 #else
1964 fmt = fmt_long;
1965 #endif
1966
1967 /* For values not yet accessed, set to the desired format: */
1968 if (FPR_STATE[fpr] == fmt_uninterpreted) {
1969 FPR_STATE[fpr] = fmt;
1970 #ifdef DEBUG
1971 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
1972 #endif /* DEBUG */
1973 }
1974 if (fmt != FPR_STATE[fpr]) {
1975 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
1976 FPR_STATE[fpr] = fmt_unknown;
1977 }
1978
1979 if (FPR_STATE[fpr] == fmt_unknown) {
1980 /* Set QNaN value: */
1981 switch (fmt) {
1982 case fmt_single:
1983 value = FPQNaN_SINGLE;
1984 break;
1985
1986 case fmt_double:
1987 value = FPQNaN_DOUBLE;
1988 break;
1989
1990 case fmt_word:
1991 value = FPQNaN_WORD;
1992 break;
1993
1994 case fmt_long:
1995 value = FPQNaN_LONG;
1996 break;
1997
1998 default:
1999 err = -1;
2000 break;
2001 }
2002 } else if (SizeFGR() == 64) {
2003 switch (fmt) {
2004 case fmt_single:
2005 case fmt_word:
2006 value = (FGR[fpr] & 0xFFFFFFFF);
2007 break;
2008
2009 case fmt_uninterpreted:
2010 case fmt_double:
2011 case fmt_long:
2012 value = FGR[fpr];
2013 break;
2014
2015 default :
2016 err = -1;
2017 break;
2018 }
2019 } else {
2020 switch (fmt) {
2021 case fmt_single:
2022 case fmt_word:
2023 value = (FGR[fpr] & 0xFFFFFFFF);
2024 break;
2025
2026 case fmt_uninterpreted:
2027 case fmt_double:
2028 case fmt_long:
2029 if ((fpr & 1) == 0) { /* even registers only */
2030 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2031 } else {
2032 SignalException(ReservedInstruction,0);
2033 }
2034 break;
2035
2036 default :
2037 err = -1;
2038 break;
2039 }
2040 }
2041
2042 if (err)
2043 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2044
2045 #ifdef DEBUG
2046 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2047 #endif /* DEBUG */
2048
2049 return(value);
2050 }
2051
2052 void
2053 store_fpr(sd,cia,fpr,fmt,value)
2054 SIM_DESC sd;
2055 address_word cia;
2056 int fpr;
2057 FP_formats fmt;
2058 uword64 value;
2059 {
2060 int err = 0;
2061
2062 #ifdef DEBUG
2063 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2064 #endif /* DEBUG */
2065
2066 if (SizeFGR() == 64) {
2067 switch (fmt) {
2068 case fmt_uninterpreted_32:
2069 fmt = fmt_uninterpreted;
2070 case fmt_single :
2071 case fmt_word :
2072 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2073 FPR_STATE[fpr] = fmt;
2074 break;
2075
2076 case fmt_uninterpreted_64:
2077 fmt = fmt_uninterpreted;
2078 case fmt_uninterpreted:
2079 case fmt_double :
2080 case fmt_long :
2081 FGR[fpr] = value;
2082 FPR_STATE[fpr] = fmt;
2083 break;
2084
2085 default :
2086 FPR_STATE[fpr] = fmt_unknown;
2087 err = -1;
2088 break;
2089 }
2090 } else {
2091 switch (fmt) {
2092 case fmt_uninterpreted_32:
2093 fmt = fmt_uninterpreted;
2094 case fmt_single :
2095 case fmt_word :
2096 FGR[fpr] = (value & 0xFFFFFFFF);
2097 FPR_STATE[fpr] = fmt;
2098 break;
2099
2100 case fmt_uninterpreted_64:
2101 fmt = fmt_uninterpreted;
2102 case fmt_uninterpreted:
2103 case fmt_double :
2104 case fmt_long :
2105 if ((fpr & 1) == 0) { /* even register number only */
2106 FGR[fpr+1] = (value >> 32);
2107 FGR[fpr] = (value & 0xFFFFFFFF);
2108 FPR_STATE[fpr + 1] = fmt;
2109 FPR_STATE[fpr] = fmt;
2110 } else {
2111 FPR_STATE[fpr] = fmt_unknown;
2112 FPR_STATE[fpr + 1] = fmt_unknown;
2113 SignalException(ReservedInstruction,0);
2114 }
2115 break;
2116
2117 default :
2118 FPR_STATE[fpr] = fmt_unknown;
2119 err = -1;
2120 break;
2121 }
2122 }
2123 #if defined(WARN_RESULT)
2124 else
2125 UndefinedResult();
2126 #endif /* WARN_RESULT */
2127
2128 if (err)
2129 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2130
2131 #ifdef DEBUG
2132 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2133 #endif /* DEBUG */
2134
2135 return;
2136 }
2137
2138 int
2139 NaN(op,fmt)
2140 uword64 op;
2141 FP_formats fmt;
2142 {
2143 int boolean = 0;
2144
2145 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
2146 know that the exponent field is biased... we we cheat and avoid
2147 removing the bias value. */
2148 switch (fmt) {
2149 case fmt_single:
2150 boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0));
2151 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2152 dealing with a SNaN or QNaN */
2153 break;
2154 case fmt_double:
2155 boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0));
2156 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2157 dealing with a SNaN or QNaN */
2158 break;
2159 case fmt_word:
2160 boolean = (op == FPQNaN_WORD);
2161 break;
2162 case fmt_long:
2163 boolean = (op == FPQNaN_LONG);
2164 break;
2165 default:
2166 fprintf (stderr, "Bad switch\n");
2167 abort ();
2168 }
2169
2170 #ifdef DEBUG
2171 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2172 #endif /* DEBUG */
2173
2174 return(boolean);
2175 }
2176
2177 int
2178 Infinity(op,fmt)
2179 uword64 op;
2180 FP_formats fmt;
2181 {
2182 int boolean = 0;
2183
2184 #ifdef DEBUG
2185 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2186 #endif /* DEBUG */
2187
2188 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
2189 know that the exponent field is biased... we we cheat and avoid
2190 removing the bias value. */
2191 switch (fmt) {
2192 case fmt_single:
2193 boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0));
2194 break;
2195 case fmt_double:
2196 boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0));
2197 break;
2198 default:
2199 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2200 break;
2201 }
2202
2203 #ifdef DEBUG
2204 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2205 #endif /* DEBUG */
2206
2207 return(boolean);
2208 }
2209
2210 int
2211 Less(op1,op2,fmt)
2212 uword64 op1;
2213 uword64 op2;
2214 FP_formats fmt;
2215 {
2216 int boolean = 0;
2217
2218 /* Argument checking already performed by the FPCOMPARE code */
2219
2220 #ifdef DEBUG
2221 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2222 #endif /* DEBUG */
2223
2224 /* The format type should already have been checked: */
2225 switch (fmt) {
2226 case fmt_single:
2227 {
2228 unsigned int wop1 = (unsigned int)op1;
2229 unsigned int wop2 = (unsigned int)op2;
2230 boolean = (*(float *)&wop1 < *(float *)&wop2);
2231 }
2232 break;
2233 case fmt_double:
2234 boolean = (*(double *)&op1 < *(double *)&op2);
2235 break;
2236 default:
2237 fprintf (stderr, "Bad switch\n");
2238 abort ();
2239 }
2240
2241 #ifdef DEBUG
2242 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2243 #endif /* DEBUG */
2244
2245 return(boolean);
2246 }
2247
2248 int
2249 Equal(op1,op2,fmt)
2250 uword64 op1;
2251 uword64 op2;
2252 FP_formats fmt;
2253 {
2254 int boolean = 0;
2255
2256 /* Argument checking already performed by the FPCOMPARE code */
2257
2258 #ifdef DEBUG
2259 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2260 #endif /* DEBUG */
2261
2262 /* The format type should already have been checked: */
2263 switch (fmt) {
2264 case fmt_single:
2265 boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF));
2266 break;
2267 case fmt_double:
2268 boolean = (op1 == op2);
2269 break;
2270 default:
2271 fprintf (stderr, "Bad switch\n");
2272 abort ();
2273 }
2274
2275 #ifdef DEBUG
2276 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2277 #endif /* DEBUG */
2278
2279 return(boolean);
2280 }
2281
2282 uword64
2283 AbsoluteValue(op,fmt)
2284 uword64 op;
2285 FP_formats fmt;
2286 {
2287 uword64 result = 0;
2288
2289 #ifdef DEBUG
2290 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2291 #endif /* DEBUG */
2292
2293 /* The format type should already have been checked: */
2294 switch (fmt) {
2295 case fmt_single:
2296 {
2297 unsigned int wop = (unsigned int)op;
2298 float tmp = ((float)fabs((double)*(float *)&wop));
2299 result = (uword64)*(unsigned int *)&tmp;
2300 }
2301 break;
2302 case fmt_double:
2303 {
2304 double tmp = (fabs(*(double *)&op));
2305 result = *(uword64 *)&tmp;
2306 }
2307 default:
2308 fprintf (stderr, "Bad switch\n");
2309 abort ();
2310 }
2311
2312 return(result);
2313 }
2314
2315 uword64
2316 Negate(op,fmt)
2317 uword64 op;
2318 FP_formats fmt;
2319 {
2320 uword64 result = 0;
2321
2322 #ifdef DEBUG
2323 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2324 #endif /* DEBUG */
2325
2326 /* The format type should already have been checked: */
2327 switch (fmt) {
2328 case fmt_single:
2329 {
2330 unsigned int wop = (unsigned int)op;
2331 float tmp = ((float)0.0 - *(float *)&wop);
2332 result = (uword64)*(unsigned int *)&tmp;
2333 }
2334 break;
2335 case fmt_double:
2336 {
2337 double tmp = ((double)0.0 - *(double *)&op);
2338 result = *(uword64 *)&tmp;
2339 }
2340 break;
2341 default:
2342 fprintf (stderr, "Bad switch\n");
2343 abort ();
2344 }
2345
2346 return(result);
2347 }
2348
2349 uword64
2350 Add(op1,op2,fmt)
2351 uword64 op1;
2352 uword64 op2;
2353 FP_formats fmt;
2354 {
2355 uword64 result = 0;
2356
2357 #ifdef DEBUG
2358 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2359 #endif /* DEBUG */
2360
2361 /* The registers must specify FPRs valid for operands of type
2362 "fmt". If they are not valid, the result is undefined. */
2363
2364 /* The format type should already have been checked: */
2365 switch (fmt) {
2366 case fmt_single:
2367 {
2368 unsigned int wop1 = (unsigned int)op1;
2369 unsigned int wop2 = (unsigned int)op2;
2370 float tmp = (*(float *)&wop1 + *(float *)&wop2);
2371 result = (uword64)*(unsigned int *)&tmp;
2372 }
2373 break;
2374 case fmt_double:
2375 {
2376 double tmp = (*(double *)&op1 + *(double *)&op2);
2377 result = *(uword64 *)&tmp;
2378 }
2379 break;
2380 default:
2381 fprintf (stderr, "Bad switch\n");
2382 abort ();
2383 }
2384
2385 #ifdef DEBUG
2386 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2387 #endif /* DEBUG */
2388
2389 return(result);
2390 }
2391
2392 uword64
2393 Sub(op1,op2,fmt)
2394 uword64 op1;
2395 uword64 op2;
2396 FP_formats fmt;
2397 {
2398 uword64 result = 0;
2399
2400 #ifdef DEBUG
2401 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2402 #endif /* DEBUG */
2403
2404 /* The registers must specify FPRs valid for operands of type
2405 "fmt". If they are not valid, the result is undefined. */
2406
2407 /* The format type should already have been checked: */
2408 switch (fmt) {
2409 case fmt_single:
2410 {
2411 unsigned int wop1 = (unsigned int)op1;
2412 unsigned int wop2 = (unsigned int)op2;
2413 float tmp = (*(float *)&wop1 - *(float *)&wop2);
2414 result = (uword64)*(unsigned int *)&tmp;
2415 }
2416 break;
2417 case fmt_double:
2418 {
2419 double tmp = (*(double *)&op1 - *(double *)&op2);
2420 result = *(uword64 *)&tmp;
2421 }
2422 break;
2423 default:
2424 fprintf (stderr, "Bad switch\n");
2425 abort ();
2426 }
2427
2428 #ifdef DEBUG
2429 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2430 #endif /* DEBUG */
2431
2432 return(result);
2433 }
2434
2435 uword64
2436 Multiply(op1,op2,fmt)
2437 uword64 op1;
2438 uword64 op2;
2439 FP_formats fmt;
2440 {
2441 uword64 result = 0;
2442
2443 #ifdef DEBUG
2444 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2445 #endif /* DEBUG */
2446
2447 /* The registers must specify FPRs valid for operands of type
2448 "fmt". If they are not valid, the result is undefined. */
2449
2450 /* The format type should already have been checked: */
2451 switch (fmt) {
2452 case fmt_single:
2453 {
2454 unsigned int wop1 = (unsigned int)op1;
2455 unsigned int wop2 = (unsigned int)op2;
2456 float tmp = (*(float *)&wop1 * *(float *)&wop2);
2457 result = (uword64)*(unsigned int *)&tmp;
2458 }
2459 break;
2460 case fmt_double:
2461 {
2462 double tmp = (*(double *)&op1 * *(double *)&op2);
2463 result = *(uword64 *)&tmp;
2464 }
2465 break;
2466 default:
2467 fprintf (stderr, "Bad switch\n");
2468 abort ();
2469 }
2470
2471 #ifdef DEBUG
2472 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2473 #endif /* DEBUG */
2474
2475 return(result);
2476 }
2477
2478 uword64
2479 Divide(op1,op2,fmt)
2480 uword64 op1;
2481 uword64 op2;
2482 FP_formats fmt;
2483 {
2484 uword64 result = 0;
2485
2486 #ifdef DEBUG
2487 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2488 #endif /* DEBUG */
2489
2490 /* The registers must specify FPRs valid for operands of type
2491 "fmt". If they are not valid, the result is undefined. */
2492
2493 /* The format type should already have been checked: */
2494 switch (fmt) {
2495 case fmt_single:
2496 {
2497 unsigned int wop1 = (unsigned int)op1;
2498 unsigned int wop2 = (unsigned int)op2;
2499 float tmp = (*(float *)&wop1 / *(float *)&wop2);
2500 result = (uword64)*(unsigned int *)&tmp;
2501 }
2502 break;
2503 case fmt_double:
2504 {
2505 double tmp = (*(double *)&op1 / *(double *)&op2);
2506 result = *(uword64 *)&tmp;
2507 }
2508 break;
2509 default:
2510 fprintf (stderr, "Bad switch\n");
2511 abort ();
2512 }
2513
2514 #ifdef DEBUG
2515 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2516 #endif /* DEBUG */
2517
2518 return(result);
2519 }
2520
2521 uword64 UNUSED
2522 Recip(op,fmt)
2523 uword64 op;
2524 FP_formats fmt;
2525 {
2526 uword64 result = 0;
2527
2528 #ifdef DEBUG
2529 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2530 #endif /* DEBUG */
2531
2532 /* The registers must specify FPRs valid for operands of type
2533 "fmt". If they are not valid, the result is undefined. */
2534
2535 /* The format type should already have been checked: */
2536 switch (fmt) {
2537 case fmt_single:
2538 {
2539 unsigned int wop = (unsigned int)op;
2540 float tmp = ((float)1.0 / *(float *)&wop);
2541 result = (uword64)*(unsigned int *)&tmp;
2542 }
2543 break;
2544 case fmt_double:
2545 {
2546 double tmp = ((double)1.0 / *(double *)&op);
2547 result = *(uword64 *)&tmp;
2548 }
2549 break;
2550 default:
2551 fprintf (stderr, "Bad switch\n");
2552 abort ();
2553 }
2554
2555 #ifdef DEBUG
2556 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2557 #endif /* DEBUG */
2558
2559 return(result);
2560 }
2561
2562 uword64
2563 SquareRoot(op,fmt)
2564 uword64 op;
2565 FP_formats fmt;
2566 {
2567 uword64 result = 0;
2568
2569 #ifdef DEBUG
2570 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2571 #endif /* DEBUG */
2572
2573 /* The registers must specify FPRs valid for operands of type
2574 "fmt". If they are not valid, the result is undefined. */
2575
2576 /* The format type should already have been checked: */
2577 switch (fmt) {
2578 case fmt_single:
2579 {
2580 unsigned int wop = (unsigned int)op;
2581 #ifdef HAVE_SQRT
2582 float tmp = ((float)sqrt((double)*(float *)&wop));
2583 result = (uword64)*(unsigned int *)&tmp;
2584 #else
2585 /* TODO: Provide square-root */
2586 result = (uword64)0;
2587 #endif
2588 }
2589 break;
2590 case fmt_double:
2591 {
2592 #ifdef HAVE_SQRT
2593 double tmp = (sqrt(*(double *)&op));
2594 result = *(uword64 *)&tmp;
2595 #else
2596 /* TODO: Provide square-root */
2597 result = (uword64)0;
2598 #endif
2599 }
2600 break;
2601 default:
2602 fprintf (stderr, "Bad switch\n");
2603 abort ();
2604 }
2605
2606 #ifdef DEBUG
2607 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2608 #endif /* DEBUG */
2609
2610 return(result);
2611 }
2612
2613 uword64
2614 convert(sd,cia,rm,op,from,to)
2615 SIM_DESC sd;
2616 address_word cia;
2617 int rm;
2618 uword64 op;
2619 FP_formats from;
2620 FP_formats to;
2621 {
2622 uword64 result = 0;
2623
2624 #ifdef DEBUG
2625 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
2626 #endif /* DEBUG */
2627
2628 /* The value "op" is converted to the destination format, rounding
2629 using mode "rm". When the destination is a fixed-point format,
2630 then a source value of Infinity, NaN or one which would round to
2631 an integer outside the fixed point range then an IEEE Invalid
2632 Operation condition is raised. */
2633 switch (to) {
2634 case fmt_single:
2635 {
2636 float tmp;
2637 switch (from) {
2638 case fmt_double:
2639 tmp = (float)(*(double *)&op);
2640 break;
2641
2642 case fmt_word:
2643 tmp = (float)((int)(op & 0xFFFFFFFF));
2644 break;
2645
2646 case fmt_long:
2647 tmp = (float)((word64)op);
2648 break;
2649 default:
2650 fprintf (stderr, "Bad switch\n");
2651 abort ();
2652 }
2653
2654 #if 0
2655 /* FIXME: This code is incorrect. The rounding mode does not
2656 round to integral values; it rounds to the nearest
2657 representable value in the format. */
2658
2659 switch (rm) {
2660 case FP_RM_NEAREST:
2661 /* Round result to nearest representable value. When two
2662 representable values are equally near, round to the value
2663 that has a least significant bit of zero (i.e. is even). */
2664 #ifdef HAVE_ANINT
2665 tmp = (float)anint((double)tmp);
2666 #else
2667 /* TODO: Provide round-to-nearest */
2668 #endif
2669 break;
2670
2671 case FP_RM_TOZERO:
2672 /* Round result to the value closest to, and not greater in
2673 magnitude than, the result. */
2674 #ifdef HAVE_AINT
2675 tmp = (float)aint((double)tmp);
2676 #else
2677 /* TODO: Provide round-to-zero */
2678 #endif
2679 break;
2680
2681 case FP_RM_TOPINF:
2682 /* Round result to the value closest to, and not less than,
2683 the result. */
2684 tmp = (float)ceil((double)tmp);
2685 break;
2686
2687 case FP_RM_TOMINF:
2688 /* Round result to the value closest to, and not greater than,
2689 the result. */
2690 tmp = (float)floor((double)tmp);
2691 break;
2692 }
2693 #endif /* 0 */
2694
2695 result = (uword64)*(unsigned int *)&tmp;
2696 }
2697 break;
2698
2699 case fmt_double:
2700 {
2701 double tmp;
2702 word64 xxx;
2703
2704 switch (from) {
2705 case fmt_single:
2706 {
2707 unsigned int wop = (unsigned int)op;
2708 tmp = (double)(*(float *)&wop);
2709 }
2710 break;
2711
2712 case fmt_word:
2713 xxx = SIGNEXTEND((op & 0xFFFFFFFF),32);
2714 tmp = (double)xxx;
2715 break;
2716
2717 case fmt_long:
2718 tmp = (double)((word64)op);
2719 break;
2720
2721 default:
2722 fprintf (stderr, "Bad switch\n");
2723 abort ();
2724 }
2725
2726 #if 0
2727 /* FIXME: This code is incorrect. The rounding mode does not
2728 round to integral values; it rounds to the nearest
2729 representable value in the format. */
2730
2731 switch (rm) {
2732 case FP_RM_NEAREST:
2733 #ifdef HAVE_ANINT
2734 tmp = anint(*(double *)&tmp);
2735 #else
2736 /* TODO: Provide round-to-nearest */
2737 #endif
2738 break;
2739
2740 case FP_RM_TOZERO:
2741 #ifdef HAVE_AINT
2742 tmp = aint(*(double *)&tmp);
2743 #else
2744 /* TODO: Provide round-to-zero */
2745 #endif
2746 break;
2747
2748 case FP_RM_TOPINF:
2749 tmp = ceil(*(double *)&tmp);
2750 break;
2751
2752 case FP_RM_TOMINF:
2753 tmp = floor(*(double *)&tmp);
2754 break;
2755 }
2756 #endif /* 0 */
2757
2758 result = *(uword64 *)&tmp;
2759 }
2760 break;
2761
2762 case fmt_word:
2763 case fmt_long:
2764 if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) {
2765 printf("DBG: TODO: update FCSR\n");
2766 SignalExceptionFPE ();
2767 } else {
2768 if (to == fmt_word) {
2769 int tmp = 0;
2770 switch (from) {
2771 case fmt_single:
2772 {
2773 unsigned int wop = (unsigned int)op;
2774 tmp = (int)*((float *)&wop);
2775 }
2776 break;
2777 case fmt_double:
2778 tmp = (int)*((double *)&op);
2779 #ifdef DEBUG
2780 printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp);
2781 #endif /* DEBUG */
2782 break;
2783 default:
2784 fprintf (stderr, "Bad switch\n");
2785 abort ();
2786 }
2787 result = (uword64)tmp;
2788 } else { /* fmt_long */
2789 word64 tmp = 0;
2790 switch (from) {
2791 case fmt_single:
2792 {
2793 unsigned int wop = (unsigned int)op;
2794 tmp = (word64)*((float *)&wop);
2795 }
2796 break;
2797 case fmt_double:
2798 tmp = (word64)*((double *)&op);
2799 break;
2800 default:
2801 fprintf (stderr, "Bad switch\n");
2802 abort ();
2803 }
2804 result = (uword64)tmp;
2805 }
2806 }
2807 break;
2808 default:
2809 fprintf (stderr, "Bad switch\n");
2810 abort ();
2811 }
2812
2813 #ifdef DEBUG
2814 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to));
2815 #endif /* DEBUG */
2816
2817 return(result);
2818 }
2819 #endif /* HASFPU */
2820
2821 /*-- co-processor support routines ------------------------------------------*/
2822
2823 static int UNUSED
2824 CoProcPresent(coproc_number)
2825 unsigned int coproc_number;
2826 {
2827 /* Return TRUE if simulator provides a model for the given co-processor number */
2828 return(0);
2829 }
2830
2831 void
2832 cop_lw(sd,cia,coproc_num,coproc_reg,memword)
2833 SIM_DESC sd;
2834 address_word cia;
2835 int coproc_num, coproc_reg;
2836 unsigned int memword;
2837 {
2838 switch (coproc_num) {
2839 #if defined(HASFPU)
2840 case 1:
2841 #ifdef DEBUG
2842 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2843 #endif
2844 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
2845 FPR_STATE[coproc_reg] = fmt_uninterpreted;
2846 break;
2847 #endif /* HASFPU */
2848
2849 default:
2850 #if 0 /* this should be controlled by a configuration option */
2851 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2852 #endif
2853 break;
2854 }
2855
2856 return;
2857 }
2858
2859 void
2860 cop_ld(sd,cia,coproc_num,coproc_reg,memword)
2861 SIM_DESC sd;
2862 address_word cia;
2863 int coproc_num, coproc_reg;
2864 uword64 memword;
2865 {
2866 switch (coproc_num) {
2867 #if defined(HASFPU)
2868 case 1:
2869 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
2870 break;
2871 #endif /* HASFPU */
2872
2873 default:
2874 #if 0 /* this message should be controlled by a configuration option */
2875 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2876 #endif
2877 break;
2878 }
2879
2880 return;
2881 }
2882
2883 unsigned int
2884 cop_sw(sd,cia,coproc_num,coproc_reg)
2885 SIM_DESC sd;
2886 address_word cia;
2887 int coproc_num, coproc_reg;
2888 {
2889 unsigned int value = 0;
2890
2891 switch (coproc_num) {
2892 #if defined(HASFPU)
2893 case 1:
2894 #if 1
2895 {
2896 FP_formats hold;
2897 hold = FPR_STATE[coproc_reg];
2898 FPR_STATE[coproc_reg] = fmt_word;
2899 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
2900 FPR_STATE[coproc_reg] = hold;
2901 }
2902 #else
2903 #if 1
2904 value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
2905 #else
2906 #ifdef DEBUG
2907 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg]));
2908 #endif /* DEBUG */
2909 value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
2910 #endif
2911 #endif
2912 break;
2913 #endif /* HASFPU */
2914
2915 default:
2916 #if 0 /* should be controlled by configuration option */
2917 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2918 #endif
2919 break;
2920 }
2921
2922 return(value);
2923 }
2924
2925 uword64
2926 cop_sd(sd,cia,coproc_num,coproc_reg)
2927 SIM_DESC sd;
2928 address_word cia;
2929 int coproc_num, coproc_reg;
2930 {
2931 uword64 value = 0;
2932 switch (coproc_num) {
2933 #if defined(HASFPU)
2934 case 1:
2935 #if 1
2936 value = ValueFPR(coproc_reg,fmt_uninterpreted);
2937 #else
2938 #if 1
2939 value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
2940 #else
2941 #ifdef DEBUG
2942 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg]));
2943 #endif /* DEBUG */
2944 value = ValueFPR(coproc_reg,fmt_double);
2945 #endif
2946 #endif
2947 break;
2948 #endif /* HASFPU */
2949
2950 default:
2951 #if 0 /* should be controlled by configuration option */
2952 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2953 #endif
2954 break;
2955 }
2956
2957 return(value);
2958 }
2959
2960 void
2961 decode_coproc(sd,cia,instruction)
2962 SIM_DESC sd;
2963 address_word cia;
2964 unsigned int instruction;
2965 {
2966 int coprocnum = ((instruction >> 26) & 3);
2967
2968 switch (coprocnum)
2969 {
2970 case 0: /* standard CPU control and cache registers */
2971 {
2972 int code = ((instruction >> 21) & 0x1F);
2973 /* R4000 Users Manual (second edition) lists the following CP0
2974 instructions:
2975 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2976 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2977 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2978 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2979 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2980 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2981 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2982 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2983 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2984 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2985 */
2986 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
2987 {
2988 int rt = ((instruction >> 16) & 0x1F);
2989 int rd = ((instruction >> 11) & 0x1F);
2990
2991 switch (rd) /* NOTEs: Standard CP0 registers */
2992 {
2993 /* 0 = Index R4000 VR4100 VR4300 */
2994 /* 1 = Random R4000 VR4100 VR4300 */
2995 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2996 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2997 /* 4 = Context R4000 VR4100 VR4300 */
2998 /* 5 = PageMask R4000 VR4100 VR4300 */
2999 /* 6 = Wired R4000 VR4100 VR4300 */
3000 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3001 /* 9 = Count R4000 VR4100 VR4300 */
3002 /* 10 = EntryHi R4000 VR4100 VR4300 */
3003 /* 11 = Compare R4000 VR4100 VR4300 */
3004 /* 12 = SR R4000 VR4100 VR4300 */
3005 case 12:
3006 if (code == 0x00)
3007 GPR[rt] = SR;
3008 else
3009 SR = GPR[rt];
3010 break;
3011 /* 13 = Cause R4000 VR4100 VR4300 */
3012 case 13:
3013 if (code == 0x00)
3014 GPR[rt] = CAUSE;
3015 else
3016 CAUSE = GPR[rt];
3017 break;
3018 /* 14 = EPC R4000 VR4100 VR4300 */
3019 /* 15 = PRId R4000 VR4100 VR4300 */
3020 #ifdef SUBTARGET_R3900
3021 /* 16 = Debug */
3022 case 16:
3023 if (code == 0x00)
3024 GPR[rt] = Debug;
3025 else
3026 Debug = GPR[rt];
3027 break;
3028 #else
3029 /* 16 = Config R4000 VR4100 VR4300 */
3030 case 16:
3031 if (code == 0x00)
3032 GPR[rt] = C0_CONFIG;
3033 else
3034 C0_CONFIG = GPR[rt];
3035 break;
3036 #endif
3037 #ifdef SUBTARGET_R3900
3038 /* 17 = Debug */
3039 case 17:
3040 if (code == 0x00)
3041 GPR[rt] = DEPC;
3042 else
3043 DEPC = GPR[rt];
3044 break;
3045 #else
3046 /* 17 = LLAddr R4000 VR4100 VR4300 */
3047 #endif
3048 /* 18 = WatchLo R4000 VR4100 VR4300 */
3049 /* 19 = WatchHi R4000 VR4100 VR4300 */
3050 /* 20 = XContext R4000 VR4100 VR4300 */
3051 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3052 /* 27 = CacheErr R4000 VR4100 */
3053 /* 28 = TagLo R4000 VR4100 VR4300 */
3054 /* 29 = TagHi R4000 VR4100 VR4300 */
3055 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3056 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3057 /* CPR[0,rd] = GPR[rt]; */
3058 default:
3059 if (code == 0x00)
3060 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3061 else
3062 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3063 }
3064 }
3065 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3066 {
3067 /* ERET */
3068 if (SR & status_ERL)
3069 {
3070 /* Oops, not yet available */
3071 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3072 PC = EPC;
3073 SR &= ~status_ERL;
3074 }
3075 else
3076 {
3077 PC = EPC;
3078 SR &= ~status_EXL;
3079 }
3080 }
3081 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3082 {
3083 /* RFE */
3084 }
3085 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3086 {
3087 /* DERET */
3088 Debug &= ~Debug_DM;
3089 DELAYSLOT();
3090 DSPC = DEPC;
3091 }
3092 else
3093 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3094 /* TODO: When executing an ERET or RFE instruction we should
3095 clear LLBIT, to ensure that any out-standing atomic
3096 read/modify/write sequence fails. */
3097 }
3098 break;
3099
3100 case 2: /* undefined co-processor */
3101 sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3102 break;
3103
3104 case 1: /* should not occur (FPU co-processor) */
3105 case 3: /* should not occur (FPU co-processor) */
3106 SignalException(ReservedInstruction,instruction);
3107 break;
3108 }
3109
3110 return;
3111 }
3112
3113 /*-- instruction simulation -------------------------------------------------*/
3114
3115 /* When the IGEN simulator is being built, the function below is be
3116 replaced by a generated version. However, WITH_IGEN == 2 indicates
3117 that the fubction below should be compiled but under a different
3118 name (to allow backward compatibility) */
3119
3120 #if (WITH_IGEN != 1)
3121 #if (WITH_IGEN > 1)
3122 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3123 void
3124 old_engine_run (sd, next_cpu_nr, siggnal)
3125 #else
3126 void
3127 sim_engine_run (sd, next_cpu_nr, siggnal)
3128 #endif
3129 SIM_DESC sd;
3130 int next_cpu_nr; /* ignore */
3131 int siggnal; /* ignore */
3132 {
3133 #if !defined(FASTSIM)
3134 unsigned int pipeline_count = 1;
3135 #endif
3136
3137 #ifdef DEBUG
3138 if (STATE_MEMORY (sd) == NULL) {
3139 printf("DBG: simulate() entered with no memory\n");
3140 exit(1);
3141 }
3142 #endif /* DEBUG */
3143
3144 #if 0 /* Disabled to check that everything works OK */
3145 /* The VR4300 seems to sign-extend the PC on its first
3146 access. However, this may just be because it is currently
3147 configured in 32bit mode. However... */
3148 PC = SIGNEXTEND(PC,32);
3149 #endif
3150
3151 /* main controlling loop */
3152 while (1) {
3153 /* vaddr is slowly being replaced with cia - current instruction
3154 address */
3155 address_word cia = (uword64)PC;
3156 address_word vaddr = cia;
3157 address_word paddr;
3158 int cca;
3159 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3160
3161 #ifdef DEBUG
3162 {
3163 printf("DBG: state = 0x%08X :",state);
3164 if (state & simHALTEX) printf(" simHALTEX");
3165 if (state & simHALTIN) printf(" simHALTIN");
3166 printf("\n");
3167 }
3168 #endif /* DEBUG */
3169
3170 DSSTATE = (STATE & simDELAYSLOT);
3171 #ifdef DEBUG
3172 if (dsstate)
3173 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3174 #endif /* DEBUG */
3175
3176 /* Fetch the next instruction from the simulator memory: */
3177 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3178 if ((vaddr & 1) == 0) {
3179 /* Copy the action of the LW instruction */
3180 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3181 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3182 uword64 value;
3183 unsigned int byte;
3184 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3185 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3186 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3187 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3188 } else {
3189 /* Copy the action of the LH instruction */
3190 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3191 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3192 uword64 value;
3193 unsigned int byte;
3194 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3195 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3196 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3197 paddr & ~ (uword64) 1,
3198 vaddr, isINSTRUCTION, isREAL);
3199 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3200 instruction = ((value >> (8 * byte)) & 0xFFFF);
3201 }
3202 } else {
3203 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3204 exit(1);
3205 }
3206
3207 #ifdef DEBUG
3208 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3209 #endif /* DEBUG */
3210
3211 /* This is required by exception processing, to ensure that we can
3212 cope with exceptions in the delay slots of branches that may
3213 already have changed the PC. */
3214 if ((vaddr & 1) == 0)
3215 PC += 4; /* increment ready for the next fetch */
3216 else
3217 PC += 2;
3218 /* NOTE: If we perform a delay slot change to the PC, this
3219 increment is not requuired. However, it would make the
3220 simulator more complicated to try and avoid this small hit. */
3221
3222 /* Currently this code provides a simple model. For more
3223 complicated models we could perform exception status checks at
3224 this point, and set the simSTOP state as required. This could
3225 also include processing any hardware interrupts raised by any
3226 I/O model attached to the simulator context.
3227
3228 Support for "asynchronous" I/O events within the simulated world
3229 could be providing by managing a counter, and calling a I/O
3230 specific handler when a particular threshold is reached. On most
3231 architectures a decrement and check for zero operation is
3232 usually quicker than an increment and compare. However, the
3233 process of managing a known value decrement to zero, is higher
3234 than the cost of using an explicit value UINT_MAX into the
3235 future. Which system is used will depend on how complicated the
3236 I/O model is, and how much it is likely to affect the simulator
3237 bandwidth.
3238
3239 If events need to be scheduled further in the future than
3240 UINT_MAX event ticks, then the I/O model should just provide its
3241 own counter, triggered from the event system. */
3242
3243 /* MIPS pipeline ticks. To allow for future support where the
3244 pipeline hit of individual instructions is known, this control
3245 loop manages a "pipeline_count" variable. It is initialised to
3246 1 (one), and will only be changed by the simulator engine when
3247 executing an instruction. If the engine does not have access to
3248 pipeline cycle count information then all instructions will be
3249 treated as using a single cycle. NOTE: A standard system is not
3250 provided by the default simulator because different MIPS
3251 architectures have different cycle counts for the same
3252 instructions.
3253
3254 [NOTE: pipeline_count has been replaced the event queue] */
3255
3256 /* shuffle the floating point status pipeline state */
3257 ENGINE_ISSUE_PREFIX_HOOK();
3258
3259 /* NOTE: For multi-context simulation environments the "instruction"
3260 variable should be local to this routine. */
3261
3262 /* Shorthand accesses for engine. Note: If we wanted to use global
3263 variables (and a single-threaded simulator engine), then we can
3264 create the actual variables with these names. */
3265
3266 if (!(STATE & simSKIPNEXT)) {
3267 /* Include the simulator engine */
3268 #include "oengine.c"
3269 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3270 #error "Mismatch between run-time simulator code and simulation engine"
3271 #endif
3272 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3273 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3274 #endif
3275 #if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU))
3276 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3277 #endif
3278
3279 #if defined(WARN_LOHI)
3280 /* Decrement the HI/LO validity ticks */
3281 if (HIACCESS > 0)
3282 HIACCESS--;
3283 if (LOACCESS > 0)
3284 LOACCESS--;
3285 /* start-sanitize-r5900 */
3286 if (HI1ACCESS > 0)
3287 HI1ACCESS--;
3288 if (LO1ACCESS > 0)
3289 LO1ACCESS--;
3290 /* end-sanitize-r5900 */
3291 #endif /* WARN_LOHI */
3292
3293 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3294 should check for it being changed. It is better doing it here,
3295 than within the simulator, since it will help keep the simulator
3296 small. */
3297 if (ZERO != 0) {
3298 #if defined(WARN_ZERO)
3299 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3300 #endif /* WARN_ZERO */
3301 ZERO = 0; /* reset back to zero before next instruction */
3302 }
3303 } else /* simSKIPNEXT check */
3304 STATE &= ~simSKIPNEXT;
3305
3306 /* If the delay slot was active before the instruction is
3307 executed, then update the PC to its new value: */
3308 if (DSSTATE) {
3309 #ifdef DEBUG
3310 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3311 #endif /* DEBUG */
3312 PC = DSPC;
3313 CANCELDELAYSLOT();
3314 }
3315
3316 if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
3317 /* Deal with pending register updates: */
3318 #ifdef DEBUG
3319 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
3320 #endif /* DEBUG */
3321 if (PENDING_OUT != PENDING_IN) {
3322 int loop;
3323 int index = PENDING_OUT;
3324 int total = PENDING_TOTAL;
3325 if (PENDING_TOTAL == 0) {
3326 fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
3327 exit(1);
3328 }
3329 for (loop = 0; (loop < total); loop++) {
3330 #ifdef DEBUG
3331 printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
3332 #endif /* DEBUG */
3333 if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
3334 #ifdef DEBUG
3335 printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
3336 #endif /* DEBUG */
3337 if (--(PENDING_SLOT_COUNT[index]) == 0) {
3338 #ifdef DEBUG
3339 printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
3340 printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
3341 #endif /* DEBUG */
3342 if (PENDING_SLOT_REG[index] == COCIDX) {
3343 #if defined(HASFPU)
3344 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3345 #else
3346 ;
3347 #endif
3348 } else {
3349 REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
3350 #if defined(HASFPU)
3351 /* The only time we have PENDING updates to FPU
3352 registers, is when performing binary transfers. This
3353 means we should update the register type field. */
3354 if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
3355 FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
3356 #endif /* HASFPU */
3357 }
3358 #ifdef DEBUG
3359 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
3360 #endif /* DEBUG */
3361 PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
3362 PENDING_OUT++;
3363 if (PENDING_OUT == PSLOTS)
3364 PENDING_OUT = 0;
3365 PENDING_TOTAL--;
3366 }
3367 }
3368 #ifdef DEBUG
3369 printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
3370 #endif /* DEBUG */
3371 index++;
3372 if (index == PSLOTS)
3373 index = 0;
3374 }
3375 }
3376 #ifdef DEBUG
3377 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
3378 #endif /* DEBUG */
3379 }
3380
3381 #if !defined(FASTSIM)
3382 if (sim_events_tickn (sd, pipeline_count))
3383 {
3384 /* cpu->cia = cia; */
3385 sim_events_process (sd);
3386 }
3387 #else
3388 if (sim_events_tick (sd))
3389 {
3390 /* cpu->cia = cia; */
3391 sim_events_process (sd);
3392 }
3393 #endif /* FASTSIM */
3394 }
3395 }
3396 #endif
3397
3398
3399 /* This code copied from gdb's utils.c. Would like to share this code,
3400 but don't know of a common place where both could get to it. */
3401
3402 /* Temporary storage using circular buffer */
3403 #define NUMCELLS 16
3404 #define CELLSIZE 32
3405 static char*
3406 get_cell()
3407 {
3408 static char buf[NUMCELLS][CELLSIZE];
3409 static int cell=0;
3410 if (++cell>=NUMCELLS) cell=0;
3411 return buf[cell];
3412 }
3413
3414 /* Print routines to handle variable size regs, etc */
3415
3416 /* Eliminate warning from compiler on 32-bit systems */
3417 static int thirty_two = 32;
3418
3419 char*
3420 pr_addr(addr)
3421 SIM_ADDR addr;
3422 {
3423 char *paddr_str=get_cell();
3424 switch (sizeof(addr))
3425 {
3426 case 8:
3427 sprintf(paddr_str,"%08lx%08lx",
3428 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3429 break;
3430 case 4:
3431 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3432 break;
3433 case 2:
3434 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3435 break;
3436 default:
3437 sprintf(paddr_str,"%x",addr);
3438 }
3439 return paddr_str;
3440 }
3441
3442 char*
3443 pr_uword64(addr)
3444 uword64 addr;
3445 {
3446 char *paddr_str=get_cell();
3447 sprintf(paddr_str,"%08lx%08lx",
3448 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3449 return paddr_str;
3450 }
3451
3452
3453 /*---------------------------------------------------------------------------*/
3454 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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