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[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 NOTEs:
17
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
21 code on the hardware.
22
23 */
24
25 #include "config.h"
26 #include "bfd.h"
27 #include "sim-main.h"
28 #include "sim-utils.h"
29 #include "sim-options.h"
30 #include "sim-assert.h"
31 #include "sim-hw.h"
32
33 #include "itable.h"
34
35
36 #include "config.h"
37
38 #include <stdio.h>
39 #include <stdarg.h>
40 #include <ansidecl.h>
41 #include <ctype.h>
42 #include <limits.h>
43 #include <math.h>
44 #ifdef HAVE_STDLIB_H
45 #include <stdlib.h>
46 #endif
47 #ifdef HAVE_STRING_H
48 #include <string.h>
49 #else
50 #ifdef HAVE_STRINGS_H
51 #include <strings.h>
52 #endif
53 #endif
54
55 #include "getopt.h"
56 #include "libiberty.h"
57 #include "bfd.h"
58 #include "gdb/callback.h" /* GDB simulator callback interface */
59 #include "gdb/remote-sim.h" /* GDB simulator interface */
60
61 char* pr_addr (SIM_ADDR addr);
62 char* pr_uword64 (uword64 addr);
63
64
65 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
66 #define CPU cpu
67 #define SD sd
68
69
70 /* The following reserved instruction value is used when a simulator
71 trap is required. NOTE: Care must be taken, since this value may be
72 used in later revisions of the MIPS ISA. */
73
74 #define RSVD_INSTRUCTION (0x00000039)
75 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
76
77 #define RSVD_INSTRUCTION_ARG_SHIFT 6
78 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
79
80
81 /* Bits in the Debug register */
82 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
83 #define Debug_DM 0x40000000 /* Debug Mode */
84 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
85
86 /*---------------------------------------------------------------------------*/
87 /*-- GDB simulator interface ------------------------------------------------*/
88 /*---------------------------------------------------------------------------*/
89
90 static void ColdReset (SIM_DESC sd);
91
92 /*---------------------------------------------------------------------------*/
93
94
95
96 #define DELAYSLOT() {\
97 if (STATE & simDELAYSLOT)\
98 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
99 STATE |= simDELAYSLOT;\
100 }
101
102 #define JALDELAYSLOT() {\
103 DELAYSLOT ();\
104 STATE |= simJALDELAYSLOT;\
105 }
106
107 #define NULLIFY() {\
108 STATE &= ~simDELAYSLOT;\
109 STATE |= simSKIPNEXT;\
110 }
111
112 #define CANCELDELAYSLOT() {\
113 DSSTATE = 0;\
114 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
115 }
116
117 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
118 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
119
120 /* Note that the monitor code essentially assumes this layout of memory.
121 If you change these, change the monitor code, too. */
122 /* FIXME Currently addresses are truncated to 32-bits, see
123 mips/sim-main.c:address_translation(). If that changes, then these
124 values will need to be extended, and tested for more carefully. */
125 #define K0BASE (0x80000000)
126 #define K0SIZE (0x20000000)
127 #define K1BASE (0xA0000000)
128 #define K1SIZE (0x20000000)
129
130 /* Simple run-time monitor support.
131
132 We emulate the monitor by placing magic reserved instructions at
133 the monitor's entry points; when we hit these instructions, instead
134 of raising an exception (as we would normally), we look at the
135 instruction and perform the appropriate monitory operation.
136
137 `*_monitor_base' are the physical addresses at which the corresponding
138 monitor vectors are located. `0' means none. By default,
139 install all three.
140 The RSVD_INSTRUCTION... macros specify the magic instructions we
141 use at the monitor entry points. */
142 static int firmware_option_p = 0;
143 static SIM_ADDR idt_monitor_base = 0xBFC00000;
144 static SIM_ADDR pmon_monitor_base = 0xBFC00500;
145 static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
146
147 static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
148
149 #define MEM_SIZE (8 << 20) /* 8 MBytes */
150
151
152 #if WITH_TRACE_ANY_P
153 static char *tracefile = "trace.din"; /* default filename for trace log */
154 FILE *tracefh = NULL;
155 static void open_trace (SIM_DESC sd);
156 #else
157 #define open_trace(sd)
158 #endif
159
160 static const char * get_insn_name (sim_cpu *, int);
161
162 /* simulation target board. NULL=canonical */
163 static char* board = NULL;
164
165
166 static DECLARE_OPTION_HANDLER (mips_option_handler);
167
168 enum {
169 OPTION_DINERO_TRACE = OPTION_START,
170 OPTION_DINERO_FILE,
171 OPTION_FIRMWARE,
172 OPTION_INFO_MEMORY,
173 OPTION_BOARD
174 };
175
176 static int display_mem_info = 0;
177
178 static SIM_RC
179 mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
180 int is_command)
181 {
182 int cpu_nr;
183 switch (opt)
184 {
185 case OPTION_DINERO_TRACE: /* ??? */
186 #if WITH_TRACE_ANY_P
187 /* Eventually the simTRACE flag could be treated as a toggle, to
188 allow external control of the program points being traced
189 (i.e. only from main onwards, excluding the run-time setup,
190 etc.). */
191 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
192 {
193 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
194 if (arg == NULL)
195 STATE |= simTRACE;
196 else if (strcmp (arg, "yes") == 0)
197 STATE |= simTRACE;
198 else if (strcmp (arg, "no") == 0)
199 STATE &= ~simTRACE;
200 else if (strcmp (arg, "on") == 0)
201 STATE |= simTRACE;
202 else if (strcmp (arg, "off") == 0)
203 STATE &= ~simTRACE;
204 else
205 {
206 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
207 return SIM_RC_FAIL;
208 }
209 }
210 return SIM_RC_OK;
211 #else /* !WITH_TRACE_ANY_P */
212 fprintf(stderr,"\
213 Simulator constructed without dinero tracing support (for performance).\n\
214 Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
215 return SIM_RC_FAIL;
216 #endif /* !WITH_TRACE_ANY_P */
217
218 case OPTION_DINERO_FILE:
219 #if WITH_TRACE_ANY_P
220 if (optarg != NULL) {
221 char *tmp;
222 tmp = (char *)malloc(strlen(optarg) + 1);
223 if (tmp == NULL)
224 {
225 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
226 return SIM_RC_FAIL;
227 }
228 else {
229 strcpy(tmp,optarg);
230 tracefile = tmp;
231 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
232 }
233 }
234 #endif /* WITH_TRACE_ANY_P */
235 return SIM_RC_OK;
236
237 case OPTION_FIRMWARE:
238 return sim_firmware_command (sd, arg);
239
240 case OPTION_BOARD:
241 {
242 if (arg)
243 {
244 board = zalloc(strlen(arg) + 1);
245 strcpy(board, arg);
246 }
247 return SIM_RC_OK;
248 }
249
250 case OPTION_INFO_MEMORY:
251 display_mem_info = 1;
252 break;
253 }
254
255 return SIM_RC_OK;
256 }
257
258
259 static const OPTION mips_options[] =
260 {
261 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
262 '\0', "on|off", "Enable dinero tracing",
263 mips_option_handler },
264 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
265 '\0', "FILE", "Write dinero trace to FILE",
266 mips_option_handler },
267 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
268 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
269 mips_option_handler },
270 { {"board", required_argument, NULL, OPTION_BOARD},
271 '\0', "none" /* rely on compile-time string concatenation for other options */
272
273 #define BOARD_JMR3904 "jmr3904"
274 "|" BOARD_JMR3904
275 #define BOARD_JMR3904_PAL "jmr3904pal"
276 "|" BOARD_JMR3904_PAL
277 #define BOARD_JMR3904_DEBUG "jmr3904debug"
278 "|" BOARD_JMR3904_DEBUG
279 #define BOARD_BSP "bsp"
280 "|" BOARD_BSP
281
282 , "Customize simulation for a particular board.", mips_option_handler },
283
284 /* These next two options have the same names as ones found in the
285 memory_options[] array in common/sim-memopt.c. This is because
286 the intention is to provide an alternative handler for those two
287 options. We need an alternative handler because the memory
288 regions are not set up until after the command line arguments
289 have been parsed, and so we cannot display the memory info whilst
290 processing the command line. There is a hack in sim_open to
291 remove these handlers when we want the real --memory-info option
292 to work. */
293 { { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
294 '\0', NULL, "List configured memory regions", mips_option_handler },
295 { { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
296 '\0', NULL, NULL, mips_option_handler },
297
298 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
299 };
300
301
302 int interrupt_pending;
303
304 void
305 interrupt_event (SIM_DESC sd, void *data)
306 {
307 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
308 address_word cia = CPU_PC_GET (cpu);
309 if (SR & status_IE)
310 {
311 interrupt_pending = 0;
312 SignalExceptionInterrupt (1); /* interrupt "1" */
313 }
314 else if (!interrupt_pending)
315 sim_events_schedule (sd, 1, interrupt_event, data);
316 }
317
318
319 /*---------------------------------------------------------------------------*/
320 /*-- Device registration hook -----------------------------------------------*/
321 /*---------------------------------------------------------------------------*/
322 static void device_init(SIM_DESC sd) {
323 #ifdef DEVICE_INIT
324 extern void register_devices(SIM_DESC);
325 register_devices(sd);
326 #endif
327 }
328
329 /*---------------------------------------------------------------------------*/
330 /*-- GDB simulator interface ------------------------------------------------*/
331 /*---------------------------------------------------------------------------*/
332
333 static sim_cia
334 mips_pc_get (sim_cpu *cpu)
335 {
336 return PC;
337 }
338
339 static void
340 mips_pc_set (sim_cpu *cpu, sim_cia pc)
341 {
342 PC = pc;
343 }
344
345 SIM_DESC
346 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
347 {
348 int i;
349 SIM_DESC sd = sim_state_alloc (kind, cb);
350 sim_cpu *cpu;
351
352 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
353
354 /* The cpu data is kept in a separately allocated chunk of memory. */
355 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
356 return 0;
357
358 cpu = STATE_CPU (sd, 0); /* FIXME */
359
360 /* FIXME: watchpoints code shouldn't need this */
361 STATE_WATCHPOINTS (sd)->pc = &(PC);
362 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
363 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
364
365 /* Initialize the mechanism for doing insn profiling. */
366 CPU_INSN_NAME (cpu) = get_insn_name;
367 CPU_MAX_INSNS (cpu) = nr_itable_entries;
368
369 STATE = 0;
370
371 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
372 return 0;
373 sim_add_option_table (sd, NULL, mips_options);
374
375
376 /* getopt will print the error message so we just have to exit if this fails.
377 FIXME: Hmmm... in the case of gdb we need getopt to call
378 print_filtered. */
379 if (sim_parse_args (sd, argv) != SIM_RC_OK)
380 {
381 /* Uninstall the modules to avoid memory leaks,
382 file descriptor leaks, etc. */
383 sim_module_uninstall (sd);
384 return 0;
385 }
386
387 /* handle board-specific memory maps */
388 if (board == NULL)
389 {
390 /* Allocate core managed memory */
391 sim_memopt *entry, *match = NULL;
392 address_word mem_size = 0;
393 int mapped = 0;
394
395 /* For compatibility with the old code - under this (at level one)
396 are the kernel spaces K0 & K1. Both of these map to a single
397 smaller sub region */
398 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
399
400 /* Look for largest memory region defined on command-line at
401 phys address 0. */
402 #ifdef SIM_HAVE_FLATMEM
403 mem_size = STATE_MEM_SIZE (sd);
404 #endif
405 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
406 {
407 /* If we find an entry at address 0, then we will end up
408 allocating a new buffer in the "memory alias" command
409 below. The region at address 0 will be deleted. */
410 address_word size = (entry->modulo != 0
411 ? entry->modulo : entry->nr_bytes);
412 if (entry->addr == 0
413 && (!match || entry->level < match->level))
414 match = entry;
415 else if (entry->addr == K0BASE || entry->addr == K1BASE)
416 mapped = 1;
417 else
418 {
419 sim_memopt *alias;
420 for (alias = entry->alias; alias != NULL; alias = alias->next)
421 {
422 if (alias->addr == 0
423 && (!match || entry->level < match->level))
424 match = entry;
425 else if (alias->addr == K0BASE || alias->addr == K1BASE)
426 mapped = 1;
427 }
428 }
429 }
430
431 if (!mapped)
432 {
433 if (match)
434 {
435 /* Get existing memory region size. */
436 mem_size = (match->modulo != 0
437 ? match->modulo : match->nr_bytes);
438 /* Delete old region. */
439 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
440 match->space, match->addr, match->level);
441 }
442 else if (mem_size == 0)
443 mem_size = MEM_SIZE;
444 /* Limit to KSEG1 size (512MB) */
445 if (mem_size > K1SIZE)
446 mem_size = K1SIZE;
447 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
448 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
449 K1BASE, K1SIZE, (long)mem_size, K0BASE);
450 }
451
452 device_init(sd);
453 }
454 else if (board != NULL
455 && (strcmp(board, BOARD_BSP) == 0))
456 {
457 int i;
458
459 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
460
461 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
462 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
463 0x9FC00000,
464 4 * 1024 * 1024, /* 4 MB */
465 0xBFC00000);
466
467 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
468 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
469 0x80000000,
470 4 * 1024 * 1024, /* 4 MB */
471 0xA0000000);
472
473 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
474 for (i=0; i<8; i++) /* 32 MB total */
475 {
476 unsigned size = 4 * 1024 * 1024; /* 4 MB */
477 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
478 0x88000000 + (i * size),
479 size,
480 0xA8000000 + (i * size));
481 }
482 }
483 #if (WITH_HW)
484 else if (board != NULL
485 && (strcmp(board, BOARD_JMR3904) == 0 ||
486 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
487 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
488 {
489 /* match VIRTUAL memory layout of JMR-TX3904 board */
490 int i;
491
492 /* --- disable monitor unless forced on by user --- */
493
494 if (! firmware_option_p)
495 {
496 idt_monitor_base = 0;
497 pmon_monitor_base = 0;
498 lsipmon_monitor_base = 0;
499 }
500
501 /* --- environment --- */
502
503 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
504
505 /* --- memory --- */
506
507 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
508 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
509 0x9FC00000,
510 4 * 1024 * 1024, /* 4 MB */
511 0xBFC00000);
512
513 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
514 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
515 0x80000000,
516 4 * 1024 * 1024, /* 4 MB */
517 0xA0000000);
518
519 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
520 for (i=0; i<8; i++) /* 32 MB total */
521 {
522 unsigned size = 4 * 1024 * 1024; /* 4 MB */
523 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
524 0x88000000 + (i * size),
525 size,
526 0xA8000000 + (i * size));
527 }
528
529 /* Dummy memory regions for unsimulated devices - sorted by address */
530
531 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
532 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
533 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
534 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
535 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
536 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
537 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
538 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
539 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
540
541
542 /* --- simulated devices --- */
543 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
544 sim_hw_parse (sd, "/tx3904cpu");
545 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
546 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
547 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
548 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
549 {
550 /* FIXME: poking at dv-sockser internals, use tcp backend if
551 --sockser_addr option was given.*/
552 extern char* sockser_addr;
553 if(sockser_addr == NULL)
554 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
555 else
556 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
557 }
558 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
559 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
560
561 /* -- device connections --- */
562 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
563 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
564 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
565 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
566 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
567 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
568
569 /* add PAL timer & I/O module */
570 if(! strcmp(board, BOARD_JMR3904_PAL))
571 {
572 /* the device */
573 sim_hw_parse (sd, "/pal@0xffff0000");
574 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
575
576 /* wire up interrupt ports to irc */
577 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
578 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
579 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
580 }
581
582 if(! strcmp(board, BOARD_JMR3904_DEBUG))
583 {
584 /* -- DEBUG: glue interrupt generators --- */
585 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
586 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
587 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
588 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
589 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
590 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
591 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
592 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
593 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
594 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
595 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
596 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
597 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
598 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
599 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
600 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
601 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
602 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
603 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
604 }
605
606 device_init(sd);
607 }
608 #endif
609
610 if (display_mem_info)
611 {
612 struct option_list * ol;
613 struct option_list * prev;
614
615 /* This is a hack. We want to execute the real --memory-info command
616 line switch which is handled in common/sim-memopts.c, not the
617 override we have defined in this file. So we remove the
618 mips_options array from the state options list. This is safe
619 because we have now processed all of the command line. */
620 for (ol = STATE_OPTIONS (sd), prev = NULL;
621 ol != NULL;
622 prev = ol, ol = ol->next)
623 if (ol->options == mips_options)
624 break;
625
626 SIM_ASSERT (ol != NULL);
627
628 if (prev == NULL)
629 STATE_OPTIONS (sd) = ol->next;
630 else
631 prev->next = ol->next;
632
633 sim_do_commandf (sd, "memory-info");
634 }
635
636 /* check for/establish the a reference program image */
637 if (sim_analyze_program (sd,
638 (STATE_PROG_ARGV (sd) != NULL
639 ? *STATE_PROG_ARGV (sd)
640 : NULL),
641 abfd) != SIM_RC_OK)
642 {
643 sim_module_uninstall (sd);
644 return 0;
645 }
646
647 /* Configure/verify the target byte order and other runtime
648 configuration options */
649 if (sim_config (sd) != SIM_RC_OK)
650 {
651 sim_module_uninstall (sd);
652 return 0;
653 }
654
655 if (sim_post_argv_init (sd) != SIM_RC_OK)
656 {
657 /* Uninstall the modules to avoid memory leaks,
658 file descriptor leaks, etc. */
659 sim_module_uninstall (sd);
660 return 0;
661 }
662
663 /* verify assumptions the simulator made about the host type system.
664 This macro does not return if there is a problem */
665 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
666 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
667
668 /* This is NASTY, in that we are assuming the size of specific
669 registers: */
670 {
671 int rn;
672 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
673 {
674 if (rn < 32)
675 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
676 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
677 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
678 else if ((rn >= 33) && (rn <= 37))
679 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
680 else if ((rn == SRIDX)
681 || (rn == FCR0IDX)
682 || (rn == FCR31IDX)
683 || ((rn >= 72) && (rn <= 89)))
684 cpu->register_widths[rn] = 32;
685 else
686 cpu->register_widths[rn] = 0;
687 }
688
689
690 }
691
692 if (STATE & simTRACE)
693 open_trace(sd);
694
695 /*
696 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
697 idt_monitor_base,
698 pmon_monitor_base,
699 lsipmon_monitor_base);
700 */
701
702 /* Write the monitor trap address handlers into the monitor (eeprom)
703 address space. This can only be done once the target endianness
704 has been determined. */
705 if (idt_monitor_base != 0)
706 {
707 unsigned loop;
708 unsigned idt_monitor_size = 1 << 11;
709
710 /* the default monitor region */
711 sim_do_commandf (sd, "memory region 0x%x,0x%x",
712 idt_monitor_base, idt_monitor_size);
713
714 /* Entry into the IDT monitor is via fixed address vectors, and
715 not using machine instructions. To avoid clashing with use of
716 the MIPS TRAP system, we place our own (simulator specific)
717 "undefined" instructions into the relevant vector slots. */
718 for (loop = 0; (loop < idt_monitor_size); loop += 4)
719 {
720 address_word vaddr = (idt_monitor_base + loop);
721 unsigned32 insn = (RSVD_INSTRUCTION |
722 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
723 << RSVD_INSTRUCTION_ARG_SHIFT));
724 H2T (insn);
725 sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
726 }
727 }
728
729 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
730 {
731 /* The PMON monitor uses the same address space, but rather than
732 branching into it the address of a routine is loaded. We can
733 cheat for the moment, and direct the PMON routine to IDT style
734 instructions within the monitor space. This relies on the IDT
735 monitor not using the locations from 0xBFC00500 onwards as its
736 entry points.*/
737 unsigned loop;
738 for (loop = 0; (loop < 24); loop++)
739 {
740 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
741 switch (loop)
742 {
743 case 0: /* read */
744 value = 7;
745 break;
746 case 1: /* write */
747 value = 8;
748 break;
749 case 2: /* open */
750 value = 6;
751 break;
752 case 3: /* close */
753 value = 10;
754 break;
755 case 5: /* printf */
756 value = ((0x500 - 16) / 8); /* not an IDT reason code */
757 break;
758 case 8: /* cliexit */
759 value = 17;
760 break;
761 case 11: /* flush_cache */
762 value = 28;
763 break;
764 }
765
766 SIM_ASSERT (idt_monitor_base != 0);
767 value = ((unsigned int) idt_monitor_base + (value * 8));
768 H2T (value);
769
770 if (pmon_monitor_base != 0)
771 {
772 address_word vaddr = (pmon_monitor_base + (loop * 4));
773 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
774 }
775
776 if (lsipmon_monitor_base != 0)
777 {
778 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
779 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
780 }
781 }
782
783 /* Write an abort sequence into the TRAP (common) exception vector
784 addresses. This is to catch code executing a TRAP (et.al.)
785 instruction without installing a trap handler. */
786 if ((idt_monitor_base != 0) ||
787 (pmon_monitor_base != 0) ||
788 (lsipmon_monitor_base != 0))
789 {
790 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
791 HALT_INSTRUCTION /* BREAK */ };
792 H2T (halt[0]);
793 H2T (halt[1]);
794 sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
795 sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
796 sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
797 /* XXX: Write here unconditionally? */
798 sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
799 sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
800 sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
801 }
802 }
803
804 /* CPU specific initialization. */
805 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
806 {
807 SIM_CPU *cpu = STATE_CPU (sd, i);
808
809 CPU_PC_FETCH (cpu) = mips_pc_get;
810 CPU_PC_STORE (cpu) = mips_pc_set;
811 }
812
813 return sd;
814 }
815
816 #if WITH_TRACE_ANY_P
817 static void
818 open_trace (SIM_DESC sd)
819 {
820 tracefh = fopen(tracefile,"wb+");
821 if (tracefh == NULL)
822 {
823 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
824 tracefh = stderr;
825 }
826 }
827 #endif
828
829 /* Return name of an insn, used by insn profiling. */
830 static const char *
831 get_insn_name (sim_cpu *cpu, int i)
832 {
833 return itable[i].name;
834 }
835
836 void
837 mips_sim_close (SIM_DESC sd, int quitting)
838 {
839 #if WITH_TRACE_ANY_P
840 if (tracefh != NULL && tracefh != stderr)
841 fclose(tracefh);
842 tracefh = NULL;
843 #endif
844 }
845
846 int
847 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
848 {
849 int index;
850 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
851
852 /* Return the number of bytes written, or zero if error. */
853 #ifdef DEBUG
854 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
855 #endif
856
857 /* We use raw read and write routines, since we do not want to count
858 the GDB memory accesses in our statistics gathering. */
859
860 for (index = 0; index < size; index++)
861 {
862 address_word vaddr = (address_word)addr + index;
863 address_word paddr;
864 int cca;
865 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
866 break;
867 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
868 break;
869 }
870
871 return(index);
872 }
873
874 int
875 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
876 {
877 int index;
878 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
879
880 /* Return the number of bytes read, or zero if error. */
881 #ifdef DEBUG
882 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
883 #endif /* DEBUG */
884
885 for (index = 0; (index < size); index++)
886 {
887 address_word vaddr = (address_word)addr + index;
888 address_word paddr;
889 int cca;
890 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
891 break;
892 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
893 break;
894 }
895
896 return(index);
897 }
898
899 int
900 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
901 {
902 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
903 /* NOTE: gdb (the client) stores registers in target byte order
904 while the simulator uses host byte order */
905 #ifdef DEBUG
906 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
907 #endif /* DEBUG */
908
909 /* Unfortunately this suffers from the same problem as the register
910 numbering one. We need to know what the width of each logical
911 register number is for the architecture being simulated. */
912
913 if (cpu->register_widths[rn] == 0)
914 {
915 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
916 return 0;
917 }
918
919
920
921 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
922 {
923 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
924 if (cpu->register_widths[rn] == 32)
925 {
926 if (length == 8)
927 {
928 cpu->fgr[rn - FGR_BASE] =
929 (unsigned32) T2H_8 (*(unsigned64*)memory);
930 return 8;
931 }
932 else
933 {
934 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
935 return 4;
936 }
937 }
938 else
939 {
940 if (length == 8)
941 {
942 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
943 return 8;
944 }
945 else
946 {
947 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
948 return 4;
949 }
950 }
951 }
952
953 if (cpu->register_widths[rn] == 32)
954 {
955 if (length == 8)
956 {
957 cpu->registers[rn] =
958 (unsigned32) T2H_8 (*(unsigned64*)memory);
959 return 8;
960 }
961 else
962 {
963 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
964 return 4;
965 }
966 }
967 else
968 {
969 if (length == 8)
970 {
971 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
972 return 8;
973 }
974 else
975 {
976 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
977 return 4;
978 }
979 }
980
981 return 0;
982 }
983
984 int
985 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
986 {
987 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
988 /* NOTE: gdb (the client) stores registers in target byte order
989 while the simulator uses host byte order */
990 #ifdef DEBUG
991 #if 0 /* FIXME: doesn't compile */
992 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
993 #endif
994 #endif /* DEBUG */
995
996 if (cpu->register_widths[rn] == 0)
997 {
998 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
999 return 0;
1000 }
1001
1002
1003
1004 /* Any floating point register */
1005 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
1006 {
1007 if (cpu->register_widths[rn] == 32)
1008 {
1009 if (length == 8)
1010 {
1011 *(unsigned64*)memory =
1012 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
1013 return 8;
1014 }
1015 else
1016 {
1017 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
1018 return 4;
1019 }
1020 }
1021 else
1022 {
1023 if (length == 8)
1024 {
1025 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
1026 return 8;
1027 }
1028 else
1029 {
1030 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
1031 return 4;
1032 }
1033 }
1034 }
1035
1036 if (cpu->register_widths[rn] == 32)
1037 {
1038 if (length == 8)
1039 {
1040 *(unsigned64*)memory =
1041 H2T_8 ((unsigned32) (cpu->registers[rn]));
1042 return 8;
1043 }
1044 else
1045 {
1046 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1047 return 4;
1048 }
1049 }
1050 else
1051 {
1052 if (length == 8)
1053 {
1054 *(unsigned64*)memory =
1055 H2T_8 ((unsigned64) (cpu->registers[rn]));
1056 return 8;
1057 }
1058 else
1059 {
1060 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1061 return 4;
1062 }
1063 }
1064
1065 return 0;
1066 }
1067
1068 SIM_RC
1069 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1070 {
1071
1072 #ifdef DEBUG
1073 #if 0 /* FIXME: doesn't compile */
1074 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1075 pr_addr(PC));
1076 #endif
1077 #endif /* DEBUG */
1078
1079 ColdReset(sd);
1080
1081 if (abfd != NULL)
1082 {
1083 /* override PC value set by ColdReset () */
1084 int cpu_nr;
1085 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1086 {
1087 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1088 CPU_PC_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1089 }
1090 }
1091
1092 #if 0 /* def DEBUG */
1093 if (argv || env)
1094 {
1095 /* We should really place the argv slot values into the argument
1096 registers, and onto the stack as required. However, this
1097 assumes that we have a stack defined, which is not
1098 necessarily true at the moment. */
1099 char **cptr;
1100 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1101 for (cptr = argv; (cptr && *cptr); cptr++)
1102 printf("DBG: arg \"%s\"\n",*cptr);
1103 }
1104 #endif /* DEBUG */
1105
1106 return SIM_RC_OK;
1107 }
1108
1109 /*---------------------------------------------------------------------------*/
1110 /*-- Private simulator support interface ------------------------------------*/
1111 /*---------------------------------------------------------------------------*/
1112
1113 /* Read a null terminated string from memory, return in a buffer */
1114 static char *
1115 fetch_str (SIM_DESC sd,
1116 address_word addr)
1117 {
1118 char *buf;
1119 int nr = 0;
1120 unsigned char null;
1121 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1122 nr++;
1123 buf = NZALLOC (char, nr + 1);
1124 sim_read (sd, addr, (unsigned char *)buf, nr);
1125 return buf;
1126 }
1127
1128
1129 /* Implements the "sim firmware" command:
1130 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1131 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1132 defaults to the normal address for that monitor.
1133 sim firmware none --- don't emulate any ROM monitor. Useful
1134 if you need a clean address space. */
1135 static SIM_RC
1136 sim_firmware_command (SIM_DESC sd, char *arg)
1137 {
1138 int address_present = 0;
1139 SIM_ADDR address;
1140
1141 /* Signal occurrence of this option. */
1142 firmware_option_p = 1;
1143
1144 /* Parse out the address, if present. */
1145 {
1146 char *p = strchr (arg, '@');
1147 if (p)
1148 {
1149 char *q;
1150 address_present = 1;
1151 p ++; /* skip over @ */
1152
1153 address = strtoul (p, &q, 0);
1154 if (*q != '\0')
1155 {
1156 sim_io_printf (sd, "Invalid address given to the"
1157 "`sim firmware NAME@ADDRESS' command: %s\n",
1158 p);
1159 return SIM_RC_FAIL;
1160 }
1161 }
1162 else
1163 {
1164 address_present = 0;
1165 address = -1; /* Dummy value. */
1166 }
1167 }
1168
1169 if (! strncmp (arg, "idt", 3))
1170 {
1171 idt_monitor_base = address_present ? address : 0xBFC00000;
1172 pmon_monitor_base = 0;
1173 lsipmon_monitor_base = 0;
1174 }
1175 else if (! strncmp (arg, "pmon", 4))
1176 {
1177 /* pmon uses indirect calls. Hook into implied idt. */
1178 pmon_monitor_base = address_present ? address : 0xBFC00500;
1179 idt_monitor_base = pmon_monitor_base - 0x500;
1180 lsipmon_monitor_base = 0;
1181 }
1182 else if (! strncmp (arg, "lsipmon", 7))
1183 {
1184 /* lsipmon uses indirect calls. Hook into implied idt. */
1185 pmon_monitor_base = 0;
1186 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1187 idt_monitor_base = lsipmon_monitor_base - 0x200;
1188 }
1189 else if (! strncmp (arg, "none", 4))
1190 {
1191 if (address_present)
1192 {
1193 sim_io_printf (sd,
1194 "The `sim firmware none' command does "
1195 "not take an `ADDRESS' argument.\n");
1196 return SIM_RC_FAIL;
1197 }
1198 idt_monitor_base = 0;
1199 pmon_monitor_base = 0;
1200 lsipmon_monitor_base = 0;
1201 }
1202 else
1203 {
1204 sim_io_printf (sd, "\
1205 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1206 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1207 arg);
1208 return SIM_RC_FAIL;
1209 }
1210
1211 return SIM_RC_OK;
1212 }
1213
1214
1215
1216 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1217 int
1218 sim_monitor (SIM_DESC sd,
1219 sim_cpu *cpu,
1220 address_word cia,
1221 unsigned int reason)
1222 {
1223 #ifdef DEBUG
1224 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1225 #endif /* DEBUG */
1226
1227 /* The IDT monitor actually allows two instructions per vector
1228 slot. However, the simulator currently causes a trap on each
1229 individual instruction. We cheat, and lose the bottom bit. */
1230 reason >>= 1;
1231
1232 /* The following callback functions are available, however the
1233 monitor we are simulating does not make use of them: get_errno,
1234 isatty, lseek, rename, system, time and unlink */
1235 switch (reason)
1236 {
1237
1238 case 6: /* int open(char *path,int flags) */
1239 {
1240 char *path = fetch_str (sd, A0);
1241 V0 = sim_io_open (sd, path, (int)A1);
1242 free (path);
1243 break;
1244 }
1245
1246 case 7: /* int read(int file,char *ptr,int len) */
1247 {
1248 int fd = A0;
1249 int nr = A2;
1250 char *buf = zalloc (nr);
1251 V0 = sim_io_read (sd, fd, buf, nr);
1252 sim_write (sd, A1, (unsigned char *)buf, nr);
1253 free (buf);
1254 }
1255 break;
1256
1257 case 8: /* int write(int file,char *ptr,int len) */
1258 {
1259 int fd = A0;
1260 int nr = A2;
1261 char *buf = zalloc (nr);
1262 sim_read (sd, A1, (unsigned char *)buf, nr);
1263 V0 = sim_io_write (sd, fd, buf, nr);
1264 if (fd == 1)
1265 sim_io_flush_stdout (sd);
1266 else if (fd == 2)
1267 sim_io_flush_stderr (sd);
1268 free (buf);
1269 break;
1270 }
1271
1272 case 10: /* int close(int file) */
1273 {
1274 V0 = sim_io_close (sd, (int)A0);
1275 break;
1276 }
1277
1278 case 2: /* Densan monitor: char inbyte(int waitflag) */
1279 {
1280 if (A0 == 0) /* waitflag == NOWAIT */
1281 V0 = (unsigned_word)-1;
1282 }
1283 /* Drop through to case 11 */
1284
1285 case 11: /* char inbyte(void) */
1286 {
1287 char tmp;
1288 /* ensure that all output has gone... */
1289 sim_io_flush_stdout (sd);
1290 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1291 {
1292 sim_io_error(sd,"Invalid return from character read");
1293 V0 = (unsigned_word)-1;
1294 }
1295 else
1296 V0 = (unsigned_word)tmp;
1297 break;
1298 }
1299
1300 case 3: /* Densan monitor: void co(char chr) */
1301 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1302 {
1303 char tmp = (char)(A0 & 0xFF);
1304 sim_io_write_stdout (sd, &tmp, sizeof(char));
1305 break;
1306 }
1307
1308 case 17: /* void _exit() */
1309 {
1310 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1311 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1312 (unsigned int)(A0 & 0xFFFFFFFF));
1313 break;
1314 }
1315
1316 case 28: /* PMON flush_cache */
1317 break;
1318
1319 case 55: /* void get_mem_info(unsigned int *ptr) */
1320 /* in: A0 = pointer to three word memory location */
1321 /* out: [A0 + 0] = size */
1322 /* [A0 + 4] = instruction cache size */
1323 /* [A0 + 8] = data cache size */
1324 {
1325 unsigned_4 value;
1326 unsigned_4 zero = 0;
1327 address_word mem_size;
1328 sim_memopt *entry, *match = NULL;
1329
1330 /* Search for memory region mapped to KSEG0 or KSEG1. */
1331 for (entry = STATE_MEMOPT (sd);
1332 entry != NULL;
1333 entry = entry->next)
1334 {
1335 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1336 && (!match || entry->level < match->level))
1337 match = entry;
1338 else
1339 {
1340 sim_memopt *alias;
1341 for (alias = entry->alias;
1342 alias != NULL;
1343 alias = alias->next)
1344 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1345 && (!match || entry->level < match->level))
1346 match = entry;
1347 }
1348 }
1349
1350 /* Get region size, limit to KSEG1 size (512MB). */
1351 SIM_ASSERT (match != NULL);
1352 mem_size = (match->modulo != 0
1353 ? match->modulo : match->nr_bytes);
1354 if (mem_size > K1SIZE)
1355 mem_size = K1SIZE;
1356
1357 value = mem_size;
1358 H2T (value);
1359 sim_write (sd, A0 + 0, (unsigned char *)&value, 4);
1360 sim_write (sd, A0 + 4, (unsigned char *)&zero, 4);
1361 sim_write (sd, A0 + 8, (unsigned char *)&zero, 4);
1362 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1363 break;
1364 }
1365
1366 case 158: /* PMON printf */
1367 /* in: A0 = pointer to format string */
1368 /* A1 = optional argument 1 */
1369 /* A2 = optional argument 2 */
1370 /* A3 = optional argument 3 */
1371 /* out: void */
1372 /* The following is based on the PMON printf source */
1373 {
1374 address_word s = A0;
1375 unsigned char c;
1376 signed_word *ap = &A1; /* 1st argument */
1377 /* This isn't the quickest way, since we call the host print
1378 routine for every character almost. But it does avoid
1379 having to allocate and manage a temporary string buffer. */
1380 /* TODO: Include check that we only use three arguments (A1,
1381 A2 and A3) */
1382 while (sim_read (sd, s++, &c, 1) && c != '\0')
1383 {
1384 if (c == '%')
1385 {
1386 char tmp[40];
1387 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1388 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1389 while (sim_read (sd, s++, &c, 1) && c != '\0')
1390 {
1391 if (strchr ("dobxXulscefg%", c))
1392 break;
1393 else if (c == '-')
1394 fmt = FMT_LJUST;
1395 else if (c == '0')
1396 fmt = FMT_RJUST0;
1397 else if (c == '~')
1398 fmt = FMT_CENTER;
1399 else if (c == '*')
1400 {
1401 if (haddot)
1402 trunc = (int)*ap++;
1403 else
1404 width = (int)*ap++;
1405 }
1406 else if (c >= '1' && c <= '9')
1407 {
1408 address_word t = s;
1409 unsigned int n;
1410 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1411 tmp[s - t] = c;
1412 tmp[s - t] = '\0';
1413 n = (unsigned int)strtol(tmp,NULL,10);
1414 if (haddot)
1415 trunc = n;
1416 else
1417 width = n;
1418 s--;
1419 }
1420 else if (c == '.')
1421 haddot = 1;
1422 }
1423 switch (c)
1424 {
1425 case '%':
1426 sim_io_printf (sd, "%%");
1427 break;
1428 case 's':
1429 if ((int)*ap != 0)
1430 {
1431 address_word p = *ap++;
1432 unsigned char ch;
1433 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1434 sim_io_printf(sd, "%c", ch);
1435 }
1436 else
1437 sim_io_printf(sd,"(null)");
1438 break;
1439 case 'c':
1440 sim_io_printf (sd, "%c", (int)*ap++);
1441 break;
1442 default:
1443 if (c == 'l')
1444 {
1445 sim_read (sd, s++, &c, 1);
1446 if (c == 'l')
1447 {
1448 longlong = 1;
1449 sim_read (sd, s++, &c, 1);
1450 }
1451 }
1452 if (strchr ("dobxXu", c))
1453 {
1454 word64 lv = (word64) *ap++;
1455 if (c == 'b')
1456 sim_io_printf(sd,"<binary not supported>");
1457 else
1458 {
1459 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1460 if (longlong)
1461 sim_io_printf(sd, tmp, lv);
1462 else
1463 sim_io_printf(sd, tmp, (int)lv);
1464 }
1465 }
1466 else if (strchr ("eEfgG", c))
1467 {
1468 double dbl = *(double*)(ap++);
1469 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1470 sim_io_printf (sd, tmp, dbl);
1471 trunc = 0;
1472 }
1473 }
1474 }
1475 else
1476 sim_io_printf(sd, "%c", c);
1477 }
1478 break;
1479 }
1480
1481 default:
1482 /* Unknown reason. */
1483 return 0;
1484 }
1485 return 1;
1486 }
1487
1488 /* Store a word into memory. */
1489
1490 static void
1491 store_word (SIM_DESC sd,
1492 sim_cpu *cpu,
1493 address_word cia,
1494 uword64 vaddr,
1495 signed_word val)
1496 {
1497 address_word paddr;
1498 int uncached;
1499
1500 if ((vaddr & 3) != 0)
1501 SignalExceptionAddressStore ();
1502 else
1503 {
1504 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1505 isTARGET, isREAL))
1506 {
1507 const uword64 mask = 7;
1508 uword64 memval;
1509 unsigned int byte;
1510
1511 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1512 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1513 memval = ((uword64) val) << (8 * byte);
1514 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1515 isREAL);
1516 }
1517 }
1518 }
1519
1520 /* Load a word from memory. */
1521
1522 static signed_word
1523 load_word (SIM_DESC sd,
1524 sim_cpu *cpu,
1525 address_word cia,
1526 uword64 vaddr)
1527 {
1528 if ((vaddr & 3) != 0)
1529 {
1530 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1531 }
1532 else
1533 {
1534 address_word paddr;
1535 int uncached;
1536
1537 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1538 isTARGET, isREAL))
1539 {
1540 const uword64 mask = 0x7;
1541 const unsigned int reverse = ReverseEndian ? 1 : 0;
1542 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1543 uword64 memval;
1544 unsigned int byte;
1545
1546 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1547 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1548 isDATA, isREAL);
1549 byte = (vaddr & mask) ^ (bigend << 2);
1550 return EXTEND32 (memval >> (8 * byte));
1551 }
1552 }
1553
1554 return 0;
1555 }
1556
1557 /* Simulate the mips16 entry and exit pseudo-instructions. These
1558 would normally be handled by the reserved instruction exception
1559 code, but for ease of simulation we just handle them directly. */
1560
1561 static void
1562 mips16_entry (SIM_DESC sd,
1563 sim_cpu *cpu,
1564 address_word cia,
1565 unsigned int insn)
1566 {
1567 int aregs, sregs, rreg;
1568
1569 #ifdef DEBUG
1570 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1571 #endif /* DEBUG */
1572
1573 aregs = (insn & 0x700) >> 8;
1574 sregs = (insn & 0x0c0) >> 6;
1575 rreg = (insn & 0x020) >> 5;
1576
1577 /* This should be checked by the caller. */
1578 if (sregs == 3)
1579 abort ();
1580
1581 if (aregs < 5)
1582 {
1583 int i;
1584 signed_word tsp;
1585
1586 /* This is the entry pseudo-instruction. */
1587
1588 for (i = 0; i < aregs; i++)
1589 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1590
1591 tsp = SP;
1592 SP -= 32;
1593
1594 if (rreg)
1595 {
1596 tsp -= 4;
1597 store_word (SD, CPU, cia, (uword64) tsp, RA);
1598 }
1599
1600 for (i = 0; i < sregs; i++)
1601 {
1602 tsp -= 4;
1603 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1604 }
1605 }
1606 else
1607 {
1608 int i;
1609 signed_word tsp;
1610
1611 /* This is the exit pseudo-instruction. */
1612
1613 tsp = SP + 32;
1614
1615 if (rreg)
1616 {
1617 tsp -= 4;
1618 RA = load_word (SD, CPU, cia, (uword64) tsp);
1619 }
1620
1621 for (i = 0; i < sregs; i++)
1622 {
1623 tsp -= 4;
1624 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1625 }
1626
1627 SP += 32;
1628
1629 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1630 {
1631 if (aregs == 5)
1632 {
1633 FGR[0] = WORD64LO (GPR[4]);
1634 FPR_STATE[0] = fmt_uninterpreted;
1635 }
1636 else if (aregs == 6)
1637 {
1638 FGR[0] = WORD64LO (GPR[5]);
1639 FGR[1] = WORD64LO (GPR[4]);
1640 FPR_STATE[0] = fmt_uninterpreted;
1641 FPR_STATE[1] = fmt_uninterpreted;
1642 }
1643 }
1644
1645 PC = RA;
1646 }
1647
1648 }
1649
1650 /*-- trace support ----------------------------------------------------------*/
1651
1652 /* The trace support is provided (if required) in the memory accessing
1653 routines. Since we are also providing the architecture specific
1654 features, the architecture simulation code can also deal with
1655 notifying the trace world of cache flushes, etc. Similarly we do
1656 not need to provide profiling support in the simulator engine,
1657 since we can sample in the instruction fetch control loop. By
1658 defining the trace manifest, we add tracing as a run-time
1659 option. */
1660
1661 #if WITH_TRACE_ANY_P
1662 /* Tracing by default produces "din" format (as required by
1663 dineroIII). Each line of such a trace file *MUST* have a din label
1664 and address field. The rest of the line is ignored, so comments can
1665 be included if desired. The first field is the label which must be
1666 one of the following values:
1667
1668 0 read data
1669 1 write data
1670 2 instruction fetch
1671 3 escape record (treated as unknown access type)
1672 4 escape record (causes cache flush)
1673
1674 The address field is a 32bit (lower-case) hexadecimal address
1675 value. The address should *NOT* be preceded by "0x".
1676
1677 The size of the memory transfer is not important when dealing with
1678 cache lines (as long as no more than a cache line can be
1679 transferred in a single operation :-), however more information
1680 could be given following the dineroIII requirement to allow more
1681 complete memory and cache simulators to provide better
1682 results. i.e. the University of Pisa has a cache simulator that can
1683 also take bus size and speed as (variable) inputs to calculate
1684 complete system performance (a much more useful ability when trying
1685 to construct an end product, rather than a processor). They
1686 currently have an ARM version of their tool called ChARM. */
1687
1688
1689 void
1690 dotrace (SIM_DESC sd,
1691 sim_cpu *cpu,
1692 FILE *tracefh,
1693 int type,
1694 SIM_ADDR address,
1695 int width,
1696 char *comment,...)
1697 {
1698 if (STATE & simTRACE) {
1699 va_list ap;
1700 fprintf(tracefh,"%d %s ; width %d ; ",
1701 type,
1702 pr_addr(address),
1703 width);
1704 va_start(ap,comment);
1705 vfprintf(tracefh,comment,ap);
1706 va_end(ap);
1707 fprintf(tracefh,"\n");
1708 }
1709 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1710 we may be generating 64bit ones, we should put the hi-32bits of the
1711 address into the comment field. */
1712
1713 /* TODO: Provide a buffer for the trace lines. We can then avoid
1714 performing writes until the buffer is filled, or the file is
1715 being closed. */
1716
1717 /* NOTE: We could consider adding a comment field to the "din" file
1718 produced using type 3 markers (unknown access). This would then
1719 allow information about the program that the "din" is for, and
1720 the MIPs world that was being simulated, to be placed into the
1721 trace file. */
1722
1723 return;
1724 }
1725 #endif /* WITH_TRACE_ANY_P */
1726
1727 /*---------------------------------------------------------------------------*/
1728 /*-- simulator engine -------------------------------------------------------*/
1729 /*---------------------------------------------------------------------------*/
1730
1731 static void
1732 ColdReset (SIM_DESC sd)
1733 {
1734 int cpu_nr;
1735 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1736 {
1737 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1738 /* RESET: Fixed PC address: */
1739 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1740 /* The reset vector address is in the unmapped, uncached memory space. */
1741
1742 SR &= ~(status_SR | status_TS | status_RP);
1743 SR |= (status_ERL | status_BEV);
1744
1745 /* Cheat and allow access to the complete register set immediately */
1746 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1747 && WITH_TARGET_WORD_BITSIZE == 64)
1748 SR |= status_FR; /* 64bit registers */
1749
1750 /* Ensure that any instructions with pending register updates are
1751 cleared: */
1752 PENDING_INVALIDATE();
1753
1754 /* Initialise the FPU registers to the unknown state */
1755 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1756 {
1757 int rn;
1758 for (rn = 0; (rn < 32); rn++)
1759 FPR_STATE[rn] = fmt_uninterpreted;
1760 }
1761
1762 /* Initialise the Config0 register. */
1763 C0_CONFIG = 0x80000000 /* Config1 present */
1764 | 2; /* KSEG0 uncached */
1765 if (WITH_TARGET_WORD_BITSIZE == 64)
1766 {
1767 /* FIXME Currently mips/sim-main.c:address_translation()
1768 truncates all addresses to 32-bits. */
1769 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1770 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1771 else
1772 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1773 }
1774 if (BigEndianMem)
1775 C0_CONFIG |= 0x00008000; /* Big Endian */
1776 }
1777 }
1778
1779
1780
1781
1782 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1783 /* Signal an exception condition. This will result in an exception
1784 that aborts the instruction. The instruction operation pseudocode
1785 will never see a return from this function call. */
1786
1787 void
1788 signal_exception (SIM_DESC sd,
1789 sim_cpu *cpu,
1790 address_word cia,
1791 int exception,...)
1792 {
1793 /* int vector; */
1794
1795 #ifdef DEBUG
1796 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1797 #endif /* DEBUG */
1798
1799 /* Ensure that any active atomic read/modify/write operation will fail: */
1800 LLBIT = 0;
1801
1802 /* Save registers before interrupt dispatching */
1803 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1804 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1805 #endif
1806
1807 switch (exception) {
1808
1809 case DebugBreakPoint:
1810 if (! (Debug & Debug_DM))
1811 {
1812 if (INDELAYSLOT())
1813 {
1814 CANCELDELAYSLOT();
1815
1816 Debug |= Debug_DBD; /* signaled from within in delay slot */
1817 DEPC = cia - 4; /* reference the branch instruction */
1818 }
1819 else
1820 {
1821 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1822 DEPC = cia;
1823 }
1824
1825 Debug |= Debug_DM; /* in debugging mode */
1826 Debug |= Debug_DBp; /* raising a DBp exception */
1827 PC = 0xBFC00200;
1828 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1829 }
1830 break;
1831
1832 case ReservedInstruction:
1833 {
1834 va_list ap;
1835 unsigned int instruction;
1836 va_start(ap,exception);
1837 instruction = va_arg(ap,unsigned int);
1838 va_end(ap);
1839 /* Provide simple monitor support using ReservedInstruction
1840 exceptions. The following code simulates the fixed vector
1841 entry points into the IDT monitor by causing a simulator
1842 trap, performing the monitor operation, and returning to
1843 the address held in the $ra register (standard PCS return
1844 address). This means we only need to pre-load the vector
1845 space with suitable instruction values. For systems were
1846 actual trap instructions are used, we would not need to
1847 perform this magic. */
1848 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1849 {
1850 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1851 if (!sim_monitor (SD, CPU, cia, reason))
1852 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1853
1854 /* NOTE: This assumes that a branch-and-link style
1855 instruction was used to enter the vector (which is the
1856 case with the current IDT monitor). */
1857 sim_engine_restart (SD, CPU, NULL, RA);
1858 }
1859 /* Look for the mips16 entry and exit instructions, and
1860 simulate a handler for them. */
1861 else if ((cia & 1) != 0
1862 && (instruction & 0xf81f) == 0xe809
1863 && (instruction & 0x0c0) != 0x0c0)
1864 {
1865 mips16_entry (SD, CPU, cia, instruction);
1866 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1867 }
1868 /* else fall through to normal exception processing */
1869 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1870 }
1871
1872 default:
1873 /* Store exception code into current exception id variable (used
1874 by exit code): */
1875
1876 /* TODO: If not simulating exceptions then stop the simulator
1877 execution. At the moment we always stop the simulation. */
1878
1879 #ifdef SUBTARGET_R3900
1880 /* update interrupt-related registers */
1881
1882 /* insert exception code in bits 6:2 */
1883 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1884 /* shift IE/KU history bits left */
1885 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1886
1887 if (STATE & simDELAYSLOT)
1888 {
1889 STATE &= ~simDELAYSLOT;
1890 CAUSE |= cause_BD;
1891 EPC = (cia - 4); /* reference the branch instruction */
1892 }
1893 else
1894 EPC = cia;
1895
1896 if (SR & status_BEV)
1897 PC = (signed)0xBFC00000 + 0x180;
1898 else
1899 PC = (signed)0x80000000 + 0x080;
1900 #else
1901 /* See figure 5-17 for an outline of the code below */
1902 if (! (SR & status_EXL))
1903 {
1904 CAUSE = (exception << 2);
1905 if (STATE & simDELAYSLOT)
1906 {
1907 STATE &= ~simDELAYSLOT;
1908 CAUSE |= cause_BD;
1909 EPC = (cia - 4); /* reference the branch instruction */
1910 }
1911 else
1912 EPC = cia;
1913 /* FIXME: TLB et.al. */
1914 /* vector = 0x180; */
1915 }
1916 else
1917 {
1918 CAUSE = (exception << 2);
1919 /* vector = 0x180; */
1920 }
1921 SR |= status_EXL;
1922 /* Store exception code into current exception id variable (used
1923 by exit code): */
1924
1925 if (SR & status_BEV)
1926 PC = (signed)0xBFC00200 + 0x180;
1927 else
1928 PC = (signed)0x80000000 + 0x180;
1929 #endif
1930
1931 switch ((CAUSE >> 2) & 0x1F)
1932 {
1933 case Interrupt:
1934 /* Interrupts arrive during event processing, no need to
1935 restart */
1936 return;
1937
1938 case NMIReset:
1939 /* Ditto */
1940 #ifdef SUBTARGET_3900
1941 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1942 PC = (signed)0xBFC00000;
1943 #endif /* SUBTARGET_3900 */
1944 return;
1945
1946 case TLBModification:
1947 case TLBLoad:
1948 case TLBStore:
1949 case AddressLoad:
1950 case AddressStore:
1951 case InstructionFetch:
1952 case DataReference:
1953 /* The following is so that the simulator will continue from the
1954 exception handler address. */
1955 sim_engine_halt (SD, CPU, NULL, PC,
1956 sim_stopped, SIM_SIGBUS);
1957
1958 case ReservedInstruction:
1959 case CoProcessorUnusable:
1960 PC = EPC;
1961 sim_engine_halt (SD, CPU, NULL, PC,
1962 sim_stopped, SIM_SIGILL);
1963
1964 case IntegerOverflow:
1965 case FPE:
1966 sim_engine_halt (SD, CPU, NULL, PC,
1967 sim_stopped, SIM_SIGFPE);
1968
1969 case BreakPoint:
1970 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1971 break;
1972
1973 case SystemCall:
1974 case Trap:
1975 sim_engine_restart (SD, CPU, NULL, PC);
1976 break;
1977
1978 case Watch:
1979 PC = EPC;
1980 sim_engine_halt (SD, CPU, NULL, PC,
1981 sim_stopped, SIM_SIGTRAP);
1982
1983 default: /* Unknown internal exception */
1984 PC = EPC;
1985 sim_engine_halt (SD, CPU, NULL, PC,
1986 sim_stopped, SIM_SIGABRT);
1987
1988 }
1989
1990 case SimulatorFault:
1991 {
1992 va_list ap;
1993 char *msg;
1994 va_start(ap,exception);
1995 msg = va_arg(ap,char *);
1996 va_end(ap);
1997 sim_engine_abort (SD, CPU, NULL_CIA,
1998 "FATAL: Simulator error \"%s\"\n",msg);
1999 }
2000 }
2001
2002 return;
2003 }
2004
2005
2006
2007 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2008 "UNPREDICTABLE" behaviour.
2009
2010 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2011 may vary from processor implementation to processor implementation,
2012 instruction to instruction, or as a function of time on the same
2013 implementation or instruction. Software can never depend on results
2014 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2015 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2016 0.95, page 2.)
2017
2018 For UNPREDICTABLE behaviour, we print a message, if possible print
2019 the offending instructions mips.igen instruction name (provided by
2020 the caller), and stop the simulator.
2021
2022 XXX FIXME: eventually, stopping the simulator should be made conditional
2023 on a command-line option. */
2024 void
2025 unpredictable_action(sim_cpu *cpu, address_word cia)
2026 {
2027 SIM_DESC sd = CPU_STATE(cpu);
2028
2029 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
2030 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
2031 }
2032
2033
2034 /*-- co-processor support routines ------------------------------------------*/
2035
2036 static int UNUSED
2037 CoProcPresent(unsigned int coproc_number)
2038 {
2039 /* Return TRUE if simulator provides a model for the given co-processor number */
2040 return(0);
2041 }
2042
2043 void
2044 cop_lw (SIM_DESC sd,
2045 sim_cpu *cpu,
2046 address_word cia,
2047 int coproc_num,
2048 int coproc_reg,
2049 unsigned int memword)
2050 {
2051 switch (coproc_num)
2052 {
2053 case 1:
2054 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2055 {
2056 #ifdef DEBUG
2057 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2058 #endif
2059 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
2060 break;
2061 }
2062
2063 default:
2064 #if 0 /* this should be controlled by a configuration option */
2065 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2066 #endif
2067 break;
2068 }
2069
2070 return;
2071 }
2072
2073 void
2074 cop_ld (SIM_DESC sd,
2075 sim_cpu *cpu,
2076 address_word cia,
2077 int coproc_num,
2078 int coproc_reg,
2079 uword64 memword)
2080 {
2081
2082 #ifdef DEBUG
2083 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2084 #endif
2085
2086 switch (coproc_num) {
2087 case 1:
2088 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2089 {
2090 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
2091 break;
2092 }
2093
2094 default:
2095 #if 0 /* this message should be controlled by a configuration option */
2096 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2097 #endif
2098 break;
2099 }
2100
2101 return;
2102 }
2103
2104
2105
2106
2107 unsigned int
2108 cop_sw (SIM_DESC sd,
2109 sim_cpu *cpu,
2110 address_word cia,
2111 int coproc_num,
2112 int coproc_reg)
2113 {
2114 unsigned int value = 0;
2115
2116 switch (coproc_num)
2117 {
2118 case 1:
2119 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2120 {
2121 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
2122 break;
2123 }
2124
2125 default:
2126 #if 0 /* should be controlled by configuration option */
2127 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2128 #endif
2129 break;
2130 }
2131
2132 return(value);
2133 }
2134
2135 uword64
2136 cop_sd (SIM_DESC sd,
2137 sim_cpu *cpu,
2138 address_word cia,
2139 int coproc_num,
2140 int coproc_reg)
2141 {
2142 uword64 value = 0;
2143 switch (coproc_num)
2144 {
2145 case 1:
2146 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2147 {
2148 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
2149 break;
2150 }
2151
2152 default:
2153 #if 0 /* should be controlled by configuration option */
2154 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2155 #endif
2156 break;
2157 }
2158
2159 return(value);
2160 }
2161
2162
2163
2164
2165 void
2166 decode_coproc (SIM_DESC sd,
2167 sim_cpu *cpu,
2168 address_word cia,
2169 unsigned int instruction,
2170 int coprocnum,
2171 CP0_operation op,
2172 int rt,
2173 int rd,
2174 int sel)
2175 {
2176 switch (coprocnum)
2177 {
2178 case 0: /* standard CPU control and cache registers */
2179 {
2180 /* R4000 Users Manual (second edition) lists the following CP0
2181 instructions:
2182 CODE><-RT><RD-><--TAIL--->
2183 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2184 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2185 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2186 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2187 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2188 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2189 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2190 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2191 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2192 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2193 */
2194 if (((op == cp0_mfc0) || (op == cp0_mtc0) /* MFC0 / MTC0 */
2195 || (op == cp0_dmfc0) || (op == cp0_dmtc0)) /* DMFC0 / DMTC0 */
2196 && sel == 0)
2197 {
2198 switch (rd) /* NOTEs: Standard CP0 registers */
2199 {
2200 /* 0 = Index R4000 VR4100 VR4300 */
2201 /* 1 = Random R4000 VR4100 VR4300 */
2202 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2203 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2204 /* 4 = Context R4000 VR4100 VR4300 */
2205 /* 5 = PageMask R4000 VR4100 VR4300 */
2206 /* 6 = Wired R4000 VR4100 VR4300 */
2207 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2208 /* 9 = Count R4000 VR4100 VR4300 */
2209 /* 10 = EntryHi R4000 VR4100 VR4300 */
2210 /* 11 = Compare R4000 VR4100 VR4300 */
2211 /* 12 = SR R4000 VR4100 VR4300 */
2212 #ifdef SUBTARGET_R3900
2213 case 3:
2214 /* 3 = Config R3900 */
2215 case 7:
2216 /* 7 = Cache R3900 */
2217 case 15:
2218 /* 15 = PRID R3900 */
2219
2220 /* ignore */
2221 break;
2222
2223 case 8:
2224 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2225 if (op == cp0_mfc0 || op == cp0_dmfc0)
2226 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
2227 else
2228 COP0_BADVADDR = GPR[rt];
2229 break;
2230
2231 #endif /* SUBTARGET_R3900 */
2232 case 12:
2233 if (op == cp0_mfc0 || op == cp0_dmfc0)
2234 GPR[rt] = SR;
2235 else
2236 SR = GPR[rt];
2237 break;
2238 /* 13 = Cause R4000 VR4100 VR4300 */
2239 case 13:
2240 if (op == cp0_mfc0 || op == cp0_dmfc0)
2241 GPR[rt] = CAUSE;
2242 else
2243 CAUSE = GPR[rt];
2244 break;
2245 /* 14 = EPC R4000 VR4100 VR4300 */
2246 case 14:
2247 if (op == cp0_mfc0 || op == cp0_dmfc0)
2248 GPR[rt] = (signed_word) (signed_address) EPC;
2249 else
2250 EPC = GPR[rt];
2251 break;
2252 /* 15 = PRId R4000 VR4100 VR4300 */
2253 #ifdef SUBTARGET_R3900
2254 /* 16 = Debug */
2255 case 16:
2256 if (op == cp0_mfc0 || op == cp0_dmfc0)
2257 GPR[rt] = Debug;
2258 else
2259 Debug = GPR[rt];
2260 break;
2261 #else
2262 /* 16 = Config R4000 VR4100 VR4300 */
2263 case 16:
2264 if (op == cp0_mfc0 || op == cp0_dmfc0)
2265 GPR[rt] = C0_CONFIG;
2266 else
2267 /* only bottom three bits are writable */
2268 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
2269 break;
2270 #endif
2271 #ifdef SUBTARGET_R3900
2272 /* 17 = Debug */
2273 case 17:
2274 if (op == cp0_mfc0 || op == cp0_dmfc0)
2275 GPR[rt] = DEPC;
2276 else
2277 DEPC = GPR[rt];
2278 break;
2279 #else
2280 /* 17 = LLAddr R4000 VR4100 VR4300 */
2281 #endif
2282 /* 18 = WatchLo R4000 VR4100 VR4300 */
2283 /* 19 = WatchHi R4000 VR4100 VR4300 */
2284 /* 20 = XContext R4000 VR4100 VR4300 */
2285 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2286 /* 27 = CacheErr R4000 VR4100 */
2287 /* 28 = TagLo R4000 VR4100 VR4300 */
2288 /* 29 = TagHi R4000 VR4100 VR4300 */
2289 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2290 if (STATE_VERBOSE_P(SD))
2291 sim_io_eprintf (SD,
2292 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2293 (unsigned long)cia);
2294 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2295 /* CPR[0,rd] = GPR[rt]; */
2296 default:
2297 if (op == cp0_mfc0 || op == cp0_dmfc0)
2298 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2299 else
2300 COP0_GPR[rd] = GPR[rt];
2301 #if 0
2302 if (code == 0x00)
2303 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2304 else
2305 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2306 #endif
2307 }
2308 }
2309 else if ((op == cp0_mfc0 || op == cp0_dmfc0)
2310 && rd == 16)
2311 {
2312 /* [D]MFC0 RT,C0_CONFIG,SEL */
2313 signed32 cfg = 0;
2314 switch (sel)
2315 {
2316 case 0:
2317 cfg = C0_CONFIG;
2318 break;
2319 case 1:
2320 /* MIPS32 r/o Config1:
2321 Config2 present */
2322 cfg = 0x80000000;
2323 /* MIPS16 implemented.
2324 XXX How to check configuration? */
2325 cfg |= 0x0000004;
2326 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2327 /* MDMX & FPU implemented */
2328 cfg |= 0x00000021;
2329 break;
2330 case 2:
2331 /* MIPS32 r/o Config2:
2332 Config3 present. */
2333 cfg = 0x80000000;
2334 break;
2335 case 3:
2336 /* MIPS32 r/o Config3:
2337 SmartMIPS implemented. */
2338 cfg = 0x00000002;
2339 break;
2340 }
2341 GPR[rt] = cfg;
2342 }
2343 else if (op == cp0_eret && sel == 0x18)
2344 {
2345 /* ERET */
2346 if (SR & status_ERL)
2347 {
2348 /* Oops, not yet available */
2349 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2350 PC = EPC;
2351 SR &= ~status_ERL;
2352 }
2353 else
2354 {
2355 PC = EPC;
2356 SR &= ~status_EXL;
2357 }
2358 }
2359 else if (op == cp0_rfe && sel == 0x10)
2360 {
2361 /* RFE */
2362 #ifdef SUBTARGET_R3900
2363 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2364
2365 /* shift IE/KU history bits right */
2366 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2367
2368 /* TODO: CACHE register */
2369 #endif /* SUBTARGET_R3900 */
2370 }
2371 else if (op == cp0_deret && sel == 0x1F)
2372 {
2373 /* DERET */
2374 Debug &= ~Debug_DM;
2375 DELAYSLOT();
2376 DSPC = DEPC;
2377 }
2378 else
2379 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2380 /* TODO: When executing an ERET or RFE instruction we should
2381 clear LLBIT, to ensure that any out-standing atomic
2382 read/modify/write sequence fails. */
2383 }
2384 break;
2385
2386 case 2: /* co-processor 2 */
2387 {
2388 int handle = 0;
2389
2390
2391 if(! handle)
2392 {
2393 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2394 instruction,pr_addr(cia));
2395 }
2396 }
2397 break;
2398
2399 case 1: /* should not occur (FPU co-processor) */
2400 case 3: /* should not occur (FPU co-processor) */
2401 SignalException(ReservedInstruction,instruction);
2402 break;
2403 }
2404
2405 return;
2406 }
2407
2408
2409 /* This code copied from gdb's utils.c. Would like to share this code,
2410 but don't know of a common place where both could get to it. */
2411
2412 /* Temporary storage using circular buffer */
2413 #define NUMCELLS 16
2414 #define CELLSIZE 32
2415 static char*
2416 get_cell (void)
2417 {
2418 static char buf[NUMCELLS][CELLSIZE];
2419 static int cell=0;
2420 if (++cell>=NUMCELLS) cell=0;
2421 return buf[cell];
2422 }
2423
2424 /* Print routines to handle variable size regs, etc */
2425
2426 /* Eliminate warning from compiler on 32-bit systems */
2427 static int thirty_two = 32;
2428
2429 char*
2430 pr_addr (SIM_ADDR addr)
2431 {
2432 char *paddr_str=get_cell();
2433 switch (sizeof(addr))
2434 {
2435 case 8:
2436 sprintf(paddr_str,"%08lx%08lx",
2437 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2438 break;
2439 case 4:
2440 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2441 break;
2442 case 2:
2443 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2444 break;
2445 default:
2446 sprintf(paddr_str,"%x",addr);
2447 }
2448 return paddr_str;
2449 }
2450
2451 char*
2452 pr_uword64 (uword64 addr)
2453 {
2454 char *paddr_str=get_cell();
2455 sprintf(paddr_str,"%08lx%08lx",
2456 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2457 return paddr_str;
2458 }
2459
2460
2461 void
2462 mips_core_signal (SIM_DESC sd,
2463 sim_cpu *cpu,
2464 sim_cia cia,
2465 unsigned map,
2466 int nr_bytes,
2467 address_word addr,
2468 transfer_type transfer,
2469 sim_core_signals sig)
2470 {
2471 const char *copy = (transfer == read_transfer ? "read" : "write");
2472 address_word ip = CIA_ADDR (cia);
2473
2474 switch (sig)
2475 {
2476 case sim_core_unmapped_signal:
2477 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2478 nr_bytes, copy,
2479 (unsigned long) addr, (unsigned long) ip);
2480 COP0_BADVADDR = addr;
2481 SignalExceptionDataReference();
2482 break;
2483
2484 case sim_core_unaligned_signal:
2485 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2486 nr_bytes, copy,
2487 (unsigned long) addr, (unsigned long) ip);
2488 COP0_BADVADDR = addr;
2489 if(transfer == read_transfer)
2490 SignalExceptionAddressLoad();
2491 else
2492 SignalExceptionAddressStore();
2493 break;
2494
2495 default:
2496 sim_engine_abort (sd, cpu, cia,
2497 "mips_core_signal - internal error - bad switch");
2498 }
2499 }
2500
2501
2502 void
2503 mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2504 {
2505 ASSERT(cpu != NULL);
2506
2507 if(cpu->exc_suspended > 0)
2508 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2509
2510 PC = cia;
2511 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2512 cpu->exc_suspended = 0;
2513 }
2514
2515 void
2516 mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2517 {
2518 ASSERT(cpu != NULL);
2519
2520 if(cpu->exc_suspended > 0)
2521 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2522 cpu->exc_suspended, exception);
2523
2524 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2525 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2526 cpu->exc_suspended = exception;
2527 }
2528
2529 void
2530 mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2531 {
2532 ASSERT(cpu != NULL);
2533
2534 if(exception == 0 && cpu->exc_suspended > 0)
2535 {
2536 /* warn not for breakpoints */
2537 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2538 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2539 cpu->exc_suspended);
2540 }
2541 else if(exception != 0 && cpu->exc_suspended > 0)
2542 {
2543 if(exception != cpu->exc_suspended)
2544 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2545 cpu->exc_suspended, exception);
2546
2547 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2548 }
2549 else if(exception != 0 && cpu->exc_suspended == 0)
2550 {
2551 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2552 }
2553 cpu->exc_suspended = 0;
2554 }
2555
2556
2557 /*---------------------------------------------------------------------------*/
2558 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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