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[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
18 $Date$
19
20 NOTEs:
21
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 code on the hardware.
26
27 */
28
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
33 #define TRACE (1)
34 #endif
35
36 #include "bfd.h"
37 #include "sim-main.h"
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
41
42 #include "config.h"
43
44 #include <stdio.h>
45 #include <stdarg.h>
46 #include <ansidecl.h>
47 #include <ctype.h>
48 #include <limits.h>
49 #include <math.h>
50 #ifdef HAVE_STDLIB_H
51 #include <stdlib.h>
52 #endif
53 #ifdef HAVE_STRING_H
54 #include <string.h>
55 #else
56 #ifdef HAVE_STRINGS_H
57 #include <strings.h>
58 #endif
59 #endif
60
61 #include "getopt.h"
62 #include "libiberty.h"
63 #include "bfd.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
66
67 #include "sysdep.h"
68
69 #ifndef PARAMS
70 #define PARAMS(x)
71 #endif
72
73 char* pr_addr PARAMS ((SIM_ADDR addr));
74 char* pr_uword64 PARAMS ((uword64 addr));
75
76
77 /* Get the simulator engine description, without including the code: */
78 #if (WITH_IGEN)
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
80 #else
81 #define SIM_MANIFESTS
82 #include "oengine.c"
83 #undef SIM_MANIFESTS
84 #endif
85
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
87 #define SD sd
88 #define CPU cpu
89
90
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
96
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
99
100
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
105
106
107
108
109
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
113
114 static void ColdReset PARAMS((SIM_DESC sd));
115
116 /*---------------------------------------------------------------------------*/
117
118
119
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
124 }
125
126 #define JALDELAYSLOT() {\
127 DELAYSLOT ();\
128 STATE |= simJALDELAYSLOT;\
129 }
130
131 #define NULLIFY() {\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
134 }
135
136 #define CANCELDELAYSLOT() {\
137 DSSTATE = 0;\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
139 }
140
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
143
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
151
152 #if defined(TRACE)
153 static char *tracefile = "trace.din"; /* default filename for trace log */
154 FILE *tracefh = NULL;
155 static void open_trace PARAMS((SIM_DESC sd));
156 #endif /* TRACE */
157
158 #define OPTION_DINERO_TRACE 200
159 #define OPTION_DINERO_FILE 201
160
161 static SIM_RC
162 mips_option_handler (sd, opt, arg)
163 SIM_DESC sd;
164 int opt;
165 char *arg;
166 {
167 int cpu_nr;
168 switch (opt)
169 {
170 case OPTION_DINERO_TRACE: /* ??? */
171 #if defined(TRACE)
172 /* Eventually the simTRACE flag could be treated as a toggle, to
173 allow external control of the program points being traced
174 (i.e. only from main onwards, excluding the run-time setup,
175 etc.). */
176 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
177 {
178 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
179 if (arg == NULL)
180 STATE |= simTRACE;
181 else if (strcmp (arg, "yes") == 0)
182 STATE |= simTRACE;
183 else if (strcmp (arg, "no") == 0)
184 STATE &= ~simTRACE;
185 else if (strcmp (arg, "on") == 0)
186 STATE |= simTRACE;
187 else if (strcmp (arg, "off") == 0)
188 STATE &= ~simTRACE;
189 else
190 {
191 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
192 return SIM_RC_FAIL;
193 }
194 }
195 return SIM_RC_OK;
196 #else /* !TRACE */
197 fprintf(stderr,"\
198 Simulator constructed without dinero tracing support (for performance).\n\
199 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
200 return SIM_RC_FAIL;
201 #endif /* !TRACE */
202
203 case OPTION_DINERO_FILE:
204 #if defined(TRACE)
205 if (optarg != NULL) {
206 char *tmp;
207 tmp = (char *)malloc(strlen(optarg) + 1);
208 if (tmp == NULL)
209 {
210 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
211 return SIM_RC_FAIL;
212 }
213 else {
214 strcpy(tmp,optarg);
215 tracefile = tmp;
216 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
217 }
218 }
219 #endif /* TRACE */
220 return SIM_RC_OK;
221
222 }
223
224 return SIM_RC_OK;
225 }
226
227 static const OPTION mips_options[] =
228 {
229 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
230 '\0', "on|off", "Enable dinero tracing",
231 mips_option_handler },
232 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
233 '\0', "FILE", "Write dinero trace to FILE",
234 mips_option_handler },
235 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
236 };
237
238
239 int interrupt_pending;
240
241 static void
242 interrupt_event (SIM_DESC sd, void *data)
243 {
244 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
245 if (SR & status_IE)
246 {
247 interrupt_pending = 0;
248 SignalExceptionInterrupt ();
249 }
250 else if (!interrupt_pending)
251 sim_events_schedule (sd, 1, interrupt_event, data);
252 }
253
254
255
256 /*---------------------------------------------------------------------------*/
257 /*-- GDB simulator interface ------------------------------------------------*/
258 /*---------------------------------------------------------------------------*/
259
260 SIM_DESC
261 sim_open (kind, cb, abfd, argv)
262 SIM_OPEN_KIND kind;
263 host_callback *cb;
264 struct _bfd *abfd;
265 char **argv;
266 {
267 SIM_DESC sd = sim_state_alloc (kind, cb);
268 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
269
270 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
271
272 /* FIXME: watchpoints code shouldn't need this */
273 STATE_WATCHPOINTS (sd)->pc = &(PC);
274 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
275 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
276
277 STATE = 0;
278
279 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
280 return 0;
281 sim_add_option_table (sd, mips_options);
282
283 /* Allocate core managed memory */
284
285 /* the monitor */
286 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
287 /* For compatibility with the old code - under this (at level one)
288 are the kernel spaces K0 & K1. Both of these map to a single
289 smaller sub region */
290 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
291 K1BASE, K0SIZE,
292 MEM_SIZE, /* actual size */
293 K0BASE);
294
295 /* getopt will print the error message so we just have to exit if this fails.
296 FIXME: Hmmm... in the case of gdb we need getopt to call
297 print_filtered. */
298 if (sim_parse_args (sd, argv) != SIM_RC_OK)
299 {
300 /* Uninstall the modules to avoid memory leaks,
301 file descriptor leaks, etc. */
302 sim_module_uninstall (sd);
303 return 0;
304 }
305
306 /* check for/establish the a reference program image */
307 if (sim_analyze_program (sd,
308 (STATE_PROG_ARGV (sd) != NULL
309 ? *STATE_PROG_ARGV (sd)
310 : NULL),
311 abfd) != SIM_RC_OK)
312 {
313 sim_module_uninstall (sd);
314 return 0;
315 }
316
317 /* Configure/verify the target byte order and other runtime
318 configuration options */
319 if (sim_config (sd) != SIM_RC_OK)
320 {
321 sim_module_uninstall (sd);
322 return 0;
323 }
324
325 if (sim_post_argv_init (sd) != SIM_RC_OK)
326 {
327 /* Uninstall the modules to avoid memory leaks,
328 file descriptor leaks, etc. */
329 sim_module_uninstall (sd);
330 return 0;
331 }
332
333 /* verify assumptions the simulator made about the host type system.
334 This macro does not return if there is a problem */
335 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
336 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
337
338 /* This is NASTY, in that we are assuming the size of specific
339 registers: */
340 {
341 int rn;
342 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
343 {
344 if (rn < 32)
345 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
346 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
347 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
348 else if ((rn >= 33) && (rn <= 37))
349 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
350 else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
351 cpu->register_widths[rn] = 32;
352 else
353 cpu->register_widths[rn] = 0;
354 }
355 /* start-sanitize-r5900 */
356
357 /* set the 5900 "upper" registers to 64 bits */
358 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
359 cpu->register_widths[rn] = 64;
360 /* end-sanitize-r5900 */
361 }
362
363 #if defined(TRACE)
364 if (STATE & simTRACE)
365 open_trace(sd);
366 #endif /* TRACE */
367
368 /* Write the monitor trap address handlers into the monitor (eeprom)
369 address space. This can only be done once the target endianness
370 has been determined. */
371 {
372 unsigned loop;
373 /* Entry into the IDT monitor is via fixed address vectors, and
374 not using machine instructions. To avoid clashing with use of
375 the MIPS TRAP system, we place our own (simulator specific)
376 "undefined" instructions into the relevant vector slots. */
377 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
378 {
379 address_word vaddr = (MONITOR_BASE + loop);
380 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
381 H2T (insn);
382 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
383 }
384 /* The PMON monitor uses the same address space, but rather than
385 branching into it the address of a routine is loaded. We can
386 cheat for the moment, and direct the PMON routine to IDT style
387 instructions within the monitor space. This relies on the IDT
388 monitor not using the locations from 0xBFC00500 onwards as its
389 entry points.*/
390 for (loop = 0; (loop < 24); loop++)
391 {
392 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
393 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
394 switch (loop)
395 {
396 case 0: /* read */
397 value = 7;
398 break;
399 case 1: /* write */
400 value = 8;
401 break;
402 case 2: /* open */
403 value = 6;
404 break;
405 case 3: /* close */
406 value = 10;
407 break;
408 case 5: /* printf */
409 value = ((0x500 - 16) / 8); /* not an IDT reason code */
410 break;
411 case 8: /* cliexit */
412 value = 17;
413 break;
414 case 11: /* flush_cache */
415 value = 28;
416 break;
417 }
418 /* FIXME - should monitor_base be SIM_ADDR?? */
419 value = ((unsigned int)MONITOR_BASE + (value * 8));
420 H2T (value);
421 sim_write (sd, vaddr, (char *)&value, sizeof (value));
422
423 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
424 vaddr -= 0x300;
425 sim_write (sd, vaddr, (char *)&value, sizeof (value));
426 }
427 }
428
429 return sd;
430 }
431
432 #if defined(TRACE)
433 static void
434 open_trace(sd)
435 SIM_DESC sd;
436 {
437 tracefh = fopen(tracefile,"wb+");
438 if (tracefh == NULL)
439 {
440 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
441 tracefh = stderr;
442 }
443 }
444 #endif /* TRACE */
445
446 void
447 sim_close (sd, quitting)
448 SIM_DESC sd;
449 int quitting;
450 {
451 #ifdef DEBUG
452 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
453 #endif
454
455 /* "quitting" is non-zero if we cannot hang on errors */
456
457 /* Ensure that any resources allocated through the callback
458 mechanism are released: */
459 sim_io_shutdown (sd);
460
461 #if defined(TRACE)
462 if (tracefh != NULL && tracefh != stderr)
463 fclose(tracefh);
464 tracefh = NULL;
465 #endif /* TRACE */
466
467 /* FIXME - free SD */
468
469 return;
470 }
471
472
473 int
474 sim_write (sd,addr,buffer,size)
475 SIM_DESC sd;
476 SIM_ADDR addr;
477 unsigned char *buffer;
478 int size;
479 {
480 int index;
481 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
482
483 /* Return the number of bytes written, or zero if error. */
484 #ifdef DEBUG
485 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
486 #endif
487
488 /* We use raw read and write routines, since we do not want to count
489 the GDB memory accesses in our statistics gathering. */
490
491 for (index = 0; index < size; index++)
492 {
493 address_word vaddr = (address_word)addr + index;
494 address_word paddr;
495 int cca;
496 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
497 break;
498 if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
499 break;
500 }
501
502 return(index);
503 }
504
505 int
506 sim_read (sd,addr,buffer,size)
507 SIM_DESC sd;
508 SIM_ADDR addr;
509 unsigned char *buffer;
510 int size;
511 {
512 int index;
513 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
514
515 /* Return the number of bytes read, or zero if error. */
516 #ifdef DEBUG
517 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
518 #endif /* DEBUG */
519
520 for (index = 0; (index < size); index++)
521 {
522 address_word vaddr = (address_word)addr + index;
523 address_word paddr;
524 int cca;
525 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
526 break;
527 if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
528 break;
529 }
530
531 return(index);
532 }
533
534 void
535 sim_store_register (sd,rn,memory)
536 SIM_DESC sd;
537 int rn;
538 unsigned char *memory;
539 {
540 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
541 /* NOTE: gdb (the client) stores registers in target byte order
542 while the simulator uses host byte order */
543 #ifdef DEBUG
544 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
545 #endif /* DEBUG */
546
547 /* Unfortunately this suffers from the same problem as the register
548 numbering one. We need to know what the width of each logical
549 register number is for the architecture being simulated. */
550
551 if (cpu->register_widths[rn] == 0)
552 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
553 /* start-sanitize-r5900 */
554 else if (rn == REGISTER_SA)
555 SA = T2H_8(*(unsigned64*)memory);
556 else if (rn > LAST_EMBED_REGNUM)
557 cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(unsigned64*)memory);
558 /* end-sanitize-r5900 */
559 else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
560 {
561 if (cpu->register_widths[rn] == 32)
562 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
563 else
564 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
565 }
566 else if (cpu->register_widths[rn] == 32)
567 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
568 else
569 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
570
571 return;
572 }
573
574 void
575 sim_fetch_register (sd,rn,memory)
576 SIM_DESC sd;
577 int rn;
578 unsigned char *memory;
579 {
580 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
581 /* NOTE: gdb (the client) stores registers in target byte order
582 while the simulator uses host byte order */
583 #ifdef DEBUG
584 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
585 #endif /* DEBUG */
586
587 if (cpu->register_widths[rn] == 0)
588 sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
589 /* start-sanitize-r5900 */
590 else if (rn == REGISTER_SA)
591 *((unsigned64*)memory) = H2T_8(SA);
592 else if (rn > LAST_EMBED_REGNUM)
593 *((unsigned64*)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
594 /* end-sanitize-r5900 */
595 else if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
596 {
597 if (cpu->register_widths[rn] == 32)
598 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
599 else
600 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
601 }
602 else if (cpu->register_widths[rn] == 32)
603 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
604 else /* 64bit register */
605 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
606
607 return;
608 }
609
610
611 void
612 sim_info (sd,verbose)
613 SIM_DESC sd;
614 int verbose;
615 {
616 /* Accessed from the GDB "info files" command: */
617 if (STATE_VERBOSE_P (sd) || verbose)
618 {
619
620 sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
621 WITH_TARGET_WORD_BITSIZE,
622 (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
623
624 #if !defined(FASTSIM)
625 /* It would be a useful feature, if when performing multi-cycle
626 simulations (rather than single-stepping) we keep the start and
627 end times of the execution, so that we can give a performance
628 figure for the simulator. */
629 #endif /* !FASTSIM */
630 sim_io_printf (sd, "Number of execution cycles = %ld\n",
631 (long) sim_events_time (sd));
632
633 /* print information pertaining to MIPS ISA and architecture being simulated */
634 /* things that may be interesting */
635 /* instructions executed - if available */
636 /* cycles executed - if available */
637 /* pipeline stalls - if available */
638 /* virtual time taken */
639 /* profiling size */
640 /* profiling frequency */
641 /* profile minpc */
642 /* profile maxpc */
643 }
644 profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL);
645 }
646
647
648 SIM_RC
649 sim_create_inferior (sd, abfd, argv,env)
650 SIM_DESC sd;
651 struct _bfd *abfd;
652 char **argv;
653 char **env;
654 {
655
656 #ifdef DEBUG
657 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
658 pr_addr(PC));
659 #endif /* DEBUG */
660
661 ColdReset(sd);
662
663 if (abfd != NULL)
664 {
665 /* override PC value set by ColdReset () */
666 int cpu_nr;
667 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
668 {
669 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
670 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
671 }
672 }
673
674 #if 0 /* def DEBUG */
675 if (argv || env)
676 {
677 /* We should really place the argv slot values into the argument
678 registers, and onto the stack as required. However, this
679 assumes that we have a stack defined, which is not
680 necessarily true at the moment. */
681 char **cptr;
682 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
683 for (cptr = argv; (cptr && *cptr); cptr++)
684 printf("DBG: arg \"%s\"\n",*cptr);
685 }
686 #endif /* DEBUG */
687
688 return SIM_RC_OK;
689 }
690
691 void
692 sim_do_command (sd,cmd)
693 SIM_DESC sd;
694 char *cmd;
695 {
696 if (sim_args_command (sd, cmd) != SIM_RC_OK)
697 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
698 cmd);
699 }
700
701 /*---------------------------------------------------------------------------*/
702 /*-- Private simulator support interface ------------------------------------*/
703 /*---------------------------------------------------------------------------*/
704
705 /* Read a null terminated string from memory, return in a buffer */
706 static char *
707 fetch_str (sd, addr)
708 SIM_DESC sd;
709 address_word addr;
710 {
711 char *buf;
712 int nr = 0;
713 char null;
714 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
715 nr++;
716 buf = NZALLOC (char, nr + 1);
717 sim_read (sd, addr, buf, nr);
718 return buf;
719 }
720
721 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
722 static void
723 sim_monitor (SIM_DESC sd,
724 sim_cpu *cpu,
725 address_word cia,
726 unsigned int reason)
727 {
728 #ifdef DEBUG
729 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
730 #endif /* DEBUG */
731
732 /* The IDT monitor actually allows two instructions per vector
733 slot. However, the simulator currently causes a trap on each
734 individual instruction. We cheat, and lose the bottom bit. */
735 reason >>= 1;
736
737 /* The following callback functions are available, however the
738 monitor we are simulating does not make use of them: get_errno,
739 isatty, lseek, rename, system, time and unlink */
740 switch (reason)
741 {
742
743 case 6: /* int open(char *path,int flags) */
744 {
745 char *path = fetch_str (sd, A0);
746 V0 = sim_io_open (sd, path, (int)A1);
747 zfree (path);
748 break;
749 }
750
751 case 7: /* int read(int file,char *ptr,int len) */
752 {
753 int fd = A0;
754 int nr = A2;
755 char *buf = zalloc (nr);
756 V0 = sim_io_read (sd, fd, buf, nr);
757 sim_write (sd, A1, buf, nr);
758 zfree (buf);
759 }
760 break;
761
762 case 8: /* int write(int file,char *ptr,int len) */
763 {
764 int fd = A0;
765 int nr = A2;
766 char *buf = zalloc (nr);
767 sim_read (sd, A1, buf, nr);
768 V0 = sim_io_write (sd, fd, buf, nr);
769 zfree (buf);
770 break;
771 }
772
773 case 10: /* int close(int file) */
774 {
775 V0 = sim_io_close (sd, (int)A0);
776 break;
777 }
778
779 case 2: /* Densan monitor: char inbyte(int waitflag) */
780 {
781 if (A0 == 0) /* waitflag == NOWAIT */
782 V0 = (unsigned_word)-1;
783 }
784 /* Drop through to case 11 */
785
786 case 11: /* char inbyte(void) */
787 {
788 char tmp;
789 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
790 {
791 sim_io_error(sd,"Invalid return from character read");
792 V0 = (unsigned_word)-1;
793 }
794 else
795 V0 = (unsigned_word)tmp;
796 break;
797 }
798
799 case 3: /* Densan monitor: void co(char chr) */
800 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
801 {
802 char tmp = (char)(A0 & 0xFF);
803 sim_io_write_stdout (sd, &tmp, sizeof(char));
804 break;
805 }
806
807 case 17: /* void _exit() */
808 {
809 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
810 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
811 (unsigned int)(A0 & 0xFFFFFFFF));
812 break;
813 }
814
815 case 28 : /* PMON flush_cache */
816 break;
817
818 case 55: /* void get_mem_info(unsigned int *ptr) */
819 /* in: A0 = pointer to three word memory location */
820 /* out: [A0 + 0] = size */
821 /* [A0 + 4] = instruction cache size */
822 /* [A0 + 8] = data cache size */
823 {
824 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
825 H2T (value);
826 sim_write (sd, A0, (char *)&value, sizeof (value));
827 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
828 break;
829 }
830
831 case 158 : /* PMON printf */
832 /* in: A0 = pointer to format string */
833 /* A1 = optional argument 1 */
834 /* A2 = optional argument 2 */
835 /* A3 = optional argument 3 */
836 /* out: void */
837 /* The following is based on the PMON printf source */
838 {
839 address_word s = A0;
840 char c;
841 signed_word *ap = &A1; /* 1st argument */
842 /* This isn't the quickest way, since we call the host print
843 routine for every character almost. But it does avoid
844 having to allocate and manage a temporary string buffer. */
845 /* TODO: Include check that we only use three arguments (A1,
846 A2 and A3) */
847 while (sim_read (sd, s++, &c, 1) && c != '\0')
848 {
849 if (c == '%')
850 {
851 char tmp[40];
852 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
853 int width = 0, trunc = 0, haddot = 0, longlong = 0;
854 while (sim_read (sd, s++, &c, 1) && c != '\0')
855 {
856 if (strchr ("dobxXulscefg%", s))
857 break;
858 else if (c == '-')
859 fmt = FMT_LJUST;
860 else if (c == '0')
861 fmt = FMT_RJUST0;
862 else if (c == '~')
863 fmt = FMT_CENTER;
864 else if (c == '*')
865 {
866 if (haddot)
867 trunc = (int)*ap++;
868 else
869 width = (int)*ap++;
870 }
871 else if (c >= '1' && c <= '9')
872 {
873 address_word t = s;
874 unsigned int n;
875 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
876 tmp[s - t] = c;
877 tmp[s - t] = '\0';
878 n = (unsigned int)strtol(tmp,NULL,10);
879 if (haddot)
880 trunc = n;
881 else
882 width = n;
883 s--;
884 }
885 else if (c == '.')
886 haddot = 1;
887 }
888 switch (c)
889 {
890 case '%':
891 sim_io_printf (sd, "%%");
892 break;
893 case 's':
894 if ((int)*ap != 0)
895 {
896 address_word p = *ap++;
897 char ch;
898 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
899 sim_io_printf(sd, "%c", ch);
900 }
901 else
902 sim_io_printf(sd,"(null)");
903 break;
904 case 'c':
905 sim_io_printf (sd, "%c", (int)*ap++);
906 break;
907 default:
908 if (c == 'l')
909 {
910 sim_read (sd, s++, &c, 1);
911 if (c == 'l')
912 {
913 longlong = 1;
914 sim_read (sd, s++, &c, 1);
915 }
916 }
917 if (strchr ("dobxXu", c))
918 {
919 word64 lv = (word64) *ap++;
920 if (c == 'b')
921 sim_io_printf(sd,"<binary not supported>");
922 else
923 {
924 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
925 if (longlong)
926 sim_io_printf(sd, tmp, lv);
927 else
928 sim_io_printf(sd, tmp, (int)lv);
929 }
930 }
931 else if (strchr ("eEfgG", c))
932 {
933 double dbl = *(double*)(ap++);
934 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
935 sim_io_printf (sd, tmp, dbl);
936 trunc = 0;
937 }
938 }
939 }
940 else
941 sim_io_printf(sd, "%c", c);
942 }
943 break;
944 }
945
946 default:
947 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
948 reason, pr_addr(cia));
949 break;
950 }
951 return;
952 }
953
954 /* Store a word into memory. */
955
956 static void
957 store_word (SIM_DESC sd,
958 sim_cpu *cpu,
959 address_word cia,
960 uword64 vaddr,
961 signed_word val)
962 {
963 address_word paddr;
964 int uncached;
965
966 if ((vaddr & 3) != 0)
967 SignalExceptionAddressStore ();
968 else
969 {
970 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
971 isTARGET, isREAL))
972 {
973 const uword64 mask = 7;
974 uword64 memval;
975 unsigned int byte;
976
977 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
978 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
979 memval = ((uword64) val) << (8 * byte);
980 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
981 isREAL);
982 }
983 }
984 }
985
986 /* Load a word from memory. */
987
988 static signed_word
989 load_word (SIM_DESC sd,
990 sim_cpu *cpu,
991 address_word cia,
992 uword64 vaddr)
993 {
994 if ((vaddr & 3) != 0)
995 SignalExceptionAddressLoad ();
996 else
997 {
998 address_word paddr;
999 int uncached;
1000
1001 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1002 isTARGET, isREAL))
1003 {
1004 const uword64 mask = 0x7;
1005 const unsigned int reverse = ReverseEndian ? 1 : 0;
1006 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1007 uword64 memval;
1008 unsigned int byte;
1009
1010 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1011 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1012 isDATA, isREAL);
1013 byte = (vaddr & mask) ^ (bigend << 2);
1014 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1015 }
1016 }
1017
1018 return 0;
1019 }
1020
1021 /* Simulate the mips16 entry and exit pseudo-instructions. These
1022 would normally be handled by the reserved instruction exception
1023 code, but for ease of simulation we just handle them directly. */
1024
1025 static void
1026 mips16_entry (SIM_DESC sd,
1027 sim_cpu *cpu,
1028 address_word cia,
1029 unsigned int insn)
1030 {
1031 int aregs, sregs, rreg;
1032
1033 #ifdef DEBUG
1034 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1035 #endif /* DEBUG */
1036
1037 aregs = (insn & 0x700) >> 8;
1038 sregs = (insn & 0x0c0) >> 6;
1039 rreg = (insn & 0x020) >> 5;
1040
1041 /* This should be checked by the caller. */
1042 if (sregs == 3)
1043 abort ();
1044
1045 if (aregs < 5)
1046 {
1047 int i;
1048 signed_word tsp;
1049
1050 /* This is the entry pseudo-instruction. */
1051
1052 for (i = 0; i < aregs; i++)
1053 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1054
1055 tsp = SP;
1056 SP -= 32;
1057
1058 if (rreg)
1059 {
1060 tsp -= 4;
1061 store_word (SD, CPU, cia, (uword64) tsp, RA);
1062 }
1063
1064 for (i = 0; i < sregs; i++)
1065 {
1066 tsp -= 4;
1067 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1068 }
1069 }
1070 else
1071 {
1072 int i;
1073 signed_word tsp;
1074
1075 /* This is the exit pseudo-instruction. */
1076
1077 tsp = SP + 32;
1078
1079 if (rreg)
1080 {
1081 tsp -= 4;
1082 RA = load_word (SD, CPU, cia, (uword64) tsp);
1083 }
1084
1085 for (i = 0; i < sregs; i++)
1086 {
1087 tsp -= 4;
1088 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1089 }
1090
1091 SP += 32;
1092
1093 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1094 {
1095 if (aregs == 5)
1096 {
1097 FGR[0] = WORD64LO (GPR[4]);
1098 FPR_STATE[0] = fmt_uninterpreted;
1099 }
1100 else if (aregs == 6)
1101 {
1102 FGR[0] = WORD64LO (GPR[5]);
1103 FGR[1] = WORD64LO (GPR[4]);
1104 FPR_STATE[0] = fmt_uninterpreted;
1105 FPR_STATE[1] = fmt_uninterpreted;
1106 }
1107 }
1108
1109 PC = RA;
1110 }
1111
1112 }
1113
1114 /*-- trace support ----------------------------------------------------------*/
1115
1116 /* The TRACE support is provided (if required) in the memory accessing
1117 routines. Since we are also providing the architecture specific
1118 features, the architecture simulation code can also deal with
1119 notifying the TRACE world of cache flushes, etc. Similarly we do
1120 not need to provide profiling support in the simulator engine,
1121 since we can sample in the instruction fetch control loop. By
1122 defining the TRACE manifest, we add tracing as a run-time
1123 option. */
1124
1125 #if defined(TRACE)
1126 /* Tracing by default produces "din" format (as required by
1127 dineroIII). Each line of such a trace file *MUST* have a din label
1128 and address field. The rest of the line is ignored, so comments can
1129 be included if desired. The first field is the label which must be
1130 one of the following values:
1131
1132 0 read data
1133 1 write data
1134 2 instruction fetch
1135 3 escape record (treated as unknown access type)
1136 4 escape record (causes cache flush)
1137
1138 The address field is a 32bit (lower-case) hexadecimal address
1139 value. The address should *NOT* be preceded by "0x".
1140
1141 The size of the memory transfer is not important when dealing with
1142 cache lines (as long as no more than a cache line can be
1143 transferred in a single operation :-), however more information
1144 could be given following the dineroIII requirement to allow more
1145 complete memory and cache simulators to provide better
1146 results. i.e. the University of Pisa has a cache simulator that can
1147 also take bus size and speed as (variable) inputs to calculate
1148 complete system performance (a much more useful ability when trying
1149 to construct an end product, rather than a processor). They
1150 currently have an ARM version of their tool called ChARM. */
1151
1152
1153 void
1154 dotrace (SIM_DESC sd,
1155 sim_cpu *cpu,
1156 FILE *tracefh,
1157 int type,
1158 SIM_ADDR address,
1159 int width,
1160 char *comment,...)
1161 {
1162 if (STATE & simTRACE) {
1163 va_list ap;
1164 fprintf(tracefh,"%d %s ; width %d ; ",
1165 type,
1166 pr_addr(address),
1167 width);
1168 va_start(ap,comment);
1169 vfprintf(tracefh,comment,ap);
1170 va_end(ap);
1171 fprintf(tracefh,"\n");
1172 }
1173 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1174 we may be generating 64bit ones, we should put the hi-32bits of the
1175 address into the comment field. */
1176
1177 /* TODO: Provide a buffer for the trace lines. We can then avoid
1178 performing writes until the buffer is filled, or the file is
1179 being closed. */
1180
1181 /* NOTE: We could consider adding a comment field to the "din" file
1182 produced using type 3 markers (unknown access). This would then
1183 allow information about the program that the "din" is for, and
1184 the MIPs world that was being simulated, to be placed into the
1185 trace file. */
1186
1187 return;
1188 }
1189 #endif /* TRACE */
1190
1191 /*---------------------------------------------------------------------------*/
1192 /*-- simulator engine -------------------------------------------------------*/
1193 /*---------------------------------------------------------------------------*/
1194
1195 static void
1196 ColdReset (SIM_DESC sd)
1197 {
1198 int cpu_nr;
1199 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1200 {
1201 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1202 /* RESET: Fixed PC address: */
1203 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
1204 /* The reset vector address is in the unmapped, uncached memory space. */
1205
1206 SR &= ~(status_SR | status_TS | status_RP);
1207 SR |= (status_ERL | status_BEV);
1208
1209 /* Cheat and allow access to the complete register set immediately */
1210 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1211 && WITH_TARGET_WORD_BITSIZE == 64)
1212 SR |= status_FR; /* 64bit registers */
1213
1214 /* Ensure that any instructions with pending register updates are
1215 cleared: */
1216 PENDING_INVALIDATE();
1217
1218 /* Initialise the FPU registers to the unknown state */
1219 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1220 {
1221 int rn;
1222 for (rn = 0; (rn < 32); rn++)
1223 FPR_STATE[rn] = fmt_uninterpreted;
1224 }
1225
1226 }
1227 }
1228
1229 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1230 (revision 3.1) */
1231 /* Translate a virtual address to a physical address and cache
1232 coherence algorithm describing the mechanism used to resolve the
1233 memory reference. Given the virtual address vAddr, and whether the
1234 reference is to Instructions ot Data (IorD), find the corresponding
1235 physical address (pAddr) and the cache coherence algorithm (CCA)
1236 used to resolve the reference. If the virtual address is in one of
1237 the unmapped address spaces the physical address and the CCA are
1238 determined directly by the virtual address. If the virtual address
1239 is in one of the mapped address spaces then the TLB is used to
1240 determine the physical address and access type; if the required
1241 translation is not present in the TLB or the desired access is not
1242 permitted the function fails and an exception is taken.
1243
1244 NOTE: Normally (RAW == 0), when address translation fails, this
1245 function raises an exception and does not return. */
1246
1247 int
1248 address_translation (SIM_DESC sd,
1249 sim_cpu *cpu,
1250 address_word cia,
1251 address_word vAddr,
1252 int IorD,
1253 int LorS,
1254 address_word *pAddr,
1255 int *CCA,
1256 int raw)
1257 {
1258 int res = -1; /* TRUE : Assume good return */
1259
1260 #ifdef DEBUG
1261 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
1262 #endif
1263
1264 /* Check that the address is valid for this memory model */
1265
1266 /* For a simple (flat) memory model, we simply pass virtual
1267 addressess through (mostly) unchanged. */
1268 vAddr &= 0xFFFFFFFF;
1269
1270 *pAddr = vAddr; /* default for isTARGET */
1271 *CCA = Uncached; /* not used for isHOST */
1272
1273 return(res);
1274 }
1275
1276 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1277 (revision 3.1) */
1278 /* Prefetch data from memory. Prefetch is an advisory instruction for
1279 which an implementation specific action is taken. The action taken
1280 may increase performance, but must not change the meaning of the
1281 program, or alter architecturally-visible state. */
1282
1283 void
1284 prefetch (SIM_DESC sd,
1285 sim_cpu *cpu,
1286 address_word cia,
1287 int CCA,
1288 address_word pAddr,
1289 address_word vAddr,
1290 int DATA,
1291 int hint)
1292 {
1293 #ifdef DEBUG
1294 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
1295 #endif /* DEBUG */
1296
1297 /* For our simple memory model we do nothing */
1298 return;
1299 }
1300
1301 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1302 (revision 3.1) */
1303 /* Load a value from memory. Use the cache and main memory as
1304 specified in the Cache Coherence Algorithm (CCA) and the sort of
1305 access (IorD) to find the contents of AccessLength memory bytes
1306 starting at physical location pAddr. The data is returned in the
1307 fixed width naturally-aligned memory element (MemElem). The
1308 low-order two (or three) bits of the address and the AccessLength
1309 indicate which of the bytes within MemElem needs to be given to the
1310 processor. If the memory access type of the reference is uncached
1311 then only the referenced bytes are read from memory and valid
1312 within the memory element. If the access type is cached, and the
1313 data is not present in cache, an implementation specific size and
1314 alignment block of memory is read and loaded into the cache to
1315 satisfy a load reference. At a minimum, the block is the entire
1316 memory element. */
1317 void
1318 load_memory (SIM_DESC sd,
1319 sim_cpu *cpu,
1320 address_word cia,
1321 uword64* memvalp,
1322 uword64* memval1p,
1323 int CCA,
1324 int AccessLength,
1325 address_word pAddr,
1326 address_word vAddr,
1327 int IorD)
1328 {
1329 uword64 value = 0;
1330 uword64 value1 = 0;
1331
1332 #ifdef DEBUG
1333 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
1334 #endif /* DEBUG */
1335
1336 #if defined(WARN_MEM)
1337 if (CCA != uncached)
1338 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1339 #endif /* WARN_MEM */
1340
1341 /* If instruction fetch then we need to check that the two lo-order
1342 bits are zero, otherwise raise a InstructionFetch exception: */
1343 if ((IorD == isINSTRUCTION)
1344 && ((pAddr & 0x3) != 0)
1345 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
1346 SignalExceptionInstructionFetch ();
1347
1348 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1349 {
1350 /* In reality this should be a Bus Error */
1351 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1352 AccessLength,
1353 (LOADDRMASK + 1) << 2,
1354 pr_addr (pAddr));
1355 }
1356
1357 #if defined(TRACE)
1358 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
1359 #endif /* TRACE */
1360
1361 /* Read the specified number of bytes from memory. Adjust for
1362 host/target byte ordering/ Align the least significant byte
1363 read. */
1364
1365 switch (AccessLength)
1366 {
1367 case AccessLength_QUADWORD :
1368 {
1369 unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA,
1370 sim_core_read_map, pAddr);
1371 value1 = VH8_16 (val);
1372 value = VL8_16 (val);
1373 break;
1374 }
1375 case AccessLength_DOUBLEWORD :
1376 value = sim_core_read_aligned_8 (cpu, NULL_CIA,
1377 sim_core_read_map, pAddr);
1378 break;
1379 case AccessLength_SEPTIBYTE :
1380 value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
1381 sim_core_read_map, pAddr);
1382 case AccessLength_SEXTIBYTE :
1383 value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
1384 sim_core_read_map, pAddr);
1385 case AccessLength_QUINTIBYTE :
1386 value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
1387 sim_core_read_map, pAddr);
1388 case AccessLength_WORD :
1389 value = sim_core_read_aligned_4 (cpu, NULL_CIA,
1390 sim_core_read_map, pAddr);
1391 break;
1392 case AccessLength_TRIPLEBYTE :
1393 value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
1394 sim_core_read_map, pAddr);
1395 case AccessLength_HALFWORD :
1396 value = sim_core_read_aligned_2 (cpu, NULL_CIA,
1397 sim_core_read_map, pAddr);
1398 break;
1399 case AccessLength_BYTE :
1400 value = sim_core_read_aligned_1 (cpu, NULL_CIA,
1401 sim_core_read_map, pAddr);
1402 break;
1403 default:
1404 abort ();
1405 }
1406
1407 #ifdef DEBUG
1408 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1409 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
1410 #endif /* DEBUG */
1411
1412 /* See also store_memory. */
1413 if (AccessLength <= AccessLength_DOUBLEWORD)
1414 {
1415 if (BigEndianMem)
1416 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1417 shifted to the most significant byte position. */
1418 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1419 else
1420 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1421 is already in the correct postition. */
1422 value <<= ((pAddr & LOADDRMASK) * 8);
1423 }
1424
1425 #ifdef DEBUG
1426 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1427 pr_uword64(value1),pr_uword64(value));
1428 #endif /* DEBUG */
1429
1430 *memvalp = value;
1431 if (memval1p) *memval1p = value1;
1432 }
1433
1434
1435 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1436 (revision 3.1) */
1437 /* Store a value to memory. The specified data is stored into the
1438 physical location pAddr using the memory hierarchy (data caches and
1439 main memory) as specified by the Cache Coherence Algorithm
1440 (CCA). The MemElem contains the data for an aligned, fixed-width
1441 memory element (word for 32-bit processors, doubleword for 64-bit
1442 processors), though only the bytes that will actually be stored to
1443 memory need to be valid. The low-order two (or three) bits of pAddr
1444 and the AccessLength field indicates which of the bytes within the
1445 MemElem data should actually be stored; only these bytes in memory
1446 will be changed. */
1447
1448 void
1449 store_memory (SIM_DESC sd,
1450 sim_cpu *cpu,
1451 address_word cia,
1452 int CCA,
1453 int AccessLength,
1454 uword64 MemElem,
1455 uword64 MemElem1, /* High order 64 bits */
1456 address_word pAddr,
1457 address_word vAddr)
1458 {
1459 #ifdef DEBUG
1460 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
1461 #endif /* DEBUG */
1462
1463 #if defined(WARN_MEM)
1464 if (CCA != uncached)
1465 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1466 #endif /* WARN_MEM */
1467
1468 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1469 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1470
1471 #if defined(TRACE)
1472 dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
1473 #endif /* TRACE */
1474
1475 #ifdef DEBUG
1476 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
1477 #endif /* DEBUG */
1478
1479 /* See also load_memory */
1480 if (AccessLength <= AccessLength_DOUBLEWORD)
1481 {
1482 if (BigEndianMem)
1483 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1484 shifted to the most significant byte position. */
1485 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1486 else
1487 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1488 is already in the correct postition. */
1489 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1490 }
1491
1492 #ifdef DEBUG
1493 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
1494 #endif /* DEBUG */
1495
1496 switch (AccessLength)
1497 {
1498 case AccessLength_QUADWORD :
1499 {
1500 unsigned_16 val = U16_8 (MemElem1, MemElem);
1501 sim_core_write_aligned_16 (cpu, NULL_CIA,
1502 sim_core_write_map, pAddr, val);
1503 break;
1504 }
1505 case AccessLength_DOUBLEWORD :
1506 sim_core_write_aligned_8 (cpu, NULL_CIA,
1507 sim_core_write_map, pAddr, MemElem);
1508 break;
1509 case AccessLength_SEPTIBYTE :
1510 sim_core_write_misaligned_7 (cpu, NULL_CIA,
1511 sim_core_write_map, pAddr, MemElem);
1512 break;
1513 case AccessLength_SEXTIBYTE :
1514 sim_core_write_misaligned_6 (cpu, NULL_CIA,
1515 sim_core_write_map, pAddr, MemElem);
1516 break;
1517 case AccessLength_QUINTIBYTE :
1518 sim_core_write_misaligned_5 (cpu, NULL_CIA,
1519 sim_core_write_map, pAddr, MemElem);
1520 break;
1521 case AccessLength_WORD :
1522 sim_core_write_aligned_4 (cpu, NULL_CIA,
1523 sim_core_write_map, pAddr, MemElem);
1524 break;
1525 case AccessLength_TRIPLEBYTE :
1526 sim_core_write_misaligned_3 (cpu, NULL_CIA,
1527 sim_core_write_map, pAddr, MemElem);
1528 break;
1529 case AccessLength_HALFWORD :
1530 sim_core_write_aligned_2 (cpu, NULL_CIA,
1531 sim_core_write_map, pAddr, MemElem);
1532 break;
1533 case AccessLength_BYTE :
1534 sim_core_write_aligned_1 (cpu, NULL_CIA,
1535 sim_core_write_map, pAddr, MemElem);
1536 break;
1537 default:
1538 abort ();
1539 }
1540
1541 return;
1542 }
1543
1544
1545 unsigned32
1546 ifetch32 (SIM_DESC sd,
1547 sim_cpu *cpu,
1548 address_word cia,
1549 address_word vaddr)
1550 {
1551 /* Copy the action of the LW instruction */
1552 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1553 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1554 unsigned64 value;
1555 address_word paddr;
1556 unsigned32 instruction;
1557 unsigned byte;
1558 int cca;
1559 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1560 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1561 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1562 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1563 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1564 return instruction;
1565 }
1566
1567
1568 unsigned16
1569 ifetch16 (SIM_DESC sd,
1570 sim_cpu *cpu,
1571 address_word cia,
1572 address_word vaddr)
1573 {
1574 /* Copy the action of the LW instruction */
1575 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1576 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1577 unsigned64 value;
1578 address_word paddr;
1579 unsigned16 instruction;
1580 unsigned byte;
1581 int cca;
1582 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1583 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1584 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1585 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1586 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1587 return instruction;
1588 }
1589
1590
1591 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1592 /* Order loads and stores to synchronise shared memory. Perform the
1593 action necessary to make the effects of groups of synchronizable
1594 loads and stores indicated by stype occur in the same order for all
1595 processors. */
1596 void
1597 sync_operation (SIM_DESC sd,
1598 sim_cpu *cpu,
1599 address_word cia,
1600 int stype)
1601 {
1602 #ifdef DEBUG
1603 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
1604 #endif /* DEBUG */
1605 return;
1606 }
1607
1608 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1609 /* Signal an exception condition. This will result in an exception
1610 that aborts the instruction. The instruction operation pseudocode
1611 will never see a return from this function call. */
1612
1613 void
1614 signal_exception (SIM_DESC sd,
1615 sim_cpu *cpu,
1616 address_word cia,
1617 int exception,...)
1618 {
1619 int vector;
1620
1621 #ifdef DEBUG
1622 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1623 #endif /* DEBUG */
1624
1625 /* Ensure that any active atomic read/modify/write operation will fail: */
1626 LLBIT = 0;
1627
1628 switch (exception) {
1629 /* TODO: For testing purposes I have been ignoring TRAPs. In
1630 reality we should either simulate them, or allow the user to
1631 ignore them at run-time.
1632 Same for SYSCALL */
1633 case Trap :
1634 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
1635 break;
1636
1637 case SystemCall :
1638 {
1639 va_list ap;
1640 unsigned int instruction;
1641 unsigned int code;
1642
1643 va_start(ap,exception);
1644 instruction = va_arg(ap,unsigned int);
1645 va_end(ap);
1646
1647 code = (instruction >> 6) & 0xFFFFF;
1648
1649 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1650 code, pr_addr(cia));
1651 }
1652 break;
1653
1654 case DebugBreakPoint :
1655 if (! (Debug & Debug_DM))
1656 {
1657 if (INDELAYSLOT())
1658 {
1659 CANCELDELAYSLOT();
1660
1661 Debug |= Debug_DBD; /* signaled from within in delay slot */
1662 DEPC = cia - 4; /* reference the branch instruction */
1663 }
1664 else
1665 {
1666 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1667 DEPC = cia;
1668 }
1669
1670 Debug |= Debug_DM; /* in debugging mode */
1671 Debug |= Debug_DBp; /* raising a DBp exception */
1672 PC = 0xBFC00200;
1673 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1674 }
1675 break;
1676
1677 case ReservedInstruction :
1678 {
1679 va_list ap;
1680 unsigned int instruction;
1681 va_start(ap,exception);
1682 instruction = va_arg(ap,unsigned int);
1683 va_end(ap);
1684 /* Provide simple monitor support using ReservedInstruction
1685 exceptions. The following code simulates the fixed vector
1686 entry points into the IDT monitor by causing a simulator
1687 trap, performing the monitor operation, and returning to
1688 the address held in the $ra register (standard PCS return
1689 address). This means we only need to pre-load the vector
1690 space with suitable instruction values. For systems were
1691 actual trap instructions are used, we would not need to
1692 perform this magic. */
1693 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1694 {
1695 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1696 /* NOTE: This assumes that a branch-and-link style
1697 instruction was used to enter the vector (which is the
1698 case with the current IDT monitor). */
1699 sim_engine_restart (SD, CPU, NULL, RA);
1700 }
1701 /* Look for the mips16 entry and exit instructions, and
1702 simulate a handler for them. */
1703 else if ((cia & 1) != 0
1704 && (instruction & 0xf81f) == 0xe809
1705 && (instruction & 0x0c0) != 0x0c0)
1706 {
1707 mips16_entry (SD, CPU, cia, instruction);
1708 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1709 }
1710 /* else fall through to normal exception processing */
1711 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
1712 }
1713
1714 case BreakPoint:
1715 #ifdef DEBUG
1716 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1717 #endif /* DEBUG */
1718 /* Keep a copy of the current A0 in-case this is the program exit
1719 breakpoint: */
1720 {
1721 va_list ap;
1722 unsigned int instruction;
1723 va_start(ap,exception);
1724 instruction = va_arg(ap,unsigned int);
1725 va_end(ap);
1726 /* Check for our special terminating BREAK: */
1727 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
1728 sim_engine_halt (SD, CPU, NULL, cia,
1729 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1730 }
1731 }
1732 if (STATE & simDELAYSLOT)
1733 PC = cia - 4; /* reference the branch instruction */
1734 else
1735 PC = cia;
1736 sim_engine_halt (SD, CPU, NULL, cia,
1737 sim_stopped, SIM_SIGTRAP);
1738
1739 default:
1740 /* Store exception code into current exception id variable (used
1741 by exit code): */
1742
1743 /* TODO: If not simulating exceptions then stop the simulator
1744 execution. At the moment we always stop the simulation. */
1745
1746 /* See figure 5-17 for an outline of the code below */
1747 if (! (SR & status_EXL))
1748 {
1749 CAUSE = (exception << 2);
1750 if (STATE & simDELAYSLOT)
1751 {
1752 STATE &= ~simDELAYSLOT;
1753 CAUSE |= cause_BD;
1754 EPC = (cia - 4); /* reference the branch instruction */
1755 }
1756 else
1757 EPC = cia;
1758 /* FIXME: TLB et.al. */
1759 vector = 0x180;
1760 }
1761 else
1762 {
1763 CAUSE = (exception << 2);
1764 vector = 0x180;
1765 }
1766 SR |= status_EXL;
1767 /* Store exception code into current exception id variable (used
1768 by exit code): */
1769 if (SR & status_BEV)
1770 PC = (signed)0xBFC00200 + 0x180;
1771 else
1772 PC = (signed)0x80000000 + 0x180;
1773
1774 switch ((CAUSE >> 2) & 0x1F)
1775 {
1776 case Interrupt:
1777 /* Interrupts arrive during event processing, no need to
1778 restart */
1779 return;
1780
1781 case TLBModification:
1782 case TLBLoad:
1783 case TLBStore:
1784 case AddressLoad:
1785 case AddressStore:
1786 case InstructionFetch:
1787 case DataReference:
1788 /* The following is so that the simulator will continue from the
1789 exception address on breakpoint operations. */
1790 PC = EPC;
1791 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1792 sim_stopped, SIM_SIGBUS);
1793
1794 case ReservedInstruction:
1795 case CoProcessorUnusable:
1796 PC = EPC;
1797 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1798 sim_stopped, SIM_SIGILL);
1799
1800 case IntegerOverflow:
1801 case FPE:
1802 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1803 sim_stopped, SIM_SIGFPE);
1804
1805 case Trap:
1806 case Watch:
1807 case SystemCall:
1808 PC = EPC;
1809 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1810 sim_stopped, SIM_SIGTRAP);
1811
1812 case BreakPoint:
1813 PC = EPC;
1814 sim_engine_abort (SD, CPU, NULL_CIA,
1815 "FATAL: Should not encounter a breakpoint\n");
1816
1817 default : /* Unknown internal exception */
1818 PC = EPC;
1819 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1820 sim_stopped, SIM_SIGABRT);
1821
1822 }
1823
1824 case SimulatorFault:
1825 {
1826 va_list ap;
1827 char *msg;
1828 va_start(ap,exception);
1829 msg = va_arg(ap,char *);
1830 va_end(ap);
1831 sim_engine_abort (SD, CPU, NULL_CIA,
1832 "FATAL: Simulator error \"%s\"\n",msg);
1833 }
1834 }
1835
1836 return;
1837 }
1838
1839 #if defined(WARN_RESULT)
1840 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1841 /* This function indicates that the result of the operation is
1842 undefined. However, this should not affect the instruction
1843 stream. All that is meant to happen is that the destination
1844 register is set to an undefined result. To keep the simulator
1845 simple, we just don't bother updating the destination register, so
1846 the overall result will be undefined. If desired we can stop the
1847 simulator by raising a pseudo-exception. */
1848 #define UndefinedResult() undefined_result (sd,cia)
1849 static void
1850 undefined_result(sd,cia)
1851 SIM_DESC sd;
1852 address_word cia;
1853 {
1854 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
1855 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1856 state |= simSTOP;
1857 #endif
1858 return;
1859 }
1860 #endif /* WARN_RESULT */
1861
1862 void
1863 cache_op (SIM_DESC sd,
1864 sim_cpu *cpu,
1865 address_word cia,
1866 int op,
1867 address_word pAddr,
1868 address_word vAddr,
1869 unsigned int instruction)
1870 {
1871 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1872 static int icache_warning = 1;
1873 static int dcache_warning = 1;
1874 #else
1875 static int icache_warning = 0;
1876 static int dcache_warning = 0;
1877 #endif
1878
1879 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1880 enable bit in the Status Register is clear - a coprocessor
1881 unusable exception is taken. */
1882 #if 0
1883 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
1884 #endif
1885
1886 switch (op & 0x3) {
1887 case 0: /* instruction cache */
1888 switch (op >> 2) {
1889 case 0: /* Index Invalidate */
1890 case 1: /* Index Load Tag */
1891 case 2: /* Index Store Tag */
1892 case 4: /* Hit Invalidate */
1893 case 5: /* Fill */
1894 case 6: /* Hit Writeback */
1895 if (!icache_warning)
1896 {
1897 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
1898 icache_warning = 1;
1899 }
1900 break;
1901
1902 default:
1903 SignalException(ReservedInstruction,instruction);
1904 break;
1905 }
1906 break;
1907
1908 case 1: /* data cache */
1909 switch (op >> 2) {
1910 case 0: /* Index Writeback Invalidate */
1911 case 1: /* Index Load Tag */
1912 case 2: /* Index Store Tag */
1913 case 3: /* Create Dirty */
1914 case 4: /* Hit Invalidate */
1915 case 5: /* Hit Writeback Invalidate */
1916 case 6: /* Hit Writeback */
1917 if (!dcache_warning)
1918 {
1919 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
1920 dcache_warning = 1;
1921 }
1922 break;
1923
1924 default:
1925 SignalException(ReservedInstruction,instruction);
1926 break;
1927 }
1928 break;
1929
1930 default: /* unrecognised cache ID */
1931 SignalException(ReservedInstruction,instruction);
1932 break;
1933 }
1934
1935 return;
1936 }
1937
1938 /*-- FPU support routines ---------------------------------------------------*/
1939
1940 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1941 formats conform to ANSI/IEEE Std 754-1985. */
1942 /* SINGLE precision floating:
1943 * seeeeeeeefffffffffffffffffffffff
1944 * s = 1bit = sign
1945 * e = 8bits = exponent
1946 * f = 23bits = fraction
1947 */
1948 /* SINGLE precision fixed:
1949 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1950 * s = 1bit = sign
1951 * i = 31bits = integer
1952 */
1953 /* DOUBLE precision floating:
1954 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1955 * s = 1bit = sign
1956 * e = 11bits = exponent
1957 * f = 52bits = fraction
1958 */
1959 /* DOUBLE precision fixed:
1960 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1961 * s = 1bit = sign
1962 * i = 63bits = integer
1963 */
1964
1965 /* Extract sign-bit: */
1966 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1967 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1968 /* Extract biased exponent: */
1969 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1970 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1971 /* Extract unbiased Exponent: */
1972 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1973 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1974 /* Extract complete fraction field: */
1975 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1976 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1977 /* Extract numbered fraction bit: */
1978 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1979 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1980
1981 /* Explicit QNaN values used when value required: */
1982 #define FPQNaN_SINGLE (0x7FBFFFFF)
1983 #define FPQNaN_WORD (0x7FFFFFFF)
1984 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1985 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1986
1987 /* Explicit Infinity values used when required: */
1988 #define FPINF_SINGLE (0x7F800000)
1989 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1990
1991 #if 1 /* def DEBUG */
1992 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1993 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1994 #endif /* DEBUG */
1995
1996 uword64
1997 value_fpr (SIM_DESC sd,
1998 sim_cpu *cpu,
1999 address_word cia,
2000 int fpr,
2001 FP_formats fmt)
2002 {
2003 uword64 value = 0;
2004 int err = 0;
2005
2006 /* Treat unused register values, as fixed-point 64bit values: */
2007 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
2008 #if 1
2009 /* If request to read data as "uninterpreted", then use the current
2010 encoding: */
2011 fmt = FPR_STATE[fpr];
2012 #else
2013 fmt = fmt_long;
2014 #endif
2015
2016 /* For values not yet accessed, set to the desired format: */
2017 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2018 FPR_STATE[fpr] = fmt;
2019 #ifdef DEBUG
2020 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2021 #endif /* DEBUG */
2022 }
2023 if (fmt != FPR_STATE[fpr]) {
2024 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2025 FPR_STATE[fpr] = fmt_unknown;
2026 }
2027
2028 if (FPR_STATE[fpr] == fmt_unknown) {
2029 /* Set QNaN value: */
2030 switch (fmt) {
2031 case fmt_single:
2032 value = FPQNaN_SINGLE;
2033 break;
2034
2035 case fmt_double:
2036 value = FPQNaN_DOUBLE;
2037 break;
2038
2039 case fmt_word:
2040 value = FPQNaN_WORD;
2041 break;
2042
2043 case fmt_long:
2044 value = FPQNaN_LONG;
2045 break;
2046
2047 default:
2048 err = -1;
2049 break;
2050 }
2051 } else if (SizeFGR() == 64) {
2052 switch (fmt) {
2053 case fmt_single:
2054 case fmt_word:
2055 value = (FGR[fpr] & 0xFFFFFFFF);
2056 break;
2057
2058 case fmt_uninterpreted:
2059 case fmt_double:
2060 case fmt_long:
2061 value = FGR[fpr];
2062 break;
2063
2064 default :
2065 err = -1;
2066 break;
2067 }
2068 } else {
2069 switch (fmt) {
2070 case fmt_single:
2071 case fmt_word:
2072 value = (FGR[fpr] & 0xFFFFFFFF);
2073 break;
2074
2075 case fmt_uninterpreted:
2076 case fmt_double:
2077 case fmt_long:
2078 if ((fpr & 1) == 0) { /* even registers only */
2079 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2080 } else {
2081 SignalException(ReservedInstruction,0);
2082 }
2083 break;
2084
2085 default :
2086 err = -1;
2087 break;
2088 }
2089 }
2090
2091 if (err)
2092 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2093
2094 #ifdef DEBUG
2095 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2096 #endif /* DEBUG */
2097
2098 return(value);
2099 }
2100
2101 void
2102 store_fpr (SIM_DESC sd,
2103 sim_cpu *cpu,
2104 address_word cia,
2105 int fpr,
2106 FP_formats fmt,
2107 uword64 value)
2108 {
2109 int err = 0;
2110
2111 #ifdef DEBUG
2112 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2113 #endif /* DEBUG */
2114
2115 if (SizeFGR() == 64) {
2116 switch (fmt) {
2117 case fmt_uninterpreted_32:
2118 fmt = fmt_uninterpreted;
2119 case fmt_single :
2120 case fmt_word :
2121 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2122 FPR_STATE[fpr] = fmt;
2123 break;
2124
2125 case fmt_uninterpreted_64:
2126 fmt = fmt_uninterpreted;
2127 case fmt_uninterpreted:
2128 case fmt_double :
2129 case fmt_long :
2130 FGR[fpr] = value;
2131 FPR_STATE[fpr] = fmt;
2132 break;
2133
2134 default :
2135 FPR_STATE[fpr] = fmt_unknown;
2136 err = -1;
2137 break;
2138 }
2139 } else {
2140 switch (fmt) {
2141 case fmt_uninterpreted_32:
2142 fmt = fmt_uninterpreted;
2143 case fmt_single :
2144 case fmt_word :
2145 FGR[fpr] = (value & 0xFFFFFFFF);
2146 FPR_STATE[fpr] = fmt;
2147 break;
2148
2149 case fmt_uninterpreted_64:
2150 fmt = fmt_uninterpreted;
2151 case fmt_uninterpreted:
2152 case fmt_double :
2153 case fmt_long :
2154 if ((fpr & 1) == 0) { /* even register number only */
2155 FGR[fpr+1] = (value >> 32);
2156 FGR[fpr] = (value & 0xFFFFFFFF);
2157 FPR_STATE[fpr + 1] = fmt;
2158 FPR_STATE[fpr] = fmt;
2159 } else {
2160 FPR_STATE[fpr] = fmt_unknown;
2161 FPR_STATE[fpr + 1] = fmt_unknown;
2162 SignalException(ReservedInstruction,0);
2163 }
2164 break;
2165
2166 default :
2167 FPR_STATE[fpr] = fmt_unknown;
2168 err = -1;
2169 break;
2170 }
2171 }
2172 #if defined(WARN_RESULT)
2173 else
2174 UndefinedResult();
2175 #endif /* WARN_RESULT */
2176
2177 if (err)
2178 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2179
2180 #ifdef DEBUG
2181 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2182 #endif /* DEBUG */
2183
2184 return;
2185 }
2186
2187 int
2188 NaN(op,fmt)
2189 uword64 op;
2190 FP_formats fmt;
2191 {
2192 int boolean = 0;
2193 switch (fmt) {
2194 case fmt_single:
2195 case fmt_word:
2196 {
2197 sim_fpu wop;
2198 sim_fpu_32to (&wop, op);
2199 boolean = sim_fpu_is_nan (&wop);
2200 break;
2201 }
2202 case fmt_double:
2203 case fmt_long:
2204 {
2205 sim_fpu wop;
2206 sim_fpu_64to (&wop, op);
2207 boolean = sim_fpu_is_nan (&wop);
2208 break;
2209 }
2210 default:
2211 fprintf (stderr, "Bad switch\n");
2212 abort ();
2213 }
2214
2215 #ifdef DEBUG
2216 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2217 #endif /* DEBUG */
2218
2219 return(boolean);
2220 }
2221
2222 int
2223 Infinity(op,fmt)
2224 uword64 op;
2225 FP_formats fmt;
2226 {
2227 int boolean = 0;
2228
2229 #ifdef DEBUG
2230 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2231 #endif /* DEBUG */
2232
2233 switch (fmt) {
2234 case fmt_single:
2235 {
2236 sim_fpu wop;
2237 sim_fpu_32to (&wop, op);
2238 boolean = sim_fpu_is_infinity (&wop);
2239 break;
2240 }
2241 case fmt_double:
2242 {
2243 sim_fpu wop;
2244 sim_fpu_64to (&wop, op);
2245 boolean = sim_fpu_is_infinity (&wop);
2246 break;
2247 }
2248 default:
2249 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2250 break;
2251 }
2252
2253 #ifdef DEBUG
2254 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2255 #endif /* DEBUG */
2256
2257 return(boolean);
2258 }
2259
2260 int
2261 Less(op1,op2,fmt)
2262 uword64 op1;
2263 uword64 op2;
2264 FP_formats fmt;
2265 {
2266 int boolean = 0;
2267
2268 /* Argument checking already performed by the FPCOMPARE code */
2269
2270 #ifdef DEBUG
2271 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2272 #endif /* DEBUG */
2273
2274 /* The format type should already have been checked: */
2275 switch (fmt) {
2276 case fmt_single:
2277 {
2278 sim_fpu wop1;
2279 sim_fpu wop2;
2280 sim_fpu_32to (&wop1, op1);
2281 sim_fpu_32to (&wop2, op2);
2282 boolean = sim_fpu_is_lt (&wop1, &wop2);
2283 break;
2284 }
2285 case fmt_double:
2286 {
2287 sim_fpu wop1;
2288 sim_fpu wop2;
2289 sim_fpu_64to (&wop1, op1);
2290 sim_fpu_64to (&wop2, op2);
2291 boolean = sim_fpu_is_lt (&wop1, &wop2);
2292 break;
2293 }
2294 default:
2295 fprintf (stderr, "Bad switch\n");
2296 abort ();
2297 }
2298
2299 #ifdef DEBUG
2300 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2301 #endif /* DEBUG */
2302
2303 return(boolean);
2304 }
2305
2306 int
2307 Equal(op1,op2,fmt)
2308 uword64 op1;
2309 uword64 op2;
2310 FP_formats fmt;
2311 {
2312 int boolean = 0;
2313
2314 /* Argument checking already performed by the FPCOMPARE code */
2315
2316 #ifdef DEBUG
2317 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2318 #endif /* DEBUG */
2319
2320 /* The format type should already have been checked: */
2321 switch (fmt) {
2322 case fmt_single:
2323 {
2324 sim_fpu wop1;
2325 sim_fpu wop2;
2326 sim_fpu_32to (&wop1, op1);
2327 sim_fpu_32to (&wop2, op2);
2328 boolean = sim_fpu_is_eq (&wop1, &wop2);
2329 break;
2330 }
2331 case fmt_double:
2332 {
2333 sim_fpu wop1;
2334 sim_fpu wop2;
2335 sim_fpu_64to (&wop1, op1);
2336 sim_fpu_64to (&wop2, op2);
2337 boolean = sim_fpu_is_eq (&wop1, &wop2);
2338 break;
2339 }
2340 default:
2341 fprintf (stderr, "Bad switch\n");
2342 abort ();
2343 }
2344
2345 #ifdef DEBUG
2346 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2347 #endif /* DEBUG */
2348
2349 return(boolean);
2350 }
2351
2352 uword64
2353 AbsoluteValue(op,fmt)
2354 uword64 op;
2355 FP_formats fmt;
2356 {
2357 uword64 result = 0;
2358
2359 #ifdef DEBUG
2360 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2361 #endif /* DEBUG */
2362
2363 /* The format type should already have been checked: */
2364 switch (fmt) {
2365 case fmt_single:
2366 {
2367 sim_fpu wop;
2368 unsigned32 ans;
2369 sim_fpu_32to (&wop, op);
2370 sim_fpu_abs (&wop, &wop);
2371 sim_fpu_to32 (&ans, &wop);
2372 result = ans;
2373 break;
2374 }
2375 case fmt_double:
2376 {
2377 sim_fpu wop;
2378 unsigned64 ans;
2379 sim_fpu_64to (&wop, op);
2380 sim_fpu_abs (&wop, &wop);
2381 sim_fpu_to64 (&ans, &wop);
2382 result = ans;
2383 break;
2384 }
2385 default:
2386 fprintf (stderr, "Bad switch\n");
2387 abort ();
2388 }
2389
2390 return(result);
2391 }
2392
2393 uword64
2394 Negate(op,fmt)
2395 uword64 op;
2396 FP_formats fmt;
2397 {
2398 uword64 result = 0;
2399
2400 #ifdef DEBUG
2401 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2402 #endif /* DEBUG */
2403
2404 /* The format type should already have been checked: */
2405 switch (fmt) {
2406 case fmt_single:
2407 {
2408 sim_fpu wop;
2409 unsigned32 ans;
2410 sim_fpu_32to (&wop, op);
2411 sim_fpu_neg (&wop, &wop);
2412 sim_fpu_to32 (&ans, &wop);
2413 result = ans;
2414 break;
2415 }
2416 case fmt_double:
2417 {
2418 sim_fpu wop;
2419 unsigned64 ans;
2420 sim_fpu_64to (&wop, op);
2421 sim_fpu_neg (&wop, &wop);
2422 sim_fpu_to64 (&ans, &wop);
2423 result = ans;
2424 break;
2425 }
2426 default:
2427 fprintf (stderr, "Bad switch\n");
2428 abort ();
2429 }
2430
2431 return(result);
2432 }
2433
2434 uword64
2435 Add(op1,op2,fmt)
2436 uword64 op1;
2437 uword64 op2;
2438 FP_formats fmt;
2439 {
2440 uword64 result = 0;
2441
2442 #ifdef DEBUG
2443 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2444 #endif /* DEBUG */
2445
2446 /* The registers must specify FPRs valid for operands of type
2447 "fmt". If they are not valid, the result is undefined. */
2448
2449 /* The format type should already have been checked: */
2450 switch (fmt) {
2451 case fmt_single:
2452 {
2453 sim_fpu wop1;
2454 sim_fpu wop2;
2455 sim_fpu ans;
2456 unsigned32 res;
2457 sim_fpu_32to (&wop1, op1);
2458 sim_fpu_32to (&wop2, op2);
2459 sim_fpu_add (&ans, &wop1, &wop2);
2460 sim_fpu_to32 (&res, &ans);
2461 result = res;
2462 break;
2463 }
2464 case fmt_double:
2465 {
2466 sim_fpu wop1;
2467 sim_fpu wop2;
2468 sim_fpu ans;
2469 unsigned64 res;
2470 sim_fpu_64to (&wop1, op1);
2471 sim_fpu_64to (&wop2, op2);
2472 sim_fpu_add (&ans, &wop1, &wop2);
2473 sim_fpu_to64 (&res, &ans);
2474 result = res;
2475 break;
2476 }
2477 default:
2478 fprintf (stderr, "Bad switch\n");
2479 abort ();
2480 }
2481
2482 #ifdef DEBUG
2483 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2484 #endif /* DEBUG */
2485
2486 return(result);
2487 }
2488
2489 uword64
2490 Sub(op1,op2,fmt)
2491 uword64 op1;
2492 uword64 op2;
2493 FP_formats fmt;
2494 {
2495 uword64 result = 0;
2496
2497 #ifdef DEBUG
2498 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2499 #endif /* DEBUG */
2500
2501 /* The registers must specify FPRs valid for operands of type
2502 "fmt". If they are not valid, the result is undefined. */
2503
2504 /* The format type should already have been checked: */
2505 switch (fmt) {
2506 case fmt_single:
2507 {
2508 sim_fpu wop1;
2509 sim_fpu wop2;
2510 sim_fpu ans;
2511 unsigned32 res;
2512 sim_fpu_32to (&wop1, op1);
2513 sim_fpu_32to (&wop2, op2);
2514 sim_fpu_sub (&ans, &wop1, &wop2);
2515 sim_fpu_to32 (&res, &ans);
2516 result = res;
2517 }
2518 break;
2519 case fmt_double:
2520 {
2521 sim_fpu wop1;
2522 sim_fpu wop2;
2523 sim_fpu ans;
2524 unsigned64 res;
2525 sim_fpu_64to (&wop1, op1);
2526 sim_fpu_64to (&wop2, op2);
2527 sim_fpu_sub (&ans, &wop1, &wop2);
2528 sim_fpu_to64 (&res, &ans);
2529 result = res;
2530 }
2531 break;
2532 default:
2533 fprintf (stderr, "Bad switch\n");
2534 abort ();
2535 }
2536
2537 #ifdef DEBUG
2538 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2539 #endif /* DEBUG */
2540
2541 return(result);
2542 }
2543
2544 uword64
2545 Multiply(op1,op2,fmt)
2546 uword64 op1;
2547 uword64 op2;
2548 FP_formats fmt;
2549 {
2550 uword64 result = 0;
2551
2552 #ifdef DEBUG
2553 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2554 #endif /* DEBUG */
2555
2556 /* The registers must specify FPRs valid for operands of type
2557 "fmt". If they are not valid, the result is undefined. */
2558
2559 /* The format type should already have been checked: */
2560 switch (fmt) {
2561 case fmt_single:
2562 {
2563 sim_fpu wop1;
2564 sim_fpu wop2;
2565 sim_fpu ans;
2566 unsigned32 res;
2567 sim_fpu_32to (&wop1, op1);
2568 sim_fpu_32to (&wop2, op2);
2569 sim_fpu_mul (&ans, &wop1, &wop2);
2570 sim_fpu_to32 (&res, &ans);
2571 result = res;
2572 break;
2573 }
2574 case fmt_double:
2575 {
2576 sim_fpu wop1;
2577 sim_fpu wop2;
2578 sim_fpu ans;
2579 unsigned64 res;
2580 sim_fpu_64to (&wop1, op1);
2581 sim_fpu_64to (&wop2, op2);
2582 sim_fpu_mul (&ans, &wop1, &wop2);
2583 sim_fpu_to64 (&res, &ans);
2584 result = res;
2585 break;
2586 }
2587 default:
2588 fprintf (stderr, "Bad switch\n");
2589 abort ();
2590 }
2591
2592 #ifdef DEBUG
2593 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2594 #endif /* DEBUG */
2595
2596 return(result);
2597 }
2598
2599 uword64
2600 Divide(op1,op2,fmt)
2601 uword64 op1;
2602 uword64 op2;
2603 FP_formats fmt;
2604 {
2605 uword64 result = 0;
2606
2607 #ifdef DEBUG
2608 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2609 #endif /* DEBUG */
2610
2611 /* The registers must specify FPRs valid for operands of type
2612 "fmt". If they are not valid, the result is undefined. */
2613
2614 /* The format type should already have been checked: */
2615 switch (fmt) {
2616 case fmt_single:
2617 {
2618 sim_fpu wop1;
2619 sim_fpu wop2;
2620 sim_fpu ans;
2621 unsigned32 res;
2622 sim_fpu_32to (&wop1, op1);
2623 sim_fpu_32to (&wop2, op2);
2624 sim_fpu_div (&ans, &wop1, &wop2);
2625 sim_fpu_to32 (&res, &ans);
2626 result = res;
2627 break;
2628 }
2629 case fmt_double:
2630 {
2631 sim_fpu wop1;
2632 sim_fpu wop2;
2633 sim_fpu ans;
2634 unsigned64 res;
2635 sim_fpu_64to (&wop1, op1);
2636 sim_fpu_64to (&wop2, op2);
2637 sim_fpu_div (&ans, &wop1, &wop2);
2638 sim_fpu_to64 (&res, &ans);
2639 result = res;
2640 break;
2641 }
2642 default:
2643 fprintf (stderr, "Bad switch\n");
2644 abort ();
2645 }
2646
2647 #ifdef DEBUG
2648 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2649 #endif /* DEBUG */
2650
2651 return(result);
2652 }
2653
2654 uword64 UNUSED
2655 Recip(op,fmt)
2656 uword64 op;
2657 FP_formats fmt;
2658 {
2659 uword64 result = 0;
2660
2661 #ifdef DEBUG
2662 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2663 #endif /* DEBUG */
2664
2665 /* The registers must specify FPRs valid for operands of type
2666 "fmt". If they are not valid, the result is undefined. */
2667
2668 /* The format type should already have been checked: */
2669 switch (fmt) {
2670 case fmt_single:
2671 {
2672 sim_fpu wop;
2673 sim_fpu ans;
2674 unsigned32 res;
2675 sim_fpu_32to (&wop, op);
2676 sim_fpu_inv (&ans, &wop);
2677 sim_fpu_to32 (&res, &ans);
2678 result = res;
2679 break;
2680 }
2681 case fmt_double:
2682 {
2683 sim_fpu wop;
2684 sim_fpu ans;
2685 unsigned64 res;
2686 sim_fpu_64to (&wop, op);
2687 sim_fpu_inv (&ans, &wop);
2688 sim_fpu_to64 (&res, &ans);
2689 result = res;
2690 break;
2691 }
2692 default:
2693 fprintf (stderr, "Bad switch\n");
2694 abort ();
2695 }
2696
2697 #ifdef DEBUG
2698 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2699 #endif /* DEBUG */
2700
2701 return(result);
2702 }
2703
2704 uword64
2705 SquareRoot(op,fmt)
2706 uword64 op;
2707 FP_formats fmt;
2708 {
2709 uword64 result = 0;
2710
2711 #ifdef DEBUG
2712 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2713 #endif /* DEBUG */
2714
2715 /* The registers must specify FPRs valid for operands of type
2716 "fmt". If they are not valid, the result is undefined. */
2717
2718 /* The format type should already have been checked: */
2719 switch (fmt) {
2720 case fmt_single:
2721 {
2722 sim_fpu wop;
2723 sim_fpu ans;
2724 unsigned32 res;
2725 sim_fpu_32to (&wop, op);
2726 sim_fpu_sqrt (&ans, &wop);
2727 sim_fpu_to32 (&res, &ans);
2728 result = res;
2729 break;
2730 }
2731 case fmt_double:
2732 {
2733 sim_fpu wop;
2734 sim_fpu ans;
2735 unsigned64 res;
2736 sim_fpu_64to (&wop, op);
2737 sim_fpu_sqrt (&ans, &wop);
2738 sim_fpu_to64 (&res, &ans);
2739 result = res;
2740 break;
2741 }
2742 default:
2743 fprintf (stderr, "Bad switch\n");
2744 abort ();
2745 }
2746
2747 #ifdef DEBUG
2748 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2749 #endif /* DEBUG */
2750
2751 return(result);
2752 }
2753
2754 uword64
2755 convert (SIM_DESC sd,
2756 sim_cpu *cpu,
2757 address_word cia,
2758 int rm,
2759 uword64 op,
2760 FP_formats from,
2761 FP_formats to)
2762 {
2763 sim_fpu wop;
2764 sim_fpu_round round;
2765 unsigned32 result32;
2766 unsigned64 result64;
2767
2768 #ifdef DEBUG
2769 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
2770 #endif /* DEBUG */
2771
2772 switch (rm)
2773 {
2774 case FP_RM_NEAREST:
2775 /* Round result to nearest representable value. When two
2776 representable values are equally near, round to the value
2777 that has a least significant bit of zero (i.e. is even). */
2778 round = sim_fpu_round_near;
2779 break;
2780 case FP_RM_TOZERO:
2781 /* Round result to the value closest to, and not greater in
2782 magnitude than, the result. */
2783 round = sim_fpu_round_zero;
2784 break;
2785 case FP_RM_TOPINF:
2786 /* Round result to the value closest to, and not less than,
2787 the result. */
2788 round = sim_fpu_round_up;
2789 break;
2790
2791 case FP_RM_TOMINF:
2792 /* Round result to the value closest to, and not greater than,
2793 the result. */
2794 round = sim_fpu_round_down;
2795 break;
2796 default:
2797 round = 0;
2798 fprintf (stderr, "Bad switch\n");
2799 abort ();
2800 }
2801
2802 /* Convert the input to sim_fpu internal format */
2803 switch (from)
2804 {
2805 case fmt_double:
2806 sim_fpu_64to (&wop, op);
2807 break;
2808 case fmt_single:
2809 sim_fpu_32to (&wop, op);
2810 break;
2811 case fmt_word:
2812 sim_fpu_i32to (&wop, op, round);
2813 break;
2814 case fmt_long:
2815 sim_fpu_i64to (&wop, op, round);
2816 break;
2817 default:
2818 fprintf (stderr, "Bad switch\n");
2819 abort ();
2820 }
2821
2822 /* Convert sim_fpu format into the output */
2823 /* The value WOP is converted to the destination format, rounding
2824 using mode RM. When the destination is a fixed-point format, then
2825 a source value of Infinity, NaN or one which would round to an
2826 integer outside the fixed point range then an IEEE Invalid
2827 Operation condition is raised. */
2828 switch (to)
2829 {
2830 case fmt_single:
2831 sim_fpu_round_32 (&wop, round, 0);
2832 sim_fpu_to32 (&result32, &wop);
2833 result64 = result32;
2834 break;
2835 case fmt_double:
2836 sim_fpu_round_64 (&wop, round, 0);
2837 sim_fpu_to64 (&result64, &wop);
2838 break;
2839 case fmt_word:
2840 sim_fpu_to32i (&result32, &wop, round);
2841 result64 = result32;
2842 break;
2843 case fmt_long:
2844 sim_fpu_to64i (&result64, &wop, round);
2845 break;
2846 default:
2847 result64 = 0;
2848 fprintf (stderr, "Bad switch\n");
2849 abort ();
2850 }
2851
2852 #ifdef DEBUG
2853 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
2854 #endif /* DEBUG */
2855
2856 return(result64);
2857 }
2858
2859
2860 /*-- co-processor support routines ------------------------------------------*/
2861
2862 static int UNUSED
2863 CoProcPresent(coproc_number)
2864 unsigned int coproc_number;
2865 {
2866 /* Return TRUE if simulator provides a model for the given co-processor number */
2867 return(0);
2868 }
2869
2870 void
2871 cop_lw (SIM_DESC sd,
2872 sim_cpu *cpu,
2873 address_word cia,
2874 int coproc_num,
2875 int coproc_reg,
2876 unsigned int memword)
2877 {
2878 switch (coproc_num)
2879 {
2880 case 1:
2881 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2882 {
2883 #ifdef DEBUG
2884 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2885 #endif
2886 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
2887 FPR_STATE[coproc_reg] = fmt_uninterpreted;
2888 break;
2889 }
2890
2891 default:
2892 #if 0 /* this should be controlled by a configuration option */
2893 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2894 #endif
2895 break;
2896 }
2897
2898 return;
2899 }
2900
2901 void
2902 cop_ld (SIM_DESC sd,
2903 sim_cpu *cpu,
2904 address_word cia,
2905 int coproc_num,
2906 int coproc_reg,
2907 uword64 memword)
2908 {
2909 switch (coproc_num) {
2910 case 1:
2911 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2912 {
2913 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
2914 break;
2915 }
2916
2917 default:
2918 #if 0 /* this message should be controlled by a configuration option */
2919 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2920 #endif
2921 break;
2922 }
2923
2924 return;
2925 }
2926
2927 unsigned int
2928 cop_sw (SIM_DESC sd,
2929 sim_cpu *cpu,
2930 address_word cia,
2931 int coproc_num,
2932 int coproc_reg)
2933 {
2934 unsigned int value = 0;
2935
2936 switch (coproc_num)
2937 {
2938 case 1:
2939 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2940 {
2941 FP_formats hold;
2942 hold = FPR_STATE[coproc_reg];
2943 FPR_STATE[coproc_reg] = fmt_word;
2944 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
2945 FPR_STATE[coproc_reg] = hold;
2946 break;
2947 }
2948
2949 default:
2950 #if 0 /* should be controlled by configuration option */
2951 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2952 #endif
2953 break;
2954 }
2955
2956 return(value);
2957 }
2958
2959 uword64
2960 cop_sd (SIM_DESC sd,
2961 sim_cpu *cpu,
2962 address_word cia,
2963 int coproc_num,
2964 int coproc_reg)
2965 {
2966 uword64 value = 0;
2967 switch (coproc_num)
2968 {
2969 case 1:
2970 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2971 {
2972 value = ValueFPR(coproc_reg,fmt_uninterpreted);
2973 break;
2974 }
2975
2976 default:
2977 #if 0 /* should be controlled by configuration option */
2978 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2979 #endif
2980 break;
2981 }
2982
2983 return(value);
2984 }
2985
2986 void
2987 decode_coproc (SIM_DESC sd,
2988 sim_cpu *cpu,
2989 address_word cia,
2990 unsigned int instruction)
2991 {
2992 int coprocnum = ((instruction >> 26) & 3);
2993
2994 switch (coprocnum)
2995 {
2996 case 0: /* standard CPU control and cache registers */
2997 {
2998 int code = ((instruction >> 21) & 0x1F);
2999 /* R4000 Users Manual (second edition) lists the following CP0
3000 instructions:
3001 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3002 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3003 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3004 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3005 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3006 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3007 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3008 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3009 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3010 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3011 */
3012 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
3013 {
3014 int rt = ((instruction >> 16) & 0x1F);
3015 int rd = ((instruction >> 11) & 0x1F);
3016
3017 switch (rd) /* NOTEs: Standard CP0 registers */
3018 {
3019 /* 0 = Index R4000 VR4100 VR4300 */
3020 /* 1 = Random R4000 VR4100 VR4300 */
3021 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3022 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3023 /* 4 = Context R4000 VR4100 VR4300 */
3024 /* 5 = PageMask R4000 VR4100 VR4300 */
3025 /* 6 = Wired R4000 VR4100 VR4300 */
3026 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3027 /* 9 = Count R4000 VR4100 VR4300 */
3028 /* 10 = EntryHi R4000 VR4100 VR4300 */
3029 /* 11 = Compare R4000 VR4100 VR4300 */
3030 /* 12 = SR R4000 VR4100 VR4300 */
3031 case 12:
3032 if (code == 0x00)
3033 GPR[rt] = SR;
3034 else
3035 SR = GPR[rt];
3036 break;
3037 /* 13 = Cause R4000 VR4100 VR4300 */
3038 case 13:
3039 if (code == 0x00)
3040 GPR[rt] = CAUSE;
3041 else
3042 CAUSE = GPR[rt];
3043 break;
3044 /* 14 = EPC R4000 VR4100 VR4300 */
3045 /* 15 = PRId R4000 VR4100 VR4300 */
3046 #ifdef SUBTARGET_R3900
3047 /* 16 = Debug */
3048 case 16:
3049 if (code == 0x00)
3050 GPR[rt] = Debug;
3051 else
3052 Debug = GPR[rt];
3053 break;
3054 #else
3055 /* 16 = Config R4000 VR4100 VR4300 */
3056 case 16:
3057 if (code == 0x00)
3058 GPR[rt] = C0_CONFIG;
3059 else
3060 C0_CONFIG = GPR[rt];
3061 break;
3062 #endif
3063 #ifdef SUBTARGET_R3900
3064 /* 17 = Debug */
3065 case 17:
3066 if (code == 0x00)
3067 GPR[rt] = DEPC;
3068 else
3069 DEPC = GPR[rt];
3070 break;
3071 #else
3072 /* 17 = LLAddr R4000 VR4100 VR4300 */
3073 #endif
3074 /* 18 = WatchLo R4000 VR4100 VR4300 */
3075 /* 19 = WatchHi R4000 VR4100 VR4300 */
3076 /* 20 = XContext R4000 VR4100 VR4300 */
3077 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3078 /* 27 = CacheErr R4000 VR4100 */
3079 /* 28 = TagLo R4000 VR4100 VR4300 */
3080 /* 29 = TagHi R4000 VR4100 VR4300 */
3081 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3082 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3083 /* CPR[0,rd] = GPR[rt]; */
3084 default:
3085 if (code == 0x00)
3086 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3087 else
3088 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3089 }
3090 }
3091 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3092 {
3093 /* ERET */
3094 if (SR & status_ERL)
3095 {
3096 /* Oops, not yet available */
3097 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3098 PC = EPC;
3099 SR &= ~status_ERL;
3100 }
3101 else
3102 {
3103 PC = EPC;
3104 SR &= ~status_EXL;
3105 }
3106 }
3107 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3108 {
3109 /* RFE */
3110 }
3111 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3112 {
3113 /* DERET */
3114 Debug &= ~Debug_DM;
3115 DELAYSLOT();
3116 DSPC = DEPC;
3117 }
3118 else
3119 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3120 /* TODO: When executing an ERET or RFE instruction we should
3121 clear LLBIT, to ensure that any out-standing atomic
3122 read/modify/write sequence fails. */
3123 }
3124 break;
3125
3126 case 2: /* undefined co-processor */
3127 sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3128 break;
3129
3130 case 1: /* should not occur (FPU co-processor) */
3131 case 3: /* should not occur (FPU co-processor) */
3132 SignalException(ReservedInstruction,instruction);
3133 break;
3134 }
3135
3136 return;
3137 }
3138
3139 /*-- instruction simulation -------------------------------------------------*/
3140
3141 /* When the IGEN simulator is being built, the function below is be
3142 replaced by a generated version. However, WITH_IGEN == 2 indicates
3143 that the fubction below should be compiled but under a different
3144 name (to allow backward compatibility) */
3145
3146 #if (WITH_IGEN != 1)
3147 #if (WITH_IGEN > 1)
3148 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3149 void
3150 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3151 #else
3152 void
3153 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3154 #endif
3155 SIM_DESC sd;
3156 int next_cpu_nr; /* ignore */
3157 int nr_cpus; /* ignore */
3158 int siggnal; /* ignore */
3159 {
3160 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
3161 #if !defined(FASTSIM)
3162 unsigned int pipeline_count = 1;
3163 #endif
3164
3165 #ifdef DEBUG
3166 if (STATE_MEMORY (sd) == NULL) {
3167 printf("DBG: simulate() entered with no memory\n");
3168 exit(1);
3169 }
3170 #endif /* DEBUG */
3171
3172 #if 0 /* Disabled to check that everything works OK */
3173 /* The VR4300 seems to sign-extend the PC on its first
3174 access. However, this may just be because it is currently
3175 configured in 32bit mode. However... */
3176 PC = SIGNEXTEND(PC,32);
3177 #endif
3178
3179 /* main controlling loop */
3180 while (1) {
3181 /* vaddr is slowly being replaced with cia - current instruction
3182 address */
3183 address_word cia = (uword64)PC;
3184 address_word vaddr = cia;
3185 address_word paddr;
3186 int cca;
3187 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3188
3189 #ifdef DEBUG
3190 {
3191 printf("DBG: state = 0x%08X :",state);
3192 if (state & simHALTEX) printf(" simHALTEX");
3193 if (state & simHALTIN) printf(" simHALTIN");
3194 printf("\n");
3195 }
3196 #endif /* DEBUG */
3197
3198 DSSTATE = (STATE & simDELAYSLOT);
3199 #ifdef DEBUG
3200 if (dsstate)
3201 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3202 #endif /* DEBUG */
3203
3204 /* Fetch the next instruction from the simulator memory: */
3205 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3206 if ((vaddr & 1) == 0) {
3207 /* Copy the action of the LW instruction */
3208 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3209 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3210 uword64 value;
3211 unsigned int byte;
3212 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3213 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3214 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3215 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3216 } else {
3217 /* Copy the action of the LH instruction */
3218 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3219 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3220 uword64 value;
3221 unsigned int byte;
3222 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3223 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3224 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3225 paddr & ~ (uword64) 1,
3226 vaddr, isINSTRUCTION, isREAL);
3227 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3228 instruction = ((value >> (8 * byte)) & 0xFFFF);
3229 }
3230 } else {
3231 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3232 exit(1);
3233 }
3234
3235 #ifdef DEBUG
3236 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3237 #endif /* DEBUG */
3238
3239 /* This is required by exception processing, to ensure that we can
3240 cope with exceptions in the delay slots of branches that may
3241 already have changed the PC. */
3242 if ((vaddr & 1) == 0)
3243 PC += 4; /* increment ready for the next fetch */
3244 else
3245 PC += 2;
3246 /* NOTE: If we perform a delay slot change to the PC, this
3247 increment is not requuired. However, it would make the
3248 simulator more complicated to try and avoid this small hit. */
3249
3250 /* Currently this code provides a simple model. For more
3251 complicated models we could perform exception status checks at
3252 this point, and set the simSTOP state as required. This could
3253 also include processing any hardware interrupts raised by any
3254 I/O model attached to the simulator context.
3255
3256 Support for "asynchronous" I/O events within the simulated world
3257 could be providing by managing a counter, and calling a I/O
3258 specific handler when a particular threshold is reached. On most
3259 architectures a decrement and check for zero operation is
3260 usually quicker than an increment and compare. However, the
3261 process of managing a known value decrement to zero, is higher
3262 than the cost of using an explicit value UINT_MAX into the
3263 future. Which system is used will depend on how complicated the
3264 I/O model is, and how much it is likely to affect the simulator
3265 bandwidth.
3266
3267 If events need to be scheduled further in the future than
3268 UINT_MAX event ticks, then the I/O model should just provide its
3269 own counter, triggered from the event system. */
3270
3271 /* MIPS pipeline ticks. To allow for future support where the
3272 pipeline hit of individual instructions is known, this control
3273 loop manages a "pipeline_count" variable. It is initialised to
3274 1 (one), and will only be changed by the simulator engine when
3275 executing an instruction. If the engine does not have access to
3276 pipeline cycle count information then all instructions will be
3277 treated as using a single cycle. NOTE: A standard system is not
3278 provided by the default simulator because different MIPS
3279 architectures have different cycle counts for the same
3280 instructions.
3281
3282 [NOTE: pipeline_count has been replaced the event queue] */
3283
3284 /* shuffle the floating point status pipeline state */
3285 ENGINE_ISSUE_PREFIX_HOOK();
3286
3287 /* NOTE: For multi-context simulation environments the "instruction"
3288 variable should be local to this routine. */
3289
3290 /* Shorthand accesses for engine. Note: If we wanted to use global
3291 variables (and a single-threaded simulator engine), then we can
3292 create the actual variables with these names. */
3293
3294 if (!(STATE & simSKIPNEXT)) {
3295 /* Include the simulator engine */
3296 #include "oengine.c"
3297 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3298 #error "Mismatch between run-time simulator code and simulation engine"
3299 #endif
3300 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3301 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3302 #endif
3303 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3304 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3305 #endif
3306
3307 #if defined(WARN_LOHI)
3308 /* Decrement the HI/LO validity ticks */
3309 if (HIACCESS > 0)
3310 HIACCESS--;
3311 if (LOACCESS > 0)
3312 LOACCESS--;
3313 /* start-sanitize-r5900 */
3314 if (HI1ACCESS > 0)
3315 HI1ACCESS--;
3316 if (LO1ACCESS > 0)
3317 LO1ACCESS--;
3318 /* end-sanitize-r5900 */
3319 #endif /* WARN_LOHI */
3320
3321 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3322 should check for it being changed. It is better doing it here,
3323 than within the simulator, since it will help keep the simulator
3324 small. */
3325 if (ZERO != 0) {
3326 #if defined(WARN_ZERO)
3327 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3328 #endif /* WARN_ZERO */
3329 ZERO = 0; /* reset back to zero before next instruction */
3330 }
3331 } else /* simSKIPNEXT check */
3332 STATE &= ~simSKIPNEXT;
3333
3334 /* If the delay slot was active before the instruction is
3335 executed, then update the PC to its new value: */
3336 if (DSSTATE) {
3337 #ifdef DEBUG
3338 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3339 #endif /* DEBUG */
3340 PC = DSPC;
3341 CANCELDELAYSLOT();
3342 }
3343
3344 if (MIPSISA < 4)
3345 PENDING_TICK();
3346
3347 #if !defined(FASTSIM)
3348 if (sim_events_tickn (sd, pipeline_count))
3349 {
3350 /* cpu->cia = cia; */
3351 sim_events_process (sd);
3352 }
3353 #else
3354 if (sim_events_tick (sd))
3355 {
3356 /* cpu->cia = cia; */
3357 sim_events_process (sd);
3358 }
3359 #endif /* FASTSIM */
3360 }
3361 }
3362 #endif
3363
3364
3365 /* This code copied from gdb's utils.c. Would like to share this code,
3366 but don't know of a common place where both could get to it. */
3367
3368 /* Temporary storage using circular buffer */
3369 #define NUMCELLS 16
3370 #define CELLSIZE 32
3371 static char*
3372 get_cell()
3373 {
3374 static char buf[NUMCELLS][CELLSIZE];
3375 static int cell=0;
3376 if (++cell>=NUMCELLS) cell=0;
3377 return buf[cell];
3378 }
3379
3380 /* Print routines to handle variable size regs, etc */
3381
3382 /* Eliminate warning from compiler on 32-bit systems */
3383 static int thirty_two = 32;
3384
3385 char*
3386 pr_addr(addr)
3387 SIM_ADDR addr;
3388 {
3389 char *paddr_str=get_cell();
3390 switch (sizeof(addr))
3391 {
3392 case 8:
3393 sprintf(paddr_str,"%08lx%08lx",
3394 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3395 break;
3396 case 4:
3397 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3398 break;
3399 case 2:
3400 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3401 break;
3402 default:
3403 sprintf(paddr_str,"%x",addr);
3404 }
3405 return paddr_str;
3406 }
3407
3408 char*
3409 pr_uword64(addr)
3410 uword64 addr;
3411 {
3412 char *paddr_str=get_cell();
3413 sprintf(paddr_str,"%08lx%08lx",
3414 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3415 return paddr_str;
3416 }
3417
3418
3419 void
3420 pending_tick (SIM_DESC sd,
3421 sim_cpu *cpu,
3422 address_word cia)
3423 {
3424 if (PENDING_TRACE)
3425 sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
3426 if (PENDING_OUT != PENDING_IN)
3427 {
3428 int loop;
3429 int index = PENDING_OUT;
3430 int total = PENDING_TOTAL;
3431 if (PENDING_TOTAL == 0)
3432 sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3433 for (loop = 0; (loop < total); loop++)
3434 {
3435 if (PENDING_SLOT_DEST[index] != NULL)
3436 {
3437 PENDING_SLOT_DELAY[index] -= 1;
3438 if (PENDING_SLOT_DELAY[index] == 0)
3439 {
3440 if (PENDING_SLOT_BIT[index] >= 0)
3441 switch (PENDING_SLOT_SIZE[index])
3442 {
3443 case 32:
3444 if (PENDING_SLOT_VALUE[index])
3445 *(unsigned32*)PENDING_SLOT_DEST[index] |=
3446 BIT32 (PENDING_SLOT_BIT[index]);
3447 else
3448 *(unsigned32*)PENDING_SLOT_DEST[index] &=
3449 BIT32 (PENDING_SLOT_BIT[index]);
3450 break;
3451 case 64:
3452 if (PENDING_SLOT_VALUE[index])
3453 *(unsigned64*)PENDING_SLOT_DEST[index] |=
3454 BIT64 (PENDING_SLOT_BIT[index]);
3455 else
3456 *(unsigned64*)PENDING_SLOT_DEST[index] &=
3457 BIT64 (PENDING_SLOT_BIT[index]);
3458 break;
3459 break;
3460 }
3461 else
3462 switch (PENDING_SLOT_SIZE[index])
3463 {
3464 case 32:
3465 *(unsigned32*)PENDING_SLOT_DEST[index] =
3466 PENDING_SLOT_VALUE[index];
3467 break;
3468 case 64:
3469 *(unsigned64*)PENDING_SLOT_DEST[index] =
3470 PENDING_SLOT_VALUE[index];
3471 break;
3472 }
3473 }
3474 if (PENDING_OUT == index)
3475 {
3476 PENDING_SLOT_DEST[index] = NULL;
3477 PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
3478 PENDING_TOTAL--;
3479 }
3480 }
3481 }
3482 index = (index + 1) % PSLOTS;
3483 }
3484 }
3485
3486 /*---------------------------------------------------------------------------*/
3487 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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