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sim: overhaul alignment settings management
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 NOTEs:
17
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
21 code on the hardware.
22
23 */
24
25 /* This must come before any other includes. */
26 #include "defs.h"
27
28 #include "bfd.h"
29 #include "sim-main.h"
30 #include "sim-utils.h"
31 #include "sim-options.h"
32 #include "sim-assert.h"
33 #include "sim-hw.h"
34
35 #include "itable.h"
36
37 #include <stdio.h>
38 #include <stdarg.h>
39 #include <ansidecl.h>
40 #include <ctype.h>
41 #include <limits.h>
42 #include <math.h>
43 #include <stdlib.h>
44 #include <string.h>
45
46 #include "getopt.h"
47 #include "libiberty.h"
48 #include "bfd.h"
49 #include "elf-bfd.h"
50 #include "sim/callback.h" /* GDB simulator callback interface */
51 #include "sim/sim.h" /* GDB simulator interface */
52 #include "sim-syscall.h" /* Simulator system call support */
53
54 char* pr_addr (SIM_ADDR addr);
55 char* pr_uword64 (uword64 addr);
56
57
58 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
59 #define CPU cpu
60 #define SD sd
61
62
63 /* The following reserved instruction value is used when a simulator
64 trap is required. NOTE: Care must be taken, since this value may be
65 used in later revisions of the MIPS ISA. */
66
67 #define RSVD_INSTRUCTION (0x00000039)
68 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
69
70 #define RSVD_INSTRUCTION_ARG_SHIFT 6
71 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
72
73
74 /* Bits in the Debug register */
75 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
76 #define Debug_DM 0x40000000 /* Debug Mode */
77 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
78
79 /*---------------------------------------------------------------------------*/
80 /*-- GDB simulator interface ------------------------------------------------*/
81 /*---------------------------------------------------------------------------*/
82
83 static void ColdReset (SIM_DESC sd);
84
85 /*---------------------------------------------------------------------------*/
86
87
88
89 #define DELAYSLOT() {\
90 if (STATE & simDELAYSLOT)\
91 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
92 STATE |= simDELAYSLOT;\
93 }
94
95 #define JALDELAYSLOT() {\
96 DELAYSLOT ();\
97 STATE |= simJALDELAYSLOT;\
98 }
99
100 #define NULLIFY() {\
101 STATE &= ~simDELAYSLOT;\
102 STATE |= simSKIPNEXT;\
103 }
104
105 #define CANCELDELAYSLOT() {\
106 DSSTATE = 0;\
107 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
108 }
109
110 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
111 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
112
113 /* Note that the monitor code essentially assumes this layout of memory.
114 If you change these, change the monitor code, too. */
115 /* FIXME Currently addresses are truncated to 32-bits, see
116 mips/sim-main.c:address_translation(). If that changes, then these
117 values will need to be extended, and tested for more carefully. */
118 #define K0BASE (0x80000000)
119 #define K0SIZE (0x20000000)
120 #define K1BASE (0xA0000000)
121 #define K1SIZE (0x20000000)
122
123 /* Simple run-time monitor support.
124
125 We emulate the monitor by placing magic reserved instructions at
126 the monitor's entry points; when we hit these instructions, instead
127 of raising an exception (as we would normally), we look at the
128 instruction and perform the appropriate monitory operation.
129
130 `*_monitor_base' are the physical addresses at which the corresponding
131 monitor vectors are located. `0' means none. By default,
132 install all three.
133 The RSVD_INSTRUCTION... macros specify the magic instructions we
134 use at the monitor entry points. */
135 static int firmware_option_p = 0;
136 static SIM_ADDR idt_monitor_base = 0xBFC00000;
137 static SIM_ADDR pmon_monitor_base = 0xBFC00500;
138 static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
139
140 static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
141
142 #define MEM_SIZE (8 << 20) /* 8 MBytes */
143
144
145 #if WITH_TRACE_ANY_P
146 static char *tracefile = "trace.din"; /* default filename for trace log */
147 FILE *tracefh = NULL;
148 static void open_trace (SIM_DESC sd);
149 #else
150 #define open_trace(sd)
151 #endif
152
153 static const char * get_insn_name (sim_cpu *, int);
154
155 /* simulation target board. NULL=canonical */
156 static char* board = NULL;
157
158
159 static DECLARE_OPTION_HANDLER (mips_option_handler);
160
161 enum {
162 OPTION_DINERO_TRACE = OPTION_START,
163 OPTION_DINERO_FILE,
164 OPTION_FIRMWARE,
165 OPTION_INFO_MEMORY,
166 OPTION_BOARD
167 };
168
169 static int display_mem_info = 0;
170
171 static SIM_RC
172 mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
173 int is_command)
174 {
175 int cpu_nr;
176 switch (opt)
177 {
178 case OPTION_DINERO_TRACE: /* ??? */
179 #if WITH_TRACE_ANY_P
180 /* Eventually the simTRACE flag could be treated as a toggle, to
181 allow external control of the program points being traced
182 (i.e. only from main onwards, excluding the run-time setup,
183 etc.). */
184 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
185 {
186 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
187 if (arg == NULL)
188 STATE |= simTRACE;
189 else if (strcmp (arg, "yes") == 0)
190 STATE |= simTRACE;
191 else if (strcmp (arg, "no") == 0)
192 STATE &= ~simTRACE;
193 else if (strcmp (arg, "on") == 0)
194 STATE |= simTRACE;
195 else if (strcmp (arg, "off") == 0)
196 STATE &= ~simTRACE;
197 else
198 {
199 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
200 return SIM_RC_FAIL;
201 }
202 }
203 return SIM_RC_OK;
204 #else /* !WITH_TRACE_ANY_P */
205 fprintf(stderr,"\
206 Simulator constructed without dinero tracing support (for performance).\n\
207 Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
208 return SIM_RC_FAIL;
209 #endif /* !WITH_TRACE_ANY_P */
210
211 case OPTION_DINERO_FILE:
212 #if WITH_TRACE_ANY_P
213 if (optarg != NULL) {
214 char *tmp;
215 tmp = (char *)malloc(strlen(optarg) + 1);
216 if (tmp == NULL)
217 {
218 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
219 return SIM_RC_FAIL;
220 }
221 else {
222 strcpy(tmp,optarg);
223 tracefile = tmp;
224 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
225 }
226 }
227 #endif /* WITH_TRACE_ANY_P */
228 return SIM_RC_OK;
229
230 case OPTION_FIRMWARE:
231 return sim_firmware_command (sd, arg);
232
233 case OPTION_BOARD:
234 {
235 if (arg)
236 {
237 board = zalloc(strlen(arg) + 1);
238 strcpy(board, arg);
239 }
240 return SIM_RC_OK;
241 }
242
243 case OPTION_INFO_MEMORY:
244 display_mem_info = 1;
245 break;
246 }
247
248 return SIM_RC_OK;
249 }
250
251
252 static const OPTION mips_options[] =
253 {
254 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
255 '\0', "on|off", "Enable dinero tracing",
256 mips_option_handler },
257 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
258 '\0', "FILE", "Write dinero trace to FILE",
259 mips_option_handler },
260 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
261 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
262 mips_option_handler },
263 { {"board", required_argument, NULL, OPTION_BOARD},
264 '\0', "none" /* rely on compile-time string concatenation for other options */
265
266 #define BOARD_JMR3904 "jmr3904"
267 "|" BOARD_JMR3904
268 #define BOARD_JMR3904_PAL "jmr3904pal"
269 "|" BOARD_JMR3904_PAL
270 #define BOARD_JMR3904_DEBUG "jmr3904debug"
271 "|" BOARD_JMR3904_DEBUG
272 #define BOARD_BSP "bsp"
273 "|" BOARD_BSP
274
275 , "Customize simulation for a particular board.", mips_option_handler },
276
277 /* These next two options have the same names as ones found in the
278 memory_options[] array in common/sim-memopt.c. This is because
279 the intention is to provide an alternative handler for those two
280 options. We need an alternative handler because the memory
281 regions are not set up until after the command line arguments
282 have been parsed, and so we cannot display the memory info whilst
283 processing the command line. There is a hack in sim_open to
284 remove these handlers when we want the real --memory-info option
285 to work. */
286 { { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
287 '\0', NULL, "List configured memory regions", mips_option_handler },
288 { { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
289 '\0', NULL, NULL, mips_option_handler },
290
291 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
292 };
293
294
295 int interrupt_pending;
296
297 void
298 interrupt_event (SIM_DESC sd, void *data)
299 {
300 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
301 address_word cia = CPU_PC_GET (cpu);
302 if (SR & status_IE)
303 {
304 interrupt_pending = 0;
305 SignalExceptionInterrupt (1); /* interrupt "1" */
306 }
307 else if (!interrupt_pending)
308 sim_events_schedule (sd, 1, interrupt_event, data);
309 }
310
311
312 /*---------------------------------------------------------------------------*/
313 /*-- Device registration hook -----------------------------------------------*/
314 /*---------------------------------------------------------------------------*/
315 static void device_init(SIM_DESC sd) {
316 #ifdef DEVICE_INIT
317 extern void register_devices(SIM_DESC);
318 register_devices(sd);
319 #endif
320 }
321
322 /*---------------------------------------------------------------------------*/
323 /*-- GDB simulator interface ------------------------------------------------*/
324 /*---------------------------------------------------------------------------*/
325
326 static sim_cia
327 mips_pc_get (sim_cpu *cpu)
328 {
329 return PC;
330 }
331
332 static void
333 mips_pc_set (sim_cpu *cpu, sim_cia pc)
334 {
335 PC = pc;
336 }
337
338 static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
339 static int mips_reg_store (SIM_CPU *, int, unsigned char *, int);
340
341 SIM_DESC
342 sim_open (SIM_OPEN_KIND kind, host_callback *cb,
343 struct bfd *abfd, char * const *argv)
344 {
345 int i;
346 SIM_DESC sd = sim_state_alloc_extra (kind, cb,
347 sizeof (struct mips_sim_state));
348 sim_cpu *cpu;
349
350 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
351
352 /* The cpu data is kept in a separately allocated chunk of memory. */
353 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
354 return 0;
355
356 cpu = STATE_CPU (sd, 0); /* FIXME */
357
358 /* FIXME: watchpoints code shouldn't need this */
359 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
360
361 /* Initialize the mechanism for doing insn profiling. */
362 CPU_INSN_NAME (cpu) = get_insn_name;
363 CPU_MAX_INSNS (cpu) = nr_itable_entries;
364
365 STATE = 0;
366
367 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
368 return 0;
369 sim_add_option_table (sd, NULL, mips_options);
370
371
372 /* The parser will print an error message for us, so we silently return. */
373 if (sim_parse_args (sd, argv) != SIM_RC_OK)
374 {
375 /* Uninstall the modules to avoid memory leaks,
376 file descriptor leaks, etc. */
377 sim_module_uninstall (sd);
378 return 0;
379 }
380
381 /* handle board-specific memory maps */
382 if (board == NULL)
383 {
384 /* Allocate core managed memory */
385 sim_memopt *entry, *match = NULL;
386 address_word mem_size = 0;
387 int mapped = 0;
388
389 /* For compatibility with the old code - under this (at level one)
390 are the kernel spaces K0 & K1. Both of these map to a single
391 smaller sub region */
392 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
393
394 /* Look for largest memory region defined on command-line at
395 phys address 0. */
396 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
397 {
398 /* If we find an entry at address 0, then we will end up
399 allocating a new buffer in the "memory alias" command
400 below. The region at address 0 will be deleted. */
401 address_word size = (entry->modulo != 0
402 ? entry->modulo : entry->nr_bytes);
403 if (entry->addr == 0
404 && (!match || entry->level < match->level))
405 match = entry;
406 else if (entry->addr == K0BASE || entry->addr == K1BASE)
407 mapped = 1;
408 else
409 {
410 sim_memopt *alias;
411 for (alias = entry->alias; alias != NULL; alias = alias->next)
412 {
413 if (alias->addr == 0
414 && (!match || entry->level < match->level))
415 match = entry;
416 else if (alias->addr == K0BASE || alias->addr == K1BASE)
417 mapped = 1;
418 }
419 }
420 }
421
422 if (!mapped)
423 {
424 if (match)
425 {
426 /* Get existing memory region size. */
427 mem_size = (match->modulo != 0
428 ? match->modulo : match->nr_bytes);
429 /* Delete old region. */
430 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
431 match->space, match->addr, match->level);
432 }
433 else if (mem_size == 0)
434 mem_size = MEM_SIZE;
435 /* Limit to KSEG1 size (512MB) */
436 if (mem_size > K1SIZE)
437 mem_size = K1SIZE;
438 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
439 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
440 K1BASE, K1SIZE, (long)mem_size, K0BASE);
441 if (WITH_TARGET_WORD_BITSIZE == 64)
442 sim_do_commandf (sd, "memory alias 0x%x,0x%" PRIxTW ",0x%" PRIxTA,
443 (K0BASE), mem_size, EXTENDED(K0BASE));
444 }
445
446 device_init(sd);
447 }
448 else if (board != NULL
449 && (strcmp(board, BOARD_BSP) == 0))
450 {
451 int i;
452
453 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
454
455 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
456 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
457 0x9FC00000,
458 4 * 1024 * 1024, /* 4 MB */
459 0xBFC00000);
460
461 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
462 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
463 0x80000000,
464 4 * 1024 * 1024, /* 4 MB */
465 0xA0000000);
466
467 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
468 for (i=0; i<8; i++) /* 32 MB total */
469 {
470 unsigned size = 4 * 1024 * 1024; /* 4 MB */
471 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
472 0x88000000 + (i * size),
473 size,
474 0xA8000000 + (i * size));
475 }
476 }
477 #if (WITH_HW)
478 else if (board != NULL
479 && (strcmp(board, BOARD_JMR3904) == 0 ||
480 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
481 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
482 {
483 /* match VIRTUAL memory layout of JMR-TX3904 board */
484 int i;
485
486 /* --- disable monitor unless forced on by user --- */
487
488 if (! firmware_option_p)
489 {
490 idt_monitor_base = 0;
491 pmon_monitor_base = 0;
492 lsipmon_monitor_base = 0;
493 }
494
495 /* --- environment --- */
496
497 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
498
499 /* --- memory --- */
500
501 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
502 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
503 0x9FC00000,
504 4 * 1024 * 1024, /* 4 MB */
505 0xBFC00000);
506
507 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
508 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
509 0x80000000,
510 4 * 1024 * 1024, /* 4 MB */
511 0xA0000000);
512
513 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
514 for (i=0; i<8; i++) /* 32 MB total */
515 {
516 unsigned size = 4 * 1024 * 1024; /* 4 MB */
517 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
518 0x88000000 + (i * size),
519 size,
520 0xA8000000 + (i * size));
521 }
522
523 /* Dummy memory regions for unsimulated devices - sorted by address */
524
525 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
526 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
527 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
528 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
529 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
530 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
531 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
532 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
533 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
534
535
536 /* --- simulated devices --- */
537 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
538 sim_hw_parse (sd, "/tx3904cpu");
539 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
540 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
541 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
542 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
543 {
544 /* FIXME: poking at dv-sockser internals, use tcp backend if
545 --sockser_addr option was given.*/
546 #ifdef HAVE_DV_SOCKSER
547 extern char* sockser_addr;
548 #else
549 # define sockser_addr NULL
550 #endif
551 if (sockser_addr == NULL)
552 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
553 else
554 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
555 }
556 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
557 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
558
559 /* -- device connections --- */
560 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
561 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
562 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
563 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
564 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
565 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
566
567 /* add PAL timer & I/O module */
568 if(! strcmp(board, BOARD_JMR3904_PAL))
569 {
570 /* the device */
571 sim_hw_parse (sd, "/pal@0xffff0000");
572 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
573
574 /* wire up interrupt ports to irc */
575 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
576 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
577 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
578 }
579
580 if(! strcmp(board, BOARD_JMR3904_DEBUG))
581 {
582 /* -- DEBUG: glue interrupt generators --- */
583 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
584 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
585 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
586 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
587 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
588 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
589 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
590 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
591 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
592 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
593 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
594 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
595 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
596 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
597 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
598 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
599 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
600 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
601 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
602 }
603
604 device_init(sd);
605 }
606 #endif
607
608 if (display_mem_info)
609 {
610 struct option_list * ol;
611 struct option_list * prev;
612
613 /* This is a hack. We want to execute the real --memory-info command
614 line switch which is handled in common/sim-memopts.c, not the
615 override we have defined in this file. So we remove the
616 mips_options array from the state options list. This is safe
617 because we have now processed all of the command line. */
618 for (ol = STATE_OPTIONS (sd), prev = NULL;
619 ol != NULL;
620 prev = ol, ol = ol->next)
621 if (ol->options == mips_options)
622 break;
623
624 SIM_ASSERT (ol != NULL);
625
626 if (prev == NULL)
627 STATE_OPTIONS (sd) = ol->next;
628 else
629 prev->next = ol->next;
630
631 sim_do_commandf (sd, "memory-info");
632 }
633
634 /* check for/establish the a reference program image */
635 if (sim_analyze_program (sd,
636 (STATE_PROG_ARGV (sd) != NULL
637 ? *STATE_PROG_ARGV (sd)
638 : NULL),
639 abfd) != SIM_RC_OK)
640 {
641 sim_module_uninstall (sd);
642 return 0;
643 }
644
645 /* Configure/verify the target byte order and other runtime
646 configuration options */
647 if (sim_config (sd) != SIM_RC_OK)
648 {
649 sim_module_uninstall (sd);
650 return 0;
651 }
652
653 if (sim_post_argv_init (sd) != SIM_RC_OK)
654 {
655 /* Uninstall the modules to avoid memory leaks,
656 file descriptor leaks, etc. */
657 sim_module_uninstall (sd);
658 return 0;
659 }
660
661 /* verify assumptions the simulator made about the host type system.
662 This macro does not return if there is a problem */
663 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
664 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
665
666 /* This is NASTY, in that we are assuming the size of specific
667 registers: */
668 {
669 int rn;
670 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
671 {
672 if (rn < 32)
673 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
674 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
675 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
676 else if ((rn >= 33) && (rn <= 37))
677 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
678 else if ((rn == SRIDX)
679 || (rn == FCR0IDX)
680 || (rn == FCR31IDX)
681 || ((rn >= 72) && (rn <= 89)))
682 cpu->register_widths[rn] = 32;
683 else
684 cpu->register_widths[rn] = 0;
685 }
686
687
688 }
689
690 if (STATE & simTRACE)
691 open_trace(sd);
692
693 /*
694 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
695 idt_monitor_base,
696 pmon_monitor_base,
697 lsipmon_monitor_base);
698 */
699
700 /* Write the monitor trap address handlers into the monitor (eeprom)
701 address space. This can only be done once the target endianness
702 has been determined. */
703 if (idt_monitor_base != 0)
704 {
705 unsigned loop;
706 address_word idt_monitor_size = 1 << 11;
707
708 /* the default monitor region */
709 if (WITH_TARGET_WORD_BITSIZE == 64)
710 sim_do_commandf (sd, "memory alias 0x%x,0x%" PRIxTW ",0x%" PRIxTA,
711 idt_monitor_base, idt_monitor_size,
712 EXTENDED (idt_monitor_base));
713 else
714 sim_do_commandf (sd, "memory region 0x%x,0x%x",
715 idt_monitor_base, idt_monitor_size);
716
717 /* Entry into the IDT monitor is via fixed address vectors, and
718 not using machine instructions. To avoid clashing with use of
719 the MIPS TRAP system, we place our own (simulator specific)
720 "undefined" instructions into the relevant vector slots. */
721 for (loop = 0; (loop < idt_monitor_size); loop += 4)
722 {
723 address_word vaddr = (idt_monitor_base + loop);
724 unsigned32 insn = (RSVD_INSTRUCTION |
725 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
726 << RSVD_INSTRUCTION_ARG_SHIFT));
727 H2T (insn);
728 sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
729 }
730 }
731
732 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
733 {
734 /* The PMON monitor uses the same address space, but rather than
735 branching into it the address of a routine is loaded. We can
736 cheat for the moment, and direct the PMON routine to IDT style
737 instructions within the monitor space. This relies on the IDT
738 monitor not using the locations from 0xBFC00500 onwards as its
739 entry points.*/
740 unsigned loop;
741 for (loop = 0; (loop < 24); loop++)
742 {
743 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
744 switch (loop)
745 {
746 case 0: /* read */
747 value = 7;
748 break;
749 case 1: /* write */
750 value = 8;
751 break;
752 case 2: /* open */
753 value = 6;
754 break;
755 case 3: /* close */
756 value = 10;
757 break;
758 case 5: /* printf */
759 value = ((0x500 - 16) / 8); /* not an IDT reason code */
760 break;
761 case 8: /* cliexit */
762 value = 17;
763 break;
764 case 11: /* flush_cache */
765 value = 28;
766 break;
767 }
768
769 SIM_ASSERT (idt_monitor_base != 0);
770 value = ((unsigned int) idt_monitor_base + (value * 8));
771 H2T (value);
772
773 if (pmon_monitor_base != 0)
774 {
775 address_word vaddr = (pmon_monitor_base + (loop * 4));
776 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
777 }
778
779 if (lsipmon_monitor_base != 0)
780 {
781 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
782 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
783 }
784 }
785
786 /* Write an abort sequence into the TRAP (common) exception vector
787 addresses. This is to catch code executing a TRAP (et.al.)
788 instruction without installing a trap handler. */
789 if ((idt_monitor_base != 0) ||
790 (pmon_monitor_base != 0) ||
791 (lsipmon_monitor_base != 0))
792 {
793 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
794 HALT_INSTRUCTION /* BREAK */ };
795 H2T (halt[0]);
796 H2T (halt[1]);
797 sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
798 sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
799 sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
800 /* XXX: Write here unconditionally? */
801 sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
802 sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
803 sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
804 }
805 }
806
807 /* CPU specific initialization. */
808 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
809 {
810 SIM_CPU *cpu = STATE_CPU (sd, i);
811
812 CPU_REG_FETCH (cpu) = mips_reg_fetch;
813 CPU_REG_STORE (cpu) = mips_reg_store;
814 CPU_PC_FETCH (cpu) = mips_pc_get;
815 CPU_PC_STORE (cpu) = mips_pc_set;
816 }
817
818 return sd;
819 }
820
821 #if WITH_TRACE_ANY_P
822 static void
823 open_trace (SIM_DESC sd)
824 {
825 tracefh = fopen(tracefile,"wb+");
826 if (tracefh == NULL)
827 {
828 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
829 tracefh = stderr;
830 }
831 }
832 #endif
833
834 /* Return name of an insn, used by insn profiling. */
835 static const char *
836 get_insn_name (sim_cpu *cpu, int i)
837 {
838 return itable[i].name;
839 }
840
841 void
842 mips_sim_close (SIM_DESC sd, int quitting)
843 {
844 #if WITH_TRACE_ANY_P
845 if (tracefh != NULL && tracefh != stderr)
846 fclose(tracefh);
847 tracefh = NULL;
848 #endif
849 }
850
851 static int
852 mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
853 {
854 /* NOTE: gdb (the client) stores registers in target byte order
855 while the simulator uses host byte order */
856
857 /* Unfortunately this suffers from the same problem as the register
858 numbering one. We need to know what the width of each logical
859 register number is for the architecture being simulated. */
860
861 if (cpu->register_widths[rn] == 0)
862 {
863 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register store ignored)\n", rn);
864 return 0;
865 }
866
867 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
868 {
869 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
870 if (cpu->register_widths[rn] == 32)
871 {
872 if (length == 8)
873 {
874 cpu->fgr[rn - FGR_BASE] =
875 (unsigned32) T2H_8 (*(unsigned64*)memory);
876 return 8;
877 }
878 else
879 {
880 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
881 return 4;
882 }
883 }
884 else
885 {
886 if (length == 8)
887 {
888 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
889 return 8;
890 }
891 else
892 {
893 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
894 return 4;
895 }
896 }
897 }
898
899 if (cpu->register_widths[rn] == 32)
900 {
901 if (length == 8)
902 {
903 cpu->registers[rn] =
904 (unsigned32) T2H_8 (*(unsigned64*)memory);
905 return 8;
906 }
907 else
908 {
909 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
910 return 4;
911 }
912 }
913 else
914 {
915 if (length == 8)
916 {
917 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
918 return 8;
919 }
920 else
921 {
922 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
923 return 4;
924 }
925 }
926
927 return 0;
928 }
929
930 static int
931 mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
932 {
933 /* NOTE: gdb (the client) stores registers in target byte order
934 while the simulator uses host byte order */
935
936 if (cpu->register_widths[rn] == 0)
937 {
938 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register fetch ignored)\n", rn);
939 return 0;
940 }
941
942 /* Any floating point register */
943 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
944 {
945 if (cpu->register_widths[rn] == 32)
946 {
947 if (length == 8)
948 {
949 *(unsigned64*)memory =
950 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
951 return 8;
952 }
953 else
954 {
955 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
956 return 4;
957 }
958 }
959 else
960 {
961 if (length == 8)
962 {
963 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
964 return 8;
965 }
966 else
967 {
968 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
969 return 4;
970 }
971 }
972 }
973
974 if (cpu->register_widths[rn] == 32)
975 {
976 if (length == 8)
977 {
978 *(unsigned64*)memory =
979 H2T_8 ((unsigned32) (cpu->registers[rn]));
980 return 8;
981 }
982 else
983 {
984 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
985 return 4;
986 }
987 }
988 else
989 {
990 if (length == 8)
991 {
992 *(unsigned64*)memory =
993 H2T_8 ((unsigned64) (cpu->registers[rn]));
994 return 8;
995 }
996 else
997 {
998 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
999 return 4;
1000 }
1001 }
1002
1003 return 0;
1004 }
1005
1006 SIM_RC
1007 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
1008 char * const *argv, char * const *env)
1009 {
1010
1011 #ifdef DEBUG
1012 #if 0 /* FIXME: doesn't compile */
1013 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1014 pr_addr(PC));
1015 #endif
1016 #endif /* DEBUG */
1017
1018 ColdReset(sd);
1019
1020 if (abfd != NULL)
1021 {
1022 /* override PC value set by ColdReset () */
1023 int cpu_nr;
1024 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1025 {
1026 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1027 sim_cia pc = bfd_get_start_address (abfd);
1028
1029 /* The 64-bit BFD sign-extends MIPS addresses to model
1030 32-bit compatibility segments with 64-bit addressing.
1031 These addresses work as is on 64-bit targets but
1032 can be truncated for 32-bit targets. */
1033 if (WITH_TARGET_WORD_BITSIZE == 32)
1034 pc = (unsigned32) pc;
1035
1036 CPU_PC_SET (cpu, pc);
1037 }
1038 }
1039
1040 #if 0 /* def DEBUG */
1041 if (argv || env)
1042 {
1043 /* We should really place the argv slot values into the argument
1044 registers, and onto the stack as required. However, this
1045 assumes that we have a stack defined, which is not
1046 necessarily true at the moment. */
1047 char **cptr;
1048 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1049 for (cptr = argv; (cptr && *cptr); cptr++)
1050 printf("DBG: arg \"%s\"\n",*cptr);
1051 }
1052 #endif /* DEBUG */
1053
1054 return SIM_RC_OK;
1055 }
1056
1057 /*---------------------------------------------------------------------------*/
1058 /*-- Private simulator support interface ------------------------------------*/
1059 /*---------------------------------------------------------------------------*/
1060
1061 /* Read a null terminated string from memory, return in a buffer */
1062 static char *
1063 fetch_str (SIM_DESC sd,
1064 address_word addr)
1065 {
1066 char *buf;
1067 int nr = 0;
1068 unsigned char null;
1069 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1070 nr++;
1071 buf = NZALLOC (char, nr + 1);
1072 sim_read (sd, addr, (unsigned char *)buf, nr);
1073 return buf;
1074 }
1075
1076
1077 /* Implements the "sim firmware" command:
1078 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1079 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1080 defaults to the normal address for that monitor.
1081 sim firmware none --- don't emulate any ROM monitor. Useful
1082 if you need a clean address space. */
1083 static SIM_RC
1084 sim_firmware_command (SIM_DESC sd, char *arg)
1085 {
1086 int address_present = 0;
1087 SIM_ADDR address;
1088
1089 /* Signal occurrence of this option. */
1090 firmware_option_p = 1;
1091
1092 /* Parse out the address, if present. */
1093 {
1094 char *p = strchr (arg, '@');
1095 if (p)
1096 {
1097 char *q;
1098 address_present = 1;
1099 p ++; /* skip over @ */
1100
1101 address = strtoul (p, &q, 0);
1102 if (*q != '\0')
1103 {
1104 sim_io_printf (sd, "Invalid address given to the"
1105 "`sim firmware NAME@ADDRESS' command: %s\n",
1106 p);
1107 return SIM_RC_FAIL;
1108 }
1109 }
1110 else
1111 {
1112 address_present = 0;
1113 address = -1; /* Dummy value. */
1114 }
1115 }
1116
1117 if (! strncmp (arg, "idt", 3))
1118 {
1119 idt_monitor_base = address_present ? address : 0xBFC00000;
1120 pmon_monitor_base = 0;
1121 lsipmon_monitor_base = 0;
1122 }
1123 else if (! strncmp (arg, "pmon", 4))
1124 {
1125 /* pmon uses indirect calls. Hook into implied idt. */
1126 pmon_monitor_base = address_present ? address : 0xBFC00500;
1127 idt_monitor_base = pmon_monitor_base - 0x500;
1128 lsipmon_monitor_base = 0;
1129 }
1130 else if (! strncmp (arg, "lsipmon", 7))
1131 {
1132 /* lsipmon uses indirect calls. Hook into implied idt. */
1133 pmon_monitor_base = 0;
1134 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1135 idt_monitor_base = lsipmon_monitor_base - 0x200;
1136 }
1137 else if (! strncmp (arg, "none", 4))
1138 {
1139 if (address_present)
1140 {
1141 sim_io_printf (sd,
1142 "The `sim firmware none' command does "
1143 "not take an `ADDRESS' argument.\n");
1144 return SIM_RC_FAIL;
1145 }
1146 idt_monitor_base = 0;
1147 pmon_monitor_base = 0;
1148 lsipmon_monitor_base = 0;
1149 }
1150 else
1151 {
1152 sim_io_printf (sd, "\
1153 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1154 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1155 arg);
1156 return SIM_RC_FAIL;
1157 }
1158
1159 return SIM_RC_OK;
1160 }
1161
1162 /* stat structures from MIPS32/64. */
1163 static const char stat32_map[] =
1164 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1165 ":st_rdev,2:st_size,4:st_atime,4:st_spare1,4:st_mtime,4:st_spare2,4"
1166 ":st_ctime,4:st_spare3,4:st_blksize,4:st_blocks,4:st_spare4,8";
1167
1168 static const char stat64_map[] =
1169 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1170 ":st_rdev,2:st_size,8:st_atime,8:st_spare1,8:st_mtime,8:st_spare2,8"
1171 ":st_ctime,8:st_spare3,8:st_blksize,8:st_blocks,8:st_spare4,16";
1172
1173 /* Map for calls using the host struct stat. */
1174 static const CB_TARGET_DEFS_MAP CB_stat_map[] =
1175 {
1176 { "stat", CB_SYS_stat, 15 },
1177 { 0, -1, -1 }
1178 };
1179
1180
1181 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1182 int
1183 sim_monitor (SIM_DESC sd,
1184 sim_cpu *cpu,
1185 address_word cia,
1186 unsigned int reason)
1187 {
1188 #ifdef DEBUG
1189 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1190 #endif /* DEBUG */
1191
1192 /* The IDT monitor actually allows two instructions per vector
1193 slot. However, the simulator currently causes a trap on each
1194 individual instruction. We cheat, and lose the bottom bit. */
1195 reason >>= 1;
1196
1197 /* The following callback functions are available, however the
1198 monitor we are simulating does not make use of them: get_errno,
1199 isatty, rename, system and time. */
1200 switch (reason)
1201 {
1202
1203 case 6: /* int open(char *path,int flags) */
1204 {
1205 char *path = fetch_str (sd, A0);
1206 V0 = sim_io_open (sd, path, (int)A1);
1207 free (path);
1208 break;
1209 }
1210
1211 case 7: /* int read(int file,char *ptr,int len) */
1212 {
1213 int fd = A0;
1214 int nr = A2;
1215 char *buf = zalloc (nr);
1216 V0 = sim_io_read (sd, fd, buf, nr);
1217 sim_write (sd, A1, (unsigned char *)buf, nr);
1218 free (buf);
1219 }
1220 break;
1221
1222 case 8: /* int write(int file,char *ptr,int len) */
1223 {
1224 int fd = A0;
1225 int nr = A2;
1226 char *buf = zalloc (nr);
1227 sim_read (sd, A1, (unsigned char *)buf, nr);
1228 V0 = sim_io_write (sd, fd, buf, nr);
1229 if (fd == 1)
1230 sim_io_flush_stdout (sd);
1231 else if (fd == 2)
1232 sim_io_flush_stderr (sd);
1233 free (buf);
1234 break;
1235 }
1236
1237 case 10: /* int close(int file) */
1238 {
1239 V0 = sim_io_close (sd, (int)A0);
1240 break;
1241 }
1242
1243 case 2: /* Densan monitor: char inbyte(int waitflag) */
1244 {
1245 if (A0 == 0) /* waitflag == NOWAIT */
1246 V0 = (unsigned_word)-1;
1247 }
1248 /* Drop through to case 11 */
1249
1250 case 11: /* char inbyte(void) */
1251 {
1252 char tmp;
1253 /* ensure that all output has gone... */
1254 sim_io_flush_stdout (sd);
1255 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1256 {
1257 sim_io_error(sd,"Invalid return from character read");
1258 V0 = (unsigned_word)-1;
1259 }
1260 else
1261 V0 = (unsigned_word)tmp;
1262 break;
1263 }
1264
1265 case 3: /* Densan monitor: void co(char chr) */
1266 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1267 {
1268 char tmp = (char)(A0 & 0xFF);
1269 sim_io_write_stdout (sd, &tmp, sizeof(char));
1270 break;
1271 }
1272
1273 case 13: /* int unlink(const char *path) */
1274 {
1275 char *path = fetch_str (sd, A0);
1276 V0 = sim_io_unlink (sd, path);
1277 free (path);
1278 break;
1279 }
1280
1281 case 14: /* int lseek(int fd, int offset, int whence) */
1282 {
1283 V0 = sim_io_lseek (sd, A0, A1, A2);
1284 break;
1285 }
1286
1287 case 15: /* int stat(const char *path, struct stat *buf); */
1288 {
1289 /* As long as the infrastructure doesn't cache anything
1290 related to the stat mapping, this trick gets us a dual
1291 "struct stat"-type mapping in the least error-prone way. */
1292 host_callback *cb = STATE_CALLBACK (sd);
1293 const char *saved_map = cb->stat_map;
1294 CB_TARGET_DEFS_MAP *saved_syscall_map = cb->syscall_map;
1295 bfd *prog_bfd = STATE_PROG_BFD (sd);
1296 int is_elf32bit = (elf_elfheader(prog_bfd)->e_ident[EI_CLASS] ==
1297 ELFCLASS32);
1298 static CB_SYSCALL s;
1299 CB_SYSCALL_INIT (&s);
1300 s.func = 15;
1301 /* Mask out the sign extension part for 64-bit targets because the
1302 MIPS simulator's memory model is still 32-bit. */
1303 s.arg1 = A0 & 0xFFFFFFFF;
1304 s.arg2 = A1 & 0xFFFFFFFF;
1305 s.p1 = (PTR) sd;
1306 s.p2 = (PTR) cpu;
1307 s.read_mem = sim_syscall_read_mem;
1308 s.write_mem = sim_syscall_write_mem;
1309
1310 cb->syscall_map = (CB_TARGET_DEFS_MAP *) CB_stat_map;
1311 cb->stat_map = is_elf32bit ? stat32_map : stat64_map;
1312
1313 if (cb_syscall (cb, &s) != CB_RC_OK)
1314 sim_engine_halt (sd, cpu, NULL, mips_pc_get (cpu),
1315 sim_stopped, SIM_SIGILL);
1316
1317 V0 = s.result;
1318 cb->stat_map = saved_map;
1319 cb->syscall_map = saved_syscall_map;
1320 break;
1321 }
1322
1323 case 17: /* void _exit() */
1324 {
1325 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1326 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1327 (unsigned int)(A0 & 0xFFFFFFFF));
1328 break;
1329 }
1330
1331 case 28: /* PMON flush_cache */
1332 break;
1333
1334 case 55: /* void get_mem_info(unsigned int *ptr) */
1335 /* in: A0 = pointer to three word memory location */
1336 /* out: [A0 + 0] = size */
1337 /* [A0 + 4] = instruction cache size */
1338 /* [A0 + 8] = data cache size */
1339 {
1340 unsigned_4 value;
1341 unsigned_4 zero = 0;
1342 address_word mem_size;
1343 sim_memopt *entry, *match = NULL;
1344
1345 /* Search for memory region mapped to KSEG0 or KSEG1. */
1346 for (entry = STATE_MEMOPT (sd);
1347 entry != NULL;
1348 entry = entry->next)
1349 {
1350 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1351 && (!match || entry->level < match->level))
1352 match = entry;
1353 else
1354 {
1355 sim_memopt *alias;
1356 for (alias = entry->alias;
1357 alias != NULL;
1358 alias = alias->next)
1359 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1360 && (!match || entry->level < match->level))
1361 match = entry;
1362 }
1363 }
1364
1365 /* Get region size, limit to KSEG1 size (512MB). */
1366 SIM_ASSERT (match != NULL);
1367 mem_size = (match->modulo != 0
1368 ? match->modulo : match->nr_bytes);
1369 if (mem_size > K1SIZE)
1370 mem_size = K1SIZE;
1371
1372 value = mem_size;
1373 H2T (value);
1374 sim_write (sd, A0 + 0, (unsigned char *)&value, 4);
1375 sim_write (sd, A0 + 4, (unsigned char *)&zero, 4);
1376 sim_write (sd, A0 + 8, (unsigned char *)&zero, 4);
1377 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1378 break;
1379 }
1380
1381 case 158: /* PMON printf */
1382 /* in: A0 = pointer to format string */
1383 /* A1 = optional argument 1 */
1384 /* A2 = optional argument 2 */
1385 /* A3 = optional argument 3 */
1386 /* out: void */
1387 /* The following is based on the PMON printf source */
1388 {
1389 address_word s = A0;
1390 unsigned char c;
1391 signed_word *ap = &A1; /* 1st argument */
1392 /* This isn't the quickest way, since we call the host print
1393 routine for every character almost. But it does avoid
1394 having to allocate and manage a temporary string buffer. */
1395 /* TODO: Include check that we only use three arguments (A1,
1396 A2 and A3) */
1397 while (sim_read (sd, s++, &c, 1) && c != '\0')
1398 {
1399 if (c == '%')
1400 {
1401 char tmp[40];
1402 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1403 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1404 while (sim_read (sd, s++, &c, 1) && c != '\0')
1405 {
1406 if (strchr ("dobxXulscefg%", c))
1407 break;
1408 else if (c == '-')
1409 fmt = FMT_LJUST;
1410 else if (c == '0')
1411 fmt = FMT_RJUST0;
1412 else if (c == '~')
1413 fmt = FMT_CENTER;
1414 else if (c == '*')
1415 {
1416 if (haddot)
1417 trunc = (int)*ap++;
1418 else
1419 width = (int)*ap++;
1420 }
1421 else if (c >= '1' && c <= '9')
1422 {
1423 address_word t = s;
1424 unsigned int n;
1425 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1426 tmp[s - t] = c;
1427 tmp[s - t] = '\0';
1428 n = (unsigned int)strtol(tmp,NULL,10);
1429 if (haddot)
1430 trunc = n;
1431 else
1432 width = n;
1433 s--;
1434 }
1435 else if (c == '.')
1436 haddot = 1;
1437 }
1438 switch (c)
1439 {
1440 case '%':
1441 sim_io_printf (sd, "%%");
1442 break;
1443 case 's':
1444 if ((int)*ap != 0)
1445 {
1446 address_word p = *ap++;
1447 unsigned char ch;
1448 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1449 sim_io_printf(sd, "%c", ch);
1450 }
1451 else
1452 sim_io_printf(sd,"(null)");
1453 break;
1454 case 'c':
1455 sim_io_printf (sd, "%c", (int)*ap++);
1456 break;
1457 default:
1458 if (c == 'l')
1459 {
1460 sim_read (sd, s++, &c, 1);
1461 if (c == 'l')
1462 {
1463 longlong = 1;
1464 sim_read (sd, s++, &c, 1);
1465 }
1466 }
1467 if (strchr ("dobxXu", c))
1468 {
1469 word64 lv = (word64) *ap++;
1470 if (c == 'b')
1471 sim_io_printf(sd,"<binary not supported>");
1472 else
1473 {
1474 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1475 if (longlong)
1476 sim_io_printf(sd, tmp, lv);
1477 else
1478 sim_io_printf(sd, tmp, (int)lv);
1479 }
1480 }
1481 else if (strchr ("eEfgG", c))
1482 {
1483 double dbl = *(double*)(ap++);
1484 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1485 sim_io_printf (sd, tmp, dbl);
1486 trunc = 0;
1487 }
1488 }
1489 }
1490 else
1491 sim_io_printf(sd, "%c", c);
1492 }
1493 break;
1494 }
1495
1496 default:
1497 /* Unknown reason. */
1498 return 0;
1499 }
1500 return 1;
1501 }
1502
1503 /* Store a word into memory. */
1504
1505 static void
1506 store_word (SIM_DESC sd,
1507 sim_cpu *cpu,
1508 address_word cia,
1509 uword64 vaddr,
1510 signed_word val)
1511 {
1512 address_word paddr = vaddr;
1513
1514 if ((vaddr & 3) != 0)
1515 SignalExceptionAddressStore ();
1516 else
1517 {
1518 const uword64 mask = 7;
1519 uword64 memval;
1520 unsigned int byte;
1521
1522 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1523 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1524 memval = ((uword64) val) << (8 * byte);
1525 StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
1526 isREAL);
1527 }
1528 }
1529
1530 /* Load a word from memory. */
1531
1532 static signed_word
1533 load_word (SIM_DESC sd,
1534 sim_cpu *cpu,
1535 address_word cia,
1536 uword64 vaddr)
1537 {
1538 if ((vaddr & 3) != 0)
1539 {
1540 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1541 }
1542 else
1543 {
1544 address_word paddr = vaddr;
1545 const uword64 mask = 0x7;
1546 const unsigned int reverse = ReverseEndian ? 1 : 0;
1547 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1548 uword64 memval;
1549 unsigned int byte;
1550
1551 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1552 LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
1553 isREAL);
1554 byte = (vaddr & mask) ^ (bigend << 2);
1555 return EXTEND32 (memval >> (8 * byte));
1556 }
1557
1558 return 0;
1559 }
1560
1561 /* Simulate the mips16 entry and exit pseudo-instructions. These
1562 would normally be handled by the reserved instruction exception
1563 code, but for ease of simulation we just handle them directly. */
1564
1565 static void
1566 mips16_entry (SIM_DESC sd,
1567 sim_cpu *cpu,
1568 address_word cia,
1569 unsigned int insn)
1570 {
1571 int aregs, sregs, rreg;
1572
1573 #ifdef DEBUG
1574 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1575 #endif /* DEBUG */
1576
1577 aregs = (insn & 0x700) >> 8;
1578 sregs = (insn & 0x0c0) >> 6;
1579 rreg = (insn & 0x020) >> 5;
1580
1581 /* This should be checked by the caller. */
1582 if (sregs == 3)
1583 abort ();
1584
1585 if (aregs < 5)
1586 {
1587 int i;
1588 signed_word tsp;
1589
1590 /* This is the entry pseudo-instruction. */
1591
1592 for (i = 0; i < aregs; i++)
1593 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1594
1595 tsp = SP;
1596 SP -= 32;
1597
1598 if (rreg)
1599 {
1600 tsp -= 4;
1601 store_word (SD, CPU, cia, (uword64) tsp, RA);
1602 }
1603
1604 for (i = 0; i < sregs; i++)
1605 {
1606 tsp -= 4;
1607 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1608 }
1609 }
1610 else
1611 {
1612 int i;
1613 signed_word tsp;
1614
1615 /* This is the exit pseudo-instruction. */
1616
1617 tsp = SP + 32;
1618
1619 if (rreg)
1620 {
1621 tsp -= 4;
1622 RA = load_word (SD, CPU, cia, (uword64) tsp);
1623 }
1624
1625 for (i = 0; i < sregs; i++)
1626 {
1627 tsp -= 4;
1628 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1629 }
1630
1631 SP += 32;
1632
1633 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1634 {
1635 if (aregs == 5)
1636 {
1637 FGR[0] = WORD64LO (GPR[4]);
1638 FPR_STATE[0] = fmt_uninterpreted;
1639 }
1640 else if (aregs == 6)
1641 {
1642 FGR[0] = WORD64LO (GPR[5]);
1643 FGR[1] = WORD64LO (GPR[4]);
1644 FPR_STATE[0] = fmt_uninterpreted;
1645 FPR_STATE[1] = fmt_uninterpreted;
1646 }
1647 }
1648
1649 PC = RA;
1650 }
1651
1652 }
1653
1654 /*-- trace support ----------------------------------------------------------*/
1655
1656 /* The trace support is provided (if required) in the memory accessing
1657 routines. Since we are also providing the architecture specific
1658 features, the architecture simulation code can also deal with
1659 notifying the trace world of cache flushes, etc. Similarly we do
1660 not need to provide profiling support in the simulator engine,
1661 since we can sample in the instruction fetch control loop. By
1662 defining the trace manifest, we add tracing as a run-time
1663 option. */
1664
1665 #if WITH_TRACE_ANY_P
1666 /* Tracing by default produces "din" format (as required by
1667 dineroIII). Each line of such a trace file *MUST* have a din label
1668 and address field. The rest of the line is ignored, so comments can
1669 be included if desired. The first field is the label which must be
1670 one of the following values:
1671
1672 0 read data
1673 1 write data
1674 2 instruction fetch
1675 3 escape record (treated as unknown access type)
1676 4 escape record (causes cache flush)
1677
1678 The address field is a 32bit (lower-case) hexadecimal address
1679 value. The address should *NOT* be preceded by "0x".
1680
1681 The size of the memory transfer is not important when dealing with
1682 cache lines (as long as no more than a cache line can be
1683 transferred in a single operation :-), however more information
1684 could be given following the dineroIII requirement to allow more
1685 complete memory and cache simulators to provide better
1686 results. i.e. the University of Pisa has a cache simulator that can
1687 also take bus size and speed as (variable) inputs to calculate
1688 complete system performance (a much more useful ability when trying
1689 to construct an end product, rather than a processor). They
1690 currently have an ARM version of their tool called ChARM. */
1691
1692
1693 void
1694 dotrace (SIM_DESC sd,
1695 sim_cpu *cpu,
1696 FILE *tracefh,
1697 int type,
1698 SIM_ADDR address,
1699 int width,
1700 char *comment,...)
1701 {
1702 if (STATE & simTRACE) {
1703 va_list ap;
1704 fprintf(tracefh,"%d %s ; width %d ; ",
1705 type,
1706 pr_addr(address),
1707 width);
1708 va_start(ap,comment);
1709 vfprintf(tracefh,comment,ap);
1710 va_end(ap);
1711 fprintf(tracefh,"\n");
1712 }
1713 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1714 we may be generating 64bit ones, we should put the hi-32bits of the
1715 address into the comment field. */
1716
1717 /* TODO: Provide a buffer for the trace lines. We can then avoid
1718 performing writes until the buffer is filled, or the file is
1719 being closed. */
1720
1721 /* NOTE: We could consider adding a comment field to the "din" file
1722 produced using type 3 markers (unknown access). This would then
1723 allow information about the program that the "din" is for, and
1724 the MIPs world that was being simulated, to be placed into the
1725 trace file. */
1726
1727 return;
1728 }
1729 #endif /* WITH_TRACE_ANY_P */
1730
1731 /*---------------------------------------------------------------------------*/
1732 /*-- simulator engine -------------------------------------------------------*/
1733 /*---------------------------------------------------------------------------*/
1734
1735 static void
1736 ColdReset (SIM_DESC sd)
1737 {
1738 int cpu_nr;
1739 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1740 {
1741 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1742 /* RESET: Fixed PC address: */
1743 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1744 /* The reset vector address is in the unmapped, uncached memory space. */
1745
1746 SR &= ~(status_SR | status_TS | status_RP);
1747 SR |= (status_ERL | status_BEV);
1748
1749 /* Cheat and allow access to the complete register set immediately */
1750 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1751 && WITH_TARGET_WORD_BITSIZE == 64)
1752 SR |= status_FR; /* 64bit registers */
1753
1754 /* Ensure that any instructions with pending register updates are
1755 cleared: */
1756 PENDING_INVALIDATE();
1757
1758 /* Initialise the FPU registers to the unknown state */
1759 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1760 {
1761 int rn;
1762 for (rn = 0; (rn < 32); rn++)
1763 FPR_STATE[rn] = fmt_uninterpreted;
1764 }
1765
1766 /* Initialise the Config0 register. */
1767 C0_CONFIG = 0x80000000 /* Config1 present */
1768 | 2; /* KSEG0 uncached */
1769 if (WITH_TARGET_WORD_BITSIZE == 64)
1770 {
1771 /* FIXME Currently mips/sim-main.c:address_translation()
1772 truncates all addresses to 32-bits. */
1773 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1774 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1775 else
1776 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1777 }
1778 if (BigEndianMem)
1779 C0_CONFIG |= 0x00008000; /* Big Endian */
1780 }
1781 }
1782
1783
1784
1785
1786 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1787 /* Signal an exception condition. This will result in an exception
1788 that aborts the instruction. The instruction operation pseudocode
1789 will never see a return from this function call. */
1790
1791 void
1792 signal_exception (SIM_DESC sd,
1793 sim_cpu *cpu,
1794 address_word cia,
1795 int exception,...)
1796 {
1797 /* int vector; */
1798
1799 #ifdef DEBUG
1800 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1801 #endif /* DEBUG */
1802
1803 /* Ensure that any active atomic read/modify/write operation will fail: */
1804 LLBIT = 0;
1805
1806 /* Save registers before interrupt dispatching */
1807 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1808 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1809 #endif
1810
1811 switch (exception) {
1812
1813 case DebugBreakPoint:
1814 if (! (Debug & Debug_DM))
1815 {
1816 if (INDELAYSLOT())
1817 {
1818 CANCELDELAYSLOT();
1819
1820 Debug |= Debug_DBD; /* signaled from within in delay slot */
1821 DEPC = cia - 4; /* reference the branch instruction */
1822 }
1823 else
1824 {
1825 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1826 DEPC = cia;
1827 }
1828
1829 Debug |= Debug_DM; /* in debugging mode */
1830 Debug |= Debug_DBp; /* raising a DBp exception */
1831 PC = 0xBFC00200;
1832 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1833 }
1834 break;
1835
1836 case ReservedInstruction:
1837 {
1838 va_list ap;
1839 unsigned int instruction;
1840 va_start(ap,exception);
1841 instruction = va_arg(ap,unsigned int);
1842 va_end(ap);
1843 /* Provide simple monitor support using ReservedInstruction
1844 exceptions. The following code simulates the fixed vector
1845 entry points into the IDT monitor by causing a simulator
1846 trap, performing the monitor operation, and returning to
1847 the address held in the $ra register (standard PCS return
1848 address). This means we only need to pre-load the vector
1849 space with suitable instruction values. For systems were
1850 actual trap instructions are used, we would not need to
1851 perform this magic. */
1852 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1853 {
1854 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1855 if (!sim_monitor (SD, CPU, cia, reason))
1856 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1857
1858 /* NOTE: This assumes that a branch-and-link style
1859 instruction was used to enter the vector (which is the
1860 case with the current IDT monitor). */
1861 sim_engine_restart (SD, CPU, NULL, RA);
1862 }
1863 /* Look for the mips16 entry and exit instructions, and
1864 simulate a handler for them. */
1865 else if ((cia & 1) != 0
1866 && (instruction & 0xf81f) == 0xe809
1867 && (instruction & 0x0c0) != 0x0c0)
1868 {
1869 mips16_entry (SD, CPU, cia, instruction);
1870 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1871 }
1872 /* else fall through to normal exception processing */
1873 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1874 }
1875
1876 default:
1877 /* Store exception code into current exception id variable (used
1878 by exit code): */
1879
1880 /* TODO: If not simulating exceptions then stop the simulator
1881 execution. At the moment we always stop the simulation. */
1882
1883 #ifdef SUBTARGET_R3900
1884 /* update interrupt-related registers */
1885
1886 /* insert exception code in bits 6:2 */
1887 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1888 /* shift IE/KU history bits left */
1889 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1890
1891 if (STATE & simDELAYSLOT)
1892 {
1893 STATE &= ~simDELAYSLOT;
1894 CAUSE |= cause_BD;
1895 EPC = (cia - 4); /* reference the branch instruction */
1896 }
1897 else
1898 EPC = cia;
1899
1900 if (SR & status_BEV)
1901 PC = (signed)0xBFC00000 + 0x180;
1902 else
1903 PC = (signed)0x80000000 + 0x080;
1904 #else
1905 /* See figure 5-17 for an outline of the code below */
1906 if (! (SR & status_EXL))
1907 {
1908 CAUSE = (exception << 2);
1909 if (STATE & simDELAYSLOT)
1910 {
1911 STATE &= ~simDELAYSLOT;
1912 CAUSE |= cause_BD;
1913 EPC = (cia - 4); /* reference the branch instruction */
1914 }
1915 else
1916 EPC = cia;
1917 /* FIXME: TLB et.al. */
1918 /* vector = 0x180; */
1919 }
1920 else
1921 {
1922 CAUSE = (exception << 2);
1923 /* vector = 0x180; */
1924 }
1925 SR |= status_EXL;
1926 /* Store exception code into current exception id variable (used
1927 by exit code): */
1928
1929 if (SR & status_BEV)
1930 PC = (signed)0xBFC00200 + 0x180;
1931 else
1932 PC = (signed)0x80000000 + 0x180;
1933 #endif
1934
1935 switch ((CAUSE >> 2) & 0x1F)
1936 {
1937 case Interrupt:
1938 /* Interrupts arrive during event processing, no need to
1939 restart */
1940 return;
1941
1942 case NMIReset:
1943 /* Ditto */
1944 #ifdef SUBTARGET_3900
1945 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1946 PC = (signed)0xBFC00000;
1947 #endif /* SUBTARGET_3900 */
1948 return;
1949
1950 case TLBModification:
1951 case TLBLoad:
1952 case TLBStore:
1953 case AddressLoad:
1954 case AddressStore:
1955 case InstructionFetch:
1956 case DataReference:
1957 /* The following is so that the simulator will continue from the
1958 exception handler address. */
1959 sim_engine_halt (SD, CPU, NULL, PC,
1960 sim_stopped, SIM_SIGBUS);
1961
1962 case ReservedInstruction:
1963 case CoProcessorUnusable:
1964 PC = EPC;
1965 sim_engine_halt (SD, CPU, NULL, PC,
1966 sim_stopped, SIM_SIGILL);
1967
1968 case IntegerOverflow:
1969 case FPE:
1970 sim_engine_halt (SD, CPU, NULL, PC,
1971 sim_stopped, SIM_SIGFPE);
1972
1973 case BreakPoint:
1974 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1975 break;
1976
1977 case SystemCall:
1978 case Trap:
1979 sim_engine_restart (SD, CPU, NULL, PC);
1980 break;
1981
1982 case Watch:
1983 PC = EPC;
1984 sim_engine_halt (SD, CPU, NULL, PC,
1985 sim_stopped, SIM_SIGTRAP);
1986
1987 default: /* Unknown internal exception */
1988 PC = EPC;
1989 sim_engine_halt (SD, CPU, NULL, PC,
1990 sim_stopped, SIM_SIGABRT);
1991
1992 }
1993
1994 case SimulatorFault:
1995 {
1996 va_list ap;
1997 char *msg;
1998 va_start(ap,exception);
1999 msg = va_arg(ap,char *);
2000 va_end(ap);
2001 sim_engine_abort (SD, CPU, NULL_CIA,
2002 "FATAL: Simulator error \"%s\"\n",msg);
2003 }
2004 }
2005
2006 return;
2007 }
2008
2009
2010
2011 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2012 "UNPREDICTABLE" behaviour.
2013
2014 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2015 may vary from processor implementation to processor implementation,
2016 instruction to instruction, or as a function of time on the same
2017 implementation or instruction. Software can never depend on results
2018 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2019 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2020 0.95, page 2.)
2021
2022 For UNPREDICTABLE behaviour, we print a message, if possible print
2023 the offending instructions mips.igen instruction name (provided by
2024 the caller), and stop the simulator.
2025
2026 XXX FIXME: eventually, stopping the simulator should be made conditional
2027 on a command-line option. */
2028 void
2029 unpredictable_action(sim_cpu *cpu, address_word cia)
2030 {
2031 SIM_DESC sd = CPU_STATE(cpu);
2032
2033 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
2034 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
2035 }
2036
2037
2038 /*-- co-processor support routines ------------------------------------------*/
2039
2040 static int UNUSED
2041 CoProcPresent(unsigned int coproc_number)
2042 {
2043 /* Return TRUE if simulator provides a model for the given co-processor number */
2044 return(0);
2045 }
2046
2047 void
2048 cop_lw (SIM_DESC sd,
2049 sim_cpu *cpu,
2050 address_word cia,
2051 int coproc_num,
2052 int coproc_reg,
2053 unsigned int memword)
2054 {
2055 switch (coproc_num)
2056 {
2057 case 1:
2058 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2059 {
2060 #ifdef DEBUG
2061 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2062 #endif
2063 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
2064 break;
2065 }
2066
2067 default:
2068 #if 0 /* this should be controlled by a configuration option */
2069 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2070 #endif
2071 break;
2072 }
2073
2074 return;
2075 }
2076
2077 void
2078 cop_ld (SIM_DESC sd,
2079 sim_cpu *cpu,
2080 address_word cia,
2081 int coproc_num,
2082 int coproc_reg,
2083 uword64 memword)
2084 {
2085
2086 #ifdef DEBUG
2087 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2088 #endif
2089
2090 switch (coproc_num) {
2091 case 1:
2092 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2093 {
2094 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
2095 break;
2096 }
2097
2098 default:
2099 #if 0 /* this message should be controlled by a configuration option */
2100 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2101 #endif
2102 break;
2103 }
2104
2105 return;
2106 }
2107
2108
2109
2110
2111 unsigned int
2112 cop_sw (SIM_DESC sd,
2113 sim_cpu *cpu,
2114 address_word cia,
2115 int coproc_num,
2116 int coproc_reg)
2117 {
2118 unsigned int value = 0;
2119
2120 switch (coproc_num)
2121 {
2122 case 1:
2123 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2124 {
2125 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
2126 break;
2127 }
2128
2129 default:
2130 #if 0 /* should be controlled by configuration option */
2131 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2132 #endif
2133 break;
2134 }
2135
2136 return(value);
2137 }
2138
2139 uword64
2140 cop_sd (SIM_DESC sd,
2141 sim_cpu *cpu,
2142 address_word cia,
2143 int coproc_num,
2144 int coproc_reg)
2145 {
2146 uword64 value = 0;
2147 switch (coproc_num)
2148 {
2149 case 1:
2150 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2151 {
2152 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
2153 break;
2154 }
2155
2156 default:
2157 #if 0 /* should be controlled by configuration option */
2158 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2159 #endif
2160 break;
2161 }
2162
2163 return(value);
2164 }
2165
2166
2167
2168
2169 void
2170 decode_coproc (SIM_DESC sd,
2171 sim_cpu *cpu,
2172 address_word cia,
2173 unsigned int instruction,
2174 int coprocnum,
2175 CP0_operation op,
2176 int rt,
2177 int rd,
2178 int sel)
2179 {
2180 switch (coprocnum)
2181 {
2182 case 0: /* standard CPU control and cache registers */
2183 {
2184 /* R4000 Users Manual (second edition) lists the following CP0
2185 instructions:
2186 CODE><-RT><RD-><--TAIL--->
2187 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2188 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2189 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2190 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2191 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2192 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2193 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2194 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2195 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2196 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2197 */
2198 if (((op == cp0_mfc0) || (op == cp0_mtc0) /* MFC0 / MTC0 */
2199 || (op == cp0_dmfc0) || (op == cp0_dmtc0)) /* DMFC0 / DMTC0 */
2200 && sel == 0)
2201 {
2202 switch (rd) /* NOTEs: Standard CP0 registers */
2203 {
2204 /* 0 = Index R4000 VR4100 VR4300 */
2205 /* 1 = Random R4000 VR4100 VR4300 */
2206 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2207 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2208 /* 4 = Context R4000 VR4100 VR4300 */
2209 /* 5 = PageMask R4000 VR4100 VR4300 */
2210 /* 6 = Wired R4000 VR4100 VR4300 */
2211 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2212 /* 9 = Count R4000 VR4100 VR4300 */
2213 /* 10 = EntryHi R4000 VR4100 VR4300 */
2214 /* 11 = Compare R4000 VR4100 VR4300 */
2215 /* 12 = SR R4000 VR4100 VR4300 */
2216 #ifdef SUBTARGET_R3900
2217 case 3:
2218 /* 3 = Config R3900 */
2219 case 7:
2220 /* 7 = Cache R3900 */
2221 case 15:
2222 /* 15 = PRID R3900 */
2223
2224 /* ignore */
2225 break;
2226
2227 case 8:
2228 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2229 if (op == cp0_mfc0 || op == cp0_dmfc0)
2230 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
2231 else
2232 COP0_BADVADDR = GPR[rt];
2233 break;
2234
2235 #endif /* SUBTARGET_R3900 */
2236 case 12:
2237 if (op == cp0_mfc0 || op == cp0_dmfc0)
2238 GPR[rt] = SR;
2239 else
2240 SR = GPR[rt];
2241 break;
2242 /* 13 = Cause R4000 VR4100 VR4300 */
2243 case 13:
2244 if (op == cp0_mfc0 || op == cp0_dmfc0)
2245 GPR[rt] = CAUSE;
2246 else
2247 CAUSE = GPR[rt];
2248 break;
2249 /* 14 = EPC R4000 VR4100 VR4300 */
2250 case 14:
2251 if (op == cp0_mfc0 || op == cp0_dmfc0)
2252 GPR[rt] = (signed_word) (signed_address) EPC;
2253 else
2254 EPC = GPR[rt];
2255 break;
2256 /* 15 = PRId R4000 VR4100 VR4300 */
2257 #ifdef SUBTARGET_R3900
2258 /* 16 = Debug */
2259 case 16:
2260 if (op == cp0_mfc0 || op == cp0_dmfc0)
2261 GPR[rt] = Debug;
2262 else
2263 Debug = GPR[rt];
2264 break;
2265 #else
2266 /* 16 = Config R4000 VR4100 VR4300 */
2267 case 16:
2268 if (op == cp0_mfc0 || op == cp0_dmfc0)
2269 GPR[rt] = C0_CONFIG;
2270 else
2271 /* only bottom three bits are writable */
2272 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
2273 break;
2274 #endif
2275 #ifdef SUBTARGET_R3900
2276 /* 17 = Debug */
2277 case 17:
2278 if (op == cp0_mfc0 || op == cp0_dmfc0)
2279 GPR[rt] = DEPC;
2280 else
2281 DEPC = GPR[rt];
2282 break;
2283 #else
2284 /* 17 = LLAddr R4000 VR4100 VR4300 */
2285 #endif
2286 /* 18 = WatchLo R4000 VR4100 VR4300 */
2287 /* 19 = WatchHi R4000 VR4100 VR4300 */
2288 /* 20 = XContext R4000 VR4100 VR4300 */
2289 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2290 /* 27 = CacheErr R4000 VR4100 */
2291 /* 28 = TagLo R4000 VR4100 VR4300 */
2292 /* 29 = TagHi R4000 VR4100 VR4300 */
2293 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2294 if (STATE_VERBOSE_P(SD))
2295 sim_io_eprintf (SD,
2296 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2297 (unsigned long)cia);
2298 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2299 /* CPR[0,rd] = GPR[rt]; */
2300 default:
2301 if (op == cp0_mfc0 || op == cp0_dmfc0)
2302 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2303 else
2304 COP0_GPR[rd] = GPR[rt];
2305 #if 0
2306 if (code == 0x00)
2307 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2308 else
2309 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2310 #endif
2311 }
2312 }
2313 else if ((op == cp0_mfc0 || op == cp0_dmfc0)
2314 && rd == 16)
2315 {
2316 /* [D]MFC0 RT,C0_CONFIG,SEL */
2317 signed32 cfg = 0;
2318 switch (sel)
2319 {
2320 case 0:
2321 cfg = C0_CONFIG;
2322 break;
2323 case 1:
2324 /* MIPS32 r/o Config1:
2325 Config2 present */
2326 cfg = 0x80000000;
2327 /* MIPS16 implemented.
2328 XXX How to check configuration? */
2329 cfg |= 0x0000004;
2330 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2331 /* MDMX & FPU implemented */
2332 cfg |= 0x00000021;
2333 break;
2334 case 2:
2335 /* MIPS32 r/o Config2:
2336 Config3 present. */
2337 cfg = 0x80000000;
2338 break;
2339 case 3:
2340 /* MIPS32 r/o Config3:
2341 SmartMIPS implemented. */
2342 cfg = 0x00000002;
2343 break;
2344 }
2345 GPR[rt] = cfg;
2346 }
2347 else if (op == cp0_eret && sel == 0x18)
2348 {
2349 /* ERET */
2350 if (SR & status_ERL)
2351 {
2352 /* Oops, not yet available */
2353 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2354 PC = EPC;
2355 SR &= ~status_ERL;
2356 }
2357 else
2358 {
2359 PC = EPC;
2360 SR &= ~status_EXL;
2361 }
2362 }
2363 else if (op == cp0_rfe && sel == 0x10)
2364 {
2365 /* RFE */
2366 #ifdef SUBTARGET_R3900
2367 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2368
2369 /* shift IE/KU history bits right */
2370 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2371
2372 /* TODO: CACHE register */
2373 #endif /* SUBTARGET_R3900 */
2374 }
2375 else if (op == cp0_deret && sel == 0x1F)
2376 {
2377 /* DERET */
2378 Debug &= ~Debug_DM;
2379 DELAYSLOT();
2380 DSPC = DEPC;
2381 }
2382 else
2383 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2384 /* TODO: When executing an ERET or RFE instruction we should
2385 clear LLBIT, to ensure that any out-standing atomic
2386 read/modify/write sequence fails. */
2387 }
2388 break;
2389
2390 case 2: /* co-processor 2 */
2391 {
2392 int handle = 0;
2393
2394
2395 if(! handle)
2396 {
2397 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2398 instruction,pr_addr(cia));
2399 }
2400 }
2401 break;
2402
2403 case 1: /* should not occur (FPU co-processor) */
2404 case 3: /* should not occur (FPU co-processor) */
2405 SignalException(ReservedInstruction,instruction);
2406 break;
2407 }
2408
2409 return;
2410 }
2411
2412
2413 /* This code copied from gdb's utils.c. Would like to share this code,
2414 but don't know of a common place where both could get to it. */
2415
2416 /* Temporary storage using circular buffer */
2417 #define NUMCELLS 16
2418 #define CELLSIZE 32
2419 static char*
2420 get_cell (void)
2421 {
2422 static char buf[NUMCELLS][CELLSIZE];
2423 static int cell=0;
2424 if (++cell>=NUMCELLS) cell=0;
2425 return buf[cell];
2426 }
2427
2428 /* Print routines to handle variable size regs, etc */
2429
2430 /* Eliminate warning from compiler on 32-bit systems */
2431 static int thirty_two = 32;
2432
2433 char*
2434 pr_addr (SIM_ADDR addr)
2435 {
2436 char *paddr_str=get_cell();
2437 switch (sizeof(addr))
2438 {
2439 case 8:
2440 sprintf(paddr_str,"%08lx%08lx",
2441 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2442 break;
2443 case 4:
2444 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2445 break;
2446 case 2:
2447 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2448 break;
2449 default:
2450 sprintf(paddr_str,"%x",addr);
2451 }
2452 return paddr_str;
2453 }
2454
2455 char*
2456 pr_uword64 (uword64 addr)
2457 {
2458 char *paddr_str=get_cell();
2459 sprintf(paddr_str,"%08lx%08lx",
2460 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2461 return paddr_str;
2462 }
2463
2464
2465 void
2466 mips_core_signal (SIM_DESC sd,
2467 sim_cpu *cpu,
2468 sim_cia cia,
2469 unsigned map,
2470 int nr_bytes,
2471 address_word addr,
2472 transfer_type transfer,
2473 sim_core_signals sig)
2474 {
2475 const char *copy = (transfer == read_transfer ? "read" : "write");
2476 address_word ip = CIA_ADDR (cia);
2477
2478 switch (sig)
2479 {
2480 case sim_core_unmapped_signal:
2481 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2482 nr_bytes, copy,
2483 (unsigned long) addr, (unsigned long) ip);
2484 COP0_BADVADDR = addr;
2485 SignalExceptionDataReference();
2486 break;
2487
2488 case sim_core_unaligned_signal:
2489 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2490 nr_bytes, copy,
2491 (unsigned long) addr, (unsigned long) ip);
2492 COP0_BADVADDR = addr;
2493 if(transfer == read_transfer)
2494 SignalExceptionAddressLoad();
2495 else
2496 SignalExceptionAddressStore();
2497 break;
2498
2499 default:
2500 sim_engine_abort (sd, cpu, cia,
2501 "mips_core_signal - internal error - bad switch");
2502 }
2503 }
2504
2505
2506 void
2507 mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2508 {
2509 ASSERT(cpu != NULL);
2510
2511 if(cpu->exc_suspended > 0)
2512 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2513
2514 PC = cia;
2515 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2516 cpu->exc_suspended = 0;
2517 }
2518
2519 void
2520 mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2521 {
2522 ASSERT(cpu != NULL);
2523
2524 if(cpu->exc_suspended > 0)
2525 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2526 cpu->exc_suspended, exception);
2527
2528 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2529 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2530 cpu->exc_suspended = exception;
2531 }
2532
2533 void
2534 mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2535 {
2536 ASSERT(cpu != NULL);
2537
2538 if(exception == 0 && cpu->exc_suspended > 0)
2539 {
2540 /* warn not for breakpoints */
2541 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2542 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2543 cpu->exc_suspended);
2544 }
2545 else if(exception != 0 && cpu->exc_suspended > 0)
2546 {
2547 if(exception != cpu->exc_suspended)
2548 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2549 cpu->exc_suspended, exception);
2550
2551 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2552 }
2553 else if(exception != 0 && cpu->exc_suspended == 0)
2554 {
2555 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2556 }
2557 cpu->exc_suspended = 0;
2558 }
2559
2560
2561 /*---------------------------------------------------------------------------*/
2562 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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