2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
114 static void ColdReset
PARAMS((SIM_DESC sd
));
116 /*---------------------------------------------------------------------------*/
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
126 #define JALDELAYSLOT() {\
128 STATE |= simJALDELAYSLOT;\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
136 #define CANCELDELAYSLOT() {\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
153 static char *tracefile
= "trace.din"; /* default filename for trace log */
154 FILE *tracefh
= NULL
;
155 static void open_trace
PARAMS((SIM_DESC sd
));
158 static DECLARE_OPTION_HANDLER (mips_option_handler
);
160 #define OPTION_DINERO_TRACE 200
161 #define OPTION_DINERO_FILE 201
164 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
174 case OPTION_DINERO_TRACE
: /* ??? */
176 /* Eventually the simTRACE flag could be treated as a toggle, to
177 allow external control of the program points being traced
178 (i.e. only from main onwards, excluding the run-time setup,
180 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
182 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
185 else if (strcmp (arg
, "yes") == 0)
187 else if (strcmp (arg
, "no") == 0)
189 else if (strcmp (arg
, "on") == 0)
191 else if (strcmp (arg
, "off") == 0)
195 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
202 Simulator constructed without dinero tracing support (for performance).\n\
203 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
207 case OPTION_DINERO_FILE
:
209 if (optarg
!= NULL
) {
211 tmp
= (char *)malloc(strlen(optarg
) + 1);
214 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
220 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
231 static const OPTION mips_options
[] =
233 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
234 '\0', "on|off", "Enable dinero tracing",
235 mips_option_handler
},
236 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
237 '\0', "FILE", "Write dinero trace to FILE",
238 mips_option_handler
},
239 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
243 int interrupt_pending
;
246 interrupt_event (SIM_DESC sd
, void *data
)
248 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
251 interrupt_pending
= 0;
252 SignalExceptionInterrupt ();
254 else if (!interrupt_pending
)
255 sim_events_schedule (sd
, 1, interrupt_event
, data
);
259 /*---------------------------------------------------------------------------*/
260 /*-- Device registration hook -----------------------------------------------*/
261 /*---------------------------------------------------------------------------*/
262 static void device_init(SIM_DESC sd
) {
264 extern void register_devices(SIM_DESC
);
265 register_devices(sd
);
269 /* start-sanitize-sky */
272 short i
[NUM_VU_INTEGER_REGS
];
273 int f
[NUM_VU_REGS
- NUM_VU_INTEGER_REGS
];
276 /* end-sanitize-sky */
278 /*---------------------------------------------------------------------------*/
279 /*-- GDB simulator interface ------------------------------------------------*/
280 /*---------------------------------------------------------------------------*/
283 sim_open (kind
, cb
, abfd
, argv
)
289 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
290 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
292 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
294 /* FIXME: watchpoints code shouldn't need this */
295 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
296 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
297 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
301 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
303 sim_add_option_table (sd
, NULL
, mips_options
);
305 /* Allocate core managed memory */
308 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
309 /* For compatibility with the old code - under this (at level one)
310 are the kernel spaces K0 & K1. Both of these map to a single
311 smaller sub region */
312 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
313 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
315 MEM_SIZE
, /* actual size */
320 /* getopt will print the error message so we just have to exit if this fails.
321 FIXME: Hmmm... in the case of gdb we need getopt to call
323 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
325 /* Uninstall the modules to avoid memory leaks,
326 file descriptor leaks, etc. */
327 sim_module_uninstall (sd
);
331 /* check for/establish the a reference program image */
332 if (sim_analyze_program (sd
,
333 (STATE_PROG_ARGV (sd
) != NULL
334 ? *STATE_PROG_ARGV (sd
)
338 sim_module_uninstall (sd
);
342 /* Configure/verify the target byte order and other runtime
343 configuration options */
344 if (sim_config (sd
) != SIM_RC_OK
)
346 sim_module_uninstall (sd
);
350 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
352 /* Uninstall the modules to avoid memory leaks,
353 file descriptor leaks, etc. */
354 sim_module_uninstall (sd
);
358 /* verify assumptions the simulator made about the host type system.
359 This macro does not return if there is a problem */
360 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
361 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
363 /* This is NASTY, in that we are assuming the size of specific
367 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
370 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
371 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
372 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
373 else if ((rn
>= 33) && (rn
<= 37))
374 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
375 else if ((rn
== SRIDX
)
378 || ((rn
>= 72) && (rn
<= 89)))
379 cpu
->register_widths
[rn
] = 32;
381 cpu
->register_widths
[rn
] = 0;
383 /* start-sanitize-r5900 */
385 /* set the 5900 "upper" registers to 64 bits */
386 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
387 cpu
->register_widths
[rn
] = 64;
388 /* end-sanitize-r5900 */
390 /* start-sanitize-sky */
392 /* Now the VU registers */
393 for( rn
= 0; rn
< NUM_VU_INTEGER_REGS
; rn
++ ) {
394 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 16;
395 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 16;
397 /* Hack for now - to test gdb interface */
398 vu_regs
[0].i
[rn
] = rn
+ 0x100;
399 vu_regs
[1].i
[rn
] = rn
+ 0x200;
402 for( rn
= NUM_VU_INTEGER_REGS
; rn
< NUM_VU_REGS
; rn
++ ) {
404 int first_vec_reg
= NUM_VU_INTEGER_REGS
+ 8;
406 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
407 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 32;
409 /* Hack for now - to test gdb interface */
410 if( rn
< first_vec_reg
) {
411 f
= rn
- NUM_VU_INTEGER_REGS
+ 100.0;
412 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
413 f
= rn
- NUM_VU_INTEGER_REGS
+ 200.0;
414 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
417 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 1000.0;
418 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
419 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 2000.0;
420 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
424 /* end-sanitize-sky */
428 if (STATE
& simTRACE
)
432 /* Write the monitor trap address handlers into the monitor (eeprom)
433 address space. This can only be done once the target endianness
434 has been determined. */
437 /* Entry into the IDT monitor is via fixed address vectors, and
438 not using machine instructions. To avoid clashing with use of
439 the MIPS TRAP system, we place our own (simulator specific)
440 "undefined" instructions into the relevant vector slots. */
441 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
443 address_word vaddr
= (MONITOR_BASE
+ loop
);
444 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
446 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
448 /* The PMON monitor uses the same address space, but rather than
449 branching into it the address of a routine is loaded. We can
450 cheat for the moment, and direct the PMON routine to IDT style
451 instructions within the monitor space. This relies on the IDT
452 monitor not using the locations from 0xBFC00500 onwards as its
454 for (loop
= 0; (loop
< 24); loop
++)
456 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
457 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
473 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
475 case 8: /* cliexit */
478 case 11: /* flush_cache */
482 /* FIXME - should monitor_base be SIM_ADDR?? */
483 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
485 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
487 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
489 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
501 tracefh
= fopen(tracefile
,"wb+");
504 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
511 sim_close (sd
, quitting
)
516 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
519 /* "quitting" is non-zero if we cannot hang on errors */
521 /* Ensure that any resources allocated through the callback
522 mechanism are released: */
523 sim_io_shutdown (sd
);
526 if (tracefh
!= NULL
&& tracefh
!= stderr
)
531 /* FIXME - free SD */
538 sim_write (sd
,addr
,buffer
,size
)
541 unsigned char *buffer
;
545 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
547 /* Return the number of bytes written, or zero if error. */
549 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
552 /* We use raw read and write routines, since we do not want to count
553 the GDB memory accesses in our statistics gathering. */
555 for (index
= 0; index
< size
; index
++)
557 address_word vaddr
= (address_word
)addr
+ index
;
560 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
562 if (sim_core_write_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
570 sim_read (sd
,addr
,buffer
,size
)
573 unsigned char *buffer
;
577 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
579 /* Return the number of bytes read, or zero if error. */
581 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
584 for (index
= 0; (index
< size
); index
++)
586 address_word vaddr
= (address_word
)addr
+ index
;
589 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
591 if (sim_core_read_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
599 sim_store_register (sd
,rn
,memory
,length
)
602 unsigned char *memory
;
605 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
606 /* NOTE: gdb (the client) stores registers in target byte order
607 while the simulator uses host byte order */
609 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
612 /* Unfortunately this suffers from the same problem as the register
613 numbering one. We need to know what the width of each logical
614 register number is for the architecture being simulated. */
616 if (cpu
->register_widths
[rn
] == 0)
618 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
622 /* start-sanitize-r5900 */
623 if (rn
>= 90 && rn
< 90 + 32)
625 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
631 SA
= T2H_8(*(unsigned64
*)memory
);
633 case 122: /* FIXME */
634 LO1
= T2H_8(*(unsigned64
*)memory
);
636 case 123: /* FIXME */
637 HI1
= T2H_8(*(unsigned64
*)memory
);
640 /* end-sanitize-r5900 */
642 /* start-sanitize-sky */
644 if (rn
>= NUM_R5900_REGS
)
646 int size
= 4; /* Default register size */
648 rn
= rn
- NUM_R5900_REGS
;
650 if (rn
< NUM_VU_INTEGER_REGS
)
652 vu_regs
[0].i
[rn
] = T2H_2( *(unsigned short *) memory
);
655 else if( rn
< NUM_VU_REGS
)
656 vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
]
657 = T2H_4( *(unsigned int *) memory
);
659 rn
= rn
- NUM_VU_REGS
;
661 if( rn
< NUM_VU_INTEGER_REGS
)
663 vu_regs
[1].i
[rn
] = T2H_2( *(unsigned short *) memory
);
666 else if( rn
< NUM_VU_REGS
)
667 vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
]
668 = T2H_4( *(unsigned int *) memory
);
670 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
676 /* end-sanitize-sky */
678 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
680 if (cpu
->register_widths
[rn
] == 32)
682 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
687 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
692 if (cpu
->register_widths
[rn
] == 32)
694 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
699 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
705 sim_fetch_register (sd
,rn
,memory
,length
)
708 unsigned char *memory
;
711 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
712 /* NOTE: gdb (the client) stores registers in target byte order
713 while the simulator uses host byte order */
715 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
718 if (cpu
->register_widths
[rn
] == 0)
720 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
724 /* start-sanitize-r5900 */
725 if (rn
>= 90 && rn
< 90 + 32)
727 *(unsigned64
*)memory
= GPR1
[rn
- 90];
733 *((unsigned64
*)memory
) = H2T_8(SA
);
735 case 122: /* FIXME */
736 *((unsigned64
*)memory
) = H2T_8(LO1
);
738 case 123: /* FIXME */
739 *((unsigned64
*)memory
) = H2T_8(HI1
);
742 /* end-sanitize-r5900 */
744 /* start-sanitize-sky */
746 if (rn
>= NUM_R5900_REGS
)
748 int size
= 4; /* default register width */
750 rn
= rn
- NUM_R5900_REGS
;
752 if (rn
< NUM_VU_INTEGER_REGS
)
754 *((unsigned short *) memory
) = H2T_2( vu_regs
[0].i
[rn
] );
757 else if (rn
< NUM_VU_REGS
)
758 *((unsigned int *) memory
)
759 = H2T_4( vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
] );
762 rn
= rn
- NUM_VU_REGS
;
764 if (rn
< NUM_VU_INTEGER_REGS
)
766 (*(unsigned short *) memory
) = H2T_2( vu_regs
[1].i
[rn
] );
769 else if (rn
< NUM_VU_REGS
)
770 (*(unsigned int *) memory
)
771 = H2T_4( vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
] );
773 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
779 /* end-sanitize-sky */
781 /* Any floating point register */
782 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
784 if (cpu
->register_widths
[rn
] == 32)
786 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
791 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
796 if (cpu
->register_widths
[rn
] == 32)
798 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
803 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
810 sim_create_inferior (sd
, abfd
, argv
,env
)
818 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
826 /* override PC value set by ColdReset () */
828 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
830 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
831 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
835 #if 0 /* def DEBUG */
838 /* We should really place the argv slot values into the argument
839 registers, and onto the stack as required. However, this
840 assumes that we have a stack defined, which is not
841 necessarily true at the moment. */
843 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
844 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
845 printf("DBG: arg \"%s\"\n",*cptr
);
853 sim_do_command (sd
,cmd
)
857 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
858 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
862 /*---------------------------------------------------------------------------*/
863 /*-- Private simulator support interface ------------------------------------*/
864 /*---------------------------------------------------------------------------*/
866 /* Read a null terminated string from memory, return in a buffer */
875 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
877 buf
= NZALLOC (char, nr
+ 1);
878 sim_read (sd
, addr
, buf
, nr
);
882 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
884 sim_monitor (SIM_DESC sd
,
890 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
893 /* The IDT monitor actually allows two instructions per vector
894 slot. However, the simulator currently causes a trap on each
895 individual instruction. We cheat, and lose the bottom bit. */
898 /* The following callback functions are available, however the
899 monitor we are simulating does not make use of them: get_errno,
900 isatty, lseek, rename, system, time and unlink */
904 case 6: /* int open(char *path,int flags) */
906 char *path
= fetch_str (sd
, A0
);
907 V0
= sim_io_open (sd
, path
, (int)A1
);
912 case 7: /* int read(int file,char *ptr,int len) */
916 char *buf
= zalloc (nr
);
917 V0
= sim_io_read (sd
, fd
, buf
, nr
);
918 sim_write (sd
, A1
, buf
, nr
);
923 case 8: /* int write(int file,char *ptr,int len) */
927 char *buf
= zalloc (nr
);
928 sim_read (sd
, A1
, buf
, nr
);
929 V0
= sim_io_write (sd
, fd
, buf
, nr
);
934 case 10: /* int close(int file) */
936 V0
= sim_io_close (sd
, (int)A0
);
940 case 2: /* Densan monitor: char inbyte(int waitflag) */
942 if (A0
== 0) /* waitflag == NOWAIT */
943 V0
= (unsigned_word
)-1;
945 /* Drop through to case 11 */
947 case 11: /* char inbyte(void) */
950 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
952 sim_io_error(sd
,"Invalid return from character read");
953 V0
= (unsigned_word
)-1;
956 V0
= (unsigned_word
)tmp
;
960 case 3: /* Densan monitor: void co(char chr) */
961 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
963 char tmp
= (char)(A0
& 0xFF);
964 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
968 case 17: /* void _exit() */
970 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
971 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
972 (unsigned int)(A0
& 0xFFFFFFFF));
976 case 28 : /* PMON flush_cache */
979 case 55: /* void get_mem_info(unsigned int *ptr) */
980 /* in: A0 = pointer to three word memory location */
981 /* out: [A0 + 0] = size */
982 /* [A0 + 4] = instruction cache size */
983 /* [A0 + 8] = data cache size */
985 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
987 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
988 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
992 case 158 : /* PMON printf */
993 /* in: A0 = pointer to format string */
994 /* A1 = optional argument 1 */
995 /* A2 = optional argument 2 */
996 /* A3 = optional argument 3 */
998 /* The following is based on the PMON printf source */
1000 address_word s
= A0
;
1002 signed_word
*ap
= &A1
; /* 1st argument */
1003 /* This isn't the quickest way, since we call the host print
1004 routine for every character almost. But it does avoid
1005 having to allocate and manage a temporary string buffer. */
1006 /* TODO: Include check that we only use three arguments (A1,
1008 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1013 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1014 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1015 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1017 if (strchr ("dobxXulscefg%", s
))
1032 else if (c
>= '1' && c
<= '9')
1036 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1039 n
= (unsigned int)strtol(tmp
,NULL
,10);
1052 sim_io_printf (sd
, "%%");
1057 address_word p
= *ap
++;
1059 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1060 sim_io_printf(sd
, "%c", ch
);
1063 sim_io_printf(sd
,"(null)");
1066 sim_io_printf (sd
, "%c", (int)*ap
++);
1071 sim_read (sd
, s
++, &c
, 1);
1075 sim_read (sd
, s
++, &c
, 1);
1078 if (strchr ("dobxXu", c
))
1080 word64 lv
= (word64
) *ap
++;
1082 sim_io_printf(sd
,"<binary not supported>");
1085 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1087 sim_io_printf(sd
, tmp
, lv
);
1089 sim_io_printf(sd
, tmp
, (int)lv
);
1092 else if (strchr ("eEfgG", c
))
1094 double dbl
= *(double*)(ap
++);
1095 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1096 sim_io_printf (sd
, tmp
, dbl
);
1102 sim_io_printf(sd
, "%c", c
);
1108 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1109 reason
, pr_addr(cia
));
1115 /* Store a word into memory. */
1118 store_word (SIM_DESC sd
,
1127 if ((vaddr
& 3) != 0)
1128 SignalExceptionAddressStore ();
1131 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1134 const uword64 mask
= 7;
1138 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1139 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1140 memval
= ((uword64
) val
) << (8 * byte
);
1141 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1147 /* Load a word from memory. */
1150 load_word (SIM_DESC sd
,
1155 if ((vaddr
& 3) != 0)
1156 SignalExceptionAddressLoad ();
1162 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1165 const uword64 mask
= 0x7;
1166 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1167 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1171 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1172 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1174 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1175 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1182 /* Simulate the mips16 entry and exit pseudo-instructions. These
1183 would normally be handled by the reserved instruction exception
1184 code, but for ease of simulation we just handle them directly. */
1187 mips16_entry (SIM_DESC sd
,
1192 int aregs
, sregs
, rreg
;
1195 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1198 aregs
= (insn
& 0x700) >> 8;
1199 sregs
= (insn
& 0x0c0) >> 6;
1200 rreg
= (insn
& 0x020) >> 5;
1202 /* This should be checked by the caller. */
1211 /* This is the entry pseudo-instruction. */
1213 for (i
= 0; i
< aregs
; i
++)
1214 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1222 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1225 for (i
= 0; i
< sregs
; i
++)
1228 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1236 /* This is the exit pseudo-instruction. */
1243 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1246 for (i
= 0; i
< sregs
; i
++)
1249 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1254 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1258 FGR
[0] = WORD64LO (GPR
[4]);
1259 FPR_STATE
[0] = fmt_uninterpreted
;
1261 else if (aregs
== 6)
1263 FGR
[0] = WORD64LO (GPR
[5]);
1264 FGR
[1] = WORD64LO (GPR
[4]);
1265 FPR_STATE
[0] = fmt_uninterpreted
;
1266 FPR_STATE
[1] = fmt_uninterpreted
;
1275 /*-- trace support ----------------------------------------------------------*/
1277 /* The TRACE support is provided (if required) in the memory accessing
1278 routines. Since we are also providing the architecture specific
1279 features, the architecture simulation code can also deal with
1280 notifying the TRACE world of cache flushes, etc. Similarly we do
1281 not need to provide profiling support in the simulator engine,
1282 since we can sample in the instruction fetch control loop. By
1283 defining the TRACE manifest, we add tracing as a run-time
1287 /* Tracing by default produces "din" format (as required by
1288 dineroIII). Each line of such a trace file *MUST* have a din label
1289 and address field. The rest of the line is ignored, so comments can
1290 be included if desired. The first field is the label which must be
1291 one of the following values:
1296 3 escape record (treated as unknown access type)
1297 4 escape record (causes cache flush)
1299 The address field is a 32bit (lower-case) hexadecimal address
1300 value. The address should *NOT* be preceded by "0x".
1302 The size of the memory transfer is not important when dealing with
1303 cache lines (as long as no more than a cache line can be
1304 transferred in a single operation :-), however more information
1305 could be given following the dineroIII requirement to allow more
1306 complete memory and cache simulators to provide better
1307 results. i.e. the University of Pisa has a cache simulator that can
1308 also take bus size and speed as (variable) inputs to calculate
1309 complete system performance (a much more useful ability when trying
1310 to construct an end product, rather than a processor). They
1311 currently have an ARM version of their tool called ChARM. */
1315 dotrace (SIM_DESC sd
,
1323 if (STATE
& simTRACE
) {
1325 fprintf(tracefh
,"%d %s ; width %d ; ",
1329 va_start(ap
,comment
);
1330 vfprintf(tracefh
,comment
,ap
);
1332 fprintf(tracefh
,"\n");
1334 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1335 we may be generating 64bit ones, we should put the hi-32bits of the
1336 address into the comment field. */
1338 /* TODO: Provide a buffer for the trace lines. We can then avoid
1339 performing writes until the buffer is filled, or the file is
1342 /* NOTE: We could consider adding a comment field to the "din" file
1343 produced using type 3 markers (unknown access). This would then
1344 allow information about the program that the "din" is for, and
1345 the MIPs world that was being simulated, to be placed into the
1352 /*---------------------------------------------------------------------------*/
1353 /*-- simulator engine -------------------------------------------------------*/
1354 /*---------------------------------------------------------------------------*/
1357 ColdReset (SIM_DESC sd
)
1360 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1362 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1363 /* RESET: Fixed PC address: */
1364 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1365 /* The reset vector address is in the unmapped, uncached memory space. */
1367 SR
&= ~(status_SR
| status_TS
| status_RP
);
1368 SR
|= (status_ERL
| status_BEV
);
1370 /* Cheat and allow access to the complete register set immediately */
1371 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1372 && WITH_TARGET_WORD_BITSIZE
== 64)
1373 SR
|= status_FR
; /* 64bit registers */
1375 /* Ensure that any instructions with pending register updates are
1377 PENDING_INVALIDATE();
1379 /* Initialise the FPU registers to the unknown state */
1380 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1383 for (rn
= 0; (rn
< 32); rn
++)
1384 FPR_STATE
[rn
] = fmt_uninterpreted
;
1390 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1392 /* Translate a virtual address to a physical address and cache
1393 coherence algorithm describing the mechanism used to resolve the
1394 memory reference. Given the virtual address vAddr, and whether the
1395 reference is to Instructions ot Data (IorD), find the corresponding
1396 physical address (pAddr) and the cache coherence algorithm (CCA)
1397 used to resolve the reference. If the virtual address is in one of
1398 the unmapped address spaces the physical address and the CCA are
1399 determined directly by the virtual address. If the virtual address
1400 is in one of the mapped address spaces then the TLB is used to
1401 determine the physical address and access type; if the required
1402 translation is not present in the TLB or the desired access is not
1403 permitted the function fails and an exception is taken.
1405 NOTE: Normally (RAW == 0), when address translation fails, this
1406 function raises an exception and does not return. */
1409 address_translation (SIM_DESC sd
,
1415 address_word
*pAddr
,
1419 int res
= -1; /* TRUE : Assume good return */
1422 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1425 /* Check that the address is valid for this memory model */
1427 /* For a simple (flat) memory model, we simply pass virtual
1428 addressess through (mostly) unchanged. */
1429 vAddr
&= 0xFFFFFFFF;
1431 *pAddr
= vAddr
; /* default for isTARGET */
1432 *CCA
= Uncached
; /* not used for isHOST */
1437 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1439 /* Prefetch data from memory. Prefetch is an advisory instruction for
1440 which an implementation specific action is taken. The action taken
1441 may increase performance, but must not change the meaning of the
1442 program, or alter architecturally-visible state. */
1445 prefetch (SIM_DESC sd
,
1455 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1458 /* For our simple memory model we do nothing */
1462 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1464 /* Load a value from memory. Use the cache and main memory as
1465 specified in the Cache Coherence Algorithm (CCA) and the sort of
1466 access (IorD) to find the contents of AccessLength memory bytes
1467 starting at physical location pAddr. The data is returned in the
1468 fixed width naturally-aligned memory element (MemElem). The
1469 low-order two (or three) bits of the address and the AccessLength
1470 indicate which of the bytes within MemElem needs to be given to the
1471 processor. If the memory access type of the reference is uncached
1472 then only the referenced bytes are read from memory and valid
1473 within the memory element. If the access type is cached, and the
1474 data is not present in cache, an implementation specific size and
1475 alignment block of memory is read and loaded into the cache to
1476 satisfy a load reference. At a minimum, the block is the entire
1479 load_memory (SIM_DESC sd
,
1494 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1497 #if defined(WARN_MEM)
1498 if (CCA
!= uncached
)
1499 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1500 #endif /* WARN_MEM */
1502 /* If instruction fetch then we need to check that the two lo-order
1503 bits are zero, otherwise raise a InstructionFetch exception: */
1504 if ((IorD
== isINSTRUCTION
)
1505 && ((pAddr
& 0x3) != 0)
1506 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1507 SignalExceptionInstructionFetch ();
1509 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1511 /* In reality this should be a Bus Error */
1512 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1514 (LOADDRMASK
+ 1) << 2,
1519 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1522 /* Read the specified number of bytes from memory. Adjust for
1523 host/target byte ordering/ Align the least significant byte
1526 switch (AccessLength
)
1528 case AccessLength_QUADWORD
:
1530 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
,
1531 sim_core_read_map
, pAddr
);
1532 value1
= VH8_16 (val
);
1533 value
= VL8_16 (val
);
1536 case AccessLength_DOUBLEWORD
:
1537 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1538 sim_core_read_map
, pAddr
);
1540 case AccessLength_SEPTIBYTE
:
1541 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1542 sim_core_read_map
, pAddr
);
1544 case AccessLength_SEXTIBYTE
:
1545 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1546 sim_core_read_map
, pAddr
);
1548 case AccessLength_QUINTIBYTE
:
1549 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1550 sim_core_read_map
, pAddr
);
1552 case AccessLength_WORD
:
1553 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1554 sim_core_read_map
, pAddr
);
1556 case AccessLength_TRIPLEBYTE
:
1557 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1558 sim_core_read_map
, pAddr
);
1560 case AccessLength_HALFWORD
:
1561 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1562 sim_core_read_map
, pAddr
);
1564 case AccessLength_BYTE
:
1565 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1566 sim_core_read_map
, pAddr
);
1573 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1574 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1577 /* See also store_memory. */
1578 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1581 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1582 shifted to the most significant byte position. */
1583 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1585 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1586 is already in the correct postition. */
1587 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1591 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1592 pr_uword64(value1
),pr_uword64(value
));
1596 if (memval1p
) *memval1p
= value1
;
1600 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1602 /* Store a value to memory. The specified data is stored into the
1603 physical location pAddr using the memory hierarchy (data caches and
1604 main memory) as specified by the Cache Coherence Algorithm
1605 (CCA). The MemElem contains the data for an aligned, fixed-width
1606 memory element (word for 32-bit processors, doubleword for 64-bit
1607 processors), though only the bytes that will actually be stored to
1608 memory need to be valid. The low-order two (or three) bits of pAddr
1609 and the AccessLength field indicates which of the bytes within the
1610 MemElem data should actually be stored; only these bytes in memory
1614 store_memory (SIM_DESC sd
,
1620 uword64 MemElem1
, /* High order 64 bits */
1625 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1628 #if defined(WARN_MEM)
1629 if (CCA
!= uncached
)
1630 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1631 #endif /* WARN_MEM */
1633 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1634 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1637 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1641 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1644 /* See also load_memory */
1645 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1648 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1649 shifted to the most significant byte position. */
1650 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1652 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1653 is already in the correct postition. */
1654 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1658 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1661 switch (AccessLength
)
1663 case AccessLength_QUADWORD
:
1665 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1666 sim_core_write_aligned_16 (cpu
, NULL_CIA
,
1667 sim_core_write_map
, pAddr
, val
);
1670 case AccessLength_DOUBLEWORD
:
1671 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1672 sim_core_write_map
, pAddr
, MemElem
);
1674 case AccessLength_SEPTIBYTE
:
1675 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1676 sim_core_write_map
, pAddr
, MemElem
);
1678 case AccessLength_SEXTIBYTE
:
1679 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1680 sim_core_write_map
, pAddr
, MemElem
);
1682 case AccessLength_QUINTIBYTE
:
1683 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1684 sim_core_write_map
, pAddr
, MemElem
);
1686 case AccessLength_WORD
:
1687 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1688 sim_core_write_map
, pAddr
, MemElem
);
1690 case AccessLength_TRIPLEBYTE
:
1691 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1692 sim_core_write_map
, pAddr
, MemElem
);
1694 case AccessLength_HALFWORD
:
1695 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1696 sim_core_write_map
, pAddr
, MemElem
);
1698 case AccessLength_BYTE
:
1699 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1700 sim_core_write_map
, pAddr
, MemElem
);
1711 ifetch32 (SIM_DESC sd
,
1716 /* Copy the action of the LW instruction */
1717 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1718 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1721 unsigned32 instruction
;
1724 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1725 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1726 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1727 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1728 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1734 ifetch16 (SIM_DESC sd
,
1739 /* Copy the action of the LW instruction */
1740 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1741 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1744 unsigned16 instruction
;
1747 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1748 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1749 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1750 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1751 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1756 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1757 /* Order loads and stores to synchronise shared memory. Perform the
1758 action necessary to make the effects of groups of synchronizable
1759 loads and stores indicated by stype occur in the same order for all
1762 sync_operation (SIM_DESC sd
,
1768 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1773 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1774 /* Signal an exception condition. This will result in an exception
1775 that aborts the instruction. The instruction operation pseudocode
1776 will never see a return from this function call. */
1779 signal_exception (SIM_DESC sd
,
1787 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1790 /* Ensure that any active atomic read/modify/write operation will fail: */
1793 switch (exception
) {
1794 /* TODO: For testing purposes I have been ignoring TRAPs. In
1795 reality we should either simulate them, or allow the user to
1796 ignore them at run-time.
1799 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1805 unsigned int instruction
;
1808 va_start(ap
,exception
);
1809 instruction
= va_arg(ap
,unsigned int);
1812 code
= (instruction
>> 6) & 0xFFFFF;
1814 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1815 code
, pr_addr(cia
));
1819 case DebugBreakPoint
:
1820 if (! (Debug
& Debug_DM
))
1826 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1827 DEPC
= cia
- 4; /* reference the branch instruction */
1831 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1835 Debug
|= Debug_DM
; /* in debugging mode */
1836 Debug
|= Debug_DBp
; /* raising a DBp exception */
1838 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1842 case ReservedInstruction
:
1845 unsigned int instruction
;
1846 va_start(ap
,exception
);
1847 instruction
= va_arg(ap
,unsigned int);
1849 /* Provide simple monitor support using ReservedInstruction
1850 exceptions. The following code simulates the fixed vector
1851 entry points into the IDT monitor by causing a simulator
1852 trap, performing the monitor operation, and returning to
1853 the address held in the $ra register (standard PCS return
1854 address). This means we only need to pre-load the vector
1855 space with suitable instruction values. For systems were
1856 actual trap instructions are used, we would not need to
1857 perform this magic. */
1858 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1860 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1861 /* NOTE: This assumes that a branch-and-link style
1862 instruction was used to enter the vector (which is the
1863 case with the current IDT monitor). */
1864 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1866 /* Look for the mips16 entry and exit instructions, and
1867 simulate a handler for them. */
1868 else if ((cia
& 1) != 0
1869 && (instruction
& 0xf81f) == 0xe809
1870 && (instruction
& 0x0c0) != 0x0c0)
1872 mips16_entry (SD
, CPU
, cia
, instruction
);
1873 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1875 /* else fall through to normal exception processing */
1876 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1881 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1883 /* Keep a copy of the current A0 in-case this is the program exit
1887 unsigned int instruction
;
1888 va_start(ap
,exception
);
1889 instruction
= va_arg(ap
,unsigned int);
1891 /* Check for our special terminating BREAK: */
1892 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1893 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1894 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1897 if (STATE
& simDELAYSLOT
)
1898 PC
= cia
- 4; /* reference the branch instruction */
1901 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1902 sim_stopped
, SIM_SIGTRAP
);
1905 /* Store exception code into current exception id variable (used
1908 /* TODO: If not simulating exceptions then stop the simulator
1909 execution. At the moment we always stop the simulation. */
1911 /* See figure 5-17 for an outline of the code below */
1912 if (! (SR
& status_EXL
))
1914 CAUSE
= (exception
<< 2);
1915 if (STATE
& simDELAYSLOT
)
1917 STATE
&= ~simDELAYSLOT
;
1919 EPC
= (cia
- 4); /* reference the branch instruction */
1923 /* FIXME: TLB et.al. */
1928 CAUSE
= (exception
<< 2);
1932 /* Store exception code into current exception id variable (used
1934 if (SR
& status_BEV
)
1935 PC
= (signed)0xBFC00200 + 0x180;
1937 PC
= (signed)0x80000000 + 0x180;
1939 switch ((CAUSE
>> 2) & 0x1F)
1942 /* Interrupts arrive during event processing, no need to
1946 case TLBModification
:
1951 case InstructionFetch
:
1953 /* The following is so that the simulator will continue from the
1954 exception address on breakpoint operations. */
1956 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1957 sim_stopped
, SIM_SIGBUS
);
1959 case ReservedInstruction
:
1960 case CoProcessorUnusable
:
1962 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1963 sim_stopped
, SIM_SIGILL
);
1965 case IntegerOverflow
:
1967 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1968 sim_stopped
, SIM_SIGFPE
);
1974 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1975 sim_stopped
, SIM_SIGTRAP
);
1979 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1980 "FATAL: Should not encounter a breakpoint\n");
1982 default : /* Unknown internal exception */
1984 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1985 sim_stopped
, SIM_SIGABRT
);
1989 case SimulatorFault
:
1993 va_start(ap
,exception
);
1994 msg
= va_arg(ap
,char *);
1996 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1997 "FATAL: Simulator error \"%s\"\n",msg
);
2004 #if defined(WARN_RESULT)
2005 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2006 /* This function indicates that the result of the operation is
2007 undefined. However, this should not affect the instruction
2008 stream. All that is meant to happen is that the destination
2009 register is set to an undefined result. To keep the simulator
2010 simple, we just don't bother updating the destination register, so
2011 the overall result will be undefined. If desired we can stop the
2012 simulator by raising a pseudo-exception. */
2013 #define UndefinedResult() undefined_result (sd,cia)
2015 undefined_result(sd
,cia
)
2019 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
2020 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2025 #endif /* WARN_RESULT */
2028 cache_op (SIM_DESC sd
,
2034 unsigned int instruction
)
2036 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2037 static int icache_warning
= 1;
2038 static int dcache_warning
= 1;
2040 static int icache_warning
= 0;
2041 static int dcache_warning
= 0;
2044 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2045 enable bit in the Status Register is clear - a coprocessor
2046 unusable exception is taken. */
2048 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
2052 case 0: /* instruction cache */
2054 case 0: /* Index Invalidate */
2055 case 1: /* Index Load Tag */
2056 case 2: /* Index Store Tag */
2057 case 4: /* Hit Invalidate */
2059 case 6: /* Hit Writeback */
2060 if (!icache_warning
)
2062 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2068 SignalException(ReservedInstruction
,instruction
);
2073 case 1: /* data cache */
2075 case 0: /* Index Writeback Invalidate */
2076 case 1: /* Index Load Tag */
2077 case 2: /* Index Store Tag */
2078 case 3: /* Create Dirty */
2079 case 4: /* Hit Invalidate */
2080 case 5: /* Hit Writeback Invalidate */
2081 case 6: /* Hit Writeback */
2082 if (!dcache_warning
)
2084 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2090 SignalException(ReservedInstruction
,instruction
);
2095 default: /* unrecognised cache ID */
2096 SignalException(ReservedInstruction
,instruction
);
2103 /*-- FPU support routines ---------------------------------------------------*/
2105 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2106 formats conform to ANSI/IEEE Std 754-1985. */
2107 /* SINGLE precision floating:
2108 * seeeeeeeefffffffffffffffffffffff
2110 * e = 8bits = exponent
2111 * f = 23bits = fraction
2113 /* SINGLE precision fixed:
2114 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2116 * i = 31bits = integer
2118 /* DOUBLE precision floating:
2119 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2121 * e = 11bits = exponent
2122 * f = 52bits = fraction
2124 /* DOUBLE precision fixed:
2125 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2127 * i = 63bits = integer
2130 /* Extract sign-bit: */
2131 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2132 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2133 /* Extract biased exponent: */
2134 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2135 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2136 /* Extract unbiased Exponent: */
2137 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2138 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2139 /* Extract complete fraction field: */
2140 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2141 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2142 /* Extract numbered fraction bit: */
2143 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2144 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2146 /* Explicit QNaN values used when value required: */
2147 #define FPQNaN_SINGLE (0x7FBFFFFF)
2148 #define FPQNaN_WORD (0x7FFFFFFF)
2149 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2150 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2152 /* Explicit Infinity values used when required: */
2153 #define FPINF_SINGLE (0x7F800000)
2154 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2156 #if 1 /* def DEBUG */
2157 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2158 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2162 value_fpr (SIM_DESC sd
,
2171 /* Treat unused register values, as fixed-point 64bit values: */
2172 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2174 /* If request to read data as "uninterpreted", then use the current
2176 fmt
= FPR_STATE
[fpr
];
2181 /* For values not yet accessed, set to the desired format: */
2182 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2183 FPR_STATE
[fpr
] = fmt
;
2185 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2188 if (fmt
!= FPR_STATE
[fpr
]) {
2189 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2190 FPR_STATE
[fpr
] = fmt_unknown
;
2193 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2194 /* Set QNaN value: */
2197 value
= FPQNaN_SINGLE
;
2201 value
= FPQNaN_DOUBLE
;
2205 value
= FPQNaN_WORD
;
2209 value
= FPQNaN_LONG
;
2216 } else if (SizeFGR() == 64) {
2220 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2223 case fmt_uninterpreted
:
2237 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2240 case fmt_uninterpreted
:
2243 if ((fpr
& 1) == 0) { /* even registers only */
2244 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2246 SignalException(ReservedInstruction
,0);
2257 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2260 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2267 store_fpr (SIM_DESC sd
,
2277 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2280 if (SizeFGR() == 64) {
2282 case fmt_uninterpreted_32
:
2283 fmt
= fmt_uninterpreted
;
2286 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2287 FPR_STATE
[fpr
] = fmt
;
2290 case fmt_uninterpreted_64
:
2291 fmt
= fmt_uninterpreted
;
2292 case fmt_uninterpreted
:
2296 FPR_STATE
[fpr
] = fmt
;
2300 FPR_STATE
[fpr
] = fmt_unknown
;
2306 case fmt_uninterpreted_32
:
2307 fmt
= fmt_uninterpreted
;
2310 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2311 FPR_STATE
[fpr
] = fmt
;
2314 case fmt_uninterpreted_64
:
2315 fmt
= fmt_uninterpreted
;
2316 case fmt_uninterpreted
:
2319 if ((fpr
& 1) == 0) { /* even register number only */
2320 FGR
[fpr
+1] = (value
>> 32);
2321 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2322 FPR_STATE
[fpr
+ 1] = fmt
;
2323 FPR_STATE
[fpr
] = fmt
;
2325 FPR_STATE
[fpr
] = fmt_unknown
;
2326 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2327 SignalException(ReservedInstruction
,0);
2332 FPR_STATE
[fpr
] = fmt_unknown
;
2337 #if defined(WARN_RESULT)
2340 #endif /* WARN_RESULT */
2343 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2346 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2363 sim_fpu_32to (&wop
, op
);
2364 boolean
= sim_fpu_is_nan (&wop
);
2371 sim_fpu_64to (&wop
, op
);
2372 boolean
= sim_fpu_is_nan (&wop
);
2376 fprintf (stderr
, "Bad switch\n");
2381 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2395 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2402 sim_fpu_32to (&wop
, op
);
2403 boolean
= sim_fpu_is_infinity (&wop
);
2409 sim_fpu_64to (&wop
, op
);
2410 boolean
= sim_fpu_is_infinity (&wop
);
2414 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2419 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2433 /* Argument checking already performed by the FPCOMPARE code */
2436 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2439 /* The format type should already have been checked: */
2445 sim_fpu_32to (&wop1
, op1
);
2446 sim_fpu_32to (&wop2
, op2
);
2447 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2454 sim_fpu_64to (&wop1
, op1
);
2455 sim_fpu_64to (&wop2
, op2
);
2456 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2460 fprintf (stderr
, "Bad switch\n");
2465 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2479 /* Argument checking already performed by the FPCOMPARE code */
2482 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2485 /* The format type should already have been checked: */
2491 sim_fpu_32to (&wop1
, op1
);
2492 sim_fpu_32to (&wop2
, op2
);
2493 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2500 sim_fpu_64to (&wop1
, op1
);
2501 sim_fpu_64to (&wop2
, op2
);
2502 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2506 fprintf (stderr
, "Bad switch\n");
2511 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2518 AbsoluteValue(op
,fmt
)
2525 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2528 /* The format type should already have been checked: */
2534 sim_fpu_32to (&wop
, op
);
2535 sim_fpu_abs (&wop
, &wop
);
2536 sim_fpu_to32 (&ans
, &wop
);
2544 sim_fpu_64to (&wop
, op
);
2545 sim_fpu_abs (&wop
, &wop
);
2546 sim_fpu_to64 (&ans
, &wop
);
2551 fprintf (stderr
, "Bad switch\n");
2566 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2569 /* The format type should already have been checked: */
2575 sim_fpu_32to (&wop
, op
);
2576 sim_fpu_neg (&wop
, &wop
);
2577 sim_fpu_to32 (&ans
, &wop
);
2585 sim_fpu_64to (&wop
, op
);
2586 sim_fpu_neg (&wop
, &wop
);
2587 sim_fpu_to64 (&ans
, &wop
);
2592 fprintf (stderr
, "Bad switch\n");
2608 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2611 /* The registers must specify FPRs valid for operands of type
2612 "fmt". If they are not valid, the result is undefined. */
2614 /* The format type should already have been checked: */
2622 sim_fpu_32to (&wop1
, op1
);
2623 sim_fpu_32to (&wop2
, op2
);
2624 sim_fpu_add (&ans
, &wop1
, &wop2
);
2625 sim_fpu_to32 (&res
, &ans
);
2635 sim_fpu_64to (&wop1
, op1
);
2636 sim_fpu_64to (&wop2
, op2
);
2637 sim_fpu_add (&ans
, &wop1
, &wop2
);
2638 sim_fpu_to64 (&res
, &ans
);
2643 fprintf (stderr
, "Bad switch\n");
2648 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2663 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2666 /* The registers must specify FPRs valid for operands of type
2667 "fmt". If they are not valid, the result is undefined. */
2669 /* The format type should already have been checked: */
2677 sim_fpu_32to (&wop1
, op1
);
2678 sim_fpu_32to (&wop2
, op2
);
2679 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2680 sim_fpu_to32 (&res
, &ans
);
2690 sim_fpu_64to (&wop1
, op1
);
2691 sim_fpu_64to (&wop2
, op2
);
2692 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2693 sim_fpu_to64 (&res
, &ans
);
2698 fprintf (stderr
, "Bad switch\n");
2703 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2710 Multiply(op1
,op2
,fmt
)
2718 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2721 /* The registers must specify FPRs valid for operands of type
2722 "fmt". If they are not valid, the result is undefined. */
2724 /* The format type should already have been checked: */
2732 sim_fpu_32to (&wop1
, op1
);
2733 sim_fpu_32to (&wop2
, op2
);
2734 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2735 sim_fpu_to32 (&res
, &ans
);
2745 sim_fpu_64to (&wop1
, op1
);
2746 sim_fpu_64to (&wop2
, op2
);
2747 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2748 sim_fpu_to64 (&res
, &ans
);
2753 fprintf (stderr
, "Bad switch\n");
2758 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2773 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2776 /* The registers must specify FPRs valid for operands of type
2777 "fmt". If they are not valid, the result is undefined. */
2779 /* The format type should already have been checked: */
2787 sim_fpu_32to (&wop1
, op1
);
2788 sim_fpu_32to (&wop2
, op2
);
2789 sim_fpu_div (&ans
, &wop1
, &wop2
);
2790 sim_fpu_to32 (&res
, &ans
);
2800 sim_fpu_64to (&wop1
, op1
);
2801 sim_fpu_64to (&wop2
, op2
);
2802 sim_fpu_div (&ans
, &wop1
, &wop2
);
2803 sim_fpu_to64 (&res
, &ans
);
2808 fprintf (stderr
, "Bad switch\n");
2813 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2827 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2830 /* The registers must specify FPRs valid for operands of type
2831 "fmt". If they are not valid, the result is undefined. */
2833 /* The format type should already have been checked: */
2840 sim_fpu_32to (&wop
, op
);
2841 sim_fpu_inv (&ans
, &wop
);
2842 sim_fpu_to32 (&res
, &ans
);
2851 sim_fpu_64to (&wop
, op
);
2852 sim_fpu_inv (&ans
, &wop
);
2853 sim_fpu_to64 (&res
, &ans
);
2858 fprintf (stderr
, "Bad switch\n");
2863 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2877 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2880 /* The registers must specify FPRs valid for operands of type
2881 "fmt". If they are not valid, the result is undefined. */
2883 /* The format type should already have been checked: */
2890 sim_fpu_32to (&wop
, op
);
2891 sim_fpu_sqrt (&ans
, &wop
);
2892 sim_fpu_to32 (&res
, &ans
);
2901 sim_fpu_64to (&wop
, op
);
2902 sim_fpu_sqrt (&ans
, &wop
);
2903 sim_fpu_to64 (&res
, &ans
);
2908 fprintf (stderr
, "Bad switch\n");
2913 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2928 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2931 /* The registers must specify FPRs valid for operands of type
2932 "fmt". If they are not valid, the result is undefined. */
2934 /* The format type should already have been checked: */
2941 sim_fpu_32to (&wop1
, op1
);
2942 sim_fpu_32to (&wop2
, op2
);
2943 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2950 sim_fpu_64to (&wop1
, op1
);
2951 sim_fpu_64to (&wop2
, op2
);
2952 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2956 fprintf (stderr
, "Bad switch\n");
2962 case SIM_FPU_IS_SNAN
:
2963 case SIM_FPU_IS_QNAN
:
2965 case SIM_FPU_IS_NINF
:
2966 case SIM_FPU_IS_NNUMBER
:
2967 case SIM_FPU_IS_NDENORM
:
2968 case SIM_FPU_IS_NZERO
:
2969 result
= op2
; /* op1 - op2 < 0 */
2970 case SIM_FPU_IS_PINF
:
2971 case SIM_FPU_IS_PNUMBER
:
2972 case SIM_FPU_IS_PDENORM
:
2973 case SIM_FPU_IS_PZERO
:
2974 result
= op1
; /* op1 - op2 > 0 */
2976 fprintf (stderr
, "Bad switch\n");
2981 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2996 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2999 /* The registers must specify FPRs valid for operands of type
3000 "fmt". If they are not valid, the result is undefined. */
3002 /* The format type should already have been checked: */
3009 sim_fpu_32to (&wop1
, op1
);
3010 sim_fpu_32to (&wop2
, op2
);
3011 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3018 sim_fpu_64to (&wop1
, op1
);
3019 sim_fpu_64to (&wop2
, op2
);
3020 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3024 fprintf (stderr
, "Bad switch\n");
3030 case SIM_FPU_IS_SNAN
:
3031 case SIM_FPU_IS_QNAN
:
3033 case SIM_FPU_IS_NINF
:
3034 case SIM_FPU_IS_NNUMBER
:
3035 case SIM_FPU_IS_NDENORM
:
3036 case SIM_FPU_IS_NZERO
:
3037 result
= op1
; /* op1 - op2 < 0 */
3038 case SIM_FPU_IS_PINF
:
3039 case SIM_FPU_IS_PNUMBER
:
3040 case SIM_FPU_IS_PDENORM
:
3041 case SIM_FPU_IS_PZERO
:
3042 result
= op2
; /* op1 - op2 > 0 */
3044 fprintf (stderr
, "Bad switch\n");
3049 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3056 convert (SIM_DESC sd
,
3065 sim_fpu_round round
;
3066 unsigned32 result32
;
3067 unsigned64 result64
;
3070 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3076 /* Round result to nearest representable value. When two
3077 representable values are equally near, round to the value
3078 that has a least significant bit of zero (i.e. is even). */
3079 round
= sim_fpu_round_near
;
3082 /* Round result to the value closest to, and not greater in
3083 magnitude than, the result. */
3084 round
= sim_fpu_round_zero
;
3087 /* Round result to the value closest to, and not less than,
3089 round
= sim_fpu_round_up
;
3093 /* Round result to the value closest to, and not greater than,
3095 round
= sim_fpu_round_down
;
3099 fprintf (stderr
, "Bad switch\n");
3103 /* Convert the input to sim_fpu internal format */
3107 sim_fpu_64to (&wop
, op
);
3110 sim_fpu_32to (&wop
, op
);
3113 sim_fpu_i32to (&wop
, op
, round
);
3116 sim_fpu_i64to (&wop
, op
, round
);
3119 fprintf (stderr
, "Bad switch\n");
3123 /* Convert sim_fpu format into the output */
3124 /* The value WOP is converted to the destination format, rounding
3125 using mode RM. When the destination is a fixed-point format, then
3126 a source value of Infinity, NaN or one which would round to an
3127 integer outside the fixed point range then an IEEE Invalid
3128 Operation condition is raised. */
3132 sim_fpu_round_32 (&wop
, round
, 0);
3133 sim_fpu_to32 (&result32
, &wop
);
3134 result64
= result32
;
3137 sim_fpu_round_64 (&wop
, round
, 0);
3138 sim_fpu_to64 (&result64
, &wop
);
3141 sim_fpu_to32i (&result32
, &wop
, round
);
3142 result64
= result32
;
3145 sim_fpu_to64i (&result64
, &wop
, round
);
3149 fprintf (stderr
, "Bad switch\n");
3154 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
3161 /*-- co-processor support routines ------------------------------------------*/
3164 CoProcPresent(coproc_number
)
3165 unsigned int coproc_number
;
3167 /* Return TRUE if simulator provides a model for the given co-processor number */
3172 cop_lw (SIM_DESC sd
,
3177 unsigned int memword
)
3182 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3185 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3187 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3188 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3193 #if 0 /* this should be controlled by a configuration option */
3194 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
3203 cop_ld (SIM_DESC sd
,
3210 switch (coproc_num
) {
3212 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3214 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3219 #if 0 /* this message should be controlled by a configuration option */
3220 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
3229 cop_sw (SIM_DESC sd
,
3235 unsigned int value
= 0;
3240 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3243 hold
= FPR_STATE
[coproc_reg
];
3244 FPR_STATE
[coproc_reg
] = fmt_word
;
3245 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3246 FPR_STATE
[coproc_reg
] = hold
;
3251 #if 0 /* should be controlled by configuration option */
3252 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3261 cop_sd (SIM_DESC sd
,
3271 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3273 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3278 #if 0 /* should be controlled by configuration option */
3279 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3288 decode_coproc (SIM_DESC sd
,
3291 unsigned int instruction
)
3293 int coprocnum
= ((instruction
>> 26) & 3);
3297 case 0: /* standard CPU control and cache registers */
3299 int code
= ((instruction
>> 21) & 0x1F);
3300 /* R4000 Users Manual (second edition) lists the following CP0
3302 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3303 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3304 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3305 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3306 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3307 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3308 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3309 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3310 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3311 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3313 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3315 int rt
= ((instruction
>> 16) & 0x1F);
3316 int rd
= ((instruction
>> 11) & 0x1F);
3318 switch (rd
) /* NOTEs: Standard CP0 registers */
3320 /* 0 = Index R4000 VR4100 VR4300 */
3321 /* 1 = Random R4000 VR4100 VR4300 */
3322 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3323 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3324 /* 4 = Context R4000 VR4100 VR4300 */
3325 /* 5 = PageMask R4000 VR4100 VR4300 */
3326 /* 6 = Wired R4000 VR4100 VR4300 */
3327 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3328 /* 9 = Count R4000 VR4100 VR4300 */
3329 /* 10 = EntryHi R4000 VR4100 VR4300 */
3330 /* 11 = Compare R4000 VR4100 VR4300 */
3331 /* 12 = SR R4000 VR4100 VR4300 */
3338 /* 13 = Cause R4000 VR4100 VR4300 */
3345 /* 14 = EPC R4000 VR4100 VR4300 */
3346 /* 15 = PRId R4000 VR4100 VR4300 */
3347 #ifdef SUBTARGET_R3900
3356 /* 16 = Config R4000 VR4100 VR4300 */
3359 GPR
[rt
] = C0_CONFIG
;
3361 C0_CONFIG
= GPR
[rt
];
3364 #ifdef SUBTARGET_R3900
3373 /* 17 = LLAddr R4000 VR4100 VR4300 */
3375 /* 18 = WatchLo R4000 VR4100 VR4300 */
3376 /* 19 = WatchHi R4000 VR4100 VR4300 */
3377 /* 20 = XContext R4000 VR4100 VR4300 */
3378 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3379 /* 27 = CacheErr R4000 VR4100 */
3380 /* 28 = TagLo R4000 VR4100 VR4300 */
3381 /* 29 = TagHi R4000 VR4100 VR4300 */
3382 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3383 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3384 /* CPR[0,rd] = GPR[rt]; */
3387 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3389 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3392 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3395 if (SR
& status_ERL
)
3397 /* Oops, not yet available */
3398 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3408 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3412 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3420 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3421 /* TODO: When executing an ERET or RFE instruction we should
3422 clear LLBIT, to ensure that any out-standing atomic
3423 read/modify/write sequence fails. */
3427 case 2: /* undefined co-processor */
3428 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3431 case 1: /* should not occur (FPU co-processor) */
3432 case 3: /* should not occur (FPU co-processor) */
3433 SignalException(ReservedInstruction
,instruction
);
3440 /*-- instruction simulation -------------------------------------------------*/
3442 /* When the IGEN simulator is being built, the function below is be
3443 replaced by a generated version. However, WITH_IGEN == 2 indicates
3444 that the fubction below should be compiled but under a different
3445 name (to allow backward compatibility) */
3447 #if (WITH_IGEN != 1)
3449 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3451 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3454 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3457 int next_cpu_nr
; /* ignore */
3458 int nr_cpus
; /* ignore */
3459 int siggnal
; /* ignore */
3461 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3462 #if !defined(FASTSIM)
3463 unsigned int pipeline_count
= 1;
3467 if (STATE_MEMORY (sd
) == NULL
) {
3468 printf("DBG: simulate() entered with no memory\n");
3473 #if 0 /* Disabled to check that everything works OK */
3474 /* The VR4300 seems to sign-extend the PC on its first
3475 access. However, this may just be because it is currently
3476 configured in 32bit mode. However... */
3477 PC
= SIGNEXTEND(PC
,32);
3480 /* main controlling loop */
3482 /* vaddr is slowly being replaced with cia - current instruction
3484 address_word cia
= (uword64
)PC
;
3485 address_word vaddr
= cia
;
3488 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3492 printf("DBG: state = 0x%08X :",state
);
3493 if (state
& simHALTEX
) printf(" simHALTEX");
3494 if (state
& simHALTIN
) printf(" simHALTIN");
3499 DSSTATE
= (STATE
& simDELAYSLOT
);
3502 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3505 /* Fetch the next instruction from the simulator memory: */
3506 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3507 if ((vaddr
& 1) == 0) {
3508 /* Copy the action of the LW instruction */
3509 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3510 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3513 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3514 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3515 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3516 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3518 /* Copy the action of the LH instruction */
3519 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3520 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3523 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3524 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3525 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3526 paddr
& ~ (uword64
) 1,
3527 vaddr
, isINSTRUCTION
, isREAL
);
3528 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3529 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3532 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3537 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3540 /* This is required by exception processing, to ensure that we can
3541 cope with exceptions in the delay slots of branches that may
3542 already have changed the PC. */
3543 if ((vaddr
& 1) == 0)
3544 PC
+= 4; /* increment ready for the next fetch */
3547 /* NOTE: If we perform a delay slot change to the PC, this
3548 increment is not requuired. However, it would make the
3549 simulator more complicated to try and avoid this small hit. */
3551 /* Currently this code provides a simple model. For more
3552 complicated models we could perform exception status checks at
3553 this point, and set the simSTOP state as required. This could
3554 also include processing any hardware interrupts raised by any
3555 I/O model attached to the simulator context.
3557 Support for "asynchronous" I/O events within the simulated world
3558 could be providing by managing a counter, and calling a I/O
3559 specific handler when a particular threshold is reached. On most
3560 architectures a decrement and check for zero operation is
3561 usually quicker than an increment and compare. However, the
3562 process of managing a known value decrement to zero, is higher
3563 than the cost of using an explicit value UINT_MAX into the
3564 future. Which system is used will depend on how complicated the
3565 I/O model is, and how much it is likely to affect the simulator
3568 If events need to be scheduled further in the future than
3569 UINT_MAX event ticks, then the I/O model should just provide its
3570 own counter, triggered from the event system. */
3572 /* MIPS pipeline ticks. To allow for future support where the
3573 pipeline hit of individual instructions is known, this control
3574 loop manages a "pipeline_count" variable. It is initialised to
3575 1 (one), and will only be changed by the simulator engine when
3576 executing an instruction. If the engine does not have access to
3577 pipeline cycle count information then all instructions will be
3578 treated as using a single cycle. NOTE: A standard system is not
3579 provided by the default simulator because different MIPS
3580 architectures have different cycle counts for the same
3583 [NOTE: pipeline_count has been replaced the event queue] */
3585 /* shuffle the floating point status pipeline state */
3586 ENGINE_ISSUE_PREFIX_HOOK();
3588 /* NOTE: For multi-context simulation environments the "instruction"
3589 variable should be local to this routine. */
3591 /* Shorthand accesses for engine. Note: If we wanted to use global
3592 variables (and a single-threaded simulator engine), then we can
3593 create the actual variables with these names. */
3595 if (!(STATE
& simSKIPNEXT
)) {
3596 /* Include the simulator engine */
3597 #include "oengine.c"
3598 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3599 #error "Mismatch between run-time simulator code and simulation engine"
3601 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3602 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3604 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3605 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3608 #if defined(WARN_LOHI)
3609 /* Decrement the HI/LO validity ticks */
3614 /* start-sanitize-r5900 */
3619 /* end-sanitize-r5900 */
3620 #endif /* WARN_LOHI */
3622 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3623 should check for it being changed. It is better doing it here,
3624 than within the simulator, since it will help keep the simulator
3627 #if defined(WARN_ZERO)
3628 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3629 #endif /* WARN_ZERO */
3630 ZERO
= 0; /* reset back to zero before next instruction */
3632 } else /* simSKIPNEXT check */
3633 STATE
&= ~simSKIPNEXT
;
3635 /* If the delay slot was active before the instruction is
3636 executed, then update the PC to its new value: */
3639 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3648 #if !defined(FASTSIM)
3649 if (sim_events_tickn (sd
, pipeline_count
))
3651 /* cpu->cia = cia; */
3652 sim_events_process (sd
);
3655 if (sim_events_tick (sd
))
3657 /* cpu->cia = cia; */
3658 sim_events_process (sd
);
3660 #endif /* FASTSIM */
3666 /* This code copied from gdb's utils.c. Would like to share this code,
3667 but don't know of a common place where both could get to it. */
3669 /* Temporary storage using circular buffer */
3675 static char buf
[NUMCELLS
][CELLSIZE
];
3677 if (++cell
>=NUMCELLS
) cell
=0;
3681 /* Print routines to handle variable size regs, etc */
3683 /* Eliminate warning from compiler on 32-bit systems */
3684 static int thirty_two
= 32;
3690 char *paddr_str
=get_cell();
3691 switch (sizeof(addr
))
3694 sprintf(paddr_str
,"%08lx%08lx",
3695 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3698 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3701 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3704 sprintf(paddr_str
,"%x",addr
);
3713 char *paddr_str
=get_cell();
3714 sprintf(paddr_str
,"%08lx%08lx",
3715 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3721 pending_tick (SIM_DESC sd
,
3726 sim_io_printf (sd
, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN
, PENDING_OUT
, PENDING_TOTAL
);
3727 if (PENDING_OUT
!= PENDING_IN
)
3730 int index
= PENDING_OUT
;
3731 int total
= PENDING_TOTAL
;
3732 if (PENDING_TOTAL
== 0)
3733 sim_engine_abort (SD
, CPU
, cia
, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3734 for (loop
= 0; (loop
< total
); loop
++)
3736 if (PENDING_SLOT_DEST
[index
] != NULL
)
3738 PENDING_SLOT_DELAY
[index
] -= 1;
3739 if (PENDING_SLOT_DELAY
[index
] == 0)
3741 if (PENDING_SLOT_BIT
[index
] >= 0)
3742 switch (PENDING_SLOT_SIZE
[index
])
3745 if (PENDING_SLOT_VALUE
[index
])
3746 *(unsigned32
*)PENDING_SLOT_DEST
[index
] |=
3747 BIT32 (PENDING_SLOT_BIT
[index
]);
3749 *(unsigned32
*)PENDING_SLOT_DEST
[index
] &=
3750 BIT32 (PENDING_SLOT_BIT
[index
]);
3753 if (PENDING_SLOT_VALUE
[index
])
3754 *(unsigned64
*)PENDING_SLOT_DEST
[index
] |=
3755 BIT64 (PENDING_SLOT_BIT
[index
]);
3757 *(unsigned64
*)PENDING_SLOT_DEST
[index
] &=
3758 BIT64 (PENDING_SLOT_BIT
[index
]);
3763 switch (PENDING_SLOT_SIZE
[index
])
3766 *(unsigned32
*)PENDING_SLOT_DEST
[index
] =
3767 PENDING_SLOT_VALUE
[index
];
3770 *(unsigned64
*)PENDING_SLOT_DEST
[index
] =
3771 PENDING_SLOT_VALUE
[index
];
3775 if (PENDING_OUT
== index
)
3777 PENDING_SLOT_DEST
[index
] = NULL
;
3778 PENDING_OUT
= (PENDING_OUT
+ 1) % PSLOTS
;
3783 index
= (index
+ 1) % PSLOTS
;
3787 /*---------------------------------------------------------------------------*/
3788 /*> EOF interp.c <*/