2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
46 /* start-sanitize-sky */
50 #include "sky-libvpe.h"
55 /* end-sanitize-sky */
77 #include "libiberty.h"
79 #include "callback.h" /* GDB simulator callback interface */
80 #include "remote-sim.h" /* GDB simulator interface */
88 char* pr_addr
PARAMS ((SIM_ADDR addr
));
89 char* pr_uword64
PARAMS ((uword64 addr
));
92 /* Get the simulator engine description, without including the code: */
99 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
104 /* The following reserved instruction value is used when a simulator
105 trap is required. NOTE: Care must be taken, since this value may be
106 used in later revisions of the MIPS ISA. */
108 #define RSVD_INSTRUCTION (0x00000005)
109 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
111 #define RSVD_INSTRUCTION_ARG_SHIFT 6
112 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
115 /* Bits in the Debug register */
116 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
117 #define Debug_DM 0x40000000 /* Debug Mode */
118 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
120 /*---------------------------------------------------------------------------*/
121 /*-- GDB simulator interface ------------------------------------------------*/
122 /*---------------------------------------------------------------------------*/
124 static void ColdReset
PARAMS((SIM_DESC sd
));
126 /*---------------------------------------------------------------------------*/
130 #define DELAYSLOT() {\
131 if (STATE & simDELAYSLOT)\
132 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
133 STATE |= simDELAYSLOT;\
136 #define JALDELAYSLOT() {\
138 STATE |= simJALDELAYSLOT;\
142 STATE &= ~simDELAYSLOT;\
143 STATE |= simSKIPNEXT;\
146 #define CANCELDELAYSLOT() {\
148 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
151 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
152 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
154 #define K0BASE (0x80000000)
155 #define K0SIZE (0x20000000)
156 #define K1BASE (0xA0000000)
157 #define K1SIZE (0x20000000)
158 #define MONITOR_BASE (0xBFC00000)
159 #define MONITOR_SIZE (1 << 11)
160 #define MEM_SIZE (2 << 20)
162 /* start-sanitize-sky */
165 #define MEM_SIZE (16 << 20) /* 16 MB */
167 #define MONITOR_SIZE 0x100000 /* 1MB */
169 /* end-sanitize-sky */
172 static char *tracefile
= "trace.din"; /* default filename for trace log */
173 FILE *tracefh
= NULL
;
174 static void open_trace
PARAMS((SIM_DESC sd
));
178 static const char * get_insn_name (sim_cpu
*, int);
181 /* simulation target board. NULL=canonical */
182 static char* board
= NULL
;
185 static DECLARE_OPTION_HANDLER (mips_option_handler
);
188 OPTION_DINERO_TRACE
= OPTION_START
,
190 /* start-stanitize-branchbug4011 */
191 OPTION_BRANCH_BUG_4011
,
192 /* end-stanitize-branchbug4011 */
198 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
208 /* start-sanitize-branchbug4011 */
209 case OPTION_BRANCH_BUG_4011
:
211 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
213 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
215 BRANCHBUG4011_OPTION
= 1;
216 else if (strcmp (arg
, "yes") == 0)
217 BRANCHBUG4011_OPTION
= 1;
218 else if (strcmp (arg
, "no") == 0)
219 BRANCHBUG4011_OPTION
= 0;
220 else if (strcmp (arg
, "on") == 0)
221 BRANCHBUG4011_OPTION
= 1;
222 else if (strcmp (arg
, "off") == 0)
223 BRANCHBUG4011_OPTION
= 0;
226 fprintf (stderr
, "Unrecognized check-4011-branch-bug option `%s'\n", arg
);
233 /* end-sanitize-branchbug4011 */
234 case OPTION_DINERO_TRACE
: /* ??? */
236 /* Eventually the simTRACE flag could be treated as a toggle, to
237 allow external control of the program points being traced
238 (i.e. only from main onwards, excluding the run-time setup,
240 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
242 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
245 else if (strcmp (arg
, "yes") == 0)
247 else if (strcmp (arg
, "no") == 0)
249 else if (strcmp (arg
, "on") == 0)
251 else if (strcmp (arg
, "off") == 0)
255 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
262 Simulator constructed without dinero tracing support (for performance).\n\
263 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
267 case OPTION_DINERO_FILE
:
269 if (optarg
!= NULL
) {
271 tmp
= (char *)malloc(strlen(optarg
) + 1);
274 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
280 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
290 board
= zalloc(strlen(arg
) + 1);
301 static const OPTION mips_options
[] =
303 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
304 '\0', "on|off", "Enable dinero tracing",
305 mips_option_handler
},
306 /* start-sanitize-branchbug4011 */
307 { {"check-4011-branch-bug", optional_argument
, NULL
, OPTION_BRANCH_BUG_4011
},
308 '\0', "on|off", "Enable checking for 4011 branch bug",
309 mips_option_handler
},
310 /* end-sanitize-branchbug4011 */
311 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
312 '\0', "FILE", "Write dinero trace to FILE",
313 mips_option_handler
},
314 { {"board", required_argument
, NULL
, OPTION_BOARD
},
315 '\0', "none" /* rely on compile-time string concatenation for other options */
317 /* start-sanitize-tx3904 */
318 #define BOARD_JMR3904 "jmr3904"
320 #define BOARD_JMR3904_PAL "jmr3904pal"
321 "|" BOARD_JMR3904_PAL
322 #define BOARD_JMR3904_DEBUG "jmr3904debug"
323 "|" BOARD_JMR3904_DEBUG
324 /* end-sanitize-tx3904 */
326 , "Customize simulation for a particular board.", mips_option_handler
},
328 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
332 int interrupt_pending
;
335 interrupt_event (SIM_DESC sd
, void *data
)
337 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
338 address_word cia
= CIA_GET (cpu
);
341 interrupt_pending
= 0;
342 SignalExceptionInterrupt (1); /* interrupt "1" */
344 else if (!interrupt_pending
)
345 sim_events_schedule (sd
, 1, interrupt_event
, data
);
349 /*---------------------------------------------------------------------------*/
350 /*-- Device registration hook -----------------------------------------------*/
351 /*---------------------------------------------------------------------------*/
352 static void device_init(SIM_DESC sd
) {
354 extern void register_devices(SIM_DESC
);
355 register_devices(sd
);
359 /*---------------------------------------------------------------------------*/
360 /*-- GDB simulator interface ------------------------------------------------*/
361 /*---------------------------------------------------------------------------*/
364 sim_open (kind
, cb
, abfd
, argv
)
370 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
371 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
373 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
375 /* FIXME: watchpoints code shouldn't need this */
376 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
377 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
378 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
381 /* Initialize the mechanism for doing insn profiling. */
382 CPU_INSN_NAME (cpu
) = get_insn_name
;
383 CPU_MAX_INSNS (cpu
) = nr_itable_entries
;
388 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
390 sim_add_option_table (sd
, NULL
, mips_options
);
392 /* start-sanitize-sky */
394 sky_command_options_open (sd
);
396 /* end-sanitize-sky */
398 /* getopt will print the error message so we just have to exit if this fails.
399 FIXME: Hmmm... in the case of gdb we need getopt to call
401 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
403 /* Uninstall the modules to avoid memory leaks,
404 file descriptor leaks, etc. */
405 sim_module_uninstall (sd
);
409 /* handle board-specific memory maps */
412 /* Allocate core managed memory */
414 /* start-sanitize-sky */
416 /* end-sanitize-sky */
418 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
419 /* For compatibility with the old code - under this (at level one)
420 are the kernel spaces K0 & K1. Both of these map to a single
421 smaller sub region */
422 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
423 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
425 MEM_SIZE
, /* actual size */
427 /* start-sanitize-sky */
430 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
- K1BASE
, MONITOR_SIZE
);
431 sim_do_command (sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
432 /* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
433 address_translation() */
434 sim_do_commandf (sd
, "memory size 0x%lx", MEM_SIZE
);
436 /* end-sanitize-sky */
441 /* start-sanitize-tx3904 */
444 && (strcmp(board
, BOARD_JMR3904
) == 0 ||
445 strcmp(board
, BOARD_JMR3904_PAL
) == 0 ||
446 strcmp(board
, BOARD_JMR3904_DEBUG
) == 0))
448 /* match VIRTUAL memory layout of JMR-TX3904 board */
450 /* --- environment --- */
452 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
456 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
457 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
459 4 * 1024 * 1024, /* 4 MB */
462 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
463 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
465 4 * 1024 * 1024, /* 4 MB */
468 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
469 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
471 32 * 1024 * 1024, /* 32 MB */
474 /* Dummy memory regions for unsimulated devices */
476 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFE010, 0x00c); /* EBIF */
477 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
478 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
480 /* --- simulated devices --- */
481 sim_hw_parse (sd
, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
482 sim_hw_parse (sd
, "/tx3904cpu");
483 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
484 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
485 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
486 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
488 /* FIXME: poking at dv-sockser internals, use tcp backend if
489 --sockser_addr option was given.*/
490 extern char* sockser_addr
;
491 if(sockser_addr
== NULL
)
492 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend stdio");
494 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend tcp");
496 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
497 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/backend stdio");
499 /* -- device connections --- */
500 sim_hw_parse (sd
, "/tx3904irc > ip level /tx3904cpu");
501 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
502 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
503 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
504 sim_hw_parse (sd
, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
505 sim_hw_parse (sd
, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
507 /* add PAL timer & I/O module */
508 if(! strcmp(board
, BOARD_JMR3904_PAL
))
511 sim_hw_parse (sd
, "/pal@0xffff0000");
512 sim_hw_parse (sd
, "/pal@0xffff0000/reg 0xffff0000 64");
514 /* wire up interrupt ports to irc */
515 sim_hw_parse (sd
, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
516 sim_hw_parse (sd
, "/pal@0x31000000 > timer tmr1 /tx3904irc");
517 sim_hw_parse (sd
, "/pal@0x31000000 > int int0 /tx3904irc");
520 if(! strcmp(board
, BOARD_JMR3904_DEBUG
))
522 /* -- DEBUG: glue interrupt generators --- */
523 sim_hw_parse (sd
, "/glue@0xffff0000/reg 0xffff0000 0x50");
524 sim_hw_parse (sd
, "/glue@0xffff0000 > int0 int0 /tx3904irc");
525 sim_hw_parse (sd
, "/glue@0xffff0000 > int1 int1 /tx3904irc");
526 sim_hw_parse (sd
, "/glue@0xffff0000 > int2 int2 /tx3904irc");
527 sim_hw_parse (sd
, "/glue@0xffff0000 > int3 int3 /tx3904irc");
528 sim_hw_parse (sd
, "/glue@0xffff0000 > int4 int4 /tx3904irc");
529 sim_hw_parse (sd
, "/glue@0xffff0000 > int5 int5 /tx3904irc");
530 sim_hw_parse (sd
, "/glue@0xffff0000 > int6 int6 /tx3904irc");
531 sim_hw_parse (sd
, "/glue@0xffff0000 > int7 int7 /tx3904irc");
532 sim_hw_parse (sd
, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
533 sim_hw_parse (sd
, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
534 sim_hw_parse (sd
, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
535 sim_hw_parse (sd
, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
536 sim_hw_parse (sd
, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
537 sim_hw_parse (sd
, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
538 sim_hw_parse (sd
, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
539 sim_hw_parse (sd
, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
540 sim_hw_parse (sd
, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
541 sim_hw_parse (sd
, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
547 /* end-sanitize-tx3904 */
550 /* check for/establish the a reference program image */
551 if (sim_analyze_program (sd
,
552 (STATE_PROG_ARGV (sd
) != NULL
553 ? *STATE_PROG_ARGV (sd
)
557 sim_module_uninstall (sd
);
561 /* Configure/verify the target byte order and other runtime
562 configuration options */
563 if (sim_config (sd
) != SIM_RC_OK
)
565 sim_module_uninstall (sd
);
569 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
571 /* Uninstall the modules to avoid memory leaks,
572 file descriptor leaks, etc. */
573 sim_module_uninstall (sd
);
577 /* verify assumptions the simulator made about the host type system.
578 This macro does not return if there is a problem */
579 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
580 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
582 /* This is NASTY, in that we are assuming the size of specific
586 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
589 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
590 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
591 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
592 else if ((rn
>= 33) && (rn
<= 37))
593 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
594 else if ((rn
== SRIDX
)
597 || ((rn
>= 72) && (rn
<= 89)))
598 cpu
->register_widths
[rn
] = 32;
600 cpu
->register_widths
[rn
] = 0;
603 /* start-sanitize-r5900 */
604 /* set the 5900 "upper" registers to 64 bits */
605 for( rn
= LAST_EMBED_REGNUM
+1; rn
< FIRST_COP0_REG
; rn
++)
606 cpu
->register_widths
[rn
] = 64;
608 for( rn
= FIRST_COP0_REG
; rn
< NUM_REGS
; rn
++)
609 cpu
->register_widths
[rn
] = 32;
610 /* end-sanitize-r5900 */
612 /* start-sanitize-sky */
614 /* Now the VU registers */
615 for( rn
= 0; rn
< NUM_VU_INTEGER_REGS
; rn
++ ) {
616 cpu
->register_widths
[rn
+ NUM_CORE_REGS
] = 16;
617 cpu
->register_widths
[rn
+ NUM_CORE_REGS
+ NUM_VU_REGS
] = 16;
620 for( rn
= NUM_VU_INTEGER_REGS
; rn
< NUM_VU_REGS
; rn
++ ) {
621 cpu
->register_widths
[rn
+ NUM_CORE_REGS
] = 32;
622 cpu
->register_widths
[rn
+ NUM_CORE_REGS
+ NUM_VU_REGS
] = 32;
625 /* Finally the VIF registers */
626 for( rn
= 2*NUM_VU_REGS
; rn
< 2*NUM_VU_REGS
+ 2*NUM_VIF_REGS
; rn
++ )
627 cpu
->register_widths
[rn
+ NUM_CORE_REGS
] = 32;
631 /* end-sanitize-sky */
635 if (STATE
& simTRACE
)
639 /* Write an abort sequence into the TRAP (common) exception vector
640 addresses. This is to catch code executing a TRAP (et.al.)
641 instruction without installing a trap handler. */
643 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
644 HALT_INSTRUCTION
/* BREAK */ };
647 sim_write (sd
, 0x80000000, (char *) halt
, sizeof (halt
));
648 sim_write (sd
, 0x80000180, (char *) halt
, sizeof (halt
));
649 sim_write (sd
, 0x80000200, (char *) halt
, sizeof (halt
));
650 sim_write (sd
, 0xBFC00200, (char *) halt
, sizeof (halt
));
651 sim_write (sd
, 0xBFC00380, (char *) halt
, sizeof (halt
));
652 sim_write (sd
, 0xBFC00400, (char *) halt
, sizeof (halt
));
656 /* Write the monitor trap address handlers into the monitor (eeprom)
657 address space. This can only be done once the target endianness
658 has been determined. */
661 /* Entry into the IDT monitor is via fixed address vectors, and
662 not using machine instructions. To avoid clashing with use of
663 the MIPS TRAP system, we place our own (simulator specific)
664 "undefined" instructions into the relevant vector slots. */
665 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
667 address_word vaddr
= (MONITOR_BASE
+ loop
);
668 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
670 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
672 /* The PMON monitor uses the same address space, but rather than
673 branching into it the address of a routine is loaded. We can
674 cheat for the moment, and direct the PMON routine to IDT style
675 instructions within the monitor space. This relies on the IDT
676 monitor not using the locations from 0xBFC00500 onwards as its
678 for (loop
= 0; (loop
< 24); loop
++)
680 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
681 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
697 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
699 case 8: /* cliexit */
702 case 11: /* flush_cache */
706 /* FIXME - should monitor_base be SIM_ADDR?? */
707 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
709 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
711 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
713 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
718 /* start-sanitize-sky */
720 /* Default TLB initialization... */
722 #define KPAGEMASK 0x001fe000
723 #define PAGE_MASK_4K 0x00000000
724 #define PAGE_MASK_16K 0x00006000
725 #define PAGE_MASK_64K 0x0001e000
726 #define PAGE_MASK_256K 0x0007e000
727 #define PAGE_MASK_1M 0x001fe000
728 #define PAGE_MASK_4M 0x007fe000
729 #define PAGE_MASK_16M 0x01ffe000
731 #define SET_TLB(index, page_mask, entry_hi, entry_lo0, entry_lo1) \
732 TLB[index].mask = page_mask; \
733 TLB[index].hi = entry_hi; \
734 TLB[index].lo0 = entry_lo0; \
735 TLB[index].lo1 = entry_lo1
737 SET_TLB(0, PAGE_MASK_16M
, 0x00000000, 0x0000001e, 0x0004001e);/*0-32M*/
739 #endif /* TARGET_SKY */
740 /* end-sanitize-sky */
750 tracefh
= fopen(tracefile
,"wb+");
753 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
760 /* Return name of an insn, used by insn profiling. */
762 get_insn_name (sim_cpu
*cpu
, int i
)
764 return itable
[i
].name
;
769 sim_close (sd
, quitting
)
774 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
777 /* start-sanitize-sky */
779 sky_command_options_close (sd
);
781 /* end-sanitize-sky */
784 /* "quitting" is non-zero if we cannot hang on errors */
786 /* Ensure that any resources allocated through the callback
787 mechanism are released: */
788 sim_io_shutdown (sd
);
791 if (tracefh
!= NULL
&& tracefh
!= stderr
)
796 /* FIXME - free SD */
803 sim_write (sd
,addr
,buffer
,size
)
806 unsigned char *buffer
;
810 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
812 /* Return the number of bytes written, or zero if error. */
814 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
817 /* We use raw read and write routines, since we do not want to count
818 the GDB memory accesses in our statistics gathering. */
820 for (index
= 0; index
< size
; index
++)
822 address_word vaddr
= (address_word
)addr
+ index
;
825 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
827 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
835 sim_read (sd
,addr
,buffer
,size
)
838 unsigned char *buffer
;
842 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
844 /* Return the number of bytes read, or zero if error. */
846 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
849 for (index
= 0; (index
< size
); index
++)
851 address_word vaddr
= (address_word
)addr
+ index
;
854 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
856 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
864 sim_store_register (sd
,rn
,memory
,length
)
867 unsigned char *memory
;
870 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
871 /* NOTE: gdb (the client) stores registers in target byte order
872 while the simulator uses host byte order */
874 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
877 /* Unfortunately this suffers from the same problem as the register
878 numbering one. We need to know what the width of each logical
879 register number is for the architecture being simulated. */
881 if (cpu
->register_widths
[rn
] == 0)
883 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
887 /* start-sanitize-r5900 */
888 if (rn
>= 90 && rn
< 90 + 32)
890 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
896 SA
= T2H_8(*(unsigned64
*)memory
);
898 case 122: /* FIXME */
899 LO1
= T2H_8(*(unsigned64
*)memory
);
901 case 123: /* FIXME */
902 HI1
= T2H_8(*(unsigned64
*)memory
);
906 if (rn
>= FIRST_COP0_REG
&& rn
< (FIRST_COP0_REG
+NUM_COP0_REGS
))
908 switch (rn
- FIRST_COP0_REG
)
910 case 12: /* Status */
912 return -1; /* Already done in regular register set */
914 EPC
= T2H_4(*((unsigned32
*) memory
));
917 C0_CONFIG
= T2H_4(*((unsigned32
*) memory
));
920 Debug
= T2H_4(*((unsigned32
*) memory
));
923 COP0_GPR
[rn
- FIRST_COP0_REG
+ 7] = T2H_4(*((unsigned32
*) memory
));
927 case 21: /* ErrorEPC */
928 COP0_GPR
[rn
- FIRST_COP0_REG
+ 9] = T2H_4(*((unsigned32
*) memory
));
931 COP0_GPR
[rn
- FIRST_COP0_REG
] = T2H_4(*((unsigned32
*) memory
));
937 /* end-sanitize-r5900 */
939 /* start-sanitize-sky */
941 if (rn
>= NUM_CORE_REGS
)
943 rn
= rn
- NUM_CORE_REGS
;
945 if( rn
< NUM_VU_REGS
)
948 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
951 if (rn
< NUM_VU_INTEGER_REGS
)
952 return write_vu_int_reg (&(vu0_device
.regs
), rn
, memory
);
953 else if (rn
>= FIRST_VEC_REG
)
956 return write_vu_vec_reg (&(vu0_device
.regs
), rn
>>2, rn
&3,
959 else switch (rn
- NUM_VU_INTEGER_REGS
)
962 return write_vu_special_reg (&vu0_device
, VU_REG_CIA
, memory
);
964 case 1: /* Can't write TPC register */
965 case 2: /* or VPU_STAT */
967 case 9: /* VU0 has no P register */
971 return write_vu_misc_reg(&(vu0_device
.regs
), VU_REG_MST
, memory
);
973 return write_vu_misc_reg(&(vu0_device
.regs
), VU_REG_MCP
, memory
);
975 return write_vu_special_reg (&vu0_device
, VU_REG_CMSAR0
, memory
);
977 return write_vu_special_reg (&vu0_device
, VU_REG_FBRST
, memory
);
979 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MR
, memory
);
981 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MI
, memory
);
983 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MQ
, memory
);
985 return write_vu_acc_reg (&(vu0_device
.regs
),
986 rn
- (NUM_VU_INTEGER_REGS
+ 12),
989 #endif /* ! TARGET_SKY_B */
992 rn
= rn
- NUM_VU_REGS
;
994 if (rn
< NUM_VU_REGS
)
996 if (rn
< NUM_VU_INTEGER_REGS
)
997 return write_vu_int_reg (&(vu1_device
.regs
), rn
, memory
);
998 else if (rn
>= FIRST_VEC_REG
)
1000 rn
-= FIRST_VEC_REG
;
1001 return write_vu_vec_reg (&(vu1_device
.regs
),
1002 rn
>> 2, rn
& 3, memory
);
1004 else switch (rn
- NUM_VU_INTEGER_REGS
)
1007 return write_vu_special_reg (&vu1_device
, VU_REG_CIA
, memory
);
1009 case 1: /* Can't write TPC register */
1010 case 2: /* or VPU_STAT */
1011 case 4: /* or MAC */
1012 case 7: /* VU1 has no FBRST register */
1016 return write_vu_misc_reg(&(vu1_device
.regs
), VU_REG_MST
, memory
);
1018 return write_vu_misc_reg(&(vu1_device
.regs
), VU_REG_MCP
, memory
);
1019 case 6: /* CMSAR1 is actually part of VU0 */
1023 return write_vu_special_reg (&vu0_device
, VU_REG_CMSAR1
, memory
);
1024 #endif /* ! TARGET_SKY_B */
1026 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MR
, memory
);
1028 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MP
, memory
);
1030 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MI
, memory
);
1032 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MQ
, memory
);
1034 return write_vu_acc_reg (&(vu1_device
.regs
),
1035 rn
- (NUM_VU_INTEGER_REGS
+ 12),
1040 rn
-= NUM_VU_REGS
; /* VIF0 registers are next */
1042 if (rn
< NUM_VIF_REGS
)
1045 sim_io_eprintf( sd
, "Invalid VIF register (register store ignored)\n" );
1048 if (rn
< NUM_VIF_REGS
-1)
1049 return write_vif_reg (&vif0_device
, rn
, memory
);
1052 sim_io_eprintf( sd
, "Can't write vif0_pc (store ignored)\n" );
1055 #endif /* ! TARGET_SKY_B */
1058 rn
-= NUM_VIF_REGS
; /* VIF1 registers are last */
1060 if (rn
< NUM_VIF_REGS
)
1062 if (rn
< NUM_VIF_REGS
-1)
1063 return write_vif_reg (&vif1_device
, rn
, memory
);
1066 sim_io_eprintf( sd
, "Can't write vif1_pc (store ignored)\n" );
1071 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
1075 /* end-sanitize-sky */
1077 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
1079 if (cpu
->register_widths
[rn
] == 32)
1081 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
1086 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
1091 if (cpu
->register_widths
[rn
] == 32)
1093 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
1098 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
1106 sim_fetch_register (sd
,rn
,memory
,length
)
1109 unsigned char *memory
;
1112 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
1113 /* NOTE: gdb (the client) stores registers in target byte order
1114 while the simulator uses host byte order */
1116 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
1119 if (cpu
->register_widths
[rn
] == 0)
1121 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
1125 /* start-sanitize-r5900 */
1126 if (rn
>= 90 && rn
< 90 + 32)
1128 *((unsigned64
*)memory
) = H2T_8 (GPR1
[rn
- 90]);
1134 *((unsigned64
*)memory
) = H2T_8(SA
);
1136 case 122: /* FIXME */
1137 *((unsigned64
*)memory
) = H2T_8(LO1
);
1139 case 123: /* FIXME */
1140 *((unsigned64
*)memory
) = H2T_8(HI1
);
1144 if (rn
>= FIRST_COP0_REG
&& rn
< (FIRST_COP0_REG
+NUM_COP0_REGS
))
1146 switch (rn
- FIRST_COP0_REG
)
1148 case 12: /* Status */
1149 case 13: /* Cause */
1150 return -1; /* Already done in regular register set */
1152 *((unsigned32
*) memory
) = H2T_4(EPC
);
1155 *((unsigned32
*) memory
) = H2T_4(C0_CONFIG
);
1157 case 17: /* Debug */
1158 *((unsigned32
*) memory
) = H2T_4(Debug
);
1161 *((unsigned32
*) memory
) = H2T_4(COP0_GPR
[rn
- FIRST_COP0_REG
+ 7]);
1163 case 19: /* TagLo */
1164 case 20: /* TagHi */
1165 case 21: /* ErrorEPC */
1166 *((unsigned32
*) memory
) = H2T_4(COP0_GPR
[rn
- FIRST_COP0_REG
+ 9]);
1169 *((unsigned32
*) memory
) = H2T_4(COP0_GPR
[rn
- FIRST_COP0_REG
]);
1175 /* end-sanitize-r5900 */
1177 /* start-sanitize-sky */
1179 if (rn
>= NUM_CORE_REGS
)
1181 rn
= rn
- NUM_CORE_REGS
;
1183 if (rn
< NUM_VU_REGS
)
1186 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
1189 if (rn
< NUM_VU_INTEGER_REGS
)
1190 return read_vu_int_reg (&(vu0_device
.regs
), rn
, memory
);
1191 else if (rn
>= FIRST_VEC_REG
)
1193 rn
-= FIRST_VEC_REG
;
1194 return read_vu_vec_reg (&(vu0_device
.regs
), rn
>>2, rn
& 3,
1197 else switch (rn
- NUM_VU_INTEGER_REGS
)
1200 return read_vu_special_reg (&vu0_device
, VU_REG_CIA
, memory
);
1202 return read_vu_misc_reg(&(vu0_device
.regs
), VU_REG_MTPC
, memory
);
1204 return read_vu_special_reg (&vu0_device
, VU_REG_STAT
, memory
);
1206 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MST
, memory
);
1208 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MMC
, memory
);
1210 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MCP
, memory
);
1212 return read_vu_special_reg (&vu0_device
, VU_REG_CMSAR0
, memory
);
1214 return read_vu_special_reg (&vu0_device
, VU_REG_FBRST
, memory
);
1216 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MR
, memory
);
1217 case 9: /* VU0 has no P register */
1218 *((int *) memory
) = 0;
1221 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MI
, memory
);
1223 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MQ
, memory
);
1225 return read_vu_acc_reg (&(vu0_device
.regs
),
1226 rn
- (NUM_VU_INTEGER_REGS
+ 12),
1229 #endif /* ! TARGET_SKY_B */
1232 rn
-= NUM_VU_REGS
; /* VU1 registers are next */
1234 if (rn
< NUM_VU_REGS
)
1236 if (rn
< NUM_VU_INTEGER_REGS
)
1237 return read_vu_int_reg (&(vu1_device
.regs
), rn
, memory
);
1238 else if (rn
>= FIRST_VEC_REG
)
1240 rn
-= FIRST_VEC_REG
;
1241 return read_vu_vec_reg (&(vu1_device
.regs
),
1242 rn
>> 2, rn
& 3, memory
);
1244 else switch (rn
- NUM_VU_INTEGER_REGS
)
1247 return read_vu_special_reg (&vu1_device
, VU_REG_CIA
, memory
);
1249 return read_vu_misc_reg(&(vu1_device
.regs
), VU_REG_MTPC
, memory
);
1251 return read_vu_special_reg (&vu1_device
, VU_REG_STAT
, memory
);
1253 return read_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MST
, memory
);
1255 return read_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MMC
, memory
);
1257 return read_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MCP
, memory
);
1258 case 6: /* CMSAR1 is actually from VU0 */
1262 return read_vu_special_reg (&vu0_device
, VU_REG_CMSAR1
, memory
);
1263 #endif /* ! TARGET_SKY_B */
1264 case 7: /* VU1 has no FBRST register */
1265 *((int *) memory
) = 0;
1268 return read_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MR
, memory
);
1270 return read_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MP
, memory
);
1272 return read_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MI
, memory
);
1274 return read_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MQ
, memory
);
1276 return read_vu_acc_reg (&(vu1_device
.regs
),
1277 rn
- (NUM_VU_INTEGER_REGS
+ 12),
1282 rn
-= NUM_VU_REGS
; /* VIF0 registers are next */
1284 if (rn
< NUM_VIF_REGS
)
1287 sim_io_eprintf( sd
, "Invalid VIF register (register fetch ignored)\n" );
1290 if (rn
< NUM_VIF_REGS
-2)
1291 return read_vif_reg (&vif0_device
, rn
, memory
);
1292 else if (rn
== NUM_VIF_REGS
-2)
1293 return read_vif_pc (&vif0_device
, memory
);
1295 return read_vif_pcx (&vif0_device
, memory
);
1296 #endif /* ! TARGET_SKY_B */
1299 rn
-= NUM_VIF_REGS
; /* VIF1 registers are last */
1301 if (rn
< NUM_VIF_REGS
)
1303 if (rn
< NUM_VIF_REGS
-2)
1304 return read_vif_reg (&vif1_device
, rn
, memory
);
1305 else if (rn
== NUM_VIF_REGS
-2)
1306 return read_vif_pc (&vif1_device
, memory
);
1308 return read_vif_pcx (&vif1_device
, memory
);
1311 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
1314 /* end-sanitize-sky */
1316 /* Any floating point register */
1317 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
1319 if (cpu
->register_widths
[rn
] == 32)
1321 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
1326 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
1331 if (cpu
->register_widths
[rn
] == 32)
1333 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
1338 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
1347 sim_create_inferior (sd
, abfd
, argv
,env
)
1355 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1363 /* override PC value set by ColdReset () */
1365 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1367 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1368 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
1372 #if 0 /* def DEBUG */
1375 /* We should really place the argv slot values into the argument
1376 registers, and onto the stack as required. However, this
1377 assumes that we have a stack defined, which is not
1378 necessarily true at the moment. */
1380 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1381 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1382 printf("DBG: arg \"%s\"\n",*cptr
);
1390 sim_do_command (sd
,cmd
)
1394 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
1395 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1399 /*---------------------------------------------------------------------------*/
1400 /*-- Private simulator support interface ------------------------------------*/
1401 /*---------------------------------------------------------------------------*/
1403 /* Read a null terminated string from memory, return in a buffer */
1405 fetch_str (sd
, addr
)
1412 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1414 buf
= NZALLOC (char, nr
+ 1);
1415 sim_read (sd
, addr
, buf
, nr
);
1419 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1421 sim_monitor (SIM_DESC sd
,
1424 unsigned int reason
)
1427 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1430 /* The IDT monitor actually allows two instructions per vector
1431 slot. However, the simulator currently causes a trap on each
1432 individual instruction. We cheat, and lose the bottom bit. */
1435 /* The following callback functions are available, however the
1436 monitor we are simulating does not make use of them: get_errno,
1437 isatty, lseek, rename, system, time and unlink */
1441 case 6: /* int open(char *path,int flags) */
1443 char *path
= fetch_str (sd
, A0
);
1444 V0
= sim_io_open (sd
, path
, (int)A1
);
1449 case 7: /* int read(int file,char *ptr,int len) */
1453 char *buf
= zalloc (nr
);
1454 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1455 sim_write (sd
, A1
, buf
, nr
);
1460 case 8: /* int write(int file,char *ptr,int len) */
1464 char *buf
= zalloc (nr
);
1465 sim_read (sd
, A1
, buf
, nr
);
1466 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1471 case 10: /* int close(int file) */
1473 V0
= sim_io_close (sd
, (int)A0
);
1477 case 2: /* Densan monitor: char inbyte(int waitflag) */
1479 if (A0
== 0) /* waitflag == NOWAIT */
1480 V0
= (unsigned_word
)-1;
1482 /* Drop through to case 11 */
1484 case 11: /* char inbyte(void) */
1487 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1489 sim_io_error(sd
,"Invalid return from character read");
1490 V0
= (unsigned_word
)-1;
1493 V0
= (unsigned_word
)tmp
;
1497 case 3: /* Densan monitor: void co(char chr) */
1498 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1500 char tmp
= (char)(A0
& 0xFF);
1501 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1505 case 17: /* void _exit() */
1507 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1508 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1509 (unsigned int)(A0
& 0xFFFFFFFF));
1513 case 28 : /* PMON flush_cache */
1516 case 55: /* void get_mem_info(unsigned int *ptr) */
1517 /* in: A0 = pointer to three word memory location */
1518 /* out: [A0 + 0] = size */
1519 /* [A0 + 4] = instruction cache size */
1520 /* [A0 + 8] = data cache size */
1522 unsigned_4 value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1523 unsigned_4 zero
= 0;
1525 sim_write (sd
, A0
+ 0, (char *)&value
, 4);
1526 sim_write (sd
, A0
+ 4, (char *)&zero
, 4);
1527 sim_write (sd
, A0
+ 8, (char *)&zero
, 4);
1528 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1532 case 158 : /* PMON printf */
1533 /* in: A0 = pointer to format string */
1534 /* A1 = optional argument 1 */
1535 /* A2 = optional argument 2 */
1536 /* A3 = optional argument 3 */
1538 /* The following is based on the PMON printf source */
1540 address_word s
= A0
;
1542 signed_word
*ap
= &A1
; /* 1st argument */
1543 /* This isn't the quickest way, since we call the host print
1544 routine for every character almost. But it does avoid
1545 having to allocate and manage a temporary string buffer. */
1546 /* TODO: Include check that we only use three arguments (A1,
1548 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1553 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1554 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1555 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1557 if (strchr ("dobxXulscefg%", c
))
1572 else if (c
>= '1' && c
<= '9')
1576 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1579 n
= (unsigned int)strtol(tmp
,NULL
,10);
1592 sim_io_printf (sd
, "%%");
1597 address_word p
= *ap
++;
1599 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1600 sim_io_printf(sd
, "%c", ch
);
1603 sim_io_printf(sd
,"(null)");
1606 sim_io_printf (sd
, "%c", (int)*ap
++);
1611 sim_read (sd
, s
++, &c
, 1);
1615 sim_read (sd
, s
++, &c
, 1);
1618 if (strchr ("dobxXu", c
))
1620 word64 lv
= (word64
) *ap
++;
1622 sim_io_printf(sd
,"<binary not supported>");
1625 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1627 sim_io_printf(sd
, tmp
, lv
);
1629 sim_io_printf(sd
, tmp
, (int)lv
);
1632 else if (strchr ("eEfgG", c
))
1634 double dbl
= *(double*)(ap
++);
1635 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1636 sim_io_printf (sd
, tmp
, dbl
);
1642 sim_io_printf(sd
, "%c", c
);
1648 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1649 reason
, pr_addr(cia
));
1655 /* Store a word into memory. */
1658 store_word (SIM_DESC sd
,
1667 if ((vaddr
& 3) != 0)
1668 SignalExceptionAddressStore ();
1671 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1674 const uword64 mask
= 7;
1678 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1679 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1680 memval
= ((uword64
) val
) << (8 * byte
);
1681 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1687 /* Load a word from memory. */
1690 load_word (SIM_DESC sd
,
1695 if ((vaddr
& 3) != 0)
1696 SignalExceptionAddressLoad ();
1702 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1705 const uword64 mask
= 0x7;
1706 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1707 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1711 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1712 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1714 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1715 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1722 /* Simulate the mips16 entry and exit pseudo-instructions. These
1723 would normally be handled by the reserved instruction exception
1724 code, but for ease of simulation we just handle them directly. */
1727 mips16_entry (SIM_DESC sd
,
1732 int aregs
, sregs
, rreg
;
1735 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1738 aregs
= (insn
& 0x700) >> 8;
1739 sregs
= (insn
& 0x0c0) >> 6;
1740 rreg
= (insn
& 0x020) >> 5;
1742 /* This should be checked by the caller. */
1751 /* This is the entry pseudo-instruction. */
1753 for (i
= 0; i
< aregs
; i
++)
1754 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1762 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1765 for (i
= 0; i
< sregs
; i
++)
1768 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1776 /* This is the exit pseudo-instruction. */
1783 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1786 for (i
= 0; i
< sregs
; i
++)
1789 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1794 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1798 FGR
[0] = WORD64LO (GPR
[4]);
1799 FPR_STATE
[0] = fmt_uninterpreted
;
1801 else if (aregs
== 6)
1803 FGR
[0] = WORD64LO (GPR
[5]);
1804 FGR
[1] = WORD64LO (GPR
[4]);
1805 FPR_STATE
[0] = fmt_uninterpreted
;
1806 FPR_STATE
[1] = fmt_uninterpreted
;
1815 /*-- trace support ----------------------------------------------------------*/
1817 /* The TRACE support is provided (if required) in the memory accessing
1818 routines. Since we are also providing the architecture specific
1819 features, the architecture simulation code can also deal with
1820 notifying the TRACE world of cache flushes, etc. Similarly we do
1821 not need to provide profiling support in the simulator engine,
1822 since we can sample in the instruction fetch control loop. By
1823 defining the TRACE manifest, we add tracing as a run-time
1827 /* Tracing by default produces "din" format (as required by
1828 dineroIII). Each line of such a trace file *MUST* have a din label
1829 and address field. The rest of the line is ignored, so comments can
1830 be included if desired. The first field is the label which must be
1831 one of the following values:
1836 3 escape record (treated as unknown access type)
1837 4 escape record (causes cache flush)
1839 The address field is a 32bit (lower-case) hexadecimal address
1840 value. The address should *NOT* be preceded by "0x".
1842 The size of the memory transfer is not important when dealing with
1843 cache lines (as long as no more than a cache line can be
1844 transferred in a single operation :-), however more information
1845 could be given following the dineroIII requirement to allow more
1846 complete memory and cache simulators to provide better
1847 results. i.e. the University of Pisa has a cache simulator that can
1848 also take bus size and speed as (variable) inputs to calculate
1849 complete system performance (a much more useful ability when trying
1850 to construct an end product, rather than a processor). They
1851 currently have an ARM version of their tool called ChARM. */
1855 dotrace (SIM_DESC sd
,
1863 if (STATE
& simTRACE
) {
1865 fprintf(tracefh
,"%d %s ; width %d ; ",
1869 va_start(ap
,comment
);
1870 vfprintf(tracefh
,comment
,ap
);
1872 fprintf(tracefh
,"\n");
1874 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1875 we may be generating 64bit ones, we should put the hi-32bits of the
1876 address into the comment field. */
1878 /* TODO: Provide a buffer for the trace lines. We can then avoid
1879 performing writes until the buffer is filled, or the file is
1882 /* NOTE: We could consider adding a comment field to the "din" file
1883 produced using type 3 markers (unknown access). This would then
1884 allow information about the program that the "din" is for, and
1885 the MIPs world that was being simulated, to be placed into the
1892 /*---------------------------------------------------------------------------*/
1893 /*-- simulator engine -------------------------------------------------------*/
1894 /*---------------------------------------------------------------------------*/
1897 ColdReset (SIM_DESC sd
)
1900 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1902 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1903 /* RESET: Fixed PC address: */
1904 PC
= (unsigned_word
) UNSIGNED64 (0xFFFFFFFFBFC00000);
1905 /* The reset vector address is in the unmapped, uncached memory space. */
1907 SR
&= ~(status_SR
| status_TS
| status_RP
);
1908 SR
|= (status_ERL
| status_BEV
);
1910 /* Cheat and allow access to the complete register set immediately */
1911 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1912 && WITH_TARGET_WORD_BITSIZE
== 64)
1913 SR
|= status_FR
; /* 64bit registers */
1915 /* Ensure that any instructions with pending register updates are
1917 PENDING_INVALIDATE();
1919 /* Initialise the FPU registers to the unknown state */
1920 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1923 for (rn
= 0; (rn
< 32); rn
++)
1924 FPR_STATE
[rn
] = fmt_uninterpreted
;
1932 /* start-sanitize-sky */
1935 /* See ch. 5 of the 5900 Users' Guide. */
1937 signal_exception (SIM_DESC sd
,
1945 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",cause
,pr_addr(cia
));
1948 /* Ensure that any active atomic read/modify/write operation will fail: */
1951 /* First, handle any simulator specific magic exceptions. These are not "real" exceptions, but
1952 are exceptions which the simulator uses to implement different features. */
1956 case SimulatorFault
:
1961 msg
= va_arg(ap
,char *);
1963 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1964 "FATAL: Simulator error \"%s\"\n",msg
);
1967 case DebugBreakPoint
:
1968 if (! (Debug
& Debug_DM
))
1974 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1975 DEPC
= cia
- 4; /* reference the branch instruction */
1979 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1983 Debug
|= Debug_DM
; /* in debugging mode */
1984 Debug
|= Debug_DBp
; /* raising a DBp exception */
1986 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1990 case ReservedInstruction
:
1993 unsigned int instruction
;
1995 instruction
= va_arg(ap
,unsigned int);
1997 /* Provide simple monitor support using ReservedInstruction
1998 exceptions. The following code simulates the fixed vector
1999 entry points into the IDT monitor by causing a simulator
2000 trap, performing the monitor operation, and returning to
2001 the address held in the $ra register (standard PCS return
2002 address). This means we only need to pre-load the vector
2003 space with suitable instruction values. For systems were
2004 actual trap instructions are used, we would not need to
2005 perform this magic. */
2006 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
2008 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
2009 /* NOTE: This assumes that a branch-and-link style
2010 instruction was used to enter the vector (which is the
2011 case with the current IDT monitor). */
2012 sim_engine_restart (SD
, CPU
, NULL
, RA
);
2014 /* Look for the mips16 entry and exit instructions, and
2015 simulate a handler for them. */
2016 else if ((cia
& 1) != 0
2017 && (instruction
& 0xf81f) == 0xe809
2018 && (instruction
& 0x0c0) != 0x0c0)
2020 mips16_entry (SD
, CPU
, cia
, instruction
);
2021 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
2023 /* else fall through to normal exception processing */
2024 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
2028 /* Now we have the code for processing "real" exceptions. */
2030 if (is5900Level2Exception(cause
)) {
2036 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2037 "FATAL: Unexpected level 2 exception %d\n", cause
);
2039 if (STATE
& simDELAYSLOT
)
2041 STATE
&= ~simDELAYSLOT
;
2042 COP0_ERROREPC
= (cia
- 4); /* reference the branch instruction */
2047 COP0_ERROREPC
= cia
;
2048 CAUSE
&= ~cause_BD2
;
2053 if (cause
== NMIReset
)
2057 ASSERT(0); /* At the moment, COUNTER, DEBUG never generated. */
2059 sim_engine_restart (SD
, CPU
, NULL
, PC
);
2061 /* A level 1 exception. */
2062 int refill
, vector_offset
;
2064 cause_set_EXC(cause
);
2065 if (SR
& status_EXL
)
2066 vector_offset
= 0x180;
2069 if (cause
== TLBLoad
|| cause
== TLBStore
) {
2071 va_start(ap
, cause
);
2072 refill
= va_arg(ap
,int);
2076 if (STATE
& simDELAYSLOT
)
2078 STATE
&= ~simDELAYSLOT
;
2080 COP0_EPC
= (cia
- 4); /* reference the branch instruction */
2090 if ((cause
== TLBLoad
|| cause
== TLBStore
) && refill
== TLB_REFILL
)
2091 vector_offset
= 0x000;
2092 else if (cause
== Interrupt
)
2093 vector_offset
= 0x200;
2095 vector_offset
= 0x180;
2097 if (SR
& status_BEV
)
2098 PC
= (signed)0xBFC00200 + vector_offset
;
2100 PC
= (signed)0x80000000 + vector_offset
;
2103 /* Now, handle the exception. */
2110 va_start(ap
, cause
);
2111 level
= va_arg(ap
,unsigned int);
2113 /* Interrupts arrive during event processing, no need to restart.
2114 Hardware interrupts on sky target are INT1 and INT2. */
2116 CAUSE
|= cause_IP3
; /* bit 11 */
2117 else if ( level
== 2 )
2118 CAUSE
|= cause_IP7
; /* bit 15 */
2120 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2121 "FATAL: Unexpected interrupt level %d\n", level
);
2126 ASSERT(0); /* NMIReset is a level 0 exception. */
2131 case InstructionFetch
:
2133 /* The following is so that the simulator will continue from the
2134 exception address on breakpoint operations. */
2136 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2137 sim_stopped
, SIM_SIGBUS
);
2140 case ReservedInstruction
:
2141 case CoProcessorUnusable
:
2143 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2144 sim_stopped
, SIM_SIGILL
);
2147 case IntegerOverflow
:
2150 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2151 sim_stopped
, SIM_SIGFPE
);
2154 case TLBModification
:
2160 sim_engine_restart (SD
, CPU
, NULL
, PC
);
2165 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2166 sim_stopped
, SIM_SIGTRAP
);
2169 default : /* Unknown internal exception */
2171 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2172 sim_stopped
, SIM_SIGABRT
);
2180 #else /* TARGET_SKY */
2181 /* end-sanitize-sky */
2183 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2184 /* Signal an exception condition. This will result in an exception
2185 that aborts the instruction. The instruction operation pseudocode
2186 will never see a return from this function call. */
2189 signal_exception (SIM_DESC sd
,
2197 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
2200 /* Ensure that any active atomic read/modify/write operation will fail: */
2203 switch (exception
) {
2205 case DebugBreakPoint
:
2206 if (! (Debug
& Debug_DM
))
2212 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
2213 DEPC
= cia
- 4; /* reference the branch instruction */
2217 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
2221 Debug
|= Debug_DM
; /* in debugging mode */
2222 Debug
|= Debug_DBp
; /* raising a DBp exception */
2224 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
2228 case ReservedInstruction
:
2231 unsigned int instruction
;
2232 va_start(ap
,exception
);
2233 instruction
= va_arg(ap
,unsigned int);
2235 /* Provide simple monitor support using ReservedInstruction
2236 exceptions. The following code simulates the fixed vector
2237 entry points into the IDT monitor by causing a simulator
2238 trap, performing the monitor operation, and returning to
2239 the address held in the $ra register (standard PCS return
2240 address). This means we only need to pre-load the vector
2241 space with suitable instruction values. For systems were
2242 actual trap instructions are used, we would not need to
2243 perform this magic. */
2244 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
2246 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
2247 /* NOTE: This assumes that a branch-and-link style
2248 instruction was used to enter the vector (which is the
2249 case with the current IDT monitor). */
2250 sim_engine_restart (SD
, CPU
, NULL
, RA
);
2252 /* Look for the mips16 entry and exit instructions, and
2253 simulate a handler for them. */
2254 else if ((cia
& 1) != 0
2255 && (instruction
& 0xf81f) == 0xe809
2256 && (instruction
& 0x0c0) != 0x0c0)
2258 mips16_entry (SD
, CPU
, cia
, instruction
);
2259 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
2261 /* else fall through to normal exception processing */
2262 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
2266 /* Store exception code into current exception id variable (used
2269 /* TODO: If not simulating exceptions then stop the simulator
2270 execution. At the moment we always stop the simulation. */
2272 #ifdef SUBTARGET_R3900
2273 /* update interrupt-related registers */
2275 /* insert exception code in bits 6:2 */
2276 CAUSE
= LSMASKED32(CAUSE
, 31, 7) | LSINSERTED32(exception
, 6, 2);
2277 /* shift IE/KU history bits left */
2278 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 3, 0), 5, 2);
2280 if (STATE
& simDELAYSLOT
)
2282 STATE
&= ~simDELAYSLOT
;
2284 EPC
= (cia
- 4); /* reference the branch instruction */
2289 if (SR
& status_BEV
)
2290 PC
= (signed)0xBFC00000 + 0x180;
2292 PC
= (signed)0x80000000 + 0x080;
2294 /* See figure 5-17 for an outline of the code below */
2295 if (! (SR
& status_EXL
))
2297 CAUSE
= (exception
<< 2);
2298 if (STATE
& simDELAYSLOT
)
2300 STATE
&= ~simDELAYSLOT
;
2302 EPC
= (cia
- 4); /* reference the branch instruction */
2306 /* FIXME: TLB et.al. */
2307 /* vector = 0x180; */
2311 CAUSE
= (exception
<< 2);
2312 /* vector = 0x180; */
2315 /* Store exception code into current exception id variable (used
2318 if (SR
& status_BEV
)
2319 PC
= (signed)0xBFC00200 + 0x180;
2321 PC
= (signed)0x80000000 + 0x180;
2324 switch ((CAUSE
>> 2) & 0x1F)
2327 /* Interrupts arrive during event processing, no need to
2333 #ifdef SUBTARGET_3900
2334 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
2335 PC
= (signed)0xBFC00000;
2336 #endif SUBTARGET_3900
2339 case TLBModification
:
2344 case InstructionFetch
:
2346 /* The following is so that the simulator will continue from the
2347 exception address on breakpoint operations. */
2349 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2350 sim_stopped
, SIM_SIGBUS
);
2352 case ReservedInstruction
:
2353 case CoProcessorUnusable
:
2355 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2356 sim_stopped
, SIM_SIGILL
);
2358 case IntegerOverflow
:
2360 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2361 sim_stopped
, SIM_SIGFPE
);
2366 sim_engine_restart (SD
, CPU
, NULL
, PC
);
2371 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2372 sim_stopped
, SIM_SIGTRAP
);
2374 default : /* Unknown internal exception */
2376 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2377 sim_stopped
, SIM_SIGABRT
);
2381 case SimulatorFault
:
2385 va_start(ap
,exception
);
2386 msg
= va_arg(ap
,char *);
2388 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2389 "FATAL: Simulator error \"%s\"\n",msg
);
2396 /* start-sanitize-sky */
2397 #endif /* ! TARGET_SKY */
2398 /* end-sanitize-sky */
2401 #if defined(WARN_RESULT)
2402 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2403 /* This function indicates that the result of the operation is
2404 undefined. However, this should not affect the instruction
2405 stream. All that is meant to happen is that the destination
2406 register is set to an undefined result. To keep the simulator
2407 simple, we just don't bother updating the destination register, so
2408 the overall result will be undefined. If desired we can stop the
2409 simulator by raising a pseudo-exception. */
2410 #define UndefinedResult() undefined_result (sd,cia)
2412 undefined_result(sd
,cia
)
2416 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
2417 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2422 #endif /* WARN_RESULT */
2424 /*-- FPU support routines ---------------------------------------------------*/
2426 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2427 formats conform to ANSI/IEEE Std 754-1985. */
2428 /* SINGLE precision floating:
2429 * seeeeeeeefffffffffffffffffffffff
2431 * e = 8bits = exponent
2432 * f = 23bits = fraction
2434 /* SINGLE precision fixed:
2435 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2437 * i = 31bits = integer
2439 /* DOUBLE precision floating:
2440 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2442 * e = 11bits = exponent
2443 * f = 52bits = fraction
2445 /* DOUBLE precision fixed:
2446 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2448 * i = 63bits = integer
2451 /* Extract sign-bit: */
2452 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2453 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2454 /* Extract biased exponent: */
2455 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2456 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2457 /* Extract unbiased Exponent: */
2458 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2459 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2460 /* Extract complete fraction field: */
2461 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2462 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2463 /* Extract numbered fraction bit: */
2464 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2465 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2467 /* Explicit QNaN values used when value required: */
2468 #define FPQNaN_SINGLE (0x7FBFFFFF)
2469 #define FPQNaN_WORD (0x7FFFFFFF)
2470 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2471 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2473 /* Explicit Infinity values used when required: */
2474 #define FPINF_SINGLE (0x7F800000)
2475 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2477 #if 1 /* def DEBUG */
2478 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2479 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2483 value_fpr (SIM_DESC sd
,
2492 /* Treat unused register values, as fixed-point 64bit values: */
2493 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2495 /* If request to read data as "uninterpreted", then use the current
2497 fmt
= FPR_STATE
[fpr
];
2502 /* For values not yet accessed, set to the desired format: */
2503 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2504 FPR_STATE
[fpr
] = fmt
;
2506 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2509 if (fmt
!= FPR_STATE
[fpr
]) {
2510 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2511 FPR_STATE
[fpr
] = fmt_unknown
;
2514 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2515 /* Set QNaN value: */
2518 value
= FPQNaN_SINGLE
;
2522 value
= FPQNaN_DOUBLE
;
2526 value
= FPQNaN_WORD
;
2530 value
= FPQNaN_LONG
;
2537 } else if (SizeFGR() == 64) {
2541 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2544 case fmt_uninterpreted
:
2558 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2561 case fmt_uninterpreted
:
2564 if ((fpr
& 1) == 0) { /* even registers only */
2565 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2567 SignalException(ReservedInstruction
,0);
2578 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2581 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2588 store_fpr (SIM_DESC sd
,
2598 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2601 if (SizeFGR() == 64) {
2603 case fmt_uninterpreted_32
:
2604 fmt
= fmt_uninterpreted
;
2607 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2608 FPR_STATE
[fpr
] = fmt
;
2611 case fmt_uninterpreted_64
:
2612 fmt
= fmt_uninterpreted
;
2613 case fmt_uninterpreted
:
2617 FPR_STATE
[fpr
] = fmt
;
2621 FPR_STATE
[fpr
] = fmt_unknown
;
2627 case fmt_uninterpreted_32
:
2628 fmt
= fmt_uninterpreted
;
2631 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2632 FPR_STATE
[fpr
] = fmt
;
2635 case fmt_uninterpreted_64
:
2636 fmt
= fmt_uninterpreted
;
2637 case fmt_uninterpreted
:
2640 if ((fpr
& 1) == 0) { /* even register number only */
2641 FGR
[fpr
+1] = (value
>> 32);
2642 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2643 FPR_STATE
[fpr
+ 1] = fmt
;
2644 FPR_STATE
[fpr
] = fmt
;
2646 FPR_STATE
[fpr
] = fmt_unknown
;
2647 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2648 SignalException(ReservedInstruction
,0);
2653 FPR_STATE
[fpr
] = fmt_unknown
;
2658 #if defined(WARN_RESULT)
2661 #endif /* WARN_RESULT */
2664 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2667 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2684 sim_fpu_32to (&wop
, op
);
2685 boolean
= sim_fpu_is_nan (&wop
);
2692 sim_fpu_64to (&wop
, op
);
2693 boolean
= sim_fpu_is_nan (&wop
);
2697 fprintf (stderr
, "Bad switch\n");
2702 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2716 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2723 sim_fpu_32to (&wop
, op
);
2724 boolean
= sim_fpu_is_infinity (&wop
);
2730 sim_fpu_64to (&wop
, op
);
2731 boolean
= sim_fpu_is_infinity (&wop
);
2735 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2740 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2754 /* Argument checking already performed by the FPCOMPARE code */
2757 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2760 /* The format type should already have been checked: */
2766 sim_fpu_32to (&wop1
, op1
);
2767 sim_fpu_32to (&wop2
, op2
);
2768 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2775 sim_fpu_64to (&wop1
, op1
);
2776 sim_fpu_64to (&wop2
, op2
);
2777 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2781 fprintf (stderr
, "Bad switch\n");
2786 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2800 /* Argument checking already performed by the FPCOMPARE code */
2803 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2806 /* The format type should already have been checked: */
2812 sim_fpu_32to (&wop1
, op1
);
2813 sim_fpu_32to (&wop2
, op2
);
2814 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2821 sim_fpu_64to (&wop1
, op1
);
2822 sim_fpu_64to (&wop2
, op2
);
2823 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2827 fprintf (stderr
, "Bad switch\n");
2832 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2839 AbsoluteValue(op
,fmt
)
2846 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2849 /* The format type should already have been checked: */
2855 sim_fpu_32to (&wop
, op
);
2856 sim_fpu_abs (&wop
, &wop
);
2857 sim_fpu_to32 (&ans
, &wop
);
2865 sim_fpu_64to (&wop
, op
);
2866 sim_fpu_abs (&wop
, &wop
);
2867 sim_fpu_to64 (&ans
, &wop
);
2872 fprintf (stderr
, "Bad switch\n");
2887 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2890 /* The format type should already have been checked: */
2896 sim_fpu_32to (&wop
, op
);
2897 sim_fpu_neg (&wop
, &wop
);
2898 sim_fpu_to32 (&ans
, &wop
);
2906 sim_fpu_64to (&wop
, op
);
2907 sim_fpu_neg (&wop
, &wop
);
2908 sim_fpu_to64 (&ans
, &wop
);
2913 fprintf (stderr
, "Bad switch\n");
2929 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2932 /* The registers must specify FPRs valid for operands of type
2933 "fmt". If they are not valid, the result is undefined. */
2935 /* The format type should already have been checked: */
2943 sim_fpu_32to (&wop1
, op1
);
2944 sim_fpu_32to (&wop2
, op2
);
2945 sim_fpu_add (&ans
, &wop1
, &wop2
);
2946 sim_fpu_to32 (&res
, &ans
);
2956 sim_fpu_64to (&wop1
, op1
);
2957 sim_fpu_64to (&wop2
, op2
);
2958 sim_fpu_add (&ans
, &wop1
, &wop2
);
2959 sim_fpu_to64 (&res
, &ans
);
2964 fprintf (stderr
, "Bad switch\n");
2969 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2984 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2987 /* The registers must specify FPRs valid for operands of type
2988 "fmt". If they are not valid, the result is undefined. */
2990 /* The format type should already have been checked: */
2998 sim_fpu_32to (&wop1
, op1
);
2999 sim_fpu_32to (&wop2
, op2
);
3000 sim_fpu_sub (&ans
, &wop1
, &wop2
);
3001 sim_fpu_to32 (&res
, &ans
);
3011 sim_fpu_64to (&wop1
, op1
);
3012 sim_fpu_64to (&wop2
, op2
);
3013 sim_fpu_sub (&ans
, &wop1
, &wop2
);
3014 sim_fpu_to64 (&res
, &ans
);
3019 fprintf (stderr
, "Bad switch\n");
3024 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3031 Multiply(op1
,op2
,fmt
)
3039 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3042 /* The registers must specify FPRs valid for operands of type
3043 "fmt". If they are not valid, the result is undefined. */
3045 /* The format type should already have been checked: */
3053 sim_fpu_32to (&wop1
, op1
);
3054 sim_fpu_32to (&wop2
, op2
);
3055 sim_fpu_mul (&ans
, &wop1
, &wop2
);
3056 sim_fpu_to32 (&res
, &ans
);
3066 sim_fpu_64to (&wop1
, op1
);
3067 sim_fpu_64to (&wop2
, op2
);
3068 sim_fpu_mul (&ans
, &wop1
, &wop2
);
3069 sim_fpu_to64 (&res
, &ans
);
3074 fprintf (stderr
, "Bad switch\n");
3079 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3094 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3097 /* The registers must specify FPRs valid for operands of type
3098 "fmt". If they are not valid, the result is undefined. */
3100 /* The format type should already have been checked: */
3108 sim_fpu_32to (&wop1
, op1
);
3109 sim_fpu_32to (&wop2
, op2
);
3110 sim_fpu_div (&ans
, &wop1
, &wop2
);
3111 sim_fpu_to32 (&res
, &ans
);
3121 sim_fpu_64to (&wop1
, op1
);
3122 sim_fpu_64to (&wop2
, op2
);
3123 sim_fpu_div (&ans
, &wop1
, &wop2
);
3124 sim_fpu_to64 (&res
, &ans
);
3129 fprintf (stderr
, "Bad switch\n");
3134 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3148 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3151 /* The registers must specify FPRs valid for operands of type
3152 "fmt". If they are not valid, the result is undefined. */
3154 /* The format type should already have been checked: */
3161 sim_fpu_32to (&wop
, op
);
3162 sim_fpu_inv (&ans
, &wop
);
3163 sim_fpu_to32 (&res
, &ans
);
3172 sim_fpu_64to (&wop
, op
);
3173 sim_fpu_inv (&ans
, &wop
);
3174 sim_fpu_to64 (&res
, &ans
);
3179 fprintf (stderr
, "Bad switch\n");
3184 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3198 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3201 /* The registers must specify FPRs valid for operands of type
3202 "fmt". If they are not valid, the result is undefined. */
3204 /* The format type should already have been checked: */
3211 sim_fpu_32to (&wop
, op
);
3212 sim_fpu_sqrt (&ans
, &wop
);
3213 sim_fpu_to32 (&res
, &ans
);
3222 sim_fpu_64to (&wop
, op
);
3223 sim_fpu_sqrt (&ans
, &wop
);
3224 sim_fpu_to64 (&res
, &ans
);
3229 fprintf (stderr
, "Bad switch\n");
3234 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3250 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3253 /* The registers must specify FPRs valid for operands of type
3254 "fmt". If they are not valid, the result is undefined. */
3256 /* The format type should already have been checked: */
3263 sim_fpu_32to (&wop1
, op1
);
3264 sim_fpu_32to (&wop2
, op2
);
3265 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3272 sim_fpu_64to (&wop1
, op1
);
3273 sim_fpu_64to (&wop2
, op2
);
3274 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3278 fprintf (stderr
, "Bad switch\n");
3284 case SIM_FPU_IS_SNAN
:
3285 case SIM_FPU_IS_QNAN
:
3287 case SIM_FPU_IS_NINF
:
3288 case SIM_FPU_IS_NNUMBER
:
3289 case SIM_FPU_IS_NDENORM
:
3290 case SIM_FPU_IS_NZERO
:
3291 result
= op2
; /* op1 - op2 < 0 */
3292 case SIM_FPU_IS_PINF
:
3293 case SIM_FPU_IS_PNUMBER
:
3294 case SIM_FPU_IS_PDENORM
:
3295 case SIM_FPU_IS_PZERO
:
3296 result
= op1
; /* op1 - op2 > 0 */
3298 fprintf (stderr
, "Bad switch\n");
3303 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3320 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3323 /* The registers must specify FPRs valid for operands of type
3324 "fmt". If they are not valid, the result is undefined. */
3326 /* The format type should already have been checked: */
3333 sim_fpu_32to (&wop1
, op1
);
3334 sim_fpu_32to (&wop2
, op2
);
3335 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3342 sim_fpu_64to (&wop1
, op1
);
3343 sim_fpu_64to (&wop2
, op2
);
3344 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3348 fprintf (stderr
, "Bad switch\n");
3354 case SIM_FPU_IS_SNAN
:
3355 case SIM_FPU_IS_QNAN
:
3357 case SIM_FPU_IS_NINF
:
3358 case SIM_FPU_IS_NNUMBER
:
3359 case SIM_FPU_IS_NDENORM
:
3360 case SIM_FPU_IS_NZERO
:
3361 result
= op1
; /* op1 - op2 < 0 */
3362 case SIM_FPU_IS_PINF
:
3363 case SIM_FPU_IS_PNUMBER
:
3364 case SIM_FPU_IS_PDENORM
:
3365 case SIM_FPU_IS_PZERO
:
3366 result
= op2
; /* op1 - op2 > 0 */
3368 fprintf (stderr
, "Bad switch\n");
3373 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3381 convert (SIM_DESC sd
,
3390 sim_fpu_round round
;
3391 unsigned32 result32
;
3392 unsigned64 result64
;
3395 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3401 /* Round result to nearest representable value. When two
3402 representable values are equally near, round to the value
3403 that has a least significant bit of zero (i.e. is even). */
3404 round
= sim_fpu_round_near
;
3407 /* Round result to the value closest to, and not greater in
3408 magnitude than, the result. */
3409 round
= sim_fpu_round_zero
;
3412 /* Round result to the value closest to, and not less than,
3414 round
= sim_fpu_round_up
;
3418 /* Round result to the value closest to, and not greater than,
3420 round
= sim_fpu_round_down
;
3424 fprintf (stderr
, "Bad switch\n");
3428 /* Convert the input to sim_fpu internal format */
3432 sim_fpu_64to (&wop
, op
);
3435 sim_fpu_32to (&wop
, op
);
3438 sim_fpu_i32to (&wop
, op
, round
);
3441 sim_fpu_i64to (&wop
, op
, round
);
3444 fprintf (stderr
, "Bad switch\n");
3448 /* Convert sim_fpu format into the output */
3449 /* The value WOP is converted to the destination format, rounding
3450 using mode RM. When the destination is a fixed-point format, then
3451 a source value of Infinity, NaN or one which would round to an
3452 integer outside the fixed point range then an IEEE Invalid
3453 Operation condition is raised. */
3457 sim_fpu_round_32 (&wop
, round
, 0);
3458 sim_fpu_to32 (&result32
, &wop
);
3459 result64
= result32
;
3462 sim_fpu_round_64 (&wop
, round
, 0);
3463 sim_fpu_to64 (&result64
, &wop
);
3466 sim_fpu_to32i (&result32
, &wop
, round
);
3467 result64
= result32
;
3470 sim_fpu_to64i (&result64
, &wop
, round
);
3474 fprintf (stderr
, "Bad switch\n");
3479 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
3486 /*-- co-processor support routines ------------------------------------------*/
3489 CoProcPresent(coproc_number
)
3490 unsigned int coproc_number
;
3492 /* Return TRUE if simulator provides a model for the given co-processor number */
3497 cop_lw (SIM_DESC sd
,
3502 unsigned int memword
)
3507 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3510 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3512 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3513 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3518 #if 0 /* this should be controlled by a configuration option */
3519 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
3528 cop_ld (SIM_DESC sd
,
3535 switch (coproc_num
) {
3537 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3539 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3544 #if 0 /* this message should be controlled by a configuration option */
3545 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
3554 /* start-sanitize-sky */
3555 #if defined(TARGET_SKY) && !defined(TARGET_SKY_B)
3557 cop_lq (SIM_DESC sd
,
3562 unsigned128 memword
)
3573 /* one word at a time, argh! */
3577 value
= H2T_4(*A4_16(& memword
, 3-i
));
3578 write_vu_vec_reg(&(vu0_device
.regs
), coproc_reg
, i
, & value
);
3584 sim_io_printf(sd
,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3585 coproc_num
,coproc_reg
,pr_addr(cia
));
3591 #endif /* TARGET_SKY */
3592 /* end-sanitize-sky */
3596 cop_sw (SIM_DESC sd
,
3602 unsigned int value
= 0;
3607 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3610 hold
= FPR_STATE
[coproc_reg
];
3611 FPR_STATE
[coproc_reg
] = fmt_word
;
3612 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3613 FPR_STATE
[coproc_reg
] = hold
;
3618 #if 0 /* should be controlled by configuration option */
3619 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3628 cop_sd (SIM_DESC sd
,
3638 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3640 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3645 #if 0 /* should be controlled by configuration option */
3646 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3655 /* start-sanitize-sky */
3656 #if defined(TARGET_SKY) && !defined(TARGET_SKY_B)
3658 cop_sq (SIM_DESC sd
,
3664 unsigned128 value
= U16_8(0, 0);
3675 /* one word at a time, argh! */
3679 read_vu_vec_reg(&(vu0_device
.regs
), coproc_reg
, i
, & value
);
3680 *A4_16(& xyzw
, 3-i
) = T2H_4(value
);
3687 sim_io_printf(sd
,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3688 coproc_num
,coproc_reg
,pr_addr(cia
));
3694 #endif /* TARGET_SKY */
3695 /* end-sanitize-sky */
3699 decode_coproc (SIM_DESC sd
,
3702 unsigned int instruction
)
3704 int coprocnum
= ((instruction
>> 26) & 3);
3708 case 0: /* standard CPU control and cache registers */
3710 int code
= ((instruction
>> 21) & 0x1F);
3711 int rt
= ((instruction
>> 16) & 0x1F);
3712 int rd
= ((instruction
>> 11) & 0x1F);
3713 int tail
= instruction
& 0x3ff;
3714 /* R4000 Users Manual (second edition) lists the following CP0
3716 CODE><-RT><RD-><--TAIL--->
3717 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3718 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3719 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3720 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3721 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3722 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3723 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3724 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3725 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3726 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3728 if (((code
== 0x00) || (code
== 0x04)) && tail
== 0)
3730 /* M[TF]C0 - 32 bit word */
3732 switch (rd
) /* NOTEs: Standard CP0 registers */
3734 /* 0 = Index R4000 VR4100 VR4300 */
3735 /* 1 = Random R4000 VR4100 VR4300 */
3736 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3737 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3738 /* 4 = Context R4000 VR4100 VR4300 */
3739 /* 5 = PageMask R4000 VR4100 VR4300 */
3740 /* 6 = Wired R4000 VR4100 VR4300 */
3741 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3742 /* 9 = Count R4000 VR4100 VR4300 */
3743 /* 10 = EntryHi R4000 VR4100 VR4300 */
3744 /* 11 = Compare R4000 VR4100 VR4300 */
3745 /* 12 = SR R4000 VR4100 VR4300 */
3746 #ifdef SUBTARGET_R3900
3750 /* 3 = Config R3900 */
3755 /* 3 = Cache R3900 */
3757 #endif /* SUBTARGET_R3900 */
3764 /* 13 = Cause R4000 VR4100 VR4300 */
3771 /* 14 = EPC R4000 VR4100 VR4300 */
3774 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
3778 /* 15 = PRId R4000 VR4100 VR4300 */
3779 #ifdef SUBTARGET_R3900
3788 /* 16 = Config R4000 VR4100 VR4300 */
3791 GPR
[rt
] = C0_CONFIG
;
3793 C0_CONFIG
= GPR
[rt
];
3796 #ifdef SUBTARGET_R3900
3805 /* 17 = LLAddr R4000 VR4100 VR4300 */
3807 /* 18 = WatchLo R4000 VR4100 VR4300 */
3808 /* 19 = WatchHi R4000 VR4100 VR4300 */
3809 /* 20 = XContext R4000 VR4100 VR4300 */
3810 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3811 /* 27 = CacheErr R4000 VR4100 */
3812 /* 28 = TagLo R4000 VR4100 VR4300 */
3813 /* 29 = TagHi R4000 VR4100 VR4300 */
3814 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3815 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3816 /* CPR[0,rd] = GPR[rt]; */
3819 GPR
[rt
] = (signed_word
) (signed32
) COP0_GPR
[rd
];
3821 COP0_GPR
[rd
] = GPR
[rt
];
3824 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3826 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3830 /* start-sanitize-r5900 */
3831 else if (((code
== 0x00) || (code
== 0x04)) && rd
== 0x18 && tail
> 0 && tail
< NR_COP0_BP
)
3832 /* Break-point registers */
3835 GPR
[rt
] = (signed_word
) (signed32
) COP0_BP
[tail
];
3837 COP0_BP
[tail
] = GPR
[rt
];
3839 else if (((code
== 0x00) || (code
== 0x04)) && rd
== 0x19 && tail
> 0 && tail
< NR_COP0_P
)
3840 /* Performance registers */
3843 GPR
[rt
] = (signed_word
) (signed32
) COP0_P
[tail
];
3845 COP0_P
[tail
] = GPR
[rt
];
3847 /* end-sanitize-r5900 */
3848 else if (code
== 0x10 && (tail
& 0x3f) == 0x18)
3851 if (SR
& status_ERL
)
3853 /* Oops, not yet available */
3854 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3864 else if (code
== 0x10 && (tail
& 0x3f) == 0x10)
3867 #ifdef SUBTARGET_R3900
3868 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3870 /* shift IE/KU history bits right */
3871 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 5, 2), 3, 0);
3873 /* TODO: CACHE register */
3874 #endif /* SUBTARGET_R3900 */
3876 else if (code
== 0x10 && (tail
& 0x3f) == 0x1F)
3884 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3885 /* TODO: When executing an ERET or RFE instruction we should
3886 clear LLBIT, to ensure that any out-standing atomic
3887 read/modify/write sequence fails. */
3891 case 2: /* co-processor 2 */
3895 /* start-sanitize-sky */
3896 #if defined(TARGET_SKY) && !defined(TARGET_SKY_B)
3897 /* On the R5900, this refers to a "VU" vector co-processor. */
3899 int i_25_21
= (instruction
>> 21) & 0x1f;
3900 int i_20_16
= (instruction
>> 16) & 0x1f;
3901 int i_20_6
= (instruction
>> 6) & 0x7fff;
3902 int i_15_11
= (instruction
>> 11) & 0x1f;
3903 int i_15_0
= instruction
& 0xffff;
3904 int i_10_1
= (instruction
>> 1) & 0x3ff;
3905 int i_10_0
= instruction
& 0x7ff;
3906 int i_10_6
= (instruction
>> 6) & 0x1f;
3907 int i_5_0
= instruction
& 0x03f;
3908 int interlock
= instruction
& 0x01;
3912 /* test COP2 usability */
3913 if(! (SR
& status_CU2
))
3915 SignalException(CoProcessorUnusable
,instruction
);
3919 /* BC2T/BC2F/BC2TL/BC2FL handled in r5900.igen */
3921 else if((i_25_21
== 0x02 && i_10_1
== 0x000) || /* CFC2 */
3922 (i_25_21
== 0x01)) /* QMFC2 */
3927 /* interlock checking */
3928 /* POLICY: never busy in macro mode */
3929 while(vu0_busy() && interlock
)
3932 /* perform VU register access */
3933 if(i_25_21
== 0x01) /* QMFC2 */
3937 /* one word at a time, argh! */
3938 read_vu_vec_reg(&(vu0_device
.regs
), id
, 3, &w
);
3939 read_vu_vec_reg(&(vu0_device
.regs
), id
, 2, &z
);
3940 read_vu_vec_reg(&(vu0_device
.regs
), id
, 1, &y
);
3941 read_vu_vec_reg(&(vu0_device
.regs
), id
, 0, &x
);
3943 GPR
[rt
] = U8_4(T2H_4(y
), T2H_4(x
));
3944 GPR1
[rt
] = U8_4(T2H_4(w
), T2H_4(z
));
3948 GPR
[rt
] = vu0_read_cop2_register(id
);
3951 else if((i_25_21
== 0x06 && i_10_1
== 0x000) || /* CTC2 */
3952 (i_25_21
== 0x05)) /* QMTC2 */
3957 /* interlock checking: wait until M or E bits set */
3958 /* POLICY: never busy in macro mode */
3959 while(vu0_busy() && interlock
)
3961 if(vu0_micro_interlock_released())
3963 vu0_micro_interlock_clear();
3970 /* perform VU register access */
3971 if(i_25_21
== 0x05) /* QMTC2 */
3975 x
= H2T_4(V4_8(GPR
[rt
], 1));
3976 y
= H2T_4(V4_8(GPR
[rt
], 0));
3977 z
= H2T_4(V4_8(GPR1
[rt
], 1));
3978 w
= H2T_4(V4_8(GPR1
[rt
], 0));
3980 /* one word at a time, argh! */
3981 write_vu_vec_reg(&(vu0_device
.regs
), id
, 3, & w
);
3982 write_vu_vec_reg(&(vu0_device
.regs
), id
, 2, & z
);
3983 write_vu_vec_reg(&(vu0_device
.regs
), id
, 1, & y
);
3984 write_vu_vec_reg(&(vu0_device
.regs
), id
, 0, & x
);
3988 vu0_write_cop2_register(id
, GPR
[rt
]);
3991 else if(i_10_0
== 0x3bf) /* VWAITQ */
3996 else if(i_5_0
== 0x38) /* VCALLMS */
3998 unsigned_4 data
= H2T_2(i_20_6
);
4003 /* write to reserved CIA register to get VU0 moving */
4004 write_vu_special_reg(& vu0_device
, VU_REG_CIA
, & data
);
4008 else if(i_5_0
== 0x39) /* VCALLMSR */
4015 read_vu_special_reg(& vu0_device
, VU_REG_CMSAR0
, & data
);
4016 /* write to reserved CIA register to get VU0 moving */
4017 write_vu_special_reg(& vu0_device
, VU_REG_CIA
, & data
);
4021 /* handle all remaining UPPER VU instructions in one block */
4022 else if((i_5_0
< 0x30) || /* VADDx .. VMINI */
4023 (i_5_0
>= 0x3c && i_10_6
< 0x0c)) /* VADDAx .. VNOP */
4025 unsigned_4 vu_upper
, vu_lower
;
4027 0x00000000 | /* bits 31 .. 25 */
4028 (instruction
& 0x01ffffff); /* bits 24 .. 0 */
4029 vu_lower
= 0x8000033c; /* NOP */
4031 /* POLICY: never busy in macro mode */
4035 vu0_macro_issue(vu_upper
, vu_lower
);
4037 /* POLICY: wait for completion of macro-instruction */
4041 /* handle all remaining LOWER VU instructions in one block */
4042 else if((i_5_0
>= 0x30 && i_5_0
<= 0x35) || /* VIADD .. VIOR */
4043 (i_5_0
>= 0x3c && i_10_6
>= 0x0c)) /* VMOVE .. VRXOR */
4044 { /* N.B.: VWAITQ already covered by prior case */
4045 unsigned_4 vu_upper
, vu_lower
;
4046 vu_upper
= 0x000002ff; /* NOP/NOP */
4048 0x80000000 | /* bits 31 .. 25 */
4049 (instruction
& 0x01ffffff); /* bits 24 .. 0 */
4051 /* POLICY: never busy in macro mode */
4055 vu0_macro_issue(vu_upper
, vu_lower
);
4057 /* POLICY: wait for completion of macro-instruction */
4061 /* ... no other COP2 instructions ... */
4064 SignalException(ReservedInstruction
, instruction
);
4068 #endif /* TARGET_SKY */
4069 /* end-sanitize-sky */
4073 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
4074 instruction
,pr_addr(cia
));
4079 case 1: /* should not occur (FPU co-processor) */
4080 case 3: /* should not occur (FPU co-processor) */
4081 SignalException(ReservedInstruction
,instruction
);
4089 /*-- instruction simulation -------------------------------------------------*/
4091 /* When the IGEN simulator is being built, the function below is be
4092 replaced by a generated version. However, WITH_IGEN == 2 indicates
4093 that the fubction below should be compiled but under a different
4094 name (to allow backward compatibility) */
4096 #if (WITH_IGEN != 1)
4098 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
4100 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
4103 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
4106 int next_cpu_nr
; /* ignore */
4107 int nr_cpus
; /* ignore */
4108 int siggnal
; /* ignore */
4110 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
4111 #if !defined(FASTSIM)
4112 unsigned int pipeline_count
= 1;
4116 if (STATE_MEMORY (sd
) == NULL
) {
4117 printf("DBG: simulate() entered with no memory\n");
4122 #if 0 /* Disabled to check that everything works OK */
4123 /* The VR4300 seems to sign-extend the PC on its first
4124 access. However, this may just be because it is currently
4125 configured in 32bit mode. However... */
4126 PC
= SIGNEXTEND(PC
,32);
4129 /* main controlling loop */
4131 /* vaddr is slowly being replaced with cia - current instruction
4133 address_word cia
= (uword64
)PC
;
4134 address_word vaddr
= cia
;
4137 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
4141 printf("DBG: state = 0x%08X :",state
);
4142 if (state
& simHALTEX
) printf(" simHALTEX");
4143 if (state
& simHALTIN
) printf(" simHALTIN");
4148 DSSTATE
= (STATE
& simDELAYSLOT
);
4151 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
4154 /* Fetch the next instruction from the simulator memory: */
4155 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
4156 if ((vaddr
& 1) == 0) {
4157 /* Copy the action of the LW instruction */
4158 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
4159 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
4162 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
4163 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
4164 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
4165 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
4167 /* Copy the action of the LH instruction */
4168 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
4169 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
4172 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
4173 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
4174 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
4175 paddr
& ~ (uword64
) 1,
4176 vaddr
, isINSTRUCTION
, isREAL
);
4177 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
4178 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
4181 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
4186 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
4189 /* This is required by exception processing, to ensure that we can
4190 cope with exceptions in the delay slots of branches that may
4191 already have changed the PC. */
4192 if ((vaddr
& 1) == 0)
4193 PC
+= 4; /* increment ready for the next fetch */
4196 /* NOTE: If we perform a delay slot change to the PC, this
4197 increment is not requuired. However, it would make the
4198 simulator more complicated to try and avoid this small hit. */
4200 /* Currently this code provides a simple model. For more
4201 complicated models we could perform exception status checks at
4202 this point, and set the simSTOP state as required. This could
4203 also include processing any hardware interrupts raised by any
4204 I/O model attached to the simulator context.
4206 Support for "asynchronous" I/O events within the simulated world
4207 could be providing by managing a counter, and calling a I/O
4208 specific handler when a particular threshold is reached. On most
4209 architectures a decrement and check for zero operation is
4210 usually quicker than an increment and compare. However, the
4211 process of managing a known value decrement to zero, is higher
4212 than the cost of using an explicit value UINT_MAX into the
4213 future. Which system is used will depend on how complicated the
4214 I/O model is, and how much it is likely to affect the simulator
4217 If events need to be scheduled further in the future than
4218 UINT_MAX event ticks, then the I/O model should just provide its
4219 own counter, triggered from the event system. */
4221 /* MIPS pipeline ticks. To allow for future support where the
4222 pipeline hit of individual instructions is known, this control
4223 loop manages a "pipeline_count" variable. It is initialised to
4224 1 (one), and will only be changed by the simulator engine when
4225 executing an instruction. If the engine does not have access to
4226 pipeline cycle count information then all instructions will be
4227 treated as using a single cycle. NOTE: A standard system is not
4228 provided by the default simulator because different MIPS
4229 architectures have different cycle counts for the same
4232 [NOTE: pipeline_count has been replaced the event queue] */
4234 /* shuffle the floating point status pipeline state */
4235 ENGINE_ISSUE_PREFIX_HOOK();
4237 /* NOTE: For multi-context simulation environments the "instruction"
4238 variable should be local to this routine. */
4240 /* Shorthand accesses for engine. Note: If we wanted to use global
4241 variables (and a single-threaded simulator engine), then we can
4242 create the actual variables with these names. */
4244 if (!(STATE
& simSKIPNEXT
)) {
4245 /* Include the simulator engine */
4246 #include "oengine.c"
4247 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
4248 #error "Mismatch between run-time simulator code and simulation engine"
4250 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
4251 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
4253 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
4254 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
4257 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
4258 should check for it being changed. It is better doing it here,
4259 than within the simulator, since it will help keep the simulator
4262 #if defined(WARN_ZERO)
4263 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
4264 #endif /* WARN_ZERO */
4265 ZERO
= 0; /* reset back to zero before next instruction */
4267 } else /* simSKIPNEXT check */
4268 STATE
&= ~simSKIPNEXT
;
4270 /* If the delay slot was active before the instruction is
4271 executed, then update the PC to its new value: */
4274 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
4283 #if !defined(FASTSIM)
4284 if (sim_events_tickn (sd
, pipeline_count
))
4286 /* cpu->cia = cia; */
4287 sim_events_process (sd
);
4290 if (sim_events_tick (sd
))
4292 /* cpu->cia = cia; */
4293 sim_events_process (sd
);
4295 #endif /* FASTSIM */
4301 /* This code copied from gdb's utils.c. Would like to share this code,
4302 but don't know of a common place where both could get to it. */
4304 /* Temporary storage using circular buffer */
4310 static char buf
[NUMCELLS
][CELLSIZE
];
4312 if (++cell
>=NUMCELLS
) cell
=0;
4316 /* Print routines to handle variable size regs, etc */
4318 /* Eliminate warning from compiler on 32-bit systems */
4319 static int thirty_two
= 32;
4325 char *paddr_str
=get_cell();
4326 switch (sizeof(addr
))
4329 sprintf(paddr_str
,"%08lx%08lx",
4330 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
4333 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
4336 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
4339 sprintf(paddr_str
,"%x",addr
);
4348 char *paddr_str
=get_cell();
4349 sprintf(paddr_str
,"%08lx%08lx",
4350 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
4356 /*---------------------------------------------------------------------------*/
4357 /*> EOF interp.c <*/