2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 /* The TRACE manifests enable the provision of extra features. If they
26 are not defined then a simpler (quicker) simulator is constructed
27 without the required run-time checks, etc. */
28 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
35 #include "sim-utils.h"
36 #include "sim-options.h"
37 #include "sim-assert.h"
63 #include "libiberty.h"
65 #include "gdb/callback.h" /* GDB simulator callback interface */
66 #include "gdb/remote-sim.h" /* GDB simulator interface */
68 char* pr_addr (SIM_ADDR addr
);
69 char* pr_uword64 (uword64 addr
);
72 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
77 /* The following reserved instruction value is used when a simulator
78 trap is required. NOTE: Care must be taken, since this value may be
79 used in later revisions of the MIPS ISA. */
81 #define RSVD_INSTRUCTION (0x00000005)
82 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
84 #define RSVD_INSTRUCTION_ARG_SHIFT 6
85 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
88 /* Bits in the Debug register */
89 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
90 #define Debug_DM 0x40000000 /* Debug Mode */
91 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
93 /*---------------------------------------------------------------------------*/
94 /*-- GDB simulator interface ------------------------------------------------*/
95 /*---------------------------------------------------------------------------*/
97 static void ColdReset (SIM_DESC sd
);
99 /*---------------------------------------------------------------------------*/
103 #define DELAYSLOT() {\
104 if (STATE & simDELAYSLOT)\
105 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
106 STATE |= simDELAYSLOT;\
109 #define JALDELAYSLOT() {\
111 STATE |= simJALDELAYSLOT;\
115 STATE &= ~simDELAYSLOT;\
116 STATE |= simSKIPNEXT;\
119 #define CANCELDELAYSLOT() {\
121 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
124 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
125 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
127 /* Note that the monitor code essentially assumes this layout of memory.
128 If you change these, change the monitor code, too. */
129 /* FIXME Currently addresses are truncated to 32-bits, see
130 mips/sim-main.c:address_translation(). If that changes, then these
131 values will need to be extended, and tested for more carefully. */
132 #define K0BASE (0x80000000)
133 #define K0SIZE (0x20000000)
134 #define K1BASE (0xA0000000)
135 #define K1SIZE (0x20000000)
137 /* Simple run-time monitor support.
139 We emulate the monitor by placing magic reserved instructions at
140 the monitor's entry points; when we hit these instructions, instead
141 of raising an exception (as we would normally), we look at the
142 instruction and perform the appropriate monitory operation.
144 `*_monitor_base' are the physical addresses at which the corresponding
145 monitor vectors are located. `0' means none. By default,
147 The RSVD_INSTRUCTION... macros specify the magic instructions we
148 use at the monitor entry points. */
149 static int firmware_option_p
= 0;
150 static SIM_ADDR idt_monitor_base
= 0xBFC00000;
151 static SIM_ADDR pmon_monitor_base
= 0xBFC00500;
152 static SIM_ADDR lsipmon_monitor_base
= 0xBFC00200;
154 static SIM_RC
sim_firmware_command (SIM_DESC sd
, char* arg
);
157 #define MEM_SIZE (8 << 20) /* 8 MBytes */
161 static char *tracefile
= "trace.din"; /* default filename for trace log */
162 FILE *tracefh
= NULL
;
163 static void open_trace (SIM_DESC sd
);
166 static const char * get_insn_name (sim_cpu
*, int);
168 /* simulation target board. NULL=canonical */
169 static char* board
= NULL
;
172 static DECLARE_OPTION_HANDLER (mips_option_handler
);
175 OPTION_DINERO_TRACE
= OPTION_START
,
182 static int display_mem_info
= 0;
185 mips_option_handler (SIM_DESC sd
, sim_cpu
*cpu
, int opt
, char *arg
,
191 case OPTION_DINERO_TRACE
: /* ??? */
193 /* Eventually the simTRACE flag could be treated as a toggle, to
194 allow external control of the program points being traced
195 (i.e. only from main onwards, excluding the run-time setup,
197 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
199 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
202 else if (strcmp (arg
, "yes") == 0)
204 else if (strcmp (arg
, "no") == 0)
206 else if (strcmp (arg
, "on") == 0)
208 else if (strcmp (arg
, "off") == 0)
212 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
219 Simulator constructed without dinero tracing support (for performance).\n\
220 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
224 case OPTION_DINERO_FILE
:
226 if (optarg
!= NULL
) {
228 tmp
= (char *)malloc(strlen(optarg
) + 1);
231 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
237 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
243 case OPTION_FIRMWARE
:
244 return sim_firmware_command (sd
, arg
);
250 board
= zalloc(strlen(arg
) + 1);
256 case OPTION_INFO_MEMORY
:
257 display_mem_info
= 1;
265 static const OPTION mips_options
[] =
267 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
268 '\0', "on|off", "Enable dinero tracing",
269 mips_option_handler
},
270 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
271 '\0', "FILE", "Write dinero trace to FILE",
272 mips_option_handler
},
273 { {"firmware", required_argument
, NULL
, OPTION_FIRMWARE
},
274 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
275 mips_option_handler
},
276 { {"board", required_argument
, NULL
, OPTION_BOARD
},
277 '\0', "none" /* rely on compile-time string concatenation for other options */
279 #define BOARD_JMR3904 "jmr3904"
281 #define BOARD_JMR3904_PAL "jmr3904pal"
282 "|" BOARD_JMR3904_PAL
283 #define BOARD_JMR3904_DEBUG "jmr3904debug"
284 "|" BOARD_JMR3904_DEBUG
285 #define BOARD_BSP "bsp"
288 , "Customize simulation for a particular board.", mips_option_handler
},
290 /* These next two options have the same names as ones found in the
291 memory_options[] array in common/sim-memopt.c. This is because
292 the intention is to provide an alternative handler for those two
293 options. We need an alternative handler because the memory
294 regions are not set up until after the command line arguments
295 have been parsed, and so we cannot display the memory info whilst
296 processing the command line. There is a hack in sim_open to
297 remove these handlers when we want the real --memory-info option
299 { { "info-memory", no_argument
, NULL
, OPTION_INFO_MEMORY
},
300 '\0', NULL
, "List configured memory regions", mips_option_handler
},
301 { { "memory-info", no_argument
, NULL
, OPTION_INFO_MEMORY
},
302 '\0', NULL
, NULL
, mips_option_handler
},
304 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
308 int interrupt_pending
;
311 interrupt_event (SIM_DESC sd
, void *data
)
313 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
314 address_word cia
= CIA_GET (cpu
);
317 interrupt_pending
= 0;
318 SignalExceptionInterrupt (1); /* interrupt "1" */
320 else if (!interrupt_pending
)
321 sim_events_schedule (sd
, 1, interrupt_event
, data
);
325 /*---------------------------------------------------------------------------*/
326 /*-- Device registration hook -----------------------------------------------*/
327 /*---------------------------------------------------------------------------*/
328 static void device_init(SIM_DESC sd
) {
330 extern void register_devices(SIM_DESC
);
331 register_devices(sd
);
335 /*---------------------------------------------------------------------------*/
336 /*-- GDB simulator interface ------------------------------------------------*/
337 /*---------------------------------------------------------------------------*/
340 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
342 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
343 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
345 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
347 /* FIXME: watchpoints code shouldn't need this */
348 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
349 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
350 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
352 /* Initialize the mechanism for doing insn profiling. */
353 CPU_INSN_NAME (cpu
) = get_insn_name
;
354 CPU_MAX_INSNS (cpu
) = nr_itable_entries
;
358 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
360 sim_add_option_table (sd
, NULL
, mips_options
);
363 /* getopt will print the error message so we just have to exit if this fails.
364 FIXME: Hmmm... in the case of gdb we need getopt to call
366 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
368 /* Uninstall the modules to avoid memory leaks,
369 file descriptor leaks, etc. */
370 sim_module_uninstall (sd
);
374 /* handle board-specific memory maps */
377 /* Allocate core managed memory */
378 sim_memopt
*entry
, *match
= NULL
;
379 address_word mem_size
= 0;
382 /* For compatibility with the old code - under this (at level one)
383 are the kernel spaces K0 & K1. Both of these map to a single
384 smaller sub region */
385 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
387 /* Look for largest memory region defined on command-line at
389 #ifdef SIM_HAVE_FLATMEM
390 mem_size
= STATE_MEM_SIZE (sd
);
392 for (entry
= STATE_MEMOPT (sd
); entry
!= NULL
; entry
= entry
->next
)
394 /* If we find an entry at address 0, then we will end up
395 allocating a new buffer in the "memory alias" command
396 below. The region at address 0 will be deleted. */
397 address_word size
= (entry
->modulo
!= 0
398 ? entry
->modulo
: entry
->nr_bytes
);
400 && (!match
|| entry
->level
< match
->level
))
402 else if (entry
->addr
== K0BASE
|| entry
->addr
== K1BASE
)
407 for (alias
= entry
->alias
; alias
!= NULL
; alias
= alias
->next
)
410 && (!match
|| entry
->level
< match
->level
))
412 else if (alias
->addr
== K0BASE
|| alias
->addr
== K1BASE
)
422 /* Get existing memory region size. */
423 mem_size
= (match
->modulo
!= 0
424 ? match
->modulo
: match
->nr_bytes
);
425 /* Delete old region. */
426 sim_do_commandf (sd
, "memory delete %d:0x%lx@%d",
427 match
->space
, match
->addr
, match
->level
);
429 else if (mem_size
== 0)
431 /* Limit to KSEG1 size (512MB) */
432 if (mem_size
> K1SIZE
)
434 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
435 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
436 K1BASE
, K1SIZE
, (long)mem_size
, K0BASE
);
441 else if (board
!= NULL
442 && (strcmp(board
, BOARD_BSP
) == 0))
446 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
448 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
449 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
451 4 * 1024 * 1024, /* 4 MB */
454 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
455 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
457 4 * 1024 * 1024, /* 4 MB */
460 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
461 for (i
=0; i
<8; i
++) /* 32 MB total */
463 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
464 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
465 0x88000000 + (i
* size
),
467 0xA8000000 + (i
* size
));
471 else if (board
!= NULL
472 && (strcmp(board
, BOARD_JMR3904
) == 0 ||
473 strcmp(board
, BOARD_JMR3904_PAL
) == 0 ||
474 strcmp(board
, BOARD_JMR3904_DEBUG
) == 0))
476 /* match VIRTUAL memory layout of JMR-TX3904 board */
479 /* --- disable monitor unless forced on by user --- */
481 if (! firmware_option_p
)
483 idt_monitor_base
= 0;
484 pmon_monitor_base
= 0;
485 lsipmon_monitor_base
= 0;
488 /* --- environment --- */
490 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
494 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
495 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
497 4 * 1024 * 1024, /* 4 MB */
500 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
501 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
503 4 * 1024 * 1024, /* 4 MB */
506 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
507 for (i
=0; i
<8; i
++) /* 32 MB total */
509 unsigned size
= 4 * 1024 * 1024; /* 4 MB */
510 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx,0x%0x",
511 0x88000000 + (i
* size
),
513 0xA8000000 + (i
* size
));
516 /* Dummy memory regions for unsimulated devices - sorted by address */
518 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
519 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
520 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
521 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
522 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
523 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
524 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
525 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
526 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
529 /* --- simulated devices --- */
530 sim_hw_parse (sd
, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
531 sim_hw_parse (sd
, "/tx3904cpu");
532 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
533 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
534 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
535 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
537 /* FIXME: poking at dv-sockser internals, use tcp backend if
538 --sockser_addr option was given.*/
539 extern char* sockser_addr
;
540 if(sockser_addr
== NULL
)
541 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend stdio");
543 sim_hw_parse (sd
, "/tx3904sio@0xfffff300/backend tcp");
545 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
546 sim_hw_parse (sd
, "/tx3904sio@0xfffff400/backend stdio");
548 /* -- device connections --- */
549 sim_hw_parse (sd
, "/tx3904irc > ip level /tx3904cpu");
550 sim_hw_parse (sd
, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
551 sim_hw_parse (sd
, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
552 sim_hw_parse (sd
, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
553 sim_hw_parse (sd
, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
554 sim_hw_parse (sd
, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
556 /* add PAL timer & I/O module */
557 if(! strcmp(board
, BOARD_JMR3904_PAL
))
560 sim_hw_parse (sd
, "/pal@0xffff0000");
561 sim_hw_parse (sd
, "/pal@0xffff0000/reg 0xffff0000 64");
563 /* wire up interrupt ports to irc */
564 sim_hw_parse (sd
, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
565 sim_hw_parse (sd
, "/pal@0x31000000 > timer tmr1 /tx3904irc");
566 sim_hw_parse (sd
, "/pal@0x31000000 > int int0 /tx3904irc");
569 if(! strcmp(board
, BOARD_JMR3904_DEBUG
))
571 /* -- DEBUG: glue interrupt generators --- */
572 sim_hw_parse (sd
, "/glue@0xffff0000/reg 0xffff0000 0x50");
573 sim_hw_parse (sd
, "/glue@0xffff0000 > int0 int0 /tx3904irc");
574 sim_hw_parse (sd
, "/glue@0xffff0000 > int1 int1 /tx3904irc");
575 sim_hw_parse (sd
, "/glue@0xffff0000 > int2 int2 /tx3904irc");
576 sim_hw_parse (sd
, "/glue@0xffff0000 > int3 int3 /tx3904irc");
577 sim_hw_parse (sd
, "/glue@0xffff0000 > int4 int4 /tx3904irc");
578 sim_hw_parse (sd
, "/glue@0xffff0000 > int5 int5 /tx3904irc");
579 sim_hw_parse (sd
, "/glue@0xffff0000 > int6 int6 /tx3904irc");
580 sim_hw_parse (sd
, "/glue@0xffff0000 > int7 int7 /tx3904irc");
581 sim_hw_parse (sd
, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
582 sim_hw_parse (sd
, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
583 sim_hw_parse (sd
, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
584 sim_hw_parse (sd
, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
585 sim_hw_parse (sd
, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
586 sim_hw_parse (sd
, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
587 sim_hw_parse (sd
, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
588 sim_hw_parse (sd
, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
589 sim_hw_parse (sd
, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
590 sim_hw_parse (sd
, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
597 if (display_mem_info
)
599 struct option_list
* ol
;
600 struct option_list
* prev
;
602 /* This is a hack. We want to execute the real --memory-info command
603 line switch which is handled in common/sim-memopts.c, not the
604 override we have defined in this file. So we remove the
605 mips_options array from the state options list. This is safe
606 because we have now processed all of the command line. */
607 for (ol
= STATE_OPTIONS (sd
), prev
= NULL
;
609 prev
= ol
, ol
= ol
->next
)
610 if (ol
->options
== mips_options
)
613 SIM_ASSERT (ol
!= NULL
);
616 STATE_OPTIONS (sd
) = ol
->next
;
618 prev
->next
= ol
->next
;
620 sim_do_commandf (sd
, "memory-info");
623 /* check for/establish the a reference program image */
624 if (sim_analyze_program (sd
,
625 (STATE_PROG_ARGV (sd
) != NULL
626 ? *STATE_PROG_ARGV (sd
)
630 sim_module_uninstall (sd
);
634 /* Configure/verify the target byte order and other runtime
635 configuration options */
636 if (sim_config (sd
) != SIM_RC_OK
)
638 sim_module_uninstall (sd
);
642 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
644 /* Uninstall the modules to avoid memory leaks,
645 file descriptor leaks, etc. */
646 sim_module_uninstall (sd
);
650 /* verify assumptions the simulator made about the host type system.
651 This macro does not return if there is a problem */
652 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
653 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
655 /* This is NASTY, in that we are assuming the size of specific
659 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
662 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
663 else if ((rn
>= FGR_BASE
) && (rn
< (FGR_BASE
+ NR_FGR
)))
664 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
665 else if ((rn
>= 33) && (rn
<= 37))
666 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
667 else if ((rn
== SRIDX
)
670 || ((rn
>= 72) && (rn
<= 89)))
671 cpu
->register_widths
[rn
] = 32;
673 cpu
->register_widths
[rn
] = 0;
680 if (STATE
& simTRACE
)
685 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
688 lsipmon_monitor_base);
691 /* Write the monitor trap address handlers into the monitor (eeprom)
692 address space. This can only be done once the target endianness
693 has been determined. */
694 if (idt_monitor_base
!= 0)
697 unsigned idt_monitor_size
= 1 << 11;
699 /* the default monitor region */
700 sim_do_commandf (sd
, "memory region 0x%x,0x%x",
701 idt_monitor_base
, idt_monitor_size
);
703 /* Entry into the IDT monitor is via fixed address vectors, and
704 not using machine instructions. To avoid clashing with use of
705 the MIPS TRAP system, we place our own (simulator specific)
706 "undefined" instructions into the relevant vector slots. */
707 for (loop
= 0; (loop
< idt_monitor_size
); loop
+= 4)
709 address_word vaddr
= (idt_monitor_base
+ loop
);
710 unsigned32 insn
= (RSVD_INSTRUCTION
|
711 (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
)
712 << RSVD_INSTRUCTION_ARG_SHIFT
));
714 sim_write (sd
, vaddr
, (unsigned char *)&insn
, sizeof (insn
));
718 if ((pmon_monitor_base
!= 0) || (lsipmon_monitor_base
!= 0))
720 /* The PMON monitor uses the same address space, but rather than
721 branching into it the address of a routine is loaded. We can
722 cheat for the moment, and direct the PMON routine to IDT style
723 instructions within the monitor space. This relies on the IDT
724 monitor not using the locations from 0xBFC00500 onwards as its
727 for (loop
= 0; (loop
< 24); loop
++)
729 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
745 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
747 case 8: /* cliexit */
750 case 11: /* flush_cache */
755 SIM_ASSERT (idt_monitor_base
!= 0);
756 value
= ((unsigned int) idt_monitor_base
+ (value
* 8));
759 if (pmon_monitor_base
!= 0)
761 address_word vaddr
= (pmon_monitor_base
+ (loop
* 4));
762 sim_write (sd
, vaddr
, (unsigned char *)&value
, sizeof (value
));
765 if (lsipmon_monitor_base
!= 0)
767 address_word vaddr
= (lsipmon_monitor_base
+ (loop
* 4));
768 sim_write (sd
, vaddr
, (unsigned char *)&value
, sizeof (value
));
772 /* Write an abort sequence into the TRAP (common) exception vector
773 addresses. This is to catch code executing a TRAP (et.al.)
774 instruction without installing a trap handler. */
775 if ((idt_monitor_base
!= 0) ||
776 (pmon_monitor_base
!= 0) ||
777 (lsipmon_monitor_base
!= 0))
779 unsigned32 halt
[2] = { 0x2404002f /* addiu r4, r0, 47 */,
780 HALT_INSTRUCTION
/* BREAK */ };
783 sim_write (sd
, 0x80000000, (unsigned char *) halt
, sizeof (halt
));
784 sim_write (sd
, 0x80000180, (unsigned char *) halt
, sizeof (halt
));
785 sim_write (sd
, 0x80000200, (unsigned char *) halt
, sizeof (halt
));
786 /* XXX: Write here unconditionally? */
787 sim_write (sd
, 0xBFC00200, (unsigned char *) halt
, sizeof (halt
));
788 sim_write (sd
, 0xBFC00380, (unsigned char *) halt
, sizeof (halt
));
789 sim_write (sd
, 0xBFC00400, (unsigned char *) halt
, sizeof (halt
));
800 open_trace (SIM_DESC sd
)
802 tracefh
= fopen(tracefile
,"wb+");
805 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
811 /* Return name of an insn, used by insn profiling. */
813 get_insn_name (sim_cpu
*cpu
, int i
)
815 return itable
[i
].name
;
819 sim_close (SIM_DESC sd
, int quitting
)
822 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
826 /* "quitting" is non-zero if we cannot hang on errors */
828 /* shut down modules */
829 sim_module_uninstall (sd
);
831 /* Ensure that any resources allocated through the callback
832 mechanism are released: */
833 sim_io_shutdown (sd
);
836 if (tracefh
!= NULL
&& tracefh
!= stderr
)
841 /* FIXME - free SD */
848 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
851 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
853 /* Return the number of bytes written, or zero if error. */
855 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
858 /* We use raw read and write routines, since we do not want to count
859 the GDB memory accesses in our statistics gathering. */
861 for (index
= 0; index
< size
; index
++)
863 address_word vaddr
= (address_word
)addr
+ index
;
866 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
868 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
876 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
879 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
881 /* Return the number of bytes read, or zero if error. */
883 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
886 for (index
= 0; (index
< size
); index
++)
888 address_word vaddr
= (address_word
)addr
+ index
;
891 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
893 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
901 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
903 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
904 /* NOTE: gdb (the client) stores registers in target byte order
905 while the simulator uses host byte order */
907 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
910 /* Unfortunately this suffers from the same problem as the register
911 numbering one. We need to know what the width of each logical
912 register number is for the architecture being simulated. */
914 if (cpu
->register_widths
[rn
] == 0)
916 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
922 if (rn
>= FGR_BASE
&& rn
< FGR_BASE
+ NR_FGR
)
924 cpu
->fpr_state
[rn
- FGR_BASE
] = fmt_uninterpreted
;
925 if (cpu
->register_widths
[rn
] == 32)
929 cpu
->fgr
[rn
- FGR_BASE
] =
930 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
935 cpu
->fgr
[rn
- FGR_BASE
] = T2H_4 (*(unsigned32
*)memory
);
943 cpu
->fgr
[rn
- FGR_BASE
] = T2H_8 (*(unsigned64
*)memory
);
948 cpu
->fgr
[rn
- FGR_BASE
] = T2H_4 (*(unsigned32
*)memory
);
954 if (cpu
->register_widths
[rn
] == 32)
959 (unsigned32
) T2H_8 (*(unsigned64
*)memory
);
964 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
972 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
977 cpu
->registers
[rn
] = (signed32
) T2H_4(*(unsigned32
*)memory
);
986 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
988 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
989 /* NOTE: gdb (the client) stores registers in target byte order
990 while the simulator uses host byte order */
992 #if 0 /* FIXME: doesn't compile */
993 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
997 if (cpu
->register_widths
[rn
] == 0)
999 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
1005 /* Any floating point register */
1006 if (rn
>= FGR_BASE
&& rn
< FGR_BASE
+ NR_FGR
)
1008 if (cpu
->register_widths
[rn
] == 32)
1012 *(unsigned64
*)memory
=
1013 H2T_8 ((unsigned32
) (cpu
->fgr
[rn
- FGR_BASE
]));
1018 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGR_BASE
]);
1026 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGR_BASE
]);
1031 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->fgr
[rn
- FGR_BASE
]));
1037 if (cpu
->register_widths
[rn
] == 32)
1041 *(unsigned64
*)memory
=
1042 H2T_8 ((unsigned32
) (cpu
->registers
[rn
]));
1047 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
1055 *(unsigned64
*)memory
=
1056 H2T_8 ((unsigned64
) (cpu
->registers
[rn
]));
1061 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
1070 sim_pc_get (sim_cpu
*cpu
)
1076 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
1080 #if 0 /* FIXME: doesn't compile */
1081 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1090 /* override PC value set by ColdReset () */
1092 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1094 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1095 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
1099 #if 0 /* def DEBUG */
1102 /* We should really place the argv slot values into the argument
1103 registers, and onto the stack as required. However, this
1104 assumes that we have a stack defined, which is not
1105 necessarily true at the moment. */
1107 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1108 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1109 printf("DBG: arg \"%s\"\n",*cptr
);
1116 /*---------------------------------------------------------------------------*/
1117 /*-- Private simulator support interface ------------------------------------*/
1118 /*---------------------------------------------------------------------------*/
1120 /* Read a null terminated string from memory, return in a buffer */
1122 fetch_str (SIM_DESC sd
,
1128 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1130 buf
= NZALLOC (char, nr
+ 1);
1131 sim_read (sd
, addr
, (unsigned char *)buf
, nr
);
1136 /* Implements the "sim firmware" command:
1137 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1138 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1139 defaults to the normal address for that monitor.
1140 sim firmware none --- don't emulate any ROM monitor. Useful
1141 if you need a clean address space. */
1143 sim_firmware_command (SIM_DESC sd
, char *arg
)
1145 int address_present
= 0;
1148 /* Signal occurrence of this option. */
1149 firmware_option_p
= 1;
1151 /* Parse out the address, if present. */
1153 char *p
= strchr (arg
, '@');
1157 address_present
= 1;
1158 p
++; /* skip over @ */
1160 address
= strtoul (p
, &q
, 0);
1163 sim_io_printf (sd
, "Invalid address given to the"
1164 "`sim firmware NAME@ADDRESS' command: %s\n",
1171 address_present
= 0;
1172 address
= -1; /* Dummy value. */
1176 if (! strncmp (arg
, "idt", 3))
1178 idt_monitor_base
= address_present
? address
: 0xBFC00000;
1179 pmon_monitor_base
= 0;
1180 lsipmon_monitor_base
= 0;
1182 else if (! strncmp (arg
, "pmon", 4))
1184 /* pmon uses indirect calls. Hook into implied idt. */
1185 pmon_monitor_base
= address_present
? address
: 0xBFC00500;
1186 idt_monitor_base
= pmon_monitor_base
- 0x500;
1187 lsipmon_monitor_base
= 0;
1189 else if (! strncmp (arg
, "lsipmon", 7))
1191 /* lsipmon uses indirect calls. Hook into implied idt. */
1192 pmon_monitor_base
= 0;
1193 lsipmon_monitor_base
= address_present
? address
: 0xBFC00200;
1194 idt_monitor_base
= lsipmon_monitor_base
- 0x200;
1196 else if (! strncmp (arg
, "none", 4))
1198 if (address_present
)
1201 "The `sim firmware none' command does "
1202 "not take an `ADDRESS' argument.\n");
1205 idt_monitor_base
= 0;
1206 pmon_monitor_base
= 0;
1207 lsipmon_monitor_base
= 0;
1211 sim_io_printf (sd
, "\
1212 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1213 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1223 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1225 sim_monitor (SIM_DESC sd
,
1228 unsigned int reason
)
1231 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1234 /* The IDT monitor actually allows two instructions per vector
1235 slot. However, the simulator currently causes a trap on each
1236 individual instruction. We cheat, and lose the bottom bit. */
1239 /* The following callback functions are available, however the
1240 monitor we are simulating does not make use of them: get_errno,
1241 isatty, lseek, rename, system, time and unlink */
1245 case 6: /* int open(char *path,int flags) */
1247 char *path
= fetch_str (sd
, A0
);
1248 V0
= sim_io_open (sd
, path
, (int)A1
);
1253 case 7: /* int read(int file,char *ptr,int len) */
1257 char *buf
= zalloc (nr
);
1258 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1259 sim_write (sd
, A1
, (unsigned char *)buf
, nr
);
1264 case 8: /* int write(int file,char *ptr,int len) */
1268 char *buf
= zalloc (nr
);
1269 sim_read (sd
, A1
, (unsigned char *)buf
, nr
);
1270 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1272 sim_io_flush_stdout (sd
);
1274 sim_io_flush_stderr (sd
);
1279 case 10: /* int close(int file) */
1281 V0
= sim_io_close (sd
, (int)A0
);
1285 case 2: /* Densan monitor: char inbyte(int waitflag) */
1287 if (A0
== 0) /* waitflag == NOWAIT */
1288 V0
= (unsigned_word
)-1;
1290 /* Drop through to case 11 */
1292 case 11: /* char inbyte(void) */
1295 /* ensure that all output has gone... */
1296 sim_io_flush_stdout (sd
);
1297 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1299 sim_io_error(sd
,"Invalid return from character read");
1300 V0
= (unsigned_word
)-1;
1303 V0
= (unsigned_word
)tmp
;
1307 case 3: /* Densan monitor: void co(char chr) */
1308 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1310 char tmp
= (char)(A0
& 0xFF);
1311 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1315 case 17: /* void _exit() */
1317 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1318 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1319 (unsigned int)(A0
& 0xFFFFFFFF));
1323 case 28: /* PMON flush_cache */
1326 case 55: /* void get_mem_info(unsigned int *ptr) */
1327 /* in: A0 = pointer to three word memory location */
1328 /* out: [A0 + 0] = size */
1329 /* [A0 + 4] = instruction cache size */
1330 /* [A0 + 8] = data cache size */
1333 unsigned_4 zero
= 0;
1334 address_word mem_size
;
1335 sim_memopt
*entry
, *match
= NULL
;
1337 /* Search for memory region mapped to KSEG0 or KSEG1. */
1338 for (entry
= STATE_MEMOPT (sd
);
1340 entry
= entry
->next
)
1342 if ((entry
->addr
== K0BASE
|| entry
->addr
== K1BASE
)
1343 && (!match
|| entry
->level
< match
->level
))
1348 for (alias
= entry
->alias
;
1350 alias
= alias
->next
)
1351 if ((alias
->addr
== K0BASE
|| alias
->addr
== K1BASE
)
1352 && (!match
|| entry
->level
< match
->level
))
1357 /* Get region size, limit to KSEG1 size (512MB). */
1358 SIM_ASSERT (match
!= NULL
);
1359 mem_size
= (match
->modulo
!= 0
1360 ? match
->modulo
: match
->nr_bytes
);
1361 if (mem_size
> K1SIZE
)
1366 sim_write (sd
, A0
+ 0, (unsigned char *)&value
, 4);
1367 sim_write (sd
, A0
+ 4, (unsigned char *)&zero
, 4);
1368 sim_write (sd
, A0
+ 8, (unsigned char *)&zero
, 4);
1369 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1373 case 158: /* PMON printf */
1374 /* in: A0 = pointer to format string */
1375 /* A1 = optional argument 1 */
1376 /* A2 = optional argument 2 */
1377 /* A3 = optional argument 3 */
1379 /* The following is based on the PMON printf source */
1381 address_word s
= A0
;
1383 signed_word
*ap
= &A1
; /* 1st argument */
1384 /* This isn't the quickest way, since we call the host print
1385 routine for every character almost. But it does avoid
1386 having to allocate and manage a temporary string buffer. */
1387 /* TODO: Include check that we only use three arguments (A1,
1389 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1394 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1395 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1396 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1398 if (strchr ("dobxXulscefg%", c
))
1413 else if (c
>= '1' && c
<= '9')
1417 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1420 n
= (unsigned int)strtol(tmp
,NULL
,10);
1433 sim_io_printf (sd
, "%%");
1438 address_word p
= *ap
++;
1440 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1441 sim_io_printf(sd
, "%c", ch
);
1444 sim_io_printf(sd
,"(null)");
1447 sim_io_printf (sd
, "%c", (int)*ap
++);
1452 sim_read (sd
, s
++, &c
, 1);
1456 sim_read (sd
, s
++, &c
, 1);
1459 if (strchr ("dobxXu", c
))
1461 word64 lv
= (word64
) *ap
++;
1463 sim_io_printf(sd
,"<binary not supported>");
1466 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1468 sim_io_printf(sd
, tmp
, lv
);
1470 sim_io_printf(sd
, tmp
, (int)lv
);
1473 else if (strchr ("eEfgG", c
))
1475 double dbl
= *(double*)(ap
++);
1476 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1477 sim_io_printf (sd
, tmp
, dbl
);
1483 sim_io_printf(sd
, "%c", c
);
1489 /* Unknown reason. */
1495 /* Store a word into memory. */
1498 store_word (SIM_DESC sd
,
1507 if ((vaddr
& 3) != 0)
1508 SignalExceptionAddressStore ();
1511 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1514 const uword64 mask
= 7;
1518 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1519 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1520 memval
= ((uword64
) val
) << (8 * byte
);
1521 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1527 /* Load a word from memory. */
1530 load_word (SIM_DESC sd
,
1535 if ((vaddr
& 3) != 0)
1537 SIM_CORE_SIGNAL (SD
, cpu
, cia
, read_map
, AccessLength_WORD
+1, vaddr
, read_transfer
, sim_core_unaligned_signal
);
1544 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1547 const uword64 mask
= 0x7;
1548 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1549 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1553 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1554 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1556 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1557 return EXTEND32 (memval
>> (8 * byte
));
1564 /* Simulate the mips16 entry and exit pseudo-instructions. These
1565 would normally be handled by the reserved instruction exception
1566 code, but for ease of simulation we just handle them directly. */
1569 mips16_entry (SIM_DESC sd
,
1574 int aregs
, sregs
, rreg
;
1577 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1580 aregs
= (insn
& 0x700) >> 8;
1581 sregs
= (insn
& 0x0c0) >> 6;
1582 rreg
= (insn
& 0x020) >> 5;
1584 /* This should be checked by the caller. */
1593 /* This is the entry pseudo-instruction. */
1595 for (i
= 0; i
< aregs
; i
++)
1596 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1604 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1607 for (i
= 0; i
< sregs
; i
++)
1610 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1618 /* This is the exit pseudo-instruction. */
1625 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1628 for (i
= 0; i
< sregs
; i
++)
1631 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1636 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1640 FGR
[0] = WORD64LO (GPR
[4]);
1641 FPR_STATE
[0] = fmt_uninterpreted
;
1643 else if (aregs
== 6)
1645 FGR
[0] = WORD64LO (GPR
[5]);
1646 FGR
[1] = WORD64LO (GPR
[4]);
1647 FPR_STATE
[0] = fmt_uninterpreted
;
1648 FPR_STATE
[1] = fmt_uninterpreted
;
1657 /*-- trace support ----------------------------------------------------------*/
1659 /* The TRACE support is provided (if required) in the memory accessing
1660 routines. Since we are also providing the architecture specific
1661 features, the architecture simulation code can also deal with
1662 notifying the TRACE world of cache flushes, etc. Similarly we do
1663 not need to provide profiling support in the simulator engine,
1664 since we can sample in the instruction fetch control loop. By
1665 defining the TRACE manifest, we add tracing as a run-time
1669 /* Tracing by default produces "din" format (as required by
1670 dineroIII). Each line of such a trace file *MUST* have a din label
1671 and address field. The rest of the line is ignored, so comments can
1672 be included if desired. The first field is the label which must be
1673 one of the following values:
1678 3 escape record (treated as unknown access type)
1679 4 escape record (causes cache flush)
1681 The address field is a 32bit (lower-case) hexadecimal address
1682 value. The address should *NOT* be preceded by "0x".
1684 The size of the memory transfer is not important when dealing with
1685 cache lines (as long as no more than a cache line can be
1686 transferred in a single operation :-), however more information
1687 could be given following the dineroIII requirement to allow more
1688 complete memory and cache simulators to provide better
1689 results. i.e. the University of Pisa has a cache simulator that can
1690 also take bus size and speed as (variable) inputs to calculate
1691 complete system performance (a much more useful ability when trying
1692 to construct an end product, rather than a processor). They
1693 currently have an ARM version of their tool called ChARM. */
1697 dotrace (SIM_DESC sd
,
1705 if (STATE
& simTRACE
) {
1707 fprintf(tracefh
,"%d %s ; width %d ; ",
1711 va_start(ap
,comment
);
1712 vfprintf(tracefh
,comment
,ap
);
1714 fprintf(tracefh
,"\n");
1716 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1717 we may be generating 64bit ones, we should put the hi-32bits of the
1718 address into the comment field. */
1720 /* TODO: Provide a buffer for the trace lines. We can then avoid
1721 performing writes until the buffer is filled, or the file is
1724 /* NOTE: We could consider adding a comment field to the "din" file
1725 produced using type 3 markers (unknown access). This would then
1726 allow information about the program that the "din" is for, and
1727 the MIPs world that was being simulated, to be placed into the
1734 /*---------------------------------------------------------------------------*/
1735 /*-- simulator engine -------------------------------------------------------*/
1736 /*---------------------------------------------------------------------------*/
1739 ColdReset (SIM_DESC sd
)
1742 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1744 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1745 /* RESET: Fixed PC address: */
1746 PC
= (unsigned_word
) UNSIGNED64 (0xFFFFFFFFBFC00000);
1747 /* The reset vector address is in the unmapped, uncached memory space. */
1749 SR
&= ~(status_SR
| status_TS
| status_RP
);
1750 SR
|= (status_ERL
| status_BEV
);
1752 /* Cheat and allow access to the complete register set immediately */
1753 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1754 && WITH_TARGET_WORD_BITSIZE
== 64)
1755 SR
|= status_FR
; /* 64bit registers */
1757 /* Ensure that any instructions with pending register updates are
1759 PENDING_INVALIDATE();
1761 /* Initialise the FPU registers to the unknown state */
1762 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1765 for (rn
= 0; (rn
< 32); rn
++)
1766 FPR_STATE
[rn
] = fmt_uninterpreted
;
1769 /* Initialise the Config0 register. */
1770 C0_CONFIG
= 0x80000000 /* Config1 present */
1771 | 2; /* KSEG0 uncached */
1772 if (WITH_TARGET_WORD_BITSIZE
== 64)
1774 /* FIXME Currently mips/sim-main.c:address_translation()
1775 truncates all addresses to 32-bits. */
1776 if (0 && WITH_TARGET_ADDRESS_BITSIZE
== 64)
1777 C0_CONFIG
|= (2 << 13); /* MIPS64, 64-bit addresses */
1779 C0_CONFIG
|= (1 << 13); /* MIPS64, 32-bit addresses */
1782 C0_CONFIG
|= 0x00008000; /* Big Endian */
1789 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1790 /* Signal an exception condition. This will result in an exception
1791 that aborts the instruction. The instruction operation pseudocode
1792 will never see a return from this function call. */
1795 signal_exception (SIM_DESC sd
,
1803 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1806 /* Ensure that any active atomic read/modify/write operation will fail: */
1809 /* Save registers before interrupt dispatching */
1810 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1811 SIM_CPU_EXCEPTION_TRIGGER(sd
, cpu
, cia
);
1814 switch (exception
) {
1816 case DebugBreakPoint
:
1817 if (! (Debug
& Debug_DM
))
1823 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1824 DEPC
= cia
- 4; /* reference the branch instruction */
1828 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1832 Debug
|= Debug_DM
; /* in debugging mode */
1833 Debug
|= Debug_DBp
; /* raising a DBp exception */
1835 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1839 case ReservedInstruction
:
1842 unsigned int instruction
;
1843 va_start(ap
,exception
);
1844 instruction
= va_arg(ap
,unsigned int);
1846 /* Provide simple monitor support using ReservedInstruction
1847 exceptions. The following code simulates the fixed vector
1848 entry points into the IDT monitor by causing a simulator
1849 trap, performing the monitor operation, and returning to
1850 the address held in the $ra register (standard PCS return
1851 address). This means we only need to pre-load the vector
1852 space with suitable instruction values. For systems were
1853 actual trap instructions are used, we would not need to
1854 perform this magic. */
1855 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1857 int reason
= (instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
;
1858 if (!sim_monitor (SD
, CPU
, cia
, reason
))
1859 sim_io_error (sd
, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason
, pr_addr (cia
));
1861 /* NOTE: This assumes that a branch-and-link style
1862 instruction was used to enter the vector (which is the
1863 case with the current IDT monitor). */
1864 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1866 /* Look for the mips16 entry and exit instructions, and
1867 simulate a handler for them. */
1868 else if ((cia
& 1) != 0
1869 && (instruction
& 0xf81f) == 0xe809
1870 && (instruction
& 0x0c0) != 0x0c0)
1872 mips16_entry (SD
, CPU
, cia
, instruction
);
1873 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1875 /* else fall through to normal exception processing */
1876 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1880 /* Store exception code into current exception id variable (used
1883 /* TODO: If not simulating exceptions then stop the simulator
1884 execution. At the moment we always stop the simulation. */
1886 #ifdef SUBTARGET_R3900
1887 /* update interrupt-related registers */
1889 /* insert exception code in bits 6:2 */
1890 CAUSE
= LSMASKED32(CAUSE
, 31, 7) | LSINSERTED32(exception
, 6, 2);
1891 /* shift IE/KU history bits left */
1892 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 3, 0), 5, 2);
1894 if (STATE
& simDELAYSLOT
)
1896 STATE
&= ~simDELAYSLOT
;
1898 EPC
= (cia
- 4); /* reference the branch instruction */
1903 if (SR
& status_BEV
)
1904 PC
= (signed)0xBFC00000 + 0x180;
1906 PC
= (signed)0x80000000 + 0x080;
1908 /* See figure 5-17 for an outline of the code below */
1909 if (! (SR
& status_EXL
))
1911 CAUSE
= (exception
<< 2);
1912 if (STATE
& simDELAYSLOT
)
1914 STATE
&= ~simDELAYSLOT
;
1916 EPC
= (cia
- 4); /* reference the branch instruction */
1920 /* FIXME: TLB et.al. */
1921 /* vector = 0x180; */
1925 CAUSE
= (exception
<< 2);
1926 /* vector = 0x180; */
1929 /* Store exception code into current exception id variable (used
1932 if (SR
& status_BEV
)
1933 PC
= (signed)0xBFC00200 + 0x180;
1935 PC
= (signed)0x80000000 + 0x180;
1938 switch ((CAUSE
>> 2) & 0x1F)
1941 /* Interrupts arrive during event processing, no need to
1947 #ifdef SUBTARGET_3900
1948 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1949 PC
= (signed)0xBFC00000;
1950 #endif /* SUBTARGET_3900 */
1953 case TLBModification
:
1958 case InstructionFetch
:
1960 /* The following is so that the simulator will continue from the
1961 exception handler address. */
1962 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1963 sim_stopped
, SIM_SIGBUS
);
1965 case ReservedInstruction
:
1966 case CoProcessorUnusable
:
1968 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1969 sim_stopped
, SIM_SIGILL
);
1971 case IntegerOverflow
:
1973 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1974 sim_stopped
, SIM_SIGFPE
);
1977 sim_engine_halt (SD
, CPU
, NULL
, PC
, sim_stopped
, SIM_SIGTRAP
);
1982 sim_engine_restart (SD
, CPU
, NULL
, PC
);
1987 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1988 sim_stopped
, SIM_SIGTRAP
);
1990 default: /* Unknown internal exception */
1992 sim_engine_halt (SD
, CPU
, NULL
, PC
,
1993 sim_stopped
, SIM_SIGABRT
);
1997 case SimulatorFault
:
2001 va_start(ap
,exception
);
2002 msg
= va_arg(ap
,char *);
2004 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2005 "FATAL: Simulator error \"%s\"\n",msg
);
2014 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2015 "UNPREDICTABLE" behaviour.
2017 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2018 may vary from processor implementation to processor implementation,
2019 instruction to instruction, or as a function of time on the same
2020 implementation or instruction. Software can never depend on results
2021 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2022 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2025 For UNPREDICTABLE behaviour, we print a message, if possible print
2026 the offending instructions mips.igen instruction name (provided by
2027 the caller), and stop the simulator.
2029 XXX FIXME: eventually, stopping the simulator should be made conditional
2030 on a command-line option. */
2032 unpredictable_action(sim_cpu
*cpu
, address_word cia
)
2034 SIM_DESC sd
= CPU_STATE(cpu
);
2036 sim_io_eprintf(sd
, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia
));
2037 sim_engine_halt (SD
, CPU
, NULL
, cia
, sim_stopped
, SIM_SIGABRT
);
2041 /*-- co-processor support routines ------------------------------------------*/
2044 CoProcPresent(unsigned int coproc_number
)
2046 /* Return TRUE if simulator provides a model for the given co-processor number */
2051 cop_lw (SIM_DESC sd
,
2056 unsigned int memword
)
2061 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2064 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2066 StoreFPR(coproc_reg
,fmt_uninterpreted_32
,(uword64
)memword
);
2071 #if 0 /* this should be controlled by a configuration option */
2072 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2081 cop_ld (SIM_DESC sd
,
2090 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num
, coproc_reg
, pr_uword64(memword
), pr_addr(cia
) );
2093 switch (coproc_num
) {
2095 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2097 StoreFPR(coproc_reg
,fmt_uninterpreted_64
,memword
);
2102 #if 0 /* this message should be controlled by a configuration option */
2103 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2115 cop_sw (SIM_DESC sd
,
2121 unsigned int value
= 0;
2126 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2128 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted_32
);
2133 #if 0 /* should be controlled by configuration option */
2134 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2143 cop_sd (SIM_DESC sd
,
2153 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2155 value
= ValueFPR(coproc_reg
,fmt_uninterpreted_64
);
2160 #if 0 /* should be controlled by configuration option */
2161 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2173 decode_coproc (SIM_DESC sd
,
2176 unsigned int instruction
)
2178 int coprocnum
= ((instruction
>> 26) & 3);
2182 case 0: /* standard CPU control and cache registers */
2184 int code
= ((instruction
>> 21) & 0x1F);
2185 int rt
= ((instruction
>> 16) & 0x1F);
2186 int rd
= ((instruction
>> 11) & 0x1F);
2187 int tail
= instruction
& 0x3ff;
2188 /* R4000 Users Manual (second edition) lists the following CP0
2190 CODE><-RT><RD-><--TAIL--->
2191 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2192 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2193 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2194 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2195 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2196 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2197 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2198 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2199 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2200 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2202 if (((code
== 0x00) || (code
== 0x04) /* MFC0 / MTC0 */
2203 || (code
== 0x01) || (code
== 0x05)) /* DMFC0 / DMTC0 */
2206 /* Clear double/single coprocessor move bit. */
2209 /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
2211 switch (rd
) /* NOTEs: Standard CP0 registers */
2213 /* 0 = Index R4000 VR4100 VR4300 */
2214 /* 1 = Random R4000 VR4100 VR4300 */
2215 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2216 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2217 /* 4 = Context R4000 VR4100 VR4300 */
2218 /* 5 = PageMask R4000 VR4100 VR4300 */
2219 /* 6 = Wired R4000 VR4100 VR4300 */
2220 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2221 /* 9 = Count R4000 VR4100 VR4300 */
2222 /* 10 = EntryHi R4000 VR4100 VR4300 */
2223 /* 11 = Compare R4000 VR4100 VR4300 */
2224 /* 12 = SR R4000 VR4100 VR4300 */
2225 #ifdef SUBTARGET_R3900
2227 /* 3 = Config R3900 */
2229 /* 7 = Cache R3900 */
2231 /* 15 = PRID R3900 */
2237 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2239 GPR
[rt
] = (signed_word
) (signed_address
) COP0_BADVADDR
;
2241 COP0_BADVADDR
= GPR
[rt
];
2244 #endif /* SUBTARGET_R3900 */
2251 /* 13 = Cause R4000 VR4100 VR4300 */
2258 /* 14 = EPC R4000 VR4100 VR4300 */
2261 GPR
[rt
] = (signed_word
) (signed_address
) EPC
;
2265 /* 15 = PRId R4000 VR4100 VR4300 */
2266 #ifdef SUBTARGET_R3900
2275 /* 16 = Config R4000 VR4100 VR4300 */
2278 GPR
[rt
] = C0_CONFIG
;
2280 /* only bottom three bits are writable */
2281 C0_CONFIG
= (C0_CONFIG
& ~0x7) | (GPR
[rt
] & 0x7);
2284 #ifdef SUBTARGET_R3900
2293 /* 17 = LLAddr R4000 VR4100 VR4300 */
2295 /* 18 = WatchLo R4000 VR4100 VR4300 */
2296 /* 19 = WatchHi R4000 VR4100 VR4300 */
2297 /* 20 = XContext R4000 VR4100 VR4300 */
2298 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2299 /* 27 = CacheErr R4000 VR4100 */
2300 /* 28 = TagLo R4000 VR4100 VR4300 */
2301 /* 29 = TagHi R4000 VR4100 VR4300 */
2302 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2303 if (STATE_VERBOSE_P(SD
))
2305 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2306 (unsigned long)cia
);
2307 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
2308 /* CPR[0,rd] = GPR[rt]; */
2311 GPR
[rt
] = (signed_word
) (signed32
) COP0_GPR
[rd
];
2313 COP0_GPR
[rd
] = GPR
[rt
];
2316 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
2318 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt
,rd
, (unsigned)cia
);
2322 else if ((code
== 0x00 || code
== 0x01)
2325 /* [D]MFC0 RT,C0_CONFIG,SEL */
2327 switch (tail
& 0x07)
2333 /* MIPS32 r/o Config1:
2336 /* MIPS16 implemented.
2337 XXX How to check configuration? */
2339 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2340 /* MDMX & FPU implemented */
2344 /* MIPS32 r/o Config2:
2349 /* MIPS32 r/o Config3:
2350 SmartMIPS implemented. */
2356 else if (code
== 0x10 && (tail
& 0x3f) == 0x18)
2359 if (SR
& status_ERL
)
2361 /* Oops, not yet available */
2362 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
2372 else if (code
== 0x10 && (tail
& 0x3f) == 0x10)
2375 #ifdef SUBTARGET_R3900
2376 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2378 /* shift IE/KU history bits right */
2379 SR
= LSMASKED32(SR
, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR
, 5, 2), 3, 0);
2381 /* TODO: CACHE register */
2382 #endif /* SUBTARGET_R3900 */
2384 else if (code
== 0x10 && (tail
& 0x3f) == 0x1F)
2392 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
2393 /* TODO: When executing an ERET or RFE instruction we should
2394 clear LLBIT, to ensure that any out-standing atomic
2395 read/modify/write sequence fails. */
2399 case 2: /* co-processor 2 */
2406 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2407 instruction
,pr_addr(cia
));
2412 case 1: /* should not occur (FPU co-processor) */
2413 case 3: /* should not occur (FPU co-processor) */
2414 SignalException(ReservedInstruction
,instruction
);
2422 /* This code copied from gdb's utils.c. Would like to share this code,
2423 but don't know of a common place where both could get to it. */
2425 /* Temporary storage using circular buffer */
2431 static char buf
[NUMCELLS
][CELLSIZE
];
2433 if (++cell
>=NUMCELLS
) cell
=0;
2437 /* Print routines to handle variable size regs, etc */
2439 /* Eliminate warning from compiler on 32-bit systems */
2440 static int thirty_two
= 32;
2443 pr_addr (SIM_ADDR addr
)
2445 char *paddr_str
=get_cell();
2446 switch (sizeof(addr
))
2449 sprintf(paddr_str
,"%08lx%08lx",
2450 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
2453 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
2456 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
2459 sprintf(paddr_str
,"%x",addr
);
2465 pr_uword64 (uword64 addr
)
2467 char *paddr_str
=get_cell();
2468 sprintf(paddr_str
,"%08lx%08lx",
2469 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
2475 mips_core_signal (SIM_DESC sd
,
2481 transfer_type transfer
,
2482 sim_core_signals sig
)
2484 const char *copy
= (transfer
== read_transfer
? "read" : "write");
2485 address_word ip
= CIA_ADDR (cia
);
2489 case sim_core_unmapped_signal
:
2490 sim_io_eprintf (sd
, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2492 (unsigned long) addr
, (unsigned long) ip
);
2493 COP0_BADVADDR
= addr
;
2494 SignalExceptionDataReference();
2497 case sim_core_unaligned_signal
:
2498 sim_io_eprintf (sd
, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2500 (unsigned long) addr
, (unsigned long) ip
);
2501 COP0_BADVADDR
= addr
;
2502 if(transfer
== read_transfer
)
2503 SignalExceptionAddressLoad();
2505 SignalExceptionAddressStore();
2509 sim_engine_abort (sd
, cpu
, cia
,
2510 "mips_core_signal - internal error - bad switch");
2516 mips_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word cia
)
2518 ASSERT(cpu
!= NULL
);
2520 if(cpu
->exc_suspended
> 0)
2521 sim_io_eprintf(sd
, "Warning, nested exception triggered (%d)\n", cpu
->exc_suspended
);
2524 memcpy(cpu
->exc_trigger_registers
, cpu
->registers
, sizeof(cpu
->exc_trigger_registers
));
2525 cpu
->exc_suspended
= 0;
2529 mips_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
2531 ASSERT(cpu
!= NULL
);
2533 if(cpu
->exc_suspended
> 0)
2534 sim_io_eprintf(sd
, "Warning, nested exception signal (%d then %d)\n",
2535 cpu
->exc_suspended
, exception
);
2537 memcpy(cpu
->exc_suspend_registers
, cpu
->registers
, sizeof(cpu
->exc_suspend_registers
));
2538 memcpy(cpu
->registers
, cpu
->exc_trigger_registers
, sizeof(cpu
->registers
));
2539 cpu
->exc_suspended
= exception
;
2543 mips_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
2545 ASSERT(cpu
!= NULL
);
2547 if(exception
== 0 && cpu
->exc_suspended
> 0)
2549 /* warn not for breakpoints */
2550 if(cpu
->exc_suspended
!= sim_signal_to_host(sd
, SIM_SIGTRAP
))
2551 sim_io_eprintf(sd
, "Warning, resuming but ignoring pending exception signal (%d)\n",
2552 cpu
->exc_suspended
);
2554 else if(exception
!= 0 && cpu
->exc_suspended
> 0)
2556 if(exception
!= cpu
->exc_suspended
)
2557 sim_io_eprintf(sd
, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2558 cpu
->exc_suspended
, exception
);
2560 memcpy(cpu
->registers
, cpu
->exc_suspend_registers
, sizeof(cpu
->registers
));
2562 else if(exception
!= 0 && cpu
->exc_suspended
== 0)
2564 sim_io_eprintf(sd
, "Warning, ignoring spontanous exception signal (%d)\n", exception
);
2566 cpu
->exc_suspended
= 0;
2570 /*---------------------------------------------------------------------------*/
2571 /*> EOF interp.c <*/