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sim: mips: Add shadow mappings for 32-bit memory address space
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 NOTEs:
17
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
21 code on the hardware.
22
23 */
24
25 /* This must come before any other includes. */
26 #include "defs.h"
27
28 #include "bfd.h"
29 #include "sim-main.h"
30 #include "sim-utils.h"
31 #include "sim-options.h"
32 #include "sim-assert.h"
33 #include "sim-hw.h"
34
35 #include "itable.h"
36
37 #include <stdio.h>
38 #include <stdarg.h>
39 #include <ansidecl.h>
40 #include <ctype.h>
41 #include <limits.h>
42 #include <math.h>
43 #include <stdlib.h>
44 #include <string.h>
45
46 #include "getopt.h"
47 #include "libiberty.h"
48 #include "bfd.h"
49 #include "elf-bfd.h"
50 #include "sim/callback.h" /* GDB simulator callback interface */
51 #include "sim/sim.h" /* GDB simulator interface */
52 #include "sim-syscall.h" /* Simulator system call support */
53
54 char* pr_addr (SIM_ADDR addr);
55 char* pr_uword64 (uword64 addr);
56
57
58 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
59 #define CPU cpu
60 #define SD sd
61
62
63 /* The following reserved instruction value is used when a simulator
64 trap is required. NOTE: Care must be taken, since this value may be
65 used in later revisions of the MIPS ISA. */
66
67 #define RSVD_INSTRUCTION (0x00000039)
68 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
69
70 #define RSVD_INSTRUCTION_ARG_SHIFT 6
71 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
72
73
74 /* Bits in the Debug register */
75 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
76 #define Debug_DM 0x40000000 /* Debug Mode */
77 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
78
79 /*---------------------------------------------------------------------------*/
80 /*-- GDB simulator interface ------------------------------------------------*/
81 /*---------------------------------------------------------------------------*/
82
83 static void ColdReset (SIM_DESC sd);
84
85 /*---------------------------------------------------------------------------*/
86
87
88
89 #define DELAYSLOT() {\
90 if (STATE & simDELAYSLOT)\
91 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
92 STATE |= simDELAYSLOT;\
93 }
94
95 #define JALDELAYSLOT() {\
96 DELAYSLOT ();\
97 STATE |= simJALDELAYSLOT;\
98 }
99
100 #define NULLIFY() {\
101 STATE &= ~simDELAYSLOT;\
102 STATE |= simSKIPNEXT;\
103 }
104
105 #define CANCELDELAYSLOT() {\
106 DSSTATE = 0;\
107 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
108 }
109
110 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
111 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
112
113 /* Note that the monitor code essentially assumes this layout of memory.
114 If you change these, change the monitor code, too. */
115 /* FIXME Currently addresses are truncated to 32-bits, see
116 mips/sim-main.c:address_translation(). If that changes, then these
117 values will need to be extended, and tested for more carefully. */
118 #define K0BASE (0x80000000)
119 #define K0SIZE (0x20000000)
120 #define K1BASE (0xA0000000)
121 #define K1SIZE (0x20000000)
122
123 /* Simple run-time monitor support.
124
125 We emulate the monitor by placing magic reserved instructions at
126 the monitor's entry points; when we hit these instructions, instead
127 of raising an exception (as we would normally), we look at the
128 instruction and perform the appropriate monitory operation.
129
130 `*_monitor_base' are the physical addresses at which the corresponding
131 monitor vectors are located. `0' means none. By default,
132 install all three.
133 The RSVD_INSTRUCTION... macros specify the magic instructions we
134 use at the monitor entry points. */
135 static int firmware_option_p = 0;
136 static SIM_ADDR idt_monitor_base = 0xBFC00000;
137 static SIM_ADDR pmon_monitor_base = 0xBFC00500;
138 static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
139
140 static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
141
142 #define MEM_SIZE (8 << 20) /* 8 MBytes */
143
144
145 #if WITH_TRACE_ANY_P
146 static char *tracefile = "trace.din"; /* default filename for trace log */
147 FILE *tracefh = NULL;
148 static void open_trace (SIM_DESC sd);
149 #else
150 #define open_trace(sd)
151 #endif
152
153 static const char * get_insn_name (sim_cpu *, int);
154
155 /* simulation target board. NULL=canonical */
156 static char* board = NULL;
157
158
159 static DECLARE_OPTION_HANDLER (mips_option_handler);
160
161 enum {
162 OPTION_DINERO_TRACE = OPTION_START,
163 OPTION_DINERO_FILE,
164 OPTION_FIRMWARE,
165 OPTION_INFO_MEMORY,
166 OPTION_BOARD
167 };
168
169 static int display_mem_info = 0;
170
171 static SIM_RC
172 mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
173 int is_command)
174 {
175 int cpu_nr;
176 switch (opt)
177 {
178 case OPTION_DINERO_TRACE: /* ??? */
179 #if WITH_TRACE_ANY_P
180 /* Eventually the simTRACE flag could be treated as a toggle, to
181 allow external control of the program points being traced
182 (i.e. only from main onwards, excluding the run-time setup,
183 etc.). */
184 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
185 {
186 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
187 if (arg == NULL)
188 STATE |= simTRACE;
189 else if (strcmp (arg, "yes") == 0)
190 STATE |= simTRACE;
191 else if (strcmp (arg, "no") == 0)
192 STATE &= ~simTRACE;
193 else if (strcmp (arg, "on") == 0)
194 STATE |= simTRACE;
195 else if (strcmp (arg, "off") == 0)
196 STATE &= ~simTRACE;
197 else
198 {
199 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
200 return SIM_RC_FAIL;
201 }
202 }
203 return SIM_RC_OK;
204 #else /* !WITH_TRACE_ANY_P */
205 fprintf(stderr,"\
206 Simulator constructed without dinero tracing support (for performance).\n\
207 Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
208 return SIM_RC_FAIL;
209 #endif /* !WITH_TRACE_ANY_P */
210
211 case OPTION_DINERO_FILE:
212 #if WITH_TRACE_ANY_P
213 if (optarg != NULL) {
214 char *tmp;
215 tmp = (char *)malloc(strlen(optarg) + 1);
216 if (tmp == NULL)
217 {
218 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
219 return SIM_RC_FAIL;
220 }
221 else {
222 strcpy(tmp,optarg);
223 tracefile = tmp;
224 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
225 }
226 }
227 #endif /* WITH_TRACE_ANY_P */
228 return SIM_RC_OK;
229
230 case OPTION_FIRMWARE:
231 return sim_firmware_command (sd, arg);
232
233 case OPTION_BOARD:
234 {
235 if (arg)
236 {
237 board = zalloc(strlen(arg) + 1);
238 strcpy(board, arg);
239 }
240 return SIM_RC_OK;
241 }
242
243 case OPTION_INFO_MEMORY:
244 display_mem_info = 1;
245 break;
246 }
247
248 return SIM_RC_OK;
249 }
250
251
252 static const OPTION mips_options[] =
253 {
254 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
255 '\0', "on|off", "Enable dinero tracing",
256 mips_option_handler },
257 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
258 '\0', "FILE", "Write dinero trace to FILE",
259 mips_option_handler },
260 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
261 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
262 mips_option_handler },
263 { {"board", required_argument, NULL, OPTION_BOARD},
264 '\0', "none" /* rely on compile-time string concatenation for other options */
265
266 #define BOARD_JMR3904 "jmr3904"
267 "|" BOARD_JMR3904
268 #define BOARD_JMR3904_PAL "jmr3904pal"
269 "|" BOARD_JMR3904_PAL
270 #define BOARD_JMR3904_DEBUG "jmr3904debug"
271 "|" BOARD_JMR3904_DEBUG
272 #define BOARD_BSP "bsp"
273 "|" BOARD_BSP
274
275 , "Customize simulation for a particular board.", mips_option_handler },
276
277 /* These next two options have the same names as ones found in the
278 memory_options[] array in common/sim-memopt.c. This is because
279 the intention is to provide an alternative handler for those two
280 options. We need an alternative handler because the memory
281 regions are not set up until after the command line arguments
282 have been parsed, and so we cannot display the memory info whilst
283 processing the command line. There is a hack in sim_open to
284 remove these handlers when we want the real --memory-info option
285 to work. */
286 { { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
287 '\0', NULL, "List configured memory regions", mips_option_handler },
288 { { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
289 '\0', NULL, NULL, mips_option_handler },
290
291 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
292 };
293
294
295 int interrupt_pending;
296
297 void
298 interrupt_event (SIM_DESC sd, void *data)
299 {
300 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
301 address_word cia = CPU_PC_GET (cpu);
302 if (SR & status_IE)
303 {
304 interrupt_pending = 0;
305 SignalExceptionInterrupt (1); /* interrupt "1" */
306 }
307 else if (!interrupt_pending)
308 sim_events_schedule (sd, 1, interrupt_event, data);
309 }
310
311
312 /*---------------------------------------------------------------------------*/
313 /*-- Device registration hook -----------------------------------------------*/
314 /*---------------------------------------------------------------------------*/
315 static void device_init(SIM_DESC sd) {
316 #ifdef DEVICE_INIT
317 extern void register_devices(SIM_DESC);
318 register_devices(sd);
319 #endif
320 }
321
322 /*---------------------------------------------------------------------------*/
323 /*-- GDB simulator interface ------------------------------------------------*/
324 /*---------------------------------------------------------------------------*/
325
326 static sim_cia
327 mips_pc_get (sim_cpu *cpu)
328 {
329 return PC;
330 }
331
332 static void
333 mips_pc_set (sim_cpu *cpu, sim_cia pc)
334 {
335 PC = pc;
336 }
337
338 static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
339 static int mips_reg_store (SIM_CPU *, int, unsigned char *, int);
340
341 SIM_DESC
342 sim_open (SIM_OPEN_KIND kind, host_callback *cb,
343 struct bfd *abfd, char * const *argv)
344 {
345 int i;
346 SIM_DESC sd = sim_state_alloc_extra (kind, cb,
347 sizeof (struct mips_sim_state));
348 sim_cpu *cpu;
349
350 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
351
352 /* The cpu data is kept in a separately allocated chunk of memory. */
353 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
354 return 0;
355
356 cpu = STATE_CPU (sd, 0); /* FIXME */
357
358 /* FIXME: watchpoints code shouldn't need this */
359 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
360
361 /* Initialize the mechanism for doing insn profiling. */
362 CPU_INSN_NAME (cpu) = get_insn_name;
363 CPU_MAX_INSNS (cpu) = nr_itable_entries;
364
365 STATE = 0;
366
367 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
368 return 0;
369 sim_add_option_table (sd, NULL, mips_options);
370
371
372 /* The parser will print an error message for us, so we silently return. */
373 if (sim_parse_args (sd, argv) != SIM_RC_OK)
374 {
375 /* Uninstall the modules to avoid memory leaks,
376 file descriptor leaks, etc. */
377 sim_module_uninstall (sd);
378 return 0;
379 }
380
381 /* handle board-specific memory maps */
382 if (board == NULL)
383 {
384 /* Allocate core managed memory */
385 sim_memopt *entry, *match = NULL;
386 address_word mem_size = 0;
387 int mapped = 0;
388
389 /* For compatibility with the old code - under this (at level one)
390 are the kernel spaces K0 & K1. Both of these map to a single
391 smaller sub region */
392 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
393
394 /* Look for largest memory region defined on command-line at
395 phys address 0. */
396 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
397 {
398 /* If we find an entry at address 0, then we will end up
399 allocating a new buffer in the "memory alias" command
400 below. The region at address 0 will be deleted. */
401 address_word size = (entry->modulo != 0
402 ? entry->modulo : entry->nr_bytes);
403 if (entry->addr == 0
404 && (!match || entry->level < match->level))
405 match = entry;
406 else if (entry->addr == K0BASE || entry->addr == K1BASE)
407 mapped = 1;
408 else
409 {
410 sim_memopt *alias;
411 for (alias = entry->alias; alias != NULL; alias = alias->next)
412 {
413 if (alias->addr == 0
414 && (!match || entry->level < match->level))
415 match = entry;
416 else if (alias->addr == K0BASE || alias->addr == K1BASE)
417 mapped = 1;
418 }
419 }
420 }
421
422 if (!mapped)
423 {
424 if (match)
425 {
426 /* Get existing memory region size. */
427 mem_size = (match->modulo != 0
428 ? match->modulo : match->nr_bytes);
429 /* Delete old region. */
430 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
431 match->space, match->addr, match->level);
432 }
433 else if (mem_size == 0)
434 mem_size = MEM_SIZE;
435 /* Limit to KSEG1 size (512MB) */
436 if (mem_size > K1SIZE)
437 mem_size = K1SIZE;
438 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
439 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
440 K1BASE, K1SIZE, (long)mem_size, K0BASE);
441 if (WITH_TARGET_WORD_BITSIZE == 64)
442 sim_do_commandf (sd, "memory alias 0x%x,0x%" PRIxTW ",0x%" PRIxTA,
443 (K0BASE), mem_size, EXTENDED(K0BASE));
444 }
445
446 device_init(sd);
447 }
448 else if (board != NULL
449 && (strcmp(board, BOARD_BSP) == 0))
450 {
451 int i;
452
453 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
454
455 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
456 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
457 0x9FC00000,
458 4 * 1024 * 1024, /* 4 MB */
459 0xBFC00000);
460
461 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
462 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
463 0x80000000,
464 4 * 1024 * 1024, /* 4 MB */
465 0xA0000000);
466
467 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
468 for (i=0; i<8; i++) /* 32 MB total */
469 {
470 unsigned size = 4 * 1024 * 1024; /* 4 MB */
471 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
472 0x88000000 + (i * size),
473 size,
474 0xA8000000 + (i * size));
475 }
476 }
477 #if (WITH_HW)
478 else if (board != NULL
479 && (strcmp(board, BOARD_JMR3904) == 0 ||
480 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
481 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
482 {
483 /* match VIRTUAL memory layout of JMR-TX3904 board */
484 int i;
485
486 /* --- disable monitor unless forced on by user --- */
487
488 if (! firmware_option_p)
489 {
490 idt_monitor_base = 0;
491 pmon_monitor_base = 0;
492 lsipmon_monitor_base = 0;
493 }
494
495 /* --- environment --- */
496
497 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
498
499 /* --- memory --- */
500
501 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
502 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
503 0x9FC00000,
504 4 * 1024 * 1024, /* 4 MB */
505 0xBFC00000);
506
507 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
508 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
509 0x80000000,
510 4 * 1024 * 1024, /* 4 MB */
511 0xA0000000);
512
513 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
514 for (i=0; i<8; i++) /* 32 MB total */
515 {
516 unsigned size = 4 * 1024 * 1024; /* 4 MB */
517 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
518 0x88000000 + (i * size),
519 size,
520 0xA8000000 + (i * size));
521 }
522
523 /* Dummy memory regions for unsimulated devices - sorted by address */
524
525 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
526 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
527 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
528 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
529 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
530 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
531 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
532 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
533 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
534
535
536 /* --- simulated devices --- */
537 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
538 sim_hw_parse (sd, "/tx3904cpu");
539 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
540 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
541 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
542 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
543 {
544 /* FIXME: poking at dv-sockser internals, use tcp backend if
545 --sockser_addr option was given.*/
546 extern char* sockser_addr;
547 if(sockser_addr == NULL)
548 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
549 else
550 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
551 }
552 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
553 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
554
555 /* -- device connections --- */
556 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
557 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
558 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
559 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
560 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
561 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
562
563 /* add PAL timer & I/O module */
564 if(! strcmp(board, BOARD_JMR3904_PAL))
565 {
566 /* the device */
567 sim_hw_parse (sd, "/pal@0xffff0000");
568 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
569
570 /* wire up interrupt ports to irc */
571 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
572 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
573 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
574 }
575
576 if(! strcmp(board, BOARD_JMR3904_DEBUG))
577 {
578 /* -- DEBUG: glue interrupt generators --- */
579 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
580 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
581 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
582 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
583 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
584 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
585 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
586 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
587 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
588 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
589 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
590 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
591 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
592 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
593 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
594 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
595 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
596 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
597 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
598 }
599
600 device_init(sd);
601 }
602 #endif
603
604 if (display_mem_info)
605 {
606 struct option_list * ol;
607 struct option_list * prev;
608
609 /* This is a hack. We want to execute the real --memory-info command
610 line switch which is handled in common/sim-memopts.c, not the
611 override we have defined in this file. So we remove the
612 mips_options array from the state options list. This is safe
613 because we have now processed all of the command line. */
614 for (ol = STATE_OPTIONS (sd), prev = NULL;
615 ol != NULL;
616 prev = ol, ol = ol->next)
617 if (ol->options == mips_options)
618 break;
619
620 SIM_ASSERT (ol != NULL);
621
622 if (prev == NULL)
623 STATE_OPTIONS (sd) = ol->next;
624 else
625 prev->next = ol->next;
626
627 sim_do_commandf (sd, "memory-info");
628 }
629
630 /* check for/establish the a reference program image */
631 if (sim_analyze_program (sd,
632 (STATE_PROG_ARGV (sd) != NULL
633 ? *STATE_PROG_ARGV (sd)
634 : NULL),
635 abfd) != SIM_RC_OK)
636 {
637 sim_module_uninstall (sd);
638 return 0;
639 }
640
641 /* Configure/verify the target byte order and other runtime
642 configuration options */
643 if (sim_config (sd) != SIM_RC_OK)
644 {
645 sim_module_uninstall (sd);
646 return 0;
647 }
648
649 if (sim_post_argv_init (sd) != SIM_RC_OK)
650 {
651 /* Uninstall the modules to avoid memory leaks,
652 file descriptor leaks, etc. */
653 sim_module_uninstall (sd);
654 return 0;
655 }
656
657 /* verify assumptions the simulator made about the host type system.
658 This macro does not return if there is a problem */
659 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
660 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
661
662 /* This is NASTY, in that we are assuming the size of specific
663 registers: */
664 {
665 int rn;
666 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
667 {
668 if (rn < 32)
669 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
670 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
671 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
672 else if ((rn >= 33) && (rn <= 37))
673 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
674 else if ((rn == SRIDX)
675 || (rn == FCR0IDX)
676 || (rn == FCR31IDX)
677 || ((rn >= 72) && (rn <= 89)))
678 cpu->register_widths[rn] = 32;
679 else
680 cpu->register_widths[rn] = 0;
681 }
682
683
684 }
685
686 if (STATE & simTRACE)
687 open_trace(sd);
688
689 /*
690 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
691 idt_monitor_base,
692 pmon_monitor_base,
693 lsipmon_monitor_base);
694 */
695
696 /* Write the monitor trap address handlers into the monitor (eeprom)
697 address space. This can only be done once the target endianness
698 has been determined. */
699 if (idt_monitor_base != 0)
700 {
701 unsigned loop;
702 address_word idt_monitor_size = 1 << 11;
703
704 /* the default monitor region */
705 if (WITH_TARGET_WORD_BITSIZE == 64)
706 sim_do_commandf (sd, "memory alias 0x%x,0x%" PRIxTW ",0x%" PRIxTA,
707 idt_monitor_base, idt_monitor_size,
708 EXTENDED (idt_monitor_base));
709 else
710 sim_do_commandf (sd, "memory region 0x%x,0x%x",
711 idt_monitor_base, idt_monitor_size);
712
713 /* Entry into the IDT monitor is via fixed address vectors, and
714 not using machine instructions. To avoid clashing with use of
715 the MIPS TRAP system, we place our own (simulator specific)
716 "undefined" instructions into the relevant vector slots. */
717 for (loop = 0; (loop < idt_monitor_size); loop += 4)
718 {
719 address_word vaddr = (idt_monitor_base + loop);
720 unsigned32 insn = (RSVD_INSTRUCTION |
721 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
722 << RSVD_INSTRUCTION_ARG_SHIFT));
723 H2T (insn);
724 sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
725 }
726 }
727
728 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
729 {
730 /* The PMON monitor uses the same address space, but rather than
731 branching into it the address of a routine is loaded. We can
732 cheat for the moment, and direct the PMON routine to IDT style
733 instructions within the monitor space. This relies on the IDT
734 monitor not using the locations from 0xBFC00500 onwards as its
735 entry points.*/
736 unsigned loop;
737 for (loop = 0; (loop < 24); loop++)
738 {
739 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
740 switch (loop)
741 {
742 case 0: /* read */
743 value = 7;
744 break;
745 case 1: /* write */
746 value = 8;
747 break;
748 case 2: /* open */
749 value = 6;
750 break;
751 case 3: /* close */
752 value = 10;
753 break;
754 case 5: /* printf */
755 value = ((0x500 - 16) / 8); /* not an IDT reason code */
756 break;
757 case 8: /* cliexit */
758 value = 17;
759 break;
760 case 11: /* flush_cache */
761 value = 28;
762 break;
763 }
764
765 SIM_ASSERT (idt_monitor_base != 0);
766 value = ((unsigned int) idt_monitor_base + (value * 8));
767 H2T (value);
768
769 if (pmon_monitor_base != 0)
770 {
771 address_word vaddr = (pmon_monitor_base + (loop * 4));
772 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
773 }
774
775 if (lsipmon_monitor_base != 0)
776 {
777 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
778 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
779 }
780 }
781
782 /* Write an abort sequence into the TRAP (common) exception vector
783 addresses. This is to catch code executing a TRAP (et.al.)
784 instruction without installing a trap handler. */
785 if ((idt_monitor_base != 0) ||
786 (pmon_monitor_base != 0) ||
787 (lsipmon_monitor_base != 0))
788 {
789 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
790 HALT_INSTRUCTION /* BREAK */ };
791 H2T (halt[0]);
792 H2T (halt[1]);
793 sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
794 sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
795 sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
796 /* XXX: Write here unconditionally? */
797 sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
798 sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
799 sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
800 }
801 }
802
803 /* CPU specific initialization. */
804 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
805 {
806 SIM_CPU *cpu = STATE_CPU (sd, i);
807
808 CPU_REG_FETCH (cpu) = mips_reg_fetch;
809 CPU_REG_STORE (cpu) = mips_reg_store;
810 CPU_PC_FETCH (cpu) = mips_pc_get;
811 CPU_PC_STORE (cpu) = mips_pc_set;
812 }
813
814 return sd;
815 }
816
817 #if WITH_TRACE_ANY_P
818 static void
819 open_trace (SIM_DESC sd)
820 {
821 tracefh = fopen(tracefile,"wb+");
822 if (tracefh == NULL)
823 {
824 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
825 tracefh = stderr;
826 }
827 }
828 #endif
829
830 /* Return name of an insn, used by insn profiling. */
831 static const char *
832 get_insn_name (sim_cpu *cpu, int i)
833 {
834 return itable[i].name;
835 }
836
837 void
838 mips_sim_close (SIM_DESC sd, int quitting)
839 {
840 #if WITH_TRACE_ANY_P
841 if (tracefh != NULL && tracefh != stderr)
842 fclose(tracefh);
843 tracefh = NULL;
844 #endif
845 }
846
847 static int
848 mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
849 {
850 /* NOTE: gdb (the client) stores registers in target byte order
851 while the simulator uses host byte order */
852
853 /* Unfortunately this suffers from the same problem as the register
854 numbering one. We need to know what the width of each logical
855 register number is for the architecture being simulated. */
856
857 if (cpu->register_widths[rn] == 0)
858 {
859 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register store ignored)\n", rn);
860 return 0;
861 }
862
863 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
864 {
865 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
866 if (cpu->register_widths[rn] == 32)
867 {
868 if (length == 8)
869 {
870 cpu->fgr[rn - FGR_BASE] =
871 (unsigned32) T2H_8 (*(unsigned64*)memory);
872 return 8;
873 }
874 else
875 {
876 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
877 return 4;
878 }
879 }
880 else
881 {
882 if (length == 8)
883 {
884 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
885 return 8;
886 }
887 else
888 {
889 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
890 return 4;
891 }
892 }
893 }
894
895 if (cpu->register_widths[rn] == 32)
896 {
897 if (length == 8)
898 {
899 cpu->registers[rn] =
900 (unsigned32) T2H_8 (*(unsigned64*)memory);
901 return 8;
902 }
903 else
904 {
905 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
906 return 4;
907 }
908 }
909 else
910 {
911 if (length == 8)
912 {
913 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
914 return 8;
915 }
916 else
917 {
918 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
919 return 4;
920 }
921 }
922
923 return 0;
924 }
925
926 static int
927 mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
928 {
929 /* NOTE: gdb (the client) stores registers in target byte order
930 while the simulator uses host byte order */
931
932 if (cpu->register_widths[rn] == 0)
933 {
934 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register fetch ignored)\n", rn);
935 return 0;
936 }
937
938 /* Any floating point register */
939 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
940 {
941 if (cpu->register_widths[rn] == 32)
942 {
943 if (length == 8)
944 {
945 *(unsigned64*)memory =
946 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
947 return 8;
948 }
949 else
950 {
951 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
952 return 4;
953 }
954 }
955 else
956 {
957 if (length == 8)
958 {
959 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
960 return 8;
961 }
962 else
963 {
964 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
965 return 4;
966 }
967 }
968 }
969
970 if (cpu->register_widths[rn] == 32)
971 {
972 if (length == 8)
973 {
974 *(unsigned64*)memory =
975 H2T_8 ((unsigned32) (cpu->registers[rn]));
976 return 8;
977 }
978 else
979 {
980 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
981 return 4;
982 }
983 }
984 else
985 {
986 if (length == 8)
987 {
988 *(unsigned64*)memory =
989 H2T_8 ((unsigned64) (cpu->registers[rn]));
990 return 8;
991 }
992 else
993 {
994 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
995 return 4;
996 }
997 }
998
999 return 0;
1000 }
1001
1002 SIM_RC
1003 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
1004 char * const *argv, char * const *env)
1005 {
1006
1007 #ifdef DEBUG
1008 #if 0 /* FIXME: doesn't compile */
1009 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1010 pr_addr(PC));
1011 #endif
1012 #endif /* DEBUG */
1013
1014 ColdReset(sd);
1015
1016 if (abfd != NULL)
1017 {
1018 /* override PC value set by ColdReset () */
1019 int cpu_nr;
1020 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1021 {
1022 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1023 sim_cia pc = bfd_get_start_address (abfd);
1024
1025 /* The 64-bit BFD sign-extends MIPS addresses to model
1026 32-bit compatibility segments with 64-bit addressing.
1027 These addresses work as is on 64-bit targets but
1028 can be truncated for 32-bit targets. */
1029 if (WITH_TARGET_WORD_BITSIZE == 32)
1030 pc = (unsigned32) pc;
1031
1032 CPU_PC_SET (cpu, pc);
1033 }
1034 }
1035
1036 #if 0 /* def DEBUG */
1037 if (argv || env)
1038 {
1039 /* We should really place the argv slot values into the argument
1040 registers, and onto the stack as required. However, this
1041 assumes that we have a stack defined, which is not
1042 necessarily true at the moment. */
1043 char **cptr;
1044 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1045 for (cptr = argv; (cptr && *cptr); cptr++)
1046 printf("DBG: arg \"%s\"\n",*cptr);
1047 }
1048 #endif /* DEBUG */
1049
1050 return SIM_RC_OK;
1051 }
1052
1053 /*---------------------------------------------------------------------------*/
1054 /*-- Private simulator support interface ------------------------------------*/
1055 /*---------------------------------------------------------------------------*/
1056
1057 /* Read a null terminated string from memory, return in a buffer */
1058 static char *
1059 fetch_str (SIM_DESC sd,
1060 address_word addr)
1061 {
1062 char *buf;
1063 int nr = 0;
1064 unsigned char null;
1065 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1066 nr++;
1067 buf = NZALLOC (char, nr + 1);
1068 sim_read (sd, addr, (unsigned char *)buf, nr);
1069 return buf;
1070 }
1071
1072
1073 /* Implements the "sim firmware" command:
1074 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1075 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1076 defaults to the normal address for that monitor.
1077 sim firmware none --- don't emulate any ROM monitor. Useful
1078 if you need a clean address space. */
1079 static SIM_RC
1080 sim_firmware_command (SIM_DESC sd, char *arg)
1081 {
1082 int address_present = 0;
1083 SIM_ADDR address;
1084
1085 /* Signal occurrence of this option. */
1086 firmware_option_p = 1;
1087
1088 /* Parse out the address, if present. */
1089 {
1090 char *p = strchr (arg, '@');
1091 if (p)
1092 {
1093 char *q;
1094 address_present = 1;
1095 p ++; /* skip over @ */
1096
1097 address = strtoul (p, &q, 0);
1098 if (*q != '\0')
1099 {
1100 sim_io_printf (sd, "Invalid address given to the"
1101 "`sim firmware NAME@ADDRESS' command: %s\n",
1102 p);
1103 return SIM_RC_FAIL;
1104 }
1105 }
1106 else
1107 {
1108 address_present = 0;
1109 address = -1; /* Dummy value. */
1110 }
1111 }
1112
1113 if (! strncmp (arg, "idt", 3))
1114 {
1115 idt_monitor_base = address_present ? address : 0xBFC00000;
1116 pmon_monitor_base = 0;
1117 lsipmon_monitor_base = 0;
1118 }
1119 else if (! strncmp (arg, "pmon", 4))
1120 {
1121 /* pmon uses indirect calls. Hook into implied idt. */
1122 pmon_monitor_base = address_present ? address : 0xBFC00500;
1123 idt_monitor_base = pmon_monitor_base - 0x500;
1124 lsipmon_monitor_base = 0;
1125 }
1126 else if (! strncmp (arg, "lsipmon", 7))
1127 {
1128 /* lsipmon uses indirect calls. Hook into implied idt. */
1129 pmon_monitor_base = 0;
1130 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1131 idt_monitor_base = lsipmon_monitor_base - 0x200;
1132 }
1133 else if (! strncmp (arg, "none", 4))
1134 {
1135 if (address_present)
1136 {
1137 sim_io_printf (sd,
1138 "The `sim firmware none' command does "
1139 "not take an `ADDRESS' argument.\n");
1140 return SIM_RC_FAIL;
1141 }
1142 idt_monitor_base = 0;
1143 pmon_monitor_base = 0;
1144 lsipmon_monitor_base = 0;
1145 }
1146 else
1147 {
1148 sim_io_printf (sd, "\
1149 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1150 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1151 arg);
1152 return SIM_RC_FAIL;
1153 }
1154
1155 return SIM_RC_OK;
1156 }
1157
1158 /* stat structures from MIPS32/64. */
1159 static const char stat32_map[] =
1160 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1161 ":st_rdev,2:st_size,4:st_atime,4:st_spare1,4:st_mtime,4:st_spare2,4"
1162 ":st_ctime,4:st_spare3,4:st_blksize,4:st_blocks,4:st_spare4,8";
1163
1164 static const char stat64_map[] =
1165 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1166 ":st_rdev,2:st_size,8:st_atime,8:st_spare1,8:st_mtime,8:st_spare2,8"
1167 ":st_ctime,8:st_spare3,8:st_blksize,8:st_blocks,8:st_spare4,16";
1168
1169 /* Map for calls using the host struct stat. */
1170 static const CB_TARGET_DEFS_MAP CB_stat_map[] =
1171 {
1172 { "stat", CB_SYS_stat, 15 },
1173 { 0, -1, -1 }
1174 };
1175
1176
1177 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1178 int
1179 sim_monitor (SIM_DESC sd,
1180 sim_cpu *cpu,
1181 address_word cia,
1182 unsigned int reason)
1183 {
1184 #ifdef DEBUG
1185 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1186 #endif /* DEBUG */
1187
1188 /* The IDT monitor actually allows two instructions per vector
1189 slot. However, the simulator currently causes a trap on each
1190 individual instruction. We cheat, and lose the bottom bit. */
1191 reason >>= 1;
1192
1193 /* The following callback functions are available, however the
1194 monitor we are simulating does not make use of them: get_errno,
1195 isatty, rename, system and time. */
1196 switch (reason)
1197 {
1198
1199 case 6: /* int open(char *path,int flags) */
1200 {
1201 char *path = fetch_str (sd, A0);
1202 V0 = sim_io_open (sd, path, (int)A1);
1203 free (path);
1204 break;
1205 }
1206
1207 case 7: /* int read(int file,char *ptr,int len) */
1208 {
1209 int fd = A0;
1210 int nr = A2;
1211 char *buf = zalloc (nr);
1212 V0 = sim_io_read (sd, fd, buf, nr);
1213 sim_write (sd, A1, (unsigned char *)buf, nr);
1214 free (buf);
1215 }
1216 break;
1217
1218 case 8: /* int write(int file,char *ptr,int len) */
1219 {
1220 int fd = A0;
1221 int nr = A2;
1222 char *buf = zalloc (nr);
1223 sim_read (sd, A1, (unsigned char *)buf, nr);
1224 V0 = sim_io_write (sd, fd, buf, nr);
1225 if (fd == 1)
1226 sim_io_flush_stdout (sd);
1227 else if (fd == 2)
1228 sim_io_flush_stderr (sd);
1229 free (buf);
1230 break;
1231 }
1232
1233 case 10: /* int close(int file) */
1234 {
1235 V0 = sim_io_close (sd, (int)A0);
1236 break;
1237 }
1238
1239 case 2: /* Densan monitor: char inbyte(int waitflag) */
1240 {
1241 if (A0 == 0) /* waitflag == NOWAIT */
1242 V0 = (unsigned_word)-1;
1243 }
1244 /* Drop through to case 11 */
1245
1246 case 11: /* char inbyte(void) */
1247 {
1248 char tmp;
1249 /* ensure that all output has gone... */
1250 sim_io_flush_stdout (sd);
1251 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1252 {
1253 sim_io_error(sd,"Invalid return from character read");
1254 V0 = (unsigned_word)-1;
1255 }
1256 else
1257 V0 = (unsigned_word)tmp;
1258 break;
1259 }
1260
1261 case 3: /* Densan monitor: void co(char chr) */
1262 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1263 {
1264 char tmp = (char)(A0 & 0xFF);
1265 sim_io_write_stdout (sd, &tmp, sizeof(char));
1266 break;
1267 }
1268
1269 case 13: /* int unlink(const char *path) */
1270 {
1271 char *path = fetch_str (sd, A0);
1272 V0 = sim_io_unlink (sd, path);
1273 free (path);
1274 break;
1275 }
1276
1277 case 14: /* int lseek(int fd, int offset, int whence) */
1278 {
1279 V0 = sim_io_lseek (sd, A0, A1, A2);
1280 break;
1281 }
1282
1283 case 15: /* int stat(const char *path, struct stat *buf); */
1284 {
1285 /* As long as the infrastructure doesn't cache anything
1286 related to the stat mapping, this trick gets us a dual
1287 "struct stat"-type mapping in the least error-prone way. */
1288 host_callback *cb = STATE_CALLBACK (sd);
1289 const char *saved_map = cb->stat_map;
1290 CB_TARGET_DEFS_MAP *saved_syscall_map = cb->syscall_map;
1291 bfd *prog_bfd = STATE_PROG_BFD (sd);
1292 int is_elf32bit = (elf_elfheader(prog_bfd)->e_ident[EI_CLASS] ==
1293 ELFCLASS32);
1294 static CB_SYSCALL s;
1295 CB_SYSCALL_INIT (&s);
1296 s.func = 15;
1297 /* Mask out the sign extension part for 64-bit targets because the
1298 MIPS simulator's memory model is still 32-bit. */
1299 s.arg1 = A0 & 0xFFFFFFFF;
1300 s.arg2 = A1 & 0xFFFFFFFF;
1301 s.p1 = (PTR) sd;
1302 s.p2 = (PTR) cpu;
1303 s.read_mem = sim_syscall_read_mem;
1304 s.write_mem = sim_syscall_write_mem;
1305
1306 cb->syscall_map = (CB_TARGET_DEFS_MAP *) CB_stat_map;
1307 cb->stat_map = is_elf32bit ? stat32_map : stat64_map;
1308
1309 if (cb_syscall (cb, &s) != CB_RC_OK)
1310 sim_engine_halt (sd, cpu, NULL, mips_pc_get (cpu),
1311 sim_stopped, SIM_SIGILL);
1312
1313 V0 = s.result;
1314 cb->stat_map = saved_map;
1315 cb->syscall_map = saved_syscall_map;
1316 break;
1317 }
1318
1319 case 17: /* void _exit() */
1320 {
1321 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1322 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1323 (unsigned int)(A0 & 0xFFFFFFFF));
1324 break;
1325 }
1326
1327 case 28: /* PMON flush_cache */
1328 break;
1329
1330 case 55: /* void get_mem_info(unsigned int *ptr) */
1331 /* in: A0 = pointer to three word memory location */
1332 /* out: [A0 + 0] = size */
1333 /* [A0 + 4] = instruction cache size */
1334 /* [A0 + 8] = data cache size */
1335 {
1336 unsigned_4 value;
1337 unsigned_4 zero = 0;
1338 address_word mem_size;
1339 sim_memopt *entry, *match = NULL;
1340
1341 /* Search for memory region mapped to KSEG0 or KSEG1. */
1342 for (entry = STATE_MEMOPT (sd);
1343 entry != NULL;
1344 entry = entry->next)
1345 {
1346 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1347 && (!match || entry->level < match->level))
1348 match = entry;
1349 else
1350 {
1351 sim_memopt *alias;
1352 for (alias = entry->alias;
1353 alias != NULL;
1354 alias = alias->next)
1355 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1356 && (!match || entry->level < match->level))
1357 match = entry;
1358 }
1359 }
1360
1361 /* Get region size, limit to KSEG1 size (512MB). */
1362 SIM_ASSERT (match != NULL);
1363 mem_size = (match->modulo != 0
1364 ? match->modulo : match->nr_bytes);
1365 if (mem_size > K1SIZE)
1366 mem_size = K1SIZE;
1367
1368 value = mem_size;
1369 H2T (value);
1370 sim_write (sd, A0 + 0, (unsigned char *)&value, 4);
1371 sim_write (sd, A0 + 4, (unsigned char *)&zero, 4);
1372 sim_write (sd, A0 + 8, (unsigned char *)&zero, 4);
1373 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1374 break;
1375 }
1376
1377 case 158: /* PMON printf */
1378 /* in: A0 = pointer to format string */
1379 /* A1 = optional argument 1 */
1380 /* A2 = optional argument 2 */
1381 /* A3 = optional argument 3 */
1382 /* out: void */
1383 /* The following is based on the PMON printf source */
1384 {
1385 address_word s = A0;
1386 unsigned char c;
1387 signed_word *ap = &A1; /* 1st argument */
1388 /* This isn't the quickest way, since we call the host print
1389 routine for every character almost. But it does avoid
1390 having to allocate and manage a temporary string buffer. */
1391 /* TODO: Include check that we only use three arguments (A1,
1392 A2 and A3) */
1393 while (sim_read (sd, s++, &c, 1) && c != '\0')
1394 {
1395 if (c == '%')
1396 {
1397 char tmp[40];
1398 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1399 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1400 while (sim_read (sd, s++, &c, 1) && c != '\0')
1401 {
1402 if (strchr ("dobxXulscefg%", c))
1403 break;
1404 else if (c == '-')
1405 fmt = FMT_LJUST;
1406 else if (c == '0')
1407 fmt = FMT_RJUST0;
1408 else if (c == '~')
1409 fmt = FMT_CENTER;
1410 else if (c == '*')
1411 {
1412 if (haddot)
1413 trunc = (int)*ap++;
1414 else
1415 width = (int)*ap++;
1416 }
1417 else if (c >= '1' && c <= '9')
1418 {
1419 address_word t = s;
1420 unsigned int n;
1421 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1422 tmp[s - t] = c;
1423 tmp[s - t] = '\0';
1424 n = (unsigned int)strtol(tmp,NULL,10);
1425 if (haddot)
1426 trunc = n;
1427 else
1428 width = n;
1429 s--;
1430 }
1431 else if (c == '.')
1432 haddot = 1;
1433 }
1434 switch (c)
1435 {
1436 case '%':
1437 sim_io_printf (sd, "%%");
1438 break;
1439 case 's':
1440 if ((int)*ap != 0)
1441 {
1442 address_word p = *ap++;
1443 unsigned char ch;
1444 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1445 sim_io_printf(sd, "%c", ch);
1446 }
1447 else
1448 sim_io_printf(sd,"(null)");
1449 break;
1450 case 'c':
1451 sim_io_printf (sd, "%c", (int)*ap++);
1452 break;
1453 default:
1454 if (c == 'l')
1455 {
1456 sim_read (sd, s++, &c, 1);
1457 if (c == 'l')
1458 {
1459 longlong = 1;
1460 sim_read (sd, s++, &c, 1);
1461 }
1462 }
1463 if (strchr ("dobxXu", c))
1464 {
1465 word64 lv = (word64) *ap++;
1466 if (c == 'b')
1467 sim_io_printf(sd,"<binary not supported>");
1468 else
1469 {
1470 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1471 if (longlong)
1472 sim_io_printf(sd, tmp, lv);
1473 else
1474 sim_io_printf(sd, tmp, (int)lv);
1475 }
1476 }
1477 else if (strchr ("eEfgG", c))
1478 {
1479 double dbl = *(double*)(ap++);
1480 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1481 sim_io_printf (sd, tmp, dbl);
1482 trunc = 0;
1483 }
1484 }
1485 }
1486 else
1487 sim_io_printf(sd, "%c", c);
1488 }
1489 break;
1490 }
1491
1492 default:
1493 /* Unknown reason. */
1494 return 0;
1495 }
1496 return 1;
1497 }
1498
1499 /* Store a word into memory. */
1500
1501 static void
1502 store_word (SIM_DESC sd,
1503 sim_cpu *cpu,
1504 address_word cia,
1505 uword64 vaddr,
1506 signed_word val)
1507 {
1508 address_word paddr = vaddr;
1509
1510 if ((vaddr & 3) != 0)
1511 SignalExceptionAddressStore ();
1512 else
1513 {
1514 const uword64 mask = 7;
1515 uword64 memval;
1516 unsigned int byte;
1517
1518 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1519 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1520 memval = ((uword64) val) << (8 * byte);
1521 StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
1522 isREAL);
1523 }
1524 }
1525
1526 /* Load a word from memory. */
1527
1528 static signed_word
1529 load_word (SIM_DESC sd,
1530 sim_cpu *cpu,
1531 address_word cia,
1532 uword64 vaddr)
1533 {
1534 if ((vaddr & 3) != 0)
1535 {
1536 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1537 }
1538 else
1539 {
1540 address_word paddr = vaddr;
1541 const uword64 mask = 0x7;
1542 const unsigned int reverse = ReverseEndian ? 1 : 0;
1543 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1544 uword64 memval;
1545 unsigned int byte;
1546
1547 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1548 LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
1549 isREAL);
1550 byte = (vaddr & mask) ^ (bigend << 2);
1551 return EXTEND32 (memval >> (8 * byte));
1552 }
1553
1554 return 0;
1555 }
1556
1557 /* Simulate the mips16 entry and exit pseudo-instructions. These
1558 would normally be handled by the reserved instruction exception
1559 code, but for ease of simulation we just handle them directly. */
1560
1561 static void
1562 mips16_entry (SIM_DESC sd,
1563 sim_cpu *cpu,
1564 address_word cia,
1565 unsigned int insn)
1566 {
1567 int aregs, sregs, rreg;
1568
1569 #ifdef DEBUG
1570 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1571 #endif /* DEBUG */
1572
1573 aregs = (insn & 0x700) >> 8;
1574 sregs = (insn & 0x0c0) >> 6;
1575 rreg = (insn & 0x020) >> 5;
1576
1577 /* This should be checked by the caller. */
1578 if (sregs == 3)
1579 abort ();
1580
1581 if (aregs < 5)
1582 {
1583 int i;
1584 signed_word tsp;
1585
1586 /* This is the entry pseudo-instruction. */
1587
1588 for (i = 0; i < aregs; i++)
1589 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1590
1591 tsp = SP;
1592 SP -= 32;
1593
1594 if (rreg)
1595 {
1596 tsp -= 4;
1597 store_word (SD, CPU, cia, (uword64) tsp, RA);
1598 }
1599
1600 for (i = 0; i < sregs; i++)
1601 {
1602 tsp -= 4;
1603 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1604 }
1605 }
1606 else
1607 {
1608 int i;
1609 signed_word tsp;
1610
1611 /* This is the exit pseudo-instruction. */
1612
1613 tsp = SP + 32;
1614
1615 if (rreg)
1616 {
1617 tsp -= 4;
1618 RA = load_word (SD, CPU, cia, (uword64) tsp);
1619 }
1620
1621 for (i = 0; i < sregs; i++)
1622 {
1623 tsp -= 4;
1624 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1625 }
1626
1627 SP += 32;
1628
1629 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1630 {
1631 if (aregs == 5)
1632 {
1633 FGR[0] = WORD64LO (GPR[4]);
1634 FPR_STATE[0] = fmt_uninterpreted;
1635 }
1636 else if (aregs == 6)
1637 {
1638 FGR[0] = WORD64LO (GPR[5]);
1639 FGR[1] = WORD64LO (GPR[4]);
1640 FPR_STATE[0] = fmt_uninterpreted;
1641 FPR_STATE[1] = fmt_uninterpreted;
1642 }
1643 }
1644
1645 PC = RA;
1646 }
1647
1648 }
1649
1650 /*-- trace support ----------------------------------------------------------*/
1651
1652 /* The trace support is provided (if required) in the memory accessing
1653 routines. Since we are also providing the architecture specific
1654 features, the architecture simulation code can also deal with
1655 notifying the trace world of cache flushes, etc. Similarly we do
1656 not need to provide profiling support in the simulator engine,
1657 since we can sample in the instruction fetch control loop. By
1658 defining the trace manifest, we add tracing as a run-time
1659 option. */
1660
1661 #if WITH_TRACE_ANY_P
1662 /* Tracing by default produces "din" format (as required by
1663 dineroIII). Each line of such a trace file *MUST* have a din label
1664 and address field. The rest of the line is ignored, so comments can
1665 be included if desired. The first field is the label which must be
1666 one of the following values:
1667
1668 0 read data
1669 1 write data
1670 2 instruction fetch
1671 3 escape record (treated as unknown access type)
1672 4 escape record (causes cache flush)
1673
1674 The address field is a 32bit (lower-case) hexadecimal address
1675 value. The address should *NOT* be preceded by "0x".
1676
1677 The size of the memory transfer is not important when dealing with
1678 cache lines (as long as no more than a cache line can be
1679 transferred in a single operation :-), however more information
1680 could be given following the dineroIII requirement to allow more
1681 complete memory and cache simulators to provide better
1682 results. i.e. the University of Pisa has a cache simulator that can
1683 also take bus size and speed as (variable) inputs to calculate
1684 complete system performance (a much more useful ability when trying
1685 to construct an end product, rather than a processor). They
1686 currently have an ARM version of their tool called ChARM. */
1687
1688
1689 void
1690 dotrace (SIM_DESC sd,
1691 sim_cpu *cpu,
1692 FILE *tracefh,
1693 int type,
1694 SIM_ADDR address,
1695 int width,
1696 char *comment,...)
1697 {
1698 if (STATE & simTRACE) {
1699 va_list ap;
1700 fprintf(tracefh,"%d %s ; width %d ; ",
1701 type,
1702 pr_addr(address),
1703 width);
1704 va_start(ap,comment);
1705 vfprintf(tracefh,comment,ap);
1706 va_end(ap);
1707 fprintf(tracefh,"\n");
1708 }
1709 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1710 we may be generating 64bit ones, we should put the hi-32bits of the
1711 address into the comment field. */
1712
1713 /* TODO: Provide a buffer for the trace lines. We can then avoid
1714 performing writes until the buffer is filled, or the file is
1715 being closed. */
1716
1717 /* NOTE: We could consider adding a comment field to the "din" file
1718 produced using type 3 markers (unknown access). This would then
1719 allow information about the program that the "din" is for, and
1720 the MIPs world that was being simulated, to be placed into the
1721 trace file. */
1722
1723 return;
1724 }
1725 #endif /* WITH_TRACE_ANY_P */
1726
1727 /*---------------------------------------------------------------------------*/
1728 /*-- simulator engine -------------------------------------------------------*/
1729 /*---------------------------------------------------------------------------*/
1730
1731 static void
1732 ColdReset (SIM_DESC sd)
1733 {
1734 int cpu_nr;
1735 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1736 {
1737 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1738 /* RESET: Fixed PC address: */
1739 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1740 /* The reset vector address is in the unmapped, uncached memory space. */
1741
1742 SR &= ~(status_SR | status_TS | status_RP);
1743 SR |= (status_ERL | status_BEV);
1744
1745 /* Cheat and allow access to the complete register set immediately */
1746 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1747 && WITH_TARGET_WORD_BITSIZE == 64)
1748 SR |= status_FR; /* 64bit registers */
1749
1750 /* Ensure that any instructions with pending register updates are
1751 cleared: */
1752 PENDING_INVALIDATE();
1753
1754 /* Initialise the FPU registers to the unknown state */
1755 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1756 {
1757 int rn;
1758 for (rn = 0; (rn < 32); rn++)
1759 FPR_STATE[rn] = fmt_uninterpreted;
1760 }
1761
1762 /* Initialise the Config0 register. */
1763 C0_CONFIG = 0x80000000 /* Config1 present */
1764 | 2; /* KSEG0 uncached */
1765 if (WITH_TARGET_WORD_BITSIZE == 64)
1766 {
1767 /* FIXME Currently mips/sim-main.c:address_translation()
1768 truncates all addresses to 32-bits. */
1769 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1770 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1771 else
1772 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1773 }
1774 if (BigEndianMem)
1775 C0_CONFIG |= 0x00008000; /* Big Endian */
1776 }
1777 }
1778
1779
1780
1781
1782 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1783 /* Signal an exception condition. This will result in an exception
1784 that aborts the instruction. The instruction operation pseudocode
1785 will never see a return from this function call. */
1786
1787 void
1788 signal_exception (SIM_DESC sd,
1789 sim_cpu *cpu,
1790 address_word cia,
1791 int exception,...)
1792 {
1793 /* int vector; */
1794
1795 #ifdef DEBUG
1796 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1797 #endif /* DEBUG */
1798
1799 /* Ensure that any active atomic read/modify/write operation will fail: */
1800 LLBIT = 0;
1801
1802 /* Save registers before interrupt dispatching */
1803 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1804 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1805 #endif
1806
1807 switch (exception) {
1808
1809 case DebugBreakPoint:
1810 if (! (Debug & Debug_DM))
1811 {
1812 if (INDELAYSLOT())
1813 {
1814 CANCELDELAYSLOT();
1815
1816 Debug |= Debug_DBD; /* signaled from within in delay slot */
1817 DEPC = cia - 4; /* reference the branch instruction */
1818 }
1819 else
1820 {
1821 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1822 DEPC = cia;
1823 }
1824
1825 Debug |= Debug_DM; /* in debugging mode */
1826 Debug |= Debug_DBp; /* raising a DBp exception */
1827 PC = 0xBFC00200;
1828 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1829 }
1830 break;
1831
1832 case ReservedInstruction:
1833 {
1834 va_list ap;
1835 unsigned int instruction;
1836 va_start(ap,exception);
1837 instruction = va_arg(ap,unsigned int);
1838 va_end(ap);
1839 /* Provide simple monitor support using ReservedInstruction
1840 exceptions. The following code simulates the fixed vector
1841 entry points into the IDT monitor by causing a simulator
1842 trap, performing the monitor operation, and returning to
1843 the address held in the $ra register (standard PCS return
1844 address). This means we only need to pre-load the vector
1845 space with suitable instruction values. For systems were
1846 actual trap instructions are used, we would not need to
1847 perform this magic. */
1848 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1849 {
1850 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1851 if (!sim_monitor (SD, CPU, cia, reason))
1852 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1853
1854 /* NOTE: This assumes that a branch-and-link style
1855 instruction was used to enter the vector (which is the
1856 case with the current IDT monitor). */
1857 sim_engine_restart (SD, CPU, NULL, RA);
1858 }
1859 /* Look for the mips16 entry and exit instructions, and
1860 simulate a handler for them. */
1861 else if ((cia & 1) != 0
1862 && (instruction & 0xf81f) == 0xe809
1863 && (instruction & 0x0c0) != 0x0c0)
1864 {
1865 mips16_entry (SD, CPU, cia, instruction);
1866 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1867 }
1868 /* else fall through to normal exception processing */
1869 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1870 }
1871
1872 default:
1873 /* Store exception code into current exception id variable (used
1874 by exit code): */
1875
1876 /* TODO: If not simulating exceptions then stop the simulator
1877 execution. At the moment we always stop the simulation. */
1878
1879 #ifdef SUBTARGET_R3900
1880 /* update interrupt-related registers */
1881
1882 /* insert exception code in bits 6:2 */
1883 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1884 /* shift IE/KU history bits left */
1885 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1886
1887 if (STATE & simDELAYSLOT)
1888 {
1889 STATE &= ~simDELAYSLOT;
1890 CAUSE |= cause_BD;
1891 EPC = (cia - 4); /* reference the branch instruction */
1892 }
1893 else
1894 EPC = cia;
1895
1896 if (SR & status_BEV)
1897 PC = (signed)0xBFC00000 + 0x180;
1898 else
1899 PC = (signed)0x80000000 + 0x080;
1900 #else
1901 /* See figure 5-17 for an outline of the code below */
1902 if (! (SR & status_EXL))
1903 {
1904 CAUSE = (exception << 2);
1905 if (STATE & simDELAYSLOT)
1906 {
1907 STATE &= ~simDELAYSLOT;
1908 CAUSE |= cause_BD;
1909 EPC = (cia - 4); /* reference the branch instruction */
1910 }
1911 else
1912 EPC = cia;
1913 /* FIXME: TLB et.al. */
1914 /* vector = 0x180; */
1915 }
1916 else
1917 {
1918 CAUSE = (exception << 2);
1919 /* vector = 0x180; */
1920 }
1921 SR |= status_EXL;
1922 /* Store exception code into current exception id variable (used
1923 by exit code): */
1924
1925 if (SR & status_BEV)
1926 PC = (signed)0xBFC00200 + 0x180;
1927 else
1928 PC = (signed)0x80000000 + 0x180;
1929 #endif
1930
1931 switch ((CAUSE >> 2) & 0x1F)
1932 {
1933 case Interrupt:
1934 /* Interrupts arrive during event processing, no need to
1935 restart */
1936 return;
1937
1938 case NMIReset:
1939 /* Ditto */
1940 #ifdef SUBTARGET_3900
1941 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1942 PC = (signed)0xBFC00000;
1943 #endif /* SUBTARGET_3900 */
1944 return;
1945
1946 case TLBModification:
1947 case TLBLoad:
1948 case TLBStore:
1949 case AddressLoad:
1950 case AddressStore:
1951 case InstructionFetch:
1952 case DataReference:
1953 /* The following is so that the simulator will continue from the
1954 exception handler address. */
1955 sim_engine_halt (SD, CPU, NULL, PC,
1956 sim_stopped, SIM_SIGBUS);
1957
1958 case ReservedInstruction:
1959 case CoProcessorUnusable:
1960 PC = EPC;
1961 sim_engine_halt (SD, CPU, NULL, PC,
1962 sim_stopped, SIM_SIGILL);
1963
1964 case IntegerOverflow:
1965 case FPE:
1966 sim_engine_halt (SD, CPU, NULL, PC,
1967 sim_stopped, SIM_SIGFPE);
1968
1969 case BreakPoint:
1970 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1971 break;
1972
1973 case SystemCall:
1974 case Trap:
1975 sim_engine_restart (SD, CPU, NULL, PC);
1976 break;
1977
1978 case Watch:
1979 PC = EPC;
1980 sim_engine_halt (SD, CPU, NULL, PC,
1981 sim_stopped, SIM_SIGTRAP);
1982
1983 default: /* Unknown internal exception */
1984 PC = EPC;
1985 sim_engine_halt (SD, CPU, NULL, PC,
1986 sim_stopped, SIM_SIGABRT);
1987
1988 }
1989
1990 case SimulatorFault:
1991 {
1992 va_list ap;
1993 char *msg;
1994 va_start(ap,exception);
1995 msg = va_arg(ap,char *);
1996 va_end(ap);
1997 sim_engine_abort (SD, CPU, NULL_CIA,
1998 "FATAL: Simulator error \"%s\"\n",msg);
1999 }
2000 }
2001
2002 return;
2003 }
2004
2005
2006
2007 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2008 "UNPREDICTABLE" behaviour.
2009
2010 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2011 may vary from processor implementation to processor implementation,
2012 instruction to instruction, or as a function of time on the same
2013 implementation or instruction. Software can never depend on results
2014 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2015 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2016 0.95, page 2.)
2017
2018 For UNPREDICTABLE behaviour, we print a message, if possible print
2019 the offending instructions mips.igen instruction name (provided by
2020 the caller), and stop the simulator.
2021
2022 XXX FIXME: eventually, stopping the simulator should be made conditional
2023 on a command-line option. */
2024 void
2025 unpredictable_action(sim_cpu *cpu, address_word cia)
2026 {
2027 SIM_DESC sd = CPU_STATE(cpu);
2028
2029 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
2030 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
2031 }
2032
2033
2034 /*-- co-processor support routines ------------------------------------------*/
2035
2036 static int UNUSED
2037 CoProcPresent(unsigned int coproc_number)
2038 {
2039 /* Return TRUE if simulator provides a model for the given co-processor number */
2040 return(0);
2041 }
2042
2043 void
2044 cop_lw (SIM_DESC sd,
2045 sim_cpu *cpu,
2046 address_word cia,
2047 int coproc_num,
2048 int coproc_reg,
2049 unsigned int memword)
2050 {
2051 switch (coproc_num)
2052 {
2053 case 1:
2054 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2055 {
2056 #ifdef DEBUG
2057 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2058 #endif
2059 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
2060 break;
2061 }
2062
2063 default:
2064 #if 0 /* this should be controlled by a configuration option */
2065 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2066 #endif
2067 break;
2068 }
2069
2070 return;
2071 }
2072
2073 void
2074 cop_ld (SIM_DESC sd,
2075 sim_cpu *cpu,
2076 address_word cia,
2077 int coproc_num,
2078 int coproc_reg,
2079 uword64 memword)
2080 {
2081
2082 #ifdef DEBUG
2083 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2084 #endif
2085
2086 switch (coproc_num) {
2087 case 1:
2088 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2089 {
2090 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
2091 break;
2092 }
2093
2094 default:
2095 #if 0 /* this message should be controlled by a configuration option */
2096 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2097 #endif
2098 break;
2099 }
2100
2101 return;
2102 }
2103
2104
2105
2106
2107 unsigned int
2108 cop_sw (SIM_DESC sd,
2109 sim_cpu *cpu,
2110 address_word cia,
2111 int coproc_num,
2112 int coproc_reg)
2113 {
2114 unsigned int value = 0;
2115
2116 switch (coproc_num)
2117 {
2118 case 1:
2119 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2120 {
2121 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
2122 break;
2123 }
2124
2125 default:
2126 #if 0 /* should be controlled by configuration option */
2127 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2128 #endif
2129 break;
2130 }
2131
2132 return(value);
2133 }
2134
2135 uword64
2136 cop_sd (SIM_DESC sd,
2137 sim_cpu *cpu,
2138 address_word cia,
2139 int coproc_num,
2140 int coproc_reg)
2141 {
2142 uword64 value = 0;
2143 switch (coproc_num)
2144 {
2145 case 1:
2146 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2147 {
2148 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
2149 break;
2150 }
2151
2152 default:
2153 #if 0 /* should be controlled by configuration option */
2154 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2155 #endif
2156 break;
2157 }
2158
2159 return(value);
2160 }
2161
2162
2163
2164
2165 void
2166 decode_coproc (SIM_DESC sd,
2167 sim_cpu *cpu,
2168 address_word cia,
2169 unsigned int instruction,
2170 int coprocnum,
2171 CP0_operation op,
2172 int rt,
2173 int rd,
2174 int sel)
2175 {
2176 switch (coprocnum)
2177 {
2178 case 0: /* standard CPU control and cache registers */
2179 {
2180 /* R4000 Users Manual (second edition) lists the following CP0
2181 instructions:
2182 CODE><-RT><RD-><--TAIL--->
2183 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2184 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2185 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2186 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2187 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2188 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2189 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2190 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2191 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2192 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2193 */
2194 if (((op == cp0_mfc0) || (op == cp0_mtc0) /* MFC0 / MTC0 */
2195 || (op == cp0_dmfc0) || (op == cp0_dmtc0)) /* DMFC0 / DMTC0 */
2196 && sel == 0)
2197 {
2198 switch (rd) /* NOTEs: Standard CP0 registers */
2199 {
2200 /* 0 = Index R4000 VR4100 VR4300 */
2201 /* 1 = Random R4000 VR4100 VR4300 */
2202 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2203 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2204 /* 4 = Context R4000 VR4100 VR4300 */
2205 /* 5 = PageMask R4000 VR4100 VR4300 */
2206 /* 6 = Wired R4000 VR4100 VR4300 */
2207 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2208 /* 9 = Count R4000 VR4100 VR4300 */
2209 /* 10 = EntryHi R4000 VR4100 VR4300 */
2210 /* 11 = Compare R4000 VR4100 VR4300 */
2211 /* 12 = SR R4000 VR4100 VR4300 */
2212 #ifdef SUBTARGET_R3900
2213 case 3:
2214 /* 3 = Config R3900 */
2215 case 7:
2216 /* 7 = Cache R3900 */
2217 case 15:
2218 /* 15 = PRID R3900 */
2219
2220 /* ignore */
2221 break;
2222
2223 case 8:
2224 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2225 if (op == cp0_mfc0 || op == cp0_dmfc0)
2226 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
2227 else
2228 COP0_BADVADDR = GPR[rt];
2229 break;
2230
2231 #endif /* SUBTARGET_R3900 */
2232 case 12:
2233 if (op == cp0_mfc0 || op == cp0_dmfc0)
2234 GPR[rt] = SR;
2235 else
2236 SR = GPR[rt];
2237 break;
2238 /* 13 = Cause R4000 VR4100 VR4300 */
2239 case 13:
2240 if (op == cp0_mfc0 || op == cp0_dmfc0)
2241 GPR[rt] = CAUSE;
2242 else
2243 CAUSE = GPR[rt];
2244 break;
2245 /* 14 = EPC R4000 VR4100 VR4300 */
2246 case 14:
2247 if (op == cp0_mfc0 || op == cp0_dmfc0)
2248 GPR[rt] = (signed_word) (signed_address) EPC;
2249 else
2250 EPC = GPR[rt];
2251 break;
2252 /* 15 = PRId R4000 VR4100 VR4300 */
2253 #ifdef SUBTARGET_R3900
2254 /* 16 = Debug */
2255 case 16:
2256 if (op == cp0_mfc0 || op == cp0_dmfc0)
2257 GPR[rt] = Debug;
2258 else
2259 Debug = GPR[rt];
2260 break;
2261 #else
2262 /* 16 = Config R4000 VR4100 VR4300 */
2263 case 16:
2264 if (op == cp0_mfc0 || op == cp0_dmfc0)
2265 GPR[rt] = C0_CONFIG;
2266 else
2267 /* only bottom three bits are writable */
2268 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
2269 break;
2270 #endif
2271 #ifdef SUBTARGET_R3900
2272 /* 17 = Debug */
2273 case 17:
2274 if (op == cp0_mfc0 || op == cp0_dmfc0)
2275 GPR[rt] = DEPC;
2276 else
2277 DEPC = GPR[rt];
2278 break;
2279 #else
2280 /* 17 = LLAddr R4000 VR4100 VR4300 */
2281 #endif
2282 /* 18 = WatchLo R4000 VR4100 VR4300 */
2283 /* 19 = WatchHi R4000 VR4100 VR4300 */
2284 /* 20 = XContext R4000 VR4100 VR4300 */
2285 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2286 /* 27 = CacheErr R4000 VR4100 */
2287 /* 28 = TagLo R4000 VR4100 VR4300 */
2288 /* 29 = TagHi R4000 VR4100 VR4300 */
2289 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2290 if (STATE_VERBOSE_P(SD))
2291 sim_io_eprintf (SD,
2292 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2293 (unsigned long)cia);
2294 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2295 /* CPR[0,rd] = GPR[rt]; */
2296 default:
2297 if (op == cp0_mfc0 || op == cp0_dmfc0)
2298 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2299 else
2300 COP0_GPR[rd] = GPR[rt];
2301 #if 0
2302 if (code == 0x00)
2303 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2304 else
2305 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2306 #endif
2307 }
2308 }
2309 else if ((op == cp0_mfc0 || op == cp0_dmfc0)
2310 && rd == 16)
2311 {
2312 /* [D]MFC0 RT,C0_CONFIG,SEL */
2313 signed32 cfg = 0;
2314 switch (sel)
2315 {
2316 case 0:
2317 cfg = C0_CONFIG;
2318 break;
2319 case 1:
2320 /* MIPS32 r/o Config1:
2321 Config2 present */
2322 cfg = 0x80000000;
2323 /* MIPS16 implemented.
2324 XXX How to check configuration? */
2325 cfg |= 0x0000004;
2326 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2327 /* MDMX & FPU implemented */
2328 cfg |= 0x00000021;
2329 break;
2330 case 2:
2331 /* MIPS32 r/o Config2:
2332 Config3 present. */
2333 cfg = 0x80000000;
2334 break;
2335 case 3:
2336 /* MIPS32 r/o Config3:
2337 SmartMIPS implemented. */
2338 cfg = 0x00000002;
2339 break;
2340 }
2341 GPR[rt] = cfg;
2342 }
2343 else if (op == cp0_eret && sel == 0x18)
2344 {
2345 /* ERET */
2346 if (SR & status_ERL)
2347 {
2348 /* Oops, not yet available */
2349 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2350 PC = EPC;
2351 SR &= ~status_ERL;
2352 }
2353 else
2354 {
2355 PC = EPC;
2356 SR &= ~status_EXL;
2357 }
2358 }
2359 else if (op == cp0_rfe && sel == 0x10)
2360 {
2361 /* RFE */
2362 #ifdef SUBTARGET_R3900
2363 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2364
2365 /* shift IE/KU history bits right */
2366 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2367
2368 /* TODO: CACHE register */
2369 #endif /* SUBTARGET_R3900 */
2370 }
2371 else if (op == cp0_deret && sel == 0x1F)
2372 {
2373 /* DERET */
2374 Debug &= ~Debug_DM;
2375 DELAYSLOT();
2376 DSPC = DEPC;
2377 }
2378 else
2379 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2380 /* TODO: When executing an ERET or RFE instruction we should
2381 clear LLBIT, to ensure that any out-standing atomic
2382 read/modify/write sequence fails. */
2383 }
2384 break;
2385
2386 case 2: /* co-processor 2 */
2387 {
2388 int handle = 0;
2389
2390
2391 if(! handle)
2392 {
2393 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2394 instruction,pr_addr(cia));
2395 }
2396 }
2397 break;
2398
2399 case 1: /* should not occur (FPU co-processor) */
2400 case 3: /* should not occur (FPU co-processor) */
2401 SignalException(ReservedInstruction,instruction);
2402 break;
2403 }
2404
2405 return;
2406 }
2407
2408
2409 /* This code copied from gdb's utils.c. Would like to share this code,
2410 but don't know of a common place where both could get to it. */
2411
2412 /* Temporary storage using circular buffer */
2413 #define NUMCELLS 16
2414 #define CELLSIZE 32
2415 static char*
2416 get_cell (void)
2417 {
2418 static char buf[NUMCELLS][CELLSIZE];
2419 static int cell=0;
2420 if (++cell>=NUMCELLS) cell=0;
2421 return buf[cell];
2422 }
2423
2424 /* Print routines to handle variable size regs, etc */
2425
2426 /* Eliminate warning from compiler on 32-bit systems */
2427 static int thirty_two = 32;
2428
2429 char*
2430 pr_addr (SIM_ADDR addr)
2431 {
2432 char *paddr_str=get_cell();
2433 switch (sizeof(addr))
2434 {
2435 case 8:
2436 sprintf(paddr_str,"%08lx%08lx",
2437 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2438 break;
2439 case 4:
2440 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2441 break;
2442 case 2:
2443 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2444 break;
2445 default:
2446 sprintf(paddr_str,"%x",addr);
2447 }
2448 return paddr_str;
2449 }
2450
2451 char*
2452 pr_uword64 (uword64 addr)
2453 {
2454 char *paddr_str=get_cell();
2455 sprintf(paddr_str,"%08lx%08lx",
2456 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2457 return paddr_str;
2458 }
2459
2460
2461 void
2462 mips_core_signal (SIM_DESC sd,
2463 sim_cpu *cpu,
2464 sim_cia cia,
2465 unsigned map,
2466 int nr_bytes,
2467 address_word addr,
2468 transfer_type transfer,
2469 sim_core_signals sig)
2470 {
2471 const char *copy = (transfer == read_transfer ? "read" : "write");
2472 address_word ip = CIA_ADDR (cia);
2473
2474 switch (sig)
2475 {
2476 case sim_core_unmapped_signal:
2477 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2478 nr_bytes, copy,
2479 (unsigned long) addr, (unsigned long) ip);
2480 COP0_BADVADDR = addr;
2481 SignalExceptionDataReference();
2482 break;
2483
2484 case sim_core_unaligned_signal:
2485 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2486 nr_bytes, copy,
2487 (unsigned long) addr, (unsigned long) ip);
2488 COP0_BADVADDR = addr;
2489 if(transfer == read_transfer)
2490 SignalExceptionAddressLoad();
2491 else
2492 SignalExceptionAddressStore();
2493 break;
2494
2495 default:
2496 sim_engine_abort (sd, cpu, cia,
2497 "mips_core_signal - internal error - bad switch");
2498 }
2499 }
2500
2501
2502 void
2503 mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2504 {
2505 ASSERT(cpu != NULL);
2506
2507 if(cpu->exc_suspended > 0)
2508 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2509
2510 PC = cia;
2511 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2512 cpu->exc_suspended = 0;
2513 }
2514
2515 void
2516 mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2517 {
2518 ASSERT(cpu != NULL);
2519
2520 if(cpu->exc_suspended > 0)
2521 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2522 cpu->exc_suspended, exception);
2523
2524 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2525 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2526 cpu->exc_suspended = exception;
2527 }
2528
2529 void
2530 mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2531 {
2532 ASSERT(cpu != NULL);
2533
2534 if(exception == 0 && cpu->exc_suspended > 0)
2535 {
2536 /* warn not for breakpoints */
2537 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2538 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2539 cpu->exc_suspended);
2540 }
2541 else if(exception != 0 && cpu->exc_suspended > 0)
2542 {
2543 if(exception != cpu->exc_suspended)
2544 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2545 cpu->exc_suspended, exception);
2546
2547 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2548 }
2549 else if(exception != 0 && cpu->exc_suspended == 0)
2550 {
2551 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2552 }
2553 cpu->exc_suspended = 0;
2554 }
2555
2556
2557 /*---------------------------------------------------------------------------*/
2558 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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