2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
41 /* start-sanitize-sky */
45 #include "sky-libvpe.h"
51 /* end-sanitize-sky */
73 #include "libiberty.h"
75 #include "callback.h" /* GDB simulator callback interface */
76 #include "remote-sim.h" /* GDB simulator interface */
84 char* pr_addr
PARAMS ((SIM_ADDR addr
));
85 char* pr_uword64
PARAMS ((uword64 addr
));
88 /* Get the simulator engine description, without including the code: */
95 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
100 /* The following reserved instruction value is used when a simulator
101 trap is required. NOTE: Care must be taken, since this value may be
102 used in later revisions of the MIPS ISA. */
103 #define RSVD_INSTRUCTION (0x00000005)
104 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
106 #define RSVD_INSTRUCTION_ARG_SHIFT 6
107 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
110 /* Bits in the Debug register */
111 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
112 #define Debug_DM 0x40000000 /* Debug Mode */
113 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
119 /*---------------------------------------------------------------------------*/
120 /*-- GDB simulator interface ------------------------------------------------*/
121 /*---------------------------------------------------------------------------*/
123 static void ColdReset
PARAMS((SIM_DESC sd
));
125 /*---------------------------------------------------------------------------*/
129 #define DELAYSLOT() {\
130 if (STATE & simDELAYSLOT)\
131 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
132 STATE |= simDELAYSLOT;\
135 #define JALDELAYSLOT() {\
137 STATE |= simJALDELAYSLOT;\
141 STATE &= ~simDELAYSLOT;\
142 STATE |= simSKIPNEXT;\
145 #define CANCELDELAYSLOT() {\
147 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
150 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
151 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
153 #define K0BASE (0x80000000)
154 #define K0SIZE (0x20000000)
155 #define K1BASE (0xA0000000)
156 #define K1SIZE (0x20000000)
157 #define MONITOR_BASE (0xBFC00000)
158 #define MONITOR_SIZE (1 << 11)
159 #define MEM_SIZE (2 << 20)
161 /* start-sanitize-sky */
164 #define MEM_SIZE (16 << 20) /* 16 MB */
166 /* end-sanitize-sky */
169 static char *tracefile
= "trace.din"; /* default filename for trace log */
170 FILE *tracefh
= NULL
;
171 static void open_trace
PARAMS((SIM_DESC sd
));
174 static DECLARE_OPTION_HANDLER (mips_option_handler
);
177 OPTION_DINERO_TRACE
= OPTION_START
,
179 /* start-sanitize-sky */
181 /* end-sanitize-sky */
185 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
195 case OPTION_DINERO_TRACE
: /* ??? */
197 /* Eventually the simTRACE flag could be treated as a toggle, to
198 allow external control of the program points being traced
199 (i.e. only from main onwards, excluding the run-time setup,
201 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
203 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
206 else if (strcmp (arg
, "yes") == 0)
208 else if (strcmp (arg
, "no") == 0)
210 else if (strcmp (arg
, "on") == 0)
212 else if (strcmp (arg
, "off") == 0)
216 fprintf (stderr
, "Unrecognized dinero-trace option `%s'\n", arg
);
223 Simulator constructed without dinero tracing support (for performance).\n\
224 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
228 case OPTION_DINERO_FILE
:
230 if (optarg
!= NULL
) {
232 tmp
= (char *)malloc(strlen(optarg
) + 1);
235 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
241 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
247 /* start-sanitize-sky */
248 case OPTION_FLOAT_TYPE
:
249 /* Use host (fast) or target (accurate) floating point implementation. */
250 if (arg
&& strcmp (arg
, "host") == 0)
251 STATE_FP_TYPE_OPT (sd
) &= ~STATE_FP_TYPE_OPT_TARGET
;
252 else if (arg
&& strcmp (arg
, "target") == 0)
253 STATE_FP_TYPE_OPT (sd
) |= STATE_FP_TYPE_OPT_TARGET
;
256 fprintf (stderr
, "Unrecognized float-type option `%s'\n", arg
);
260 /* end-sanitize-sky */
266 static const OPTION mips_options
[] =
268 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
269 '\0', "on|off", "Enable dinero tracing",
270 mips_option_handler
},
271 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
272 '\0', "FILE", "Write dinero trace to FILE",
273 mips_option_handler
},
274 /* start-sanitize-sky */
275 { {"float-type", required_argument
, NULL
, OPTION_FLOAT_TYPE
},
276 '\0', "host|target", "Use host (fast) or target (accurate) floating point",
277 mips_option_handler
},
278 /* end-sanitize-sky */
279 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
283 int interrupt_pending
;
286 interrupt_event (SIM_DESC sd
, void *data
)
288 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
291 interrupt_pending
= 0;
292 SignalExceptionInterrupt ();
294 else if (!interrupt_pending
)
295 sim_events_schedule (sd
, 1, interrupt_event
, data
);
299 /*---------------------------------------------------------------------------*/
300 /*-- Device registration hook -----------------------------------------------*/
301 /*---------------------------------------------------------------------------*/
302 static void device_init(SIM_DESC sd
) {
304 extern void register_devices(SIM_DESC
);
305 register_devices(sd
);
309 /*---------------------------------------------------------------------------*/
310 /*-- GDB simulator interface ------------------------------------------------*/
311 /*---------------------------------------------------------------------------*/
314 sim_open (kind
, cb
, abfd
, argv
)
320 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
321 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
323 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
325 /* FIXME: watchpoints code shouldn't need this */
326 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
327 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
328 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
332 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
334 sim_add_option_table (sd
, NULL
, mips_options
);
336 /* Allocate core managed memory */
339 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
340 /* For compatibility with the old code - under this (at level one)
341 are the kernel spaces K0 & K1. Both of these map to a single
342 smaller sub region */
343 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
344 /* start-sanitize-sky */
346 /* end-sanitize-sky */
347 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
349 MEM_SIZE
, /* actual size */
351 /* start-sanitize-sky */
353 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
355 MEM_SIZE
, /* actual size */
357 0); /* add alias at 0x0000 */
359 /* end-sanitize-sky */
363 /* getopt will print the error message so we just have to exit if this fails.
364 FIXME: Hmmm... in the case of gdb we need getopt to call
366 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
368 /* Uninstall the modules to avoid memory leaks,
369 file descriptor leaks, etc. */
370 sim_module_uninstall (sd
);
374 /* check for/establish the a reference program image */
375 if (sim_analyze_program (sd
,
376 (STATE_PROG_ARGV (sd
) != NULL
377 ? *STATE_PROG_ARGV (sd
)
381 sim_module_uninstall (sd
);
385 /* Configure/verify the target byte order and other runtime
386 configuration options */
387 if (sim_config (sd
) != SIM_RC_OK
)
389 sim_module_uninstall (sd
);
393 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
395 /* Uninstall the modules to avoid memory leaks,
396 file descriptor leaks, etc. */
397 sim_module_uninstall (sd
);
401 /* verify assumptions the simulator made about the host type system.
402 This macro does not return if there is a problem */
403 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
404 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
406 /* This is NASTY, in that we are assuming the size of specific
410 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
413 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
414 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
415 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
416 else if ((rn
>= 33) && (rn
<= 37))
417 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
418 else if ((rn
== SRIDX
)
421 || ((rn
>= 72) && (rn
<= 89)))
422 cpu
->register_widths
[rn
] = 32;
424 cpu
->register_widths
[rn
] = 0;
426 /* start-sanitize-r5900 */
428 /* set the 5900 "upper" registers to 64 bits */
429 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
430 cpu
->register_widths
[rn
] = 64;
431 /* end-sanitize-r5900 */
433 /* start-sanitize-sky */
435 /* Now the VU registers */
436 for( rn
= 0; rn
< NUM_VU_INTEGER_REGS
; rn
++ ) {
437 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 16;
438 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 16;
441 for( rn
= NUM_VU_INTEGER_REGS
; rn
< NUM_VU_REGS
; rn
++ ) {
442 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
443 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 32;
446 /* Finally the VIF registers */
447 for( rn
= 2*NUM_VU_REGS
; rn
< 2*NUM_VU_REGS
+ 2*NUM_VIF_REGS
; rn
++ )
448 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
450 /* end-sanitize-sky */
454 if (STATE
& simTRACE
)
458 /* Write the monitor trap address handlers into the monitor (eeprom)
459 address space. This can only be done once the target endianness
460 has been determined. */
463 /* Entry into the IDT monitor is via fixed address vectors, and
464 not using machine instructions. To avoid clashing with use of
465 the MIPS TRAP system, we place our own (simulator specific)
466 "undefined" instructions into the relevant vector slots. */
467 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
469 address_word vaddr
= (MONITOR_BASE
+ loop
);
470 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
472 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
474 /* The PMON monitor uses the same address space, but rather than
475 branching into it the address of a routine is loaded. We can
476 cheat for the moment, and direct the PMON routine to IDT style
477 instructions within the monitor space. This relies on the IDT
478 monitor not using the locations from 0xBFC00500 onwards as its
480 for (loop
= 0; (loop
< 24); loop
++)
482 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
483 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
499 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
501 case 8: /* cliexit */
504 case 11: /* flush_cache */
508 /* FIXME - should monitor_base be SIM_ADDR?? */
509 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
511 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
513 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
515 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
527 tracefh
= fopen(tracefile
,"wb+");
530 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
537 sim_close (sd
, quitting
)
542 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
545 /* "quitting" is non-zero if we cannot hang on errors */
547 /* Ensure that any resources allocated through the callback
548 mechanism are released: */
549 sim_io_shutdown (sd
);
552 if (tracefh
!= NULL
&& tracefh
!= stderr
)
557 /* FIXME - free SD */
564 sim_write (sd
,addr
,buffer
,size
)
567 unsigned char *buffer
;
571 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
573 /* Return the number of bytes written, or zero if error. */
575 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
578 /* We use raw read and write routines, since we do not want to count
579 the GDB memory accesses in our statistics gathering. */
581 for (index
= 0; index
< size
; index
++)
583 address_word vaddr
= (address_word
)addr
+ index
;
586 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
588 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
596 sim_read (sd
,addr
,buffer
,size
)
599 unsigned char *buffer
;
603 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
605 /* Return the number of bytes read, or zero if error. */
607 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
610 for (index
= 0; (index
< size
); index
++)
612 address_word vaddr
= (address_word
)addr
+ index
;
615 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
617 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
625 sim_store_register (sd
,rn
,memory
,length
)
628 unsigned char *memory
;
631 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
632 /* NOTE: gdb (the client) stores registers in target byte order
633 while the simulator uses host byte order */
635 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
638 /* Unfortunately this suffers from the same problem as the register
639 numbering one. We need to know what the width of each logical
640 register number is for the architecture being simulated. */
642 if (cpu
->register_widths
[rn
] == 0)
644 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
648 /* start-sanitize-r5900 */
649 if (rn
>= 90 && rn
< 90 + 32)
651 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
657 SA
= T2H_8(*(unsigned64
*)memory
);
659 case 122: /* FIXME */
660 LO1
= T2H_8(*(unsigned64
*)memory
);
662 case 123: /* FIXME */
663 HI1
= T2H_8(*(unsigned64
*)memory
);
666 /* end-sanitize-r5900 */
668 /* start-sanitize-sky */
670 if (rn
>= NUM_R5900_REGS
)
672 rn
= rn
- NUM_R5900_REGS
;
674 if( rn
< NUM_VU_REGS
)
676 if (rn
< NUM_VU_INTEGER_REGS
)
677 return write_vu_int_reg (&(vu0_device
.regs
), rn
, memory
);
678 else if (rn
>= FIRST_VEC_REG
)
681 return write_vu_vec_reg (&(vu0_device
.regs
), rn
>>2, rn
&3,
684 else switch (rn
- NUM_VU_INTEGER_REGS
)
687 return write_vu_special_reg (&vu0_device
, VU_REG_CIA
,
690 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MR
,
692 case 2: /* VU0 has no P register */
695 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MI
,
698 return write_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MQ
,
701 return write_vu_acc_reg (&(vu0_device
.regs
),
702 rn
- (NUM_VU_INTEGER_REGS
+ 5),
707 rn
= rn
- NUM_VU_REGS
;
709 if (rn
< NUM_VU_REGS
)
711 if (rn
< NUM_VU_INTEGER_REGS
)
712 return write_vu_int_reg (&(vu1_device
.regs
), rn
, memory
);
713 else if (rn
>= FIRST_VEC_REG
)
716 return write_vu_vec_reg (&(vu1_device
.regs
),
717 rn
>> 2, rn
& 3, memory
);
719 else switch (rn
- NUM_VU_INTEGER_REGS
)
722 return write_vu_special_reg (&vu1_device
, VU_REG_CIA
,
725 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MR
,
728 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MP
,
731 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MI
,
734 return write_vu_misc_reg (&(vu1_device
.regs
), VU_REG_MQ
,
737 return write_vu_acc_reg (&(vu1_device
.regs
),
738 rn
- (NUM_VU_INTEGER_REGS
+ 5),
743 rn
-= NUM_VU_REGS
; /* VIF0 registers are next */
745 if (rn
< NUM_VIF_REGS
)
747 if (rn
< NUM_VIF_REGS
-1)
748 return write_pke_reg (&pke0_device
, rn
, memory
);
751 sim_io_eprintf( sd
, "Can't write vif0_pc (store ignored)\n" );
756 rn
-= NUM_VIF_REGS
; /* VIF1 registers are last */
758 if (rn
< NUM_VIF_REGS
)
760 if (rn
< NUM_VIF_REGS
-1)
761 return write_pke_reg (&pke1_device
, rn
, memory
);
764 sim_io_eprintf( sd
, "Can't write vif1_pc (store ignored)\n" );
769 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
773 /* end-sanitize-sky */
775 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
777 if (cpu
->register_widths
[rn
] == 32)
779 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
784 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
789 if (cpu
->register_widths
[rn
] == 32)
791 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
796 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
804 sim_fetch_register (sd
,rn
,memory
,length
)
807 unsigned char *memory
;
810 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
811 /* NOTE: gdb (the client) stores registers in target byte order
812 while the simulator uses host byte order */
814 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
817 if (cpu
->register_widths
[rn
] == 0)
819 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
823 /* start-sanitize-r5900 */
824 if (rn
>= 90 && rn
< 90 + 32)
826 *(unsigned64
*)memory
= GPR1
[rn
- 90];
832 *((unsigned64
*)memory
) = H2T_8(SA
);
834 case 122: /* FIXME */
835 *((unsigned64
*)memory
) = H2T_8(LO1
);
837 case 123: /* FIXME */
838 *((unsigned64
*)memory
) = H2T_8(HI1
);
841 /* end-sanitize-r5900 */
843 /* start-sanitize-sky */
845 if (rn
>= NUM_R5900_REGS
)
847 rn
= rn
- NUM_R5900_REGS
;
849 if (rn
< NUM_VU_REGS
)
851 if (rn
< NUM_VU_INTEGER_REGS
)
852 return read_vu_int_reg (&(vu0_device
.regs
), rn
, memory
);
853 else if (rn
>= FIRST_VEC_REG
)
856 return read_vu_vec_reg (&(vu0_device
.regs
), rn
>>2, rn
& 3,
859 else switch (rn
- NUM_VU_INTEGER_REGS
)
862 return read_vu_special_reg(&vu0_device
, VU_REG_CIA
, memory
);
864 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MR
,
866 case 2: /* VU0 has no P register */
867 *((int *) memory
) = 0;
870 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MI
,
873 return read_vu_misc_reg (&(vu0_device
.regs
), VU_REG_MQ
,
876 return read_vu_acc_reg (&(vu0_device
.regs
),
877 rn
- (NUM_VU_INTEGER_REGS
+ 5),
882 rn
-= NUM_VU_REGS
; /* VU1 registers are next */
884 if (rn
< NUM_VU_REGS
)
886 if (rn
< NUM_VU_INTEGER_REGS
)
887 return read_vu_int_reg (&(vu1_device
.regs
), rn
, memory
);
888 else if (rn
>= FIRST_VEC_REG
)
891 return read_vu_vec_reg (&(vu1_device
.regs
),
892 rn
>> 2, rn
& 3, memory
);
894 else switch (rn
- NUM_VU_INTEGER_REGS
)
897 return read_vu_special_reg(&vu1_device
, VU_REG_CIA
, memory
);
899 return read_vu_misc_reg (&(vu1_device
.regs
),
902 return read_vu_misc_reg (&(vu1_device
.regs
),
905 return read_vu_misc_reg (&(vu1_device
.regs
),
908 return read_vu_misc_reg (&(vu1_device
.regs
),
911 return read_vu_acc_reg (&(vu1_device
.regs
),
912 rn
- (NUM_VU_INTEGER_REGS
+ 5),
917 rn
-= NUM_VU_REGS
; /* VIF0 registers are next */
919 if (rn
< NUM_VIF_REGS
)
921 if (rn
< NUM_VIF_REGS
-1)
922 return read_pke_reg (&pke0_device
, rn
, memory
);
924 return read_pke_pc (&pke0_device
, memory
);
927 rn
-= NUM_VIF_REGS
; /* VIF1 registers are last */
929 if (rn
< NUM_VIF_REGS
)
931 if (rn
< NUM_VIF_REGS
-1)
932 return read_pke_reg (&pke1_device
, rn
, memory
);
934 return read_pke_pc (&pke1_device
, memory
);
937 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
940 /* end-sanitize-sky */
942 /* Any floating point register */
943 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
945 if (cpu
->register_widths
[rn
] == 32)
947 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
952 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
957 if (cpu
->register_widths
[rn
] == 32)
959 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
964 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
973 sim_create_inferior (sd
, abfd
, argv
,env
)
981 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
989 /* override PC value set by ColdReset () */
991 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
993 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
994 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
998 #if 0 /* def DEBUG */
1001 /* We should really place the argv slot values into the argument
1002 registers, and onto the stack as required. However, this
1003 assumes that we have a stack defined, which is not
1004 necessarily true at the moment. */
1006 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
1007 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1008 printf("DBG: arg \"%s\"\n",*cptr
);
1016 sim_do_command (sd
,cmd
)
1020 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
1021 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1025 /*---------------------------------------------------------------------------*/
1026 /*-- Private simulator support interface ------------------------------------*/
1027 /*---------------------------------------------------------------------------*/
1029 /* Read a null terminated string from memory, return in a buffer */
1031 fetch_str (sd
, addr
)
1038 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
1040 buf
= NZALLOC (char, nr
+ 1);
1041 sim_read (sd
, addr
, buf
, nr
);
1045 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1047 sim_monitor (SIM_DESC sd
,
1050 unsigned int reason
)
1053 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1056 /* The IDT monitor actually allows two instructions per vector
1057 slot. However, the simulator currently causes a trap on each
1058 individual instruction. We cheat, and lose the bottom bit. */
1061 /* The following callback functions are available, however the
1062 monitor we are simulating does not make use of them: get_errno,
1063 isatty, lseek, rename, system, time and unlink */
1067 case 6: /* int open(char *path,int flags) */
1069 char *path
= fetch_str (sd
, A0
);
1070 V0
= sim_io_open (sd
, path
, (int)A1
);
1075 case 7: /* int read(int file,char *ptr,int len) */
1079 char *buf
= zalloc (nr
);
1080 V0
= sim_io_read (sd
, fd
, buf
, nr
);
1081 sim_write (sd
, A1
, buf
, nr
);
1086 case 8: /* int write(int file,char *ptr,int len) */
1090 char *buf
= zalloc (nr
);
1091 sim_read (sd
, A1
, buf
, nr
);
1092 V0
= sim_io_write (sd
, fd
, buf
, nr
);
1097 case 10: /* int close(int file) */
1099 V0
= sim_io_close (sd
, (int)A0
);
1103 case 2: /* Densan monitor: char inbyte(int waitflag) */
1105 if (A0
== 0) /* waitflag == NOWAIT */
1106 V0
= (unsigned_word
)-1;
1108 /* Drop through to case 11 */
1110 case 11: /* char inbyte(void) */
1113 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
1115 sim_io_error(sd
,"Invalid return from character read");
1116 V0
= (unsigned_word
)-1;
1119 V0
= (unsigned_word
)tmp
;
1123 case 3: /* Densan monitor: void co(char chr) */
1124 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1126 char tmp
= (char)(A0
& 0xFF);
1127 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
1131 case 17: /* void _exit() */
1133 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
1134 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
1135 (unsigned int)(A0
& 0xFFFFFFFF));
1139 case 28 : /* PMON flush_cache */
1142 case 55: /* void get_mem_info(unsigned int *ptr) */
1143 /* in: A0 = pointer to three word memory location */
1144 /* out: [A0 + 0] = size */
1145 /* [A0 + 4] = instruction cache size */
1146 /* [A0 + 8] = data cache size */
1148 unsigned_4 value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1149 unsigned_4 zero
= 0;
1151 sim_write (sd
, A0
+ 0, (char *)&value
, 4);
1152 sim_write (sd
, A0
+ 4, (char *)&zero
, 4);
1153 sim_write (sd
, A0
+ 8, (char *)&zero
, 4);
1154 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1158 case 158 : /* PMON printf */
1159 /* in: A0 = pointer to format string */
1160 /* A1 = optional argument 1 */
1161 /* A2 = optional argument 2 */
1162 /* A3 = optional argument 3 */
1164 /* The following is based on the PMON printf source */
1166 address_word s
= A0
;
1168 signed_word
*ap
= &A1
; /* 1st argument */
1169 /* This isn't the quickest way, since we call the host print
1170 routine for every character almost. But it does avoid
1171 having to allocate and manage a temporary string buffer. */
1172 /* TODO: Include check that we only use three arguments (A1,
1174 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1179 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1180 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1181 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1183 if (strchr ("dobxXulscefg%", s
))
1198 else if (c
>= '1' && c
<= '9')
1202 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1205 n
= (unsigned int)strtol(tmp
,NULL
,10);
1218 sim_io_printf (sd
, "%%");
1223 address_word p
= *ap
++;
1225 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1226 sim_io_printf(sd
, "%c", ch
);
1229 sim_io_printf(sd
,"(null)");
1232 sim_io_printf (sd
, "%c", (int)*ap
++);
1237 sim_read (sd
, s
++, &c
, 1);
1241 sim_read (sd
, s
++, &c
, 1);
1244 if (strchr ("dobxXu", c
))
1246 word64 lv
= (word64
) *ap
++;
1248 sim_io_printf(sd
,"<binary not supported>");
1251 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1253 sim_io_printf(sd
, tmp
, lv
);
1255 sim_io_printf(sd
, tmp
, (int)lv
);
1258 else if (strchr ("eEfgG", c
))
1260 double dbl
= *(double*)(ap
++);
1261 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1262 sim_io_printf (sd
, tmp
, dbl
);
1268 sim_io_printf(sd
, "%c", c
);
1274 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1275 reason
, pr_addr(cia
));
1281 /* Store a word into memory. */
1284 store_word (SIM_DESC sd
,
1293 if ((vaddr
& 3) != 0)
1294 SignalExceptionAddressStore ();
1297 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1300 const uword64 mask
= 7;
1304 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1305 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1306 memval
= ((uword64
) val
) << (8 * byte
);
1307 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1313 /* Load a word from memory. */
1316 load_word (SIM_DESC sd
,
1321 if ((vaddr
& 3) != 0)
1322 SignalExceptionAddressLoad ();
1328 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1331 const uword64 mask
= 0x7;
1332 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1333 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1337 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1338 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1340 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1341 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1348 /* Simulate the mips16 entry and exit pseudo-instructions. These
1349 would normally be handled by the reserved instruction exception
1350 code, but for ease of simulation we just handle them directly. */
1353 mips16_entry (SIM_DESC sd
,
1358 int aregs
, sregs
, rreg
;
1361 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1364 aregs
= (insn
& 0x700) >> 8;
1365 sregs
= (insn
& 0x0c0) >> 6;
1366 rreg
= (insn
& 0x020) >> 5;
1368 /* This should be checked by the caller. */
1377 /* This is the entry pseudo-instruction. */
1379 for (i
= 0; i
< aregs
; i
++)
1380 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1388 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1391 for (i
= 0; i
< sregs
; i
++)
1394 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1402 /* This is the exit pseudo-instruction. */
1409 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1412 for (i
= 0; i
< sregs
; i
++)
1415 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1420 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1424 FGR
[0] = WORD64LO (GPR
[4]);
1425 FPR_STATE
[0] = fmt_uninterpreted
;
1427 else if (aregs
== 6)
1429 FGR
[0] = WORD64LO (GPR
[5]);
1430 FGR
[1] = WORD64LO (GPR
[4]);
1431 FPR_STATE
[0] = fmt_uninterpreted
;
1432 FPR_STATE
[1] = fmt_uninterpreted
;
1441 /*-- trace support ----------------------------------------------------------*/
1443 /* The TRACE support is provided (if required) in the memory accessing
1444 routines. Since we are also providing the architecture specific
1445 features, the architecture simulation code can also deal with
1446 notifying the TRACE world of cache flushes, etc. Similarly we do
1447 not need to provide profiling support in the simulator engine,
1448 since we can sample in the instruction fetch control loop. By
1449 defining the TRACE manifest, we add tracing as a run-time
1453 /* Tracing by default produces "din" format (as required by
1454 dineroIII). Each line of such a trace file *MUST* have a din label
1455 and address field. The rest of the line is ignored, so comments can
1456 be included if desired. The first field is the label which must be
1457 one of the following values:
1462 3 escape record (treated as unknown access type)
1463 4 escape record (causes cache flush)
1465 The address field is a 32bit (lower-case) hexadecimal address
1466 value. The address should *NOT* be preceded by "0x".
1468 The size of the memory transfer is not important when dealing with
1469 cache lines (as long as no more than a cache line can be
1470 transferred in a single operation :-), however more information
1471 could be given following the dineroIII requirement to allow more
1472 complete memory and cache simulators to provide better
1473 results. i.e. the University of Pisa has a cache simulator that can
1474 also take bus size and speed as (variable) inputs to calculate
1475 complete system performance (a much more useful ability when trying
1476 to construct an end product, rather than a processor). They
1477 currently have an ARM version of their tool called ChARM. */
1481 dotrace (SIM_DESC sd
,
1489 if (STATE
& simTRACE
) {
1491 fprintf(tracefh
,"%d %s ; width %d ; ",
1495 va_start(ap
,comment
);
1496 vfprintf(tracefh
,comment
,ap
);
1498 fprintf(tracefh
,"\n");
1500 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1501 we may be generating 64bit ones, we should put the hi-32bits of the
1502 address into the comment field. */
1504 /* TODO: Provide a buffer for the trace lines. We can then avoid
1505 performing writes until the buffer is filled, or the file is
1508 /* NOTE: We could consider adding a comment field to the "din" file
1509 produced using type 3 markers (unknown access). This would then
1510 allow information about the program that the "din" is for, and
1511 the MIPs world that was being simulated, to be placed into the
1518 /*---------------------------------------------------------------------------*/
1519 /*-- simulator engine -------------------------------------------------------*/
1520 /*---------------------------------------------------------------------------*/
1523 ColdReset (SIM_DESC sd
)
1526 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1528 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1529 /* RESET: Fixed PC address: */
1530 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1531 /* The reset vector address is in the unmapped, uncached memory space. */
1533 SR
&= ~(status_SR
| status_TS
| status_RP
);
1534 SR
|= (status_ERL
| status_BEV
);
1536 /* Cheat and allow access to the complete register set immediately */
1537 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1538 && WITH_TARGET_WORD_BITSIZE
== 64)
1539 SR
|= status_FR
; /* 64bit registers */
1541 /* Ensure that any instructions with pending register updates are
1543 PENDING_INVALIDATE();
1545 /* Initialise the FPU registers to the unknown state */
1546 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1549 for (rn
= 0; (rn
< 32); rn
++)
1550 FPR_STATE
[rn
] = fmt_uninterpreted
;
1556 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1557 /* Signal an exception condition. This will result in an exception
1558 that aborts the instruction. The instruction operation pseudocode
1559 will never see a return from this function call. */
1562 signal_exception (SIM_DESC sd
,
1570 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1573 /* Ensure that any active atomic read/modify/write operation will fail: */
1576 switch (exception
) {
1577 /* TODO: For testing purposes I have been ignoring TRAPs. In
1578 reality we should either simulate them, or allow the user to
1579 ignore them at run-time.
1582 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1588 unsigned int instruction
;
1591 va_start(ap
,exception
);
1592 instruction
= va_arg(ap
,unsigned int);
1595 code
= (instruction
>> 6) & 0xFFFFF;
1597 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1598 code
, pr_addr(cia
));
1602 case DebugBreakPoint
:
1603 if (! (Debug
& Debug_DM
))
1609 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1610 DEPC
= cia
- 4; /* reference the branch instruction */
1614 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1618 Debug
|= Debug_DM
; /* in debugging mode */
1619 Debug
|= Debug_DBp
; /* raising a DBp exception */
1621 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1625 case ReservedInstruction
:
1628 unsigned int instruction
;
1629 va_start(ap
,exception
);
1630 instruction
= va_arg(ap
,unsigned int);
1632 /* Provide simple monitor support using ReservedInstruction
1633 exceptions. The following code simulates the fixed vector
1634 entry points into the IDT monitor by causing a simulator
1635 trap, performing the monitor operation, and returning to
1636 the address held in the $ra register (standard PCS return
1637 address). This means we only need to pre-load the vector
1638 space with suitable instruction values. For systems were
1639 actual trap instructions are used, we would not need to
1640 perform this magic. */
1641 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1643 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1644 /* NOTE: This assumes that a branch-and-link style
1645 instruction was used to enter the vector (which is the
1646 case with the current IDT monitor). */
1647 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1649 /* Look for the mips16 entry and exit instructions, and
1650 simulate a handler for them. */
1651 else if ((cia
& 1) != 0
1652 && (instruction
& 0xf81f) == 0xe809
1653 && (instruction
& 0x0c0) != 0x0c0)
1655 mips16_entry (SD
, CPU
, cia
, instruction
);
1656 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1658 /* else fall through to normal exception processing */
1659 sim_io_eprintf(sd
,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia
));
1664 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1666 /* Keep a copy of the current A0 in-case this is the program exit
1670 unsigned int instruction
;
1671 va_start(ap
,exception
);
1672 instruction
= va_arg(ap
,unsigned int);
1674 /* Check for our special terminating BREAK: */
1675 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1676 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1677 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1680 if (STATE
& simDELAYSLOT
)
1681 PC
= cia
- 4; /* reference the branch instruction */
1684 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1685 sim_stopped
, SIM_SIGTRAP
);
1688 /* Store exception code into current exception id variable (used
1691 /* TODO: If not simulating exceptions then stop the simulator
1692 execution. At the moment we always stop the simulation. */
1694 /* See figure 5-17 for an outline of the code below */
1695 if (! (SR
& status_EXL
))
1697 CAUSE
= (exception
<< 2);
1698 if (STATE
& simDELAYSLOT
)
1700 STATE
&= ~simDELAYSLOT
;
1702 EPC
= (cia
- 4); /* reference the branch instruction */
1706 /* FIXME: TLB et.al. */
1711 CAUSE
= (exception
<< 2);
1715 /* Store exception code into current exception id variable (used
1717 if (SR
& status_BEV
)
1718 PC
= (signed)0xBFC00200 + 0x180;
1720 PC
= (signed)0x80000000 + 0x180;
1722 switch ((CAUSE
>> 2) & 0x1F)
1725 /* Interrupts arrive during event processing, no need to
1729 case TLBModification
:
1734 case InstructionFetch
:
1736 /* The following is so that the simulator will continue from the
1737 exception address on breakpoint operations. */
1739 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1740 sim_stopped
, SIM_SIGBUS
);
1742 case ReservedInstruction
:
1743 case CoProcessorUnusable
:
1745 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1746 sim_stopped
, SIM_SIGILL
);
1748 case IntegerOverflow
:
1750 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1751 sim_stopped
, SIM_SIGFPE
);
1757 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1758 sim_stopped
, SIM_SIGTRAP
);
1762 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1763 "FATAL: Should not encounter a breakpoint\n");
1765 default : /* Unknown internal exception */
1767 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1768 sim_stopped
, SIM_SIGABRT
);
1772 case SimulatorFault
:
1776 va_start(ap
,exception
);
1777 msg
= va_arg(ap
,char *);
1779 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1780 "FATAL: Simulator error \"%s\"\n",msg
);
1787 #if defined(WARN_RESULT)
1788 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1789 /* This function indicates that the result of the operation is
1790 undefined. However, this should not affect the instruction
1791 stream. All that is meant to happen is that the destination
1792 register is set to an undefined result. To keep the simulator
1793 simple, we just don't bother updating the destination register, so
1794 the overall result will be undefined. If desired we can stop the
1795 simulator by raising a pseudo-exception. */
1796 #define UndefinedResult() undefined_result (sd,cia)
1798 undefined_result(sd
,cia
)
1802 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1803 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1808 #endif /* WARN_RESULT */
1810 /*-- FPU support routines ---------------------------------------------------*/
1812 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1813 formats conform to ANSI/IEEE Std 754-1985. */
1814 /* SINGLE precision floating:
1815 * seeeeeeeefffffffffffffffffffffff
1817 * e = 8bits = exponent
1818 * f = 23bits = fraction
1820 /* SINGLE precision fixed:
1821 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1823 * i = 31bits = integer
1825 /* DOUBLE precision floating:
1826 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1828 * e = 11bits = exponent
1829 * f = 52bits = fraction
1831 /* DOUBLE precision fixed:
1832 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1834 * i = 63bits = integer
1837 /* Extract sign-bit: */
1838 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1839 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1840 /* Extract biased exponent: */
1841 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1842 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1843 /* Extract unbiased Exponent: */
1844 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1845 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1846 /* Extract complete fraction field: */
1847 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1848 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1849 /* Extract numbered fraction bit: */
1850 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1851 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1853 /* Explicit QNaN values used when value required: */
1854 #define FPQNaN_SINGLE (0x7FBFFFFF)
1855 #define FPQNaN_WORD (0x7FFFFFFF)
1856 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1857 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1859 /* Explicit Infinity values used when required: */
1860 #define FPINF_SINGLE (0x7F800000)
1861 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1863 #if 1 /* def DEBUG */
1864 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1865 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1869 value_fpr (SIM_DESC sd
,
1878 /* Treat unused register values, as fixed-point 64bit values: */
1879 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1881 /* If request to read data as "uninterpreted", then use the current
1883 fmt
= FPR_STATE
[fpr
];
1888 /* For values not yet accessed, set to the desired format: */
1889 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1890 FPR_STATE
[fpr
] = fmt
;
1892 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1895 if (fmt
!= FPR_STATE
[fpr
]) {
1896 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1897 FPR_STATE
[fpr
] = fmt_unknown
;
1900 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1901 /* Set QNaN value: */
1904 value
= FPQNaN_SINGLE
;
1908 value
= FPQNaN_DOUBLE
;
1912 value
= FPQNaN_WORD
;
1916 value
= FPQNaN_LONG
;
1923 } else if (SizeFGR() == 64) {
1927 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1930 case fmt_uninterpreted
:
1944 value
= (FGR
[fpr
] & 0xFFFFFFFF);
1947 case fmt_uninterpreted
:
1950 if ((fpr
& 1) == 0) { /* even registers only */
1951 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
1953 SignalException(ReservedInstruction
,0);
1964 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
1967 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
1974 store_fpr (SIM_DESC sd
,
1984 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
1987 if (SizeFGR() == 64) {
1989 case fmt_uninterpreted_32
:
1990 fmt
= fmt_uninterpreted
;
1993 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
1994 FPR_STATE
[fpr
] = fmt
;
1997 case fmt_uninterpreted_64
:
1998 fmt
= fmt_uninterpreted
;
1999 case fmt_uninterpreted
:
2003 FPR_STATE
[fpr
] = fmt
;
2007 FPR_STATE
[fpr
] = fmt_unknown
;
2013 case fmt_uninterpreted_32
:
2014 fmt
= fmt_uninterpreted
;
2017 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2018 FPR_STATE
[fpr
] = fmt
;
2021 case fmt_uninterpreted_64
:
2022 fmt
= fmt_uninterpreted
;
2023 case fmt_uninterpreted
:
2026 if ((fpr
& 1) == 0) { /* even register number only */
2027 FGR
[fpr
+1] = (value
>> 32);
2028 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2029 FPR_STATE
[fpr
+ 1] = fmt
;
2030 FPR_STATE
[fpr
] = fmt
;
2032 FPR_STATE
[fpr
] = fmt_unknown
;
2033 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2034 SignalException(ReservedInstruction
,0);
2039 FPR_STATE
[fpr
] = fmt_unknown
;
2044 #if defined(WARN_RESULT)
2047 #endif /* WARN_RESULT */
2050 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2053 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2070 sim_fpu_32to (&wop
, op
);
2071 boolean
= sim_fpu_is_nan (&wop
);
2078 sim_fpu_64to (&wop
, op
);
2079 boolean
= sim_fpu_is_nan (&wop
);
2083 fprintf (stderr
, "Bad switch\n");
2088 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2102 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2109 sim_fpu_32to (&wop
, op
);
2110 boolean
= sim_fpu_is_infinity (&wop
);
2116 sim_fpu_64to (&wop
, op
);
2117 boolean
= sim_fpu_is_infinity (&wop
);
2121 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2126 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2140 /* Argument checking already performed by the FPCOMPARE code */
2143 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2146 /* The format type should already have been checked: */
2152 sim_fpu_32to (&wop1
, op1
);
2153 sim_fpu_32to (&wop2
, op2
);
2154 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2161 sim_fpu_64to (&wop1
, op1
);
2162 sim_fpu_64to (&wop2
, op2
);
2163 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2167 fprintf (stderr
, "Bad switch\n");
2172 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2186 /* Argument checking already performed by the FPCOMPARE code */
2189 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2192 /* The format type should already have been checked: */
2198 sim_fpu_32to (&wop1
, op1
);
2199 sim_fpu_32to (&wop2
, op2
);
2200 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2207 sim_fpu_64to (&wop1
, op1
);
2208 sim_fpu_64to (&wop2
, op2
);
2209 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2213 fprintf (stderr
, "Bad switch\n");
2218 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2225 AbsoluteValue(op
,fmt
)
2232 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2235 /* The format type should already have been checked: */
2241 sim_fpu_32to (&wop
, op
);
2242 sim_fpu_abs (&wop
, &wop
);
2243 sim_fpu_to32 (&ans
, &wop
);
2251 sim_fpu_64to (&wop
, op
);
2252 sim_fpu_abs (&wop
, &wop
);
2253 sim_fpu_to64 (&ans
, &wop
);
2258 fprintf (stderr
, "Bad switch\n");
2273 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2276 /* The format type should already have been checked: */
2282 sim_fpu_32to (&wop
, op
);
2283 sim_fpu_neg (&wop
, &wop
);
2284 sim_fpu_to32 (&ans
, &wop
);
2292 sim_fpu_64to (&wop
, op
);
2293 sim_fpu_neg (&wop
, &wop
);
2294 sim_fpu_to64 (&ans
, &wop
);
2299 fprintf (stderr
, "Bad switch\n");
2315 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2318 /* The registers must specify FPRs valid for operands of type
2319 "fmt". If they are not valid, the result is undefined. */
2321 /* The format type should already have been checked: */
2329 sim_fpu_32to (&wop1
, op1
);
2330 sim_fpu_32to (&wop2
, op2
);
2331 sim_fpu_add (&ans
, &wop1
, &wop2
);
2332 sim_fpu_to32 (&res
, &ans
);
2342 sim_fpu_64to (&wop1
, op1
);
2343 sim_fpu_64to (&wop2
, op2
);
2344 sim_fpu_add (&ans
, &wop1
, &wop2
);
2345 sim_fpu_to64 (&res
, &ans
);
2350 fprintf (stderr
, "Bad switch\n");
2355 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2370 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2373 /* The registers must specify FPRs valid for operands of type
2374 "fmt". If they are not valid, the result is undefined. */
2376 /* The format type should already have been checked: */
2384 sim_fpu_32to (&wop1
, op1
);
2385 sim_fpu_32to (&wop2
, op2
);
2386 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2387 sim_fpu_to32 (&res
, &ans
);
2397 sim_fpu_64to (&wop1
, op1
);
2398 sim_fpu_64to (&wop2
, op2
);
2399 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2400 sim_fpu_to64 (&res
, &ans
);
2405 fprintf (stderr
, "Bad switch\n");
2410 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2417 Multiply(op1
,op2
,fmt
)
2425 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2428 /* The registers must specify FPRs valid for operands of type
2429 "fmt". If they are not valid, the result is undefined. */
2431 /* The format type should already have been checked: */
2439 sim_fpu_32to (&wop1
, op1
);
2440 sim_fpu_32to (&wop2
, op2
);
2441 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2442 sim_fpu_to32 (&res
, &ans
);
2452 sim_fpu_64to (&wop1
, op1
);
2453 sim_fpu_64to (&wop2
, op2
);
2454 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2455 sim_fpu_to64 (&res
, &ans
);
2460 fprintf (stderr
, "Bad switch\n");
2465 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2480 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2483 /* The registers must specify FPRs valid for operands of type
2484 "fmt". If they are not valid, the result is undefined. */
2486 /* The format type should already have been checked: */
2494 sim_fpu_32to (&wop1
, op1
);
2495 sim_fpu_32to (&wop2
, op2
);
2496 sim_fpu_div (&ans
, &wop1
, &wop2
);
2497 sim_fpu_to32 (&res
, &ans
);
2507 sim_fpu_64to (&wop1
, op1
);
2508 sim_fpu_64to (&wop2
, op2
);
2509 sim_fpu_div (&ans
, &wop1
, &wop2
);
2510 sim_fpu_to64 (&res
, &ans
);
2515 fprintf (stderr
, "Bad switch\n");
2520 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2534 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2537 /* The registers must specify FPRs valid for operands of type
2538 "fmt". If they are not valid, the result is undefined. */
2540 /* The format type should already have been checked: */
2547 sim_fpu_32to (&wop
, op
);
2548 sim_fpu_inv (&ans
, &wop
);
2549 sim_fpu_to32 (&res
, &ans
);
2558 sim_fpu_64to (&wop
, op
);
2559 sim_fpu_inv (&ans
, &wop
);
2560 sim_fpu_to64 (&res
, &ans
);
2565 fprintf (stderr
, "Bad switch\n");
2570 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2584 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2587 /* The registers must specify FPRs valid for operands of type
2588 "fmt". If they are not valid, the result is undefined. */
2590 /* The format type should already have been checked: */
2597 sim_fpu_32to (&wop
, op
);
2598 sim_fpu_sqrt (&ans
, &wop
);
2599 sim_fpu_to32 (&res
, &ans
);
2608 sim_fpu_64to (&wop
, op
);
2609 sim_fpu_sqrt (&ans
, &wop
);
2610 sim_fpu_to64 (&res
, &ans
);
2615 fprintf (stderr
, "Bad switch\n");
2620 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2636 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2639 /* The registers must specify FPRs valid for operands of type
2640 "fmt". If they are not valid, the result is undefined. */
2642 /* The format type should already have been checked: */
2649 sim_fpu_32to (&wop1
, op1
);
2650 sim_fpu_32to (&wop2
, op2
);
2651 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2658 sim_fpu_64to (&wop1
, op1
);
2659 sim_fpu_64to (&wop2
, op2
);
2660 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2664 fprintf (stderr
, "Bad switch\n");
2670 case SIM_FPU_IS_SNAN
:
2671 case SIM_FPU_IS_QNAN
:
2673 case SIM_FPU_IS_NINF
:
2674 case SIM_FPU_IS_NNUMBER
:
2675 case SIM_FPU_IS_NDENORM
:
2676 case SIM_FPU_IS_NZERO
:
2677 result
= op2
; /* op1 - op2 < 0 */
2678 case SIM_FPU_IS_PINF
:
2679 case SIM_FPU_IS_PNUMBER
:
2680 case SIM_FPU_IS_PDENORM
:
2681 case SIM_FPU_IS_PZERO
:
2682 result
= op1
; /* op1 - op2 > 0 */
2684 fprintf (stderr
, "Bad switch\n");
2689 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2706 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2709 /* The registers must specify FPRs valid for operands of type
2710 "fmt". If they are not valid, the result is undefined. */
2712 /* The format type should already have been checked: */
2719 sim_fpu_32to (&wop1
, op1
);
2720 sim_fpu_32to (&wop2
, op2
);
2721 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2728 sim_fpu_64to (&wop1
, op1
);
2729 sim_fpu_64to (&wop2
, op2
);
2730 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2734 fprintf (stderr
, "Bad switch\n");
2740 case SIM_FPU_IS_SNAN
:
2741 case SIM_FPU_IS_QNAN
:
2743 case SIM_FPU_IS_NINF
:
2744 case SIM_FPU_IS_NNUMBER
:
2745 case SIM_FPU_IS_NDENORM
:
2746 case SIM_FPU_IS_NZERO
:
2747 result
= op1
; /* op1 - op2 < 0 */
2748 case SIM_FPU_IS_PINF
:
2749 case SIM_FPU_IS_PNUMBER
:
2750 case SIM_FPU_IS_PDENORM
:
2751 case SIM_FPU_IS_PZERO
:
2752 result
= op2
; /* op1 - op2 > 0 */
2754 fprintf (stderr
, "Bad switch\n");
2759 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2767 convert (SIM_DESC sd
,
2776 sim_fpu_round round
;
2777 unsigned32 result32
;
2778 unsigned64 result64
;
2781 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2787 /* Round result to nearest representable value. When two
2788 representable values are equally near, round to the value
2789 that has a least significant bit of zero (i.e. is even). */
2790 round
= sim_fpu_round_near
;
2793 /* Round result to the value closest to, and not greater in
2794 magnitude than, the result. */
2795 round
= sim_fpu_round_zero
;
2798 /* Round result to the value closest to, and not less than,
2800 round
= sim_fpu_round_up
;
2804 /* Round result to the value closest to, and not greater than,
2806 round
= sim_fpu_round_down
;
2810 fprintf (stderr
, "Bad switch\n");
2814 /* Convert the input to sim_fpu internal format */
2818 sim_fpu_64to (&wop
, op
);
2821 sim_fpu_32to (&wop
, op
);
2824 sim_fpu_i32to (&wop
, op
, round
);
2827 sim_fpu_i64to (&wop
, op
, round
);
2830 fprintf (stderr
, "Bad switch\n");
2834 /* Convert sim_fpu format into the output */
2835 /* The value WOP is converted to the destination format, rounding
2836 using mode RM. When the destination is a fixed-point format, then
2837 a source value of Infinity, NaN or one which would round to an
2838 integer outside the fixed point range then an IEEE Invalid
2839 Operation condition is raised. */
2843 sim_fpu_round_32 (&wop
, round
, 0);
2844 sim_fpu_to32 (&result32
, &wop
);
2845 result64
= result32
;
2848 sim_fpu_round_64 (&wop
, round
, 0);
2849 sim_fpu_to64 (&result64
, &wop
);
2852 sim_fpu_to32i (&result32
, &wop
, round
);
2853 result64
= result32
;
2856 sim_fpu_to64i (&result64
, &wop
, round
);
2860 fprintf (stderr
, "Bad switch\n");
2865 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2872 /*-- co-processor support routines ------------------------------------------*/
2875 CoProcPresent(coproc_number
)
2876 unsigned int coproc_number
;
2878 /* Return TRUE if simulator provides a model for the given co-processor number */
2883 cop_lw (SIM_DESC sd
,
2888 unsigned int memword
)
2893 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2896 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2898 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2899 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2904 #if 0 /* this should be controlled by a configuration option */
2905 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2914 cop_ld (SIM_DESC sd
,
2921 switch (coproc_num
) {
2923 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2925 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2930 #if 0 /* this message should be controlled by a configuration option */
2931 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2940 /* start-sanitize-sky */
2943 cop_lq (SIM_DESC sd
,
2948 unsigned128 memword
)
2959 /* one word at a time, argh! */
2963 value
= H2T_4(*A4_16(& memword
, 3-i
));
2964 write_vu_vec_reg(&(vu0_device
.regs
), coproc_reg
, i
, & value
);
2970 sim_io_printf(sd
,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
2971 coproc_num
,coproc_reg
,pr_addr(cia
));
2977 #endif /* TARGET_SKY */
2978 /* end-sanitize-sky */
2982 cop_sw (SIM_DESC sd
,
2988 unsigned int value
= 0;
2993 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2996 hold
= FPR_STATE
[coproc_reg
];
2997 FPR_STATE
[coproc_reg
] = fmt_word
;
2998 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
2999 FPR_STATE
[coproc_reg
] = hold
;
3004 #if 0 /* should be controlled by configuration option */
3005 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3014 cop_sd (SIM_DESC sd
,
3024 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3026 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3031 #if 0 /* should be controlled by configuration option */
3032 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3041 /* start-sanitize-sky */
3044 cop_sq (SIM_DESC sd
,
3050 unsigned128 value
= U16_8(0, 0);
3061 /* one word at a time, argh! */
3065 read_vu_vec_reg(&(vu0_device
.regs
), coproc_reg
, i
, & value
);
3066 *A4_16(& xyzw
, 3-i
) = T2H_4(value
);
3073 sim_io_printf(sd
,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3074 coproc_num
,coproc_reg
,pr_addr(cia
));
3080 #endif /* TARGET_SKY */
3081 /* end-sanitize-sky */
3085 decode_coproc (SIM_DESC sd
,
3088 unsigned int instruction
)
3090 int coprocnum
= ((instruction
>> 26) & 3);
3094 case 0: /* standard CPU control and cache registers */
3096 int code
= ((instruction
>> 21) & 0x1F);
3097 /* R4000 Users Manual (second edition) lists the following CP0
3099 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3100 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3101 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3102 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3103 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3104 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3105 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3106 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3107 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3108 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3110 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3112 int rt
= ((instruction
>> 16) & 0x1F);
3113 int rd
= ((instruction
>> 11) & 0x1F);
3115 switch (rd
) /* NOTEs: Standard CP0 registers */
3117 /* 0 = Index R4000 VR4100 VR4300 */
3118 /* 1 = Random R4000 VR4100 VR4300 */
3119 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3120 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3121 /* 4 = Context R4000 VR4100 VR4300 */
3122 /* 5 = PageMask R4000 VR4100 VR4300 */
3123 /* 6 = Wired R4000 VR4100 VR4300 */
3124 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3125 /* 9 = Count R4000 VR4100 VR4300 */
3126 /* 10 = EntryHi R4000 VR4100 VR4300 */
3127 /* 11 = Compare R4000 VR4100 VR4300 */
3128 /* 12 = SR R4000 VR4100 VR4300 */
3135 /* 13 = Cause R4000 VR4100 VR4300 */
3142 /* 14 = EPC R4000 VR4100 VR4300 */
3143 /* 15 = PRId R4000 VR4100 VR4300 */
3144 #ifdef SUBTARGET_R3900
3153 /* 16 = Config R4000 VR4100 VR4300 */
3156 GPR
[rt
] = C0_CONFIG
;
3158 C0_CONFIG
= GPR
[rt
];
3161 #ifdef SUBTARGET_R3900
3170 /* 17 = LLAddr R4000 VR4100 VR4300 */
3172 /* 18 = WatchLo R4000 VR4100 VR4300 */
3173 /* 19 = WatchHi R4000 VR4100 VR4300 */
3174 /* 20 = XContext R4000 VR4100 VR4300 */
3175 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3176 /* 27 = CacheErr R4000 VR4100 */
3177 /* 28 = TagLo R4000 VR4100 VR4300 */
3178 /* 29 = TagHi R4000 VR4100 VR4300 */
3179 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3180 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3181 /* CPR[0,rd] = GPR[rt]; */
3184 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3186 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3189 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3192 if (SR
& status_ERL
)
3194 /* Oops, not yet available */
3195 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3205 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3209 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3217 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3218 /* TODO: When executing an ERET or RFE instruction we should
3219 clear LLBIT, to ensure that any out-standing atomic
3220 read/modify/write sequence fails. */
3224 case 2: /* co-processor 2 */
3228 /* start-sanitize-sky */
3230 /* On the R5900, this refers to a "VU" vector co-processor. */
3232 int i_25_21
= (instruction
>> 21) & 0x1f;
3233 int i_20_16
= (instruction
>> 16) & 0x1f;
3234 int i_20_6
= (instruction
>> 6) & 0x7fff;
3235 int i_15_11
= (instruction
>> 11) & 0x1f;
3236 int i_15_0
= instruction
& 0xffff;
3237 int i_10_1
= (instruction
>> 1) & 0x3ff;
3238 int i_10_0
= instruction
& 0x7ff;
3239 int i_10_6
= (instruction
>> 6) & 0x1f;
3240 int i_5_0
= instruction
& 0x03f;
3241 int interlock
= instruction
& 0x01;
3242 /* setup for semantic.c-like actions below */
3243 typedef unsigned_4 instruction_word
;
3249 /* test COP2 usability */
3250 if(! (SR
& status_CU2
))
3252 SignalException(CoProcessorUnusable
,instruction
);
3256 #define MY_INDEX itable_COPz_NORMAL
3257 #define MY_PREFIX COPz_NORMAL
3258 #define MY_NAME "COPz_NORMAL"
3260 /* classify & execute basic COP2 instructions */
3261 if(i_25_21
== 0x08 && i_20_16
== 0x00) /* BC2F */
3263 address_word offset
= EXTEND16(i_15_0
) << 2;
3264 if(! vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3266 else if(i_25_21
== 0x08 && i_20_16
==0x02) /* BC2FL */
3268 address_word offset
= EXTEND16(i_15_0
) << 2;
3269 if(! vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3270 else NULLIFY_NEXT_INSTRUCTION();
3272 else if(i_25_21
== 0x08 && i_20_16
== 0x01) /* BC2T */
3274 address_word offset
= EXTEND16(i_15_0
) << 2;
3275 if(vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3277 else if(i_25_21
== 0x08 && i_20_16
== 0x03) /* BC2TL */
3279 address_word offset
= EXTEND16(i_15_0
) << 2;
3280 if(vu0_busy()) DELAY_SLOT(cia
+ 4 + offset
);
3281 else NULLIFY_NEXT_INSTRUCTION();
3283 else if((i_25_21
== 0x02 && i_10_1
== 0x000) || /* CFC2 */
3284 (i_25_21
== 0x01)) /* QMFC2 */
3289 /* interlock checking */
3290 /* POLICY: never busy in macro mode */
3291 while(vu0_busy() && interlock
)
3294 /* perform VU register address */
3295 if(i_25_21
== 0x01) /* QMFC2 */
3298 /* one word at a time, argh! */
3299 read_vu_vec_reg(&(vu0_device
.regs
), id
, 0, A4_16(& xyzw
, 3));
3300 read_vu_vec_reg(&(vu0_device
.regs
), id
, 1, A4_16(& xyzw
, 2));
3301 read_vu_vec_reg(&(vu0_device
.regs
), id
, 2, A4_16(& xyzw
, 1));
3302 read_vu_vec_reg(&(vu0_device
.regs
), id
, 3, A4_16(& xyzw
, 0));
3303 GPR
[rt
] = T2H_8(* A8_16(& xyzw
, 1));
3304 GPR1
[rt
] = T2H_8(* A8_16(& xyzw
, 0));
3309 /* enum + int calculation, argh! */
3310 id
= VU_REG_MST
+ 16 * id
;
3311 read_vu_misc_reg(&(vu0_device
.regs
), id
, & data
);
3312 GPR
[rt
] = EXTEND32(T2H_4(data
));
3315 else if((i_25_21
== 0x06 && i_10_1
== 0x000) || /* CTC2 */
3316 (i_25_21
== 0x05)) /* QMTC2 */
3321 /* interlock checking: wait until M or E bits set */
3322 /* POLICY: never busy in macro mode */
3323 while(vu0_busy() && interlock
)
3325 if(vu0_micro_interlock_released())
3327 vu0_micro_interlock_clear();
3334 /* perform VU register address */
3335 if(i_25_21
== 0x05) /* QMTC2 */
3337 unsigned_16 xyzw
= U16_8(GPR1
[rt
], GPR
[rt
]);
3339 xyzw
= H2T_16(xyzw
);
3340 /* one word at a time, argh! */
3341 write_vu_vec_reg(&(vu0_device
.regs
), id
, 0, A4_16(& xyzw
, 3));
3342 write_vu_vec_reg(&(vu0_device
.regs
), id
, 1, A4_16(& xyzw
, 2));
3343 write_vu_vec_reg(&(vu0_device
.regs
), id
, 2, A4_16(& xyzw
, 1));
3344 write_vu_vec_reg(&(vu0_device
.regs
), id
, 3, A4_16(& xyzw
, 0));
3348 unsigned_4 data
= H2T_4(GPR
[rt
]);
3349 /* enum + int calculation, argh! */
3350 id
= VU_REG_MST
+ 16 * id
;
3351 write_vu_misc_reg(&(vu0_device
.regs
), id
, & data
);
3354 else if(i_10_0
== 0x3bf) /* VWAITQ */
3359 else if(i_5_0
== 0x38) /* VCALLMS */
3361 unsigned_4 data
= H2T_2(i_20_6
);
3366 /* write to reserved CIA register to get VU0 moving */
3367 write_vu_special_reg(& vu0_device
, VU_REG_CIA
, & data
);
3371 else if(i_5_0
== 0x39) /* VCALLMSR */
3378 read_vu_special_reg(& vu0_device
, VU_REG_CMSAR0
, & data
);
3379 /* write to reserved CIA register to get VU0 moving */
3380 write_vu_special_reg(& vu0_device
, VU_REG_CIA
, & data
);
3384 /* handle all remaining UPPER VU instructions in one block */
3385 else if((i_5_0
< 0x30) || /* VADDx .. VMINI */
3386 (i_5_0
>= 0x3c && i_10_6
< 0x0c)) /* VADDAx .. VNOP */
3388 unsigned_4 vu_upper
, vu_lower
;
3390 0x00000000 | /* bits 31 .. 25 */
3391 (instruction
& 0x01ffffff); /* bits 24 .. 0 */
3392 vu_lower
= 0x8000033c; /* NOP */
3394 /* POLICY: never busy in macro mode */
3398 vu0_macro_issue(vu_upper
, vu_lower
);
3400 /* POLICY: wait for completion of macro-instruction */
3404 /* handle all remaining LOWER VU instructions in one block */
3405 else if((i_5_0
>= 0x30 && i_5_0
<= 0x35) || /* VIADD .. VIOR */
3406 (i_5_0
>= 0x3c && i_10_6
>= 0x0c)) /* VMOVE .. VRXOR */
3407 { /* N.B.: VWAITQ already covered by prior case */
3408 unsigned_4 vu_upper
, vu_lower
;
3409 vu_upper
= 0x000002ff; /* NOP/NOP */
3411 0x80000000 | /* bits 31 .. 25 */
3412 (instruction
& 0x01ffffff); /* bits 24 .. 0 */
3414 /* POLICY: never busy in macro mode */
3418 vu0_macro_issue(vu_upper
, vu_lower
);
3420 /* POLICY: wait for completion of macro-instruction */
3424 /* ... no other COP2 instructions ... */
3427 SignalException(ReservedInstruction
, instruction
);
3431 /* cleanup for semantic.c-like actions above */
3438 #endif /* TARGET_SKY */
3439 /* end-sanitize-sky */
3443 sim_io_eprintf(sd
, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3444 instruction
,pr_addr(cia
));
3449 case 1: /* should not occur (FPU co-processor) */
3450 case 3: /* should not occur (FPU co-processor) */
3451 SignalException(ReservedInstruction
,instruction
);
3459 /*-- instruction simulation -------------------------------------------------*/
3461 /* When the IGEN simulator is being built, the function below is be
3462 replaced by a generated version. However, WITH_IGEN == 2 indicates
3463 that the fubction below should be compiled but under a different
3464 name (to allow backward compatibility) */
3466 #if (WITH_IGEN != 1)
3468 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3470 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3473 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3476 int next_cpu_nr
; /* ignore */
3477 int nr_cpus
; /* ignore */
3478 int siggnal
; /* ignore */
3480 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3481 #if !defined(FASTSIM)
3482 unsigned int pipeline_count
= 1;
3486 if (STATE_MEMORY (sd
) == NULL
) {
3487 printf("DBG: simulate() entered with no memory\n");
3492 #if 0 /* Disabled to check that everything works OK */
3493 /* The VR4300 seems to sign-extend the PC on its first
3494 access. However, this may just be because it is currently
3495 configured in 32bit mode. However... */
3496 PC
= SIGNEXTEND(PC
,32);
3499 /* main controlling loop */
3501 /* vaddr is slowly being replaced with cia - current instruction
3503 address_word cia
= (uword64
)PC
;
3504 address_word vaddr
= cia
;
3507 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3511 printf("DBG: state = 0x%08X :",state
);
3512 if (state
& simHALTEX
) printf(" simHALTEX");
3513 if (state
& simHALTIN
) printf(" simHALTIN");
3518 DSSTATE
= (STATE
& simDELAYSLOT
);
3521 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3524 /* Fetch the next instruction from the simulator memory: */
3525 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3526 if ((vaddr
& 1) == 0) {
3527 /* Copy the action of the LW instruction */
3528 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3529 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3532 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3533 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3534 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3535 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3537 /* Copy the action of the LH instruction */
3538 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3539 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3542 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3543 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3544 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3545 paddr
& ~ (uword64
) 1,
3546 vaddr
, isINSTRUCTION
, isREAL
);
3547 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3548 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3551 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3556 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3559 /* This is required by exception processing, to ensure that we can
3560 cope with exceptions in the delay slots of branches that may
3561 already have changed the PC. */
3562 if ((vaddr
& 1) == 0)
3563 PC
+= 4; /* increment ready for the next fetch */
3566 /* NOTE: If we perform a delay slot change to the PC, this
3567 increment is not requuired. However, it would make the
3568 simulator more complicated to try and avoid this small hit. */
3570 /* Currently this code provides a simple model. For more
3571 complicated models we could perform exception status checks at
3572 this point, and set the simSTOP state as required. This could
3573 also include processing any hardware interrupts raised by any
3574 I/O model attached to the simulator context.
3576 Support for "asynchronous" I/O events within the simulated world
3577 could be providing by managing a counter, and calling a I/O
3578 specific handler when a particular threshold is reached. On most
3579 architectures a decrement and check for zero operation is
3580 usually quicker than an increment and compare. However, the
3581 process of managing a known value decrement to zero, is higher
3582 than the cost of using an explicit value UINT_MAX into the
3583 future. Which system is used will depend on how complicated the
3584 I/O model is, and how much it is likely to affect the simulator
3587 If events need to be scheduled further in the future than
3588 UINT_MAX event ticks, then the I/O model should just provide its
3589 own counter, triggered from the event system. */
3591 /* MIPS pipeline ticks. To allow for future support where the
3592 pipeline hit of individual instructions is known, this control
3593 loop manages a "pipeline_count" variable. It is initialised to
3594 1 (one), and will only be changed by the simulator engine when
3595 executing an instruction. If the engine does not have access to
3596 pipeline cycle count information then all instructions will be
3597 treated as using a single cycle. NOTE: A standard system is not
3598 provided by the default simulator because different MIPS
3599 architectures have different cycle counts for the same
3602 [NOTE: pipeline_count has been replaced the event queue] */
3604 /* shuffle the floating point status pipeline state */
3605 ENGINE_ISSUE_PREFIX_HOOK();
3607 /* NOTE: For multi-context simulation environments the "instruction"
3608 variable should be local to this routine. */
3610 /* Shorthand accesses for engine. Note: If we wanted to use global
3611 variables (and a single-threaded simulator engine), then we can
3612 create the actual variables with these names. */
3614 if (!(STATE
& simSKIPNEXT
)) {
3615 /* Include the simulator engine */
3616 #include "oengine.c"
3617 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3618 #error "Mismatch between run-time simulator code and simulation engine"
3620 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3621 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3623 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3624 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3627 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3628 should check for it being changed. It is better doing it here,
3629 than within the simulator, since it will help keep the simulator
3632 #if defined(WARN_ZERO)
3633 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3634 #endif /* WARN_ZERO */
3635 ZERO
= 0; /* reset back to zero before next instruction */
3637 } else /* simSKIPNEXT check */
3638 STATE
&= ~simSKIPNEXT
;
3640 /* If the delay slot was active before the instruction is
3641 executed, then update the PC to its new value: */
3644 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3653 #if !defined(FASTSIM)
3654 if (sim_events_tickn (sd
, pipeline_count
))
3656 /* cpu->cia = cia; */
3657 sim_events_process (sd
);
3660 if (sim_events_tick (sd
))
3662 /* cpu->cia = cia; */
3663 sim_events_process (sd
);
3665 #endif /* FASTSIM */
3671 /* This code copied from gdb's utils.c. Would like to share this code,
3672 but don't know of a common place where both could get to it. */
3674 /* Temporary storage using circular buffer */
3680 static char buf
[NUMCELLS
][CELLSIZE
];
3682 if (++cell
>=NUMCELLS
) cell
=0;
3686 /* Print routines to handle variable size regs, etc */
3688 /* Eliminate warning from compiler on 32-bit systems */
3689 static int thirty_two
= 32;
3695 char *paddr_str
=get_cell();
3696 switch (sizeof(addr
))
3699 sprintf(paddr_str
,"%08lx%08lx",
3700 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3703 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3706 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3709 sprintf(paddr_str
,"%x",addr
);
3718 char *paddr_str
=get_cell();
3719 sprintf(paddr_str
,"%08lx%08lx",
3720 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3726 /*---------------------------------------------------------------------------*/
3727 /*> EOF interp.c <*/