2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 We only need to take account of the target endianness when moving data
23 between the simulator and the host. We do not need to worry about the
24 endianness of the host, since this sim code and GDB are executing in
27 The IDT monitor (found on the VR4300 board), seems to lie about
28 register contents. It seems to treat the registers as sign-extended
29 32-bit values. This cause *REAL* problems when single-stepping 64-bit
34 /* The TRACE and PROFILE manifests enable the provision of extra
35 features. If they are not defined then a simpler (quicker)
36 simulator is constructed without the required run-time checks,
38 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
64 #include "libiberty.h"
66 #include "remote-sim.h" /* GDB simulator interface */
67 #include "callback.h" /* GDB simulator callback interface */
69 #include "support.h" /* internal support manifests */
74 #define SIGBUS SIGSEGV
77 /* Get the simulator engine description, without including the code: */
82 /* This variable holds the GDB view of the target endianness: */
83 extern int target_byte_order
;
85 /* The following reserved instruction value is used when a simulator
86 trap is required. NOTE: Care must be taken, since this value may be
87 used in later revisions of the MIPS ISA. */
88 #define RSVD_INSTRUCTION (0x7C000000)
89 #define RSVD_INSTRUCTION_AMASK (0x03FFFFFF)
91 /* NOTE: These numbers depend on the processor architecture being
94 #define TLBModification (1)
97 #define AddressLoad (4)
98 #define AddressStore (5)
99 #define InstructionFetch (6)
100 #define DataReference (7)
101 #define SystemCall (8)
102 #define BreakPoint (9)
103 #define ReservedInstruction (10)
104 #define CoProcessorUnusable (11)
105 #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
110 /* The following exception code is actually private to the simulator
111 world. It is *NOT* a processor feature, and is used to signal
112 run-time errors in the simulator. */
113 #define SimulatorFault (0xFFFFFFFF)
115 /* The following are generic to all versions of the MIPS architecture
117 /* Memory Access Types (for CCA): */
119 #define CachedNoncoherent (1)
120 #define CachedCoherent (2)
123 #define isINSTRUCTION (1 == 0) /* FALSE */
124 #define isDATA (1 == 1) /* TRUE */
126 #define isLOAD (1 == 0) /* FALSE */
127 #define isSTORE (1 == 1) /* TRUE */
129 #define isREAL (1 == 0) /* FALSE */
130 #define isRAW (1 == 1) /* TRUE */
132 #define isTARGET (1 == 0) /* FALSE */
133 #define isHOST (1 == 1) /* TRUE */
135 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
136 is the number of bytes minus 1. */
137 #define AccessLength_BYTE (0)
138 #define AccessLength_HALFWORD (1)
139 #define AccessLength_TRIPLEBYTE (2)
140 #define AccessLength_WORD (3)
141 #define AccessLength_QUINTIBYTE (4)
142 #define AccessLength_SEXTIBYTE (5)
143 #define AccessLength_SEPTIBYTE (6)
144 #define AccessLength_DOUBLEWORD (7)
147 /* FPU registers must be one of the following types. All other values
148 are reserved (and undefined). */
154 /* The following are well outside the normal acceptable format
155 range, and are used in the register status vector. */
156 fmt_unknown
= 0x10000000,
157 fmt_uninterpreted
= 0x20000000,
161 /* NOTE: We cannot avoid globals, since the GDB "sim_" interface does
162 not allow a private variable to be passed around. This means that
163 simulators under GDB can only be single-threaded. However, it would
164 be possible for the simulators to be multi-threaded if GDB allowed
165 for a private pointer to be maintained. i.e. a general "void **ptr"
166 variable that GDB passed around in the argument list to all of
167 sim_xxx() routines. It could be initialised to NULL by GDB, and
168 then updated by sim_open() and used by the other sim_xxx() support
169 functions. This would allow new features in the simulator world,
170 like storing a context - continuing execution to gather a result,
171 and then going back to the point where the context was saved and
172 changing some state before continuing. i.e. the ability to perform
173 UNDOs on simulations. It would also allow the simulation of
174 shared-memory multi-processor systems. */
176 static host_callback
*callback
= NULL
; /* handle onto the current callback structure */
178 /* This is nasty, since we have to rely on matching the register
179 numbers used by GDB. Unfortunately, depending on the MIPS target
180 GDB uses different register numbers. We cannot just include the
181 relevant "gdb/tm.h" link, since GDB may not be configured before
182 the sim world, and also the GDB header file requires too much other
184 /* TODO: Sort out a scheme for *KNOWING* the mapping between real
185 registers, and the numbers that GDB uses. At the moment due to the
186 order that the tools are built, we cannot rely on a configured GDB
187 world whilst constructing the simulator. This means we have to
188 assume the GDB register number mapping. */
189 #define LAST_EMBED_REGNUM (89)
191 /* To keep this default simulator simple, and fast, we use a direct
192 vector of registers. The internal simulator engine then uses
193 manifests to access the correct slot. */
194 static ut_reg registers
[LAST_EMBED_REGNUM
+ 1];
195 static int register_widths
[LAST_EMBED_REGNUM
+ 1];
197 #define GPR (®isters[0])
200 #define FGR (®isters[FGRIDX])
202 #define LO (registers[33])
203 #define HI (registers[34])
204 #define PC (registers[37])
205 #define CAUSE (registers[36])
207 #define SR (registers[SRIDX]) /* CPU status register */
209 #define FCR0 (registers[FCR0IDX]) /* really a 32bit register */
210 #define FCR31IDX (70)
211 #define FCR31 (registers[FCR31IDX]) /* really a 32bit register */
213 #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
215 /* The following are pseudonyms for standard registers */
216 #define ZERO (registers[0])
217 #define V0 (registers[2])
218 #define A0 (registers[4])
219 #define A1 (registers[5])
220 #define A2 (registers[6])
221 #define A3 (registers[7])
222 #define SP (registers[29])
223 #define RA (registers[31])
225 static ut_reg EPC
= 0; /* Exception PC */
228 /* Keep the current format state for each register: */
229 static FP_formats fpr_state
[32];
232 /* VR4300 CP0 configuration register: */
233 static unsigned int CONFIG
= 0;
235 /* The following are internal simulator state variables: */
236 static ut_reg IPC
= 0; /* internal Instruction PC */
237 static ut_reg DSPC
= 0; /* delay-slot PC */
240 /* TODO : these should be the bitmasks for these bits within the
241 status register. At the moment the following are VR4300
243 #define status_KSU_mask (0x3) /* mask for KSU bits */
244 #define status_KSU_shift (3) /* shift for field */
245 #define ksu_kernel (0x0)
246 #define ksu_supervisor (0x1)
247 #define ksu_user (0x2)
248 #define ksu_unknown (0x3)
250 #define status_RE (1 << 25) /* Reverse Endian in user mode */
251 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
252 #define status_SR (1 << 20) /* soft reset or NMI */
253 #define status_BEV (1 << 22) /* Location of general exception vectors */
254 #define status_TS (1 << 21) /* TLB shutdown has occurred */
255 #define status_ERL (1 << 2) /* Error level */
256 #define status_RP (1 << 27) /* Reduced Power mode */
258 #define config_EP_mask (0xF)
259 #define config_EP_shift (27)
260 #define config_EP_D (0x0)
261 #define config_EP_DxxDxx (0x6)
263 #define config_BE (1 << 15)
265 #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
268 /* Macro to update FPSR condition-code field. This is complicated by
269 the fact that there is a hole in the index range of the bits within
270 the FCSR register. Also, the number of bits visible depends on the
271 MIPS ISA version being supported. */
272 #define SETFCC(cc,v) {\
273 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
274 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
276 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
278 /* This should be the COC1 value at the start of the preceding
280 #define PREVCOC1() ((state & simPCOC1) ? 1 : 0)
283 /* Standard FCRS bits: */
284 #define IR (0) /* Inexact Result */
285 #define UF (1) /* UnderFlow */
286 #define OF (2) /* OverFlow */
287 #define DZ (3) /* Division by Zero */
288 #define IO (4) /* Invalid Operation */
289 #define UO (5) /* Unimplemented Operation */
291 /* Get masks for individual flags: */
292 #if 1 /* SAFE version */
293 #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
294 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
295 #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
297 #define FP_FLAGS(b) (1 << ((b) + 2))
298 #define FP_ENABLE(b) (1 << ((b) + 7))
299 #define FP_CAUSE(b) (1 << ((b) + 12))
302 #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
304 #define FP_MASK_RM (0x3)
306 #define FP_RM_NEAREST (0) /* Round to nearest (Round) */
307 #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
308 #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
309 #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
310 #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
312 /* Slots for delayed register updates. For the moment we just have a
313 fixed number of slots (rather than a more generic, dynamic
314 system). This keeps the simulator fast. However, we only allow for
315 the register update to be delayed for a single instruction
317 #define PSLOTS (5) /* Maximum number of instruction cycles */
318 static int pending_in
;
319 static int pending_out
;
320 static int pending_total
;
321 static int pending_slot_count
[PSLOTS
];
322 static int pending_slot_reg
[PSLOTS
];
323 static ut_reg pending_slot_value
[PSLOTS
];
325 /* The following are not used for MIPS IV onwards: */
326 #define PENDING_FILL(r,v) {\
327 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); */\
328 if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\
329 sim_warning("Attempt to over-write pending value");\
330 pending_slot_count[pending_in] = 2;\
331 pending_slot_reg[pending_in] = (r);\
332 pending_slot_value[pending_in] = (uword64)(v);\
333 /*printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));*/\
336 if (pending_in == PSLOTS)\
338 /*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);*/\
341 static int LLBIT
= 0;
342 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
343 read-write instructions. It is set when a linked load occurs. It is
344 tested and cleared by the conditional store. It is cleared (during
345 other CPU operations) when a store to the location would no longer
346 be atomic. In particular, it is cleared by exception return
349 static int HIACCESS
= 0;
350 static int LOACCESS
= 0;
351 /* The HIACCESS and LOACCESS counts are used to ensure that
352 corruptions caused by using the HI or LO register to close to a
353 following operation are spotted. */
354 static ut_reg HLPC
= 0;
356 /* TODO: The 4300 has interlocks so we should not need to warn of the possible over-write (CHECK THIS) */
357 /* If either of the preceding two instructions have accessed the HI or
358 LO registers, then the values they see should be
359 undefined. However, to keep the simulator world simple, we just let
360 them use the value read and raise a warning to notify the user: */
361 #define CHECKHILO(s) {\
362 if ((HIACCESS != 0) || (LOACCESS != 0))\
363 sim_warning("%s over-writing HI and LO registers values (PC = 0x%08X%08X HLPC = 0x%08X%08X)\n",(s),(unsigned int)(PC>>32),(unsigned int)(PC&0xFFFFFFFF),(unsigned int)(HLPC>>32),(unsigned int)(HLPC&0xFFFFFFFF));\
366 /* NOTE: We keep the following status flags as bit values (1 for true,
367 0 for false). This allows them to be used in binary boolean
368 operations without worrying about what exactly the non-zero true
372 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
375 /* Hardware configuration. Affects endianness of LoadMemory and
376 StoreMemory and the endianness of Kernel and Supervisor mode
377 execution. The value is 0 for little-endian; 1 for big-endian. */
378 #define BigEndianMem ((CONFIG & config_BE) ? 1 : 0)
379 /* NOTE: Problems will occur if the simulator memory model does not
380 match the host program expectation. i.e. if the host is writing
381 big-endian values to a little-endian memory model. */
384 /* This mode is selected if in User mode with the RE bit being set in
385 SR (Status Register). It reverses the endianness of load and store
387 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
390 /* The endianness for load and store instructions (0=little;1=big). In
391 User mode this endianness may be switched by setting the state_RE
392 bit in the SR register. Thus, BigEndianCPU may be computed as
393 (BigEndienMem EOR ReverseEndian). */
394 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
396 #if !defined(FASTSIM) || defined(PROFILE)
397 /* At the moment these values will be the same, since we do not have
398 access to the pipeline cycle count information from the simulator
400 static unsigned int instruction_fetches
= 0;
401 static unsigned int instruction_fetch_overflow
= 0;
402 static unsigned int pipeline_ticks
= 0;
405 /* Flags in the "state" variable: */
406 #define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */
407 #define simSTEP (1 << 1) /* 0 = run; 1 = single-step */
408 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
409 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
410 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
411 #define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */
412 #define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */
413 /* Whilst simSTOP is not set, the simulator control loop should just
414 keep simulating instructions. The simSTEP flag is used to force
415 single-step execution. */
416 #define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */
417 #define simPCOC0 (1 << 17) /* COC[1] from current */
418 #define simPCOC1 (1 << 18) /* COC[1] from previous */
419 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
420 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
421 #define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
422 #define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
424 static unsigned int state
= 0;
425 static unsigned int rcexit
= 0; /* _exit() reason code holder */
427 #define DELAYSLOT() {\
428 if (state & simDELAYSLOT)\
429 sim_warning("Delay slot already activated (branch in delay slot?)");\
430 state |= simDELAYSLOT;\
434 state &= ~simDELAYSLOT;\
435 state |= simSKIPNEXT;\
438 #define K0BASE (0x80000000)
439 #define K0SIZE (0x20000000)
440 #define K1BASE (0xA0000000)
441 #define K1SIZE (0x20000000)
443 /* Very simple memory model to start with: */
444 static unsigned char *membank
= NULL
;
445 static ut_reg membank_base
= K1BASE
;
446 static unsigned membank_size
= (1 << 20); /* (16 << 20); */ /* power-of-2 */
448 /* Simple run-time monitor support */
449 static unsigned char *monitor
= NULL
;
450 static ut_reg monitor_base
= 0xBFC00000;
451 static unsigned monitor_size
= (1 << 11); /* power-of-2 */
453 static char *logfile
= NULL
; /* logging disabled by default */
454 static FILE *logfh
= NULL
;
457 static char *tracefile
= "trace.din"; /* default filename for trace log */
458 static FILE *tracefh
= NULL
;
462 static unsigned profile_frequency
= 256;
463 static unsigned profile_nsamples
= (128 << 10);
464 static unsigned short *profile_hist
= NULL
;
465 static ut_reg profile_minpc
;
466 static ut_reg profile_maxpc
;
467 static int profile_shift
= 0; /* address shift amount */
470 /* The following are used to provide shortcuts to the required version
471 of host<->target copying. This avoids run-time conditionals, which
472 would slow the simulator throughput. */
473 typedef unsigned int (*fnptr_read_word
) PARAMS((unsigned char *memory
));
474 typedef unsigned int (*fnptr_swap_word
) PARAMS((unsigned int data
));
475 typedef uword64 (*fnptr_read_long
) PARAMS((unsigned char *memory
));
476 typedef uword64 (*fnptr_swap_long
) PARAMS((uword64 data
));
478 static fnptr_read_word host_read_word
;
479 static fnptr_read_long host_read_long
;
480 static fnptr_swap_word host_swap_word
;
481 static fnptr_swap_long host_swap_long
;
483 /*---------------------------------------------------------------------------*/
484 /*-- GDB simulator interface ------------------------------------------------*/
485 /*---------------------------------------------------------------------------*/
487 static void dotrace
PARAMS((FILE *tracefh
,int type
,unsigned int address
,int width
,char *comment
,...));
488 static void sim_warning
PARAMS((char *fmt
,...));
489 extern void sim_error
PARAMS((char *fmt
,...));
490 static void ColdReset
PARAMS((void));
491 static int AddressTranslation
PARAMS((uword64 vAddr
,int IorD
,int LorS
,uword64
*pAddr
,int *CCA
,int host
,int raw
));
492 static void StoreMemory
PARAMS((int CCA
,int AccessLength
,uword64 MemElem
,uword64 pAddr
,uword64 vAddr
,int raw
));
493 static uword64 LoadMemory
PARAMS((int CCA
,int AccessLength
,uword64 pAddr
,uword64 vAddr
,int IorD
,int raw
));
494 static void SignalException
PARAMS((int exception
,...));
495 static void simulate
PARAMS((void));
496 static long getnum
PARAMS((char *value
));
497 extern void sim_size
PARAMS((unsigned int newsize
));
498 extern void sim_set_profile
PARAMS((int frequency
));
499 static unsigned int power2
PARAMS((unsigned int value
));
501 /*---------------------------------------------------------------------------*/
507 if (callback
== NULL
) {
508 fprintf(stderr
,"SIM Error: sim_open() called without callbacks attached\n");
512 /* The following ensures that the standard file handles for stdin,
513 stdout and stderr are initialised: */
514 callback
->init(callback
);
518 if (state
& simEXCEPTION
) {
519 fprintf(stderr
,"This simulator is not suitable for this host configuration\n");
525 if (*((char *)&data
) != 0x12)
526 state
|= simHOSTBE
; /* big-endian host */
530 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
531 and DOUBLE binary formats. This is a bit nasty, requiring that we
532 trust the explicit manifests held in the source: */
535 s
[state
& simHOSTBE
? 0 : 1] = 0x40805A5A;
536 s
[state
& simHOSTBE
? 1 : 0] = 0x00000000;
538 /* TODO: We need to cope with the simulated target and the host
539 not having the same endianness. This will require the high and
540 low words of a (double) to be swapped when converting between
541 the host and the simulated target. */
543 if (((float)4.01102924346923828125 != *(float *)(s
+ ((state
& simHOSTBE
) ? 0 : 1))) || ((double)523.2939453125 != *(double *)s
)) {
544 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
545 fprintf(stderr
,"*(float *)s = %.20f (4.01102924346923828125)\n",*(float *)s
);
546 fprintf(stderr
,"*(double *)s = %.20f (523.2939453125)\n",*(double *)s
);
552 /* This is NASTY, in that we are assuming the size of specific
556 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
558 register_widths
[rn
] = GPRLEN
;
559 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
560 register_widths
[rn
] = GPRLEN
;
561 else if ((rn
>= 33) && (rn
<= 37))
562 register_widths
[rn
] = GPRLEN
;
563 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
564 register_widths
[rn
] = 32;
566 register_widths
[rn
] = 0;
570 /* It would be good if we could select particular named MIPS
571 architecture simulators. However, having a pre-built, fixed
572 engine would mean including multiple engines. If the simulator is
573 changed to a run-time conditional version, then the ability to
574 select a particular architecture would be straightforward. */
580 static struct option cmdline
[] = {
584 {"profile", 0,0,'p'},
587 {"tracefile",1,0,'z'},
588 {"frequency",1,0,'y'},
589 {"samples", 1,0,'x'},
593 /* Unfortunately, getopt_long() is designed to be used with
594 vectors, where the first option is normally program name (and
595 ignored). We cheat by creating a dummy first argument, so that
596 we can use the standard argument processing. */
597 #define DUMMYARG "simulator "
598 cline
= (char *)malloc(strlen(args
) + strlen(DUMMYARG
) + 1);
600 fprintf(stderr
,"Failed to allocate memory for command line buffer\n");
603 sprintf(cline
,"%s%s",DUMMYARG
,args
);
604 argv
= buildargv(cline
);
605 for (argc
= 0; argv
[argc
]; argc
++);
607 /* Unfortunately, getopt_long() assumes that it is ignoring the
608 first argument (normally the program name). This means it
609 ignores the first option on our "args" line. */
610 optind
= 0; /* Force reset of argument processing */
612 int option_index
= 0;
614 c
= getopt_long(argc
,argv
,"hn:s:tp",cmdline
,&option_index
);
620 callback
->printf_filtered(callback
,"Usage:\n\t\
621 target sim [-h] [--log=<file>] [--name=<model>] [--size=<amount>]");
623 callback
->printf_filtered(callback
," [-t [--tracefile=<name>]]");
626 callback
->printf_filtered(callback
," [-p [--frequency=<count>] [--samples=<count>]]");
628 callback
->printf_filtered(callback
,"\n");
632 if (optarg
!= NULL
) {
634 tmp
= (char *)malloc(strlen(optarg
) + 1);
636 callback
->printf_filtered(callback
,"Failed to allocate buffer for logfile name \"%s\"\n",optarg
);
645 callback
->printf_filtered(callback
,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg
);
649 membank_size
= (unsigned)getnum(optarg
);
654 /* Eventually the simTRACE flag could be treated as a toggle, to
655 allow external control of the program points being traced
656 (i.e. only from main onwards, excluding the run-time setup,
661 Simulator constructed without tracing support (for performance).\n\
662 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
668 if (optarg
!= NULL
) {
670 tmp
= (char *)malloc(strlen(optarg
) + 1);
672 callback
->printf_filtered(callback
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
676 callback
->printf_filtered(callback
,"Placing trace information into file \"%s\"\n",tracefile
);
687 Simulator constructed without profiling support (for performance).\n\
688 Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
689 #endif /* !PROFILE */
694 profile_nsamples
= (unsigned)getnum(optarg
);
700 sim_set_profile((int)getnum(optarg
));
705 callback
->printf_filtered(callback
,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c
);
713 callback
->printf_filtered(callback
,"Warning: Ignoring spurious non-option arguments ");
714 while (optind
< argc
)
715 callback
->printf_filtered(callback
,"\"%s\" ",argv
[optind
++]);
716 callback
->printf_filtered(callback
,"\n");
723 if (logfile
!= NULL
) {
724 if (strcmp(logfile
,"-") == 0)
727 logfh
= fopen(logfile
,"wb+");
729 callback
->printf_filtered(callback
,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile
);
735 /* If the host has "mmap" available we could use it to provide a
736 very large virtual address space for the simulator, since memory
737 would only be allocated within the "mmap" space as it is
738 accessed. This can also be linked to the architecture specific
739 support, required to simulate the MMU. */
740 sim_size(membank_size
);
741 /* NOTE: The above will also have enabled any profiling state */
744 /* If we were providing a more complete I/O, co-processor or memory
745 simulation, we should perform any "device" initialisation at this
746 point. This can include pre-loading memory areas with particular
747 patterns (e.g. simulating ROM monitors). */
749 /* We can start writing to the memory, now that the processor has
751 monitor
= (unsigned char *)calloc(1,monitor_size
);
753 fprintf(stderr
,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size
);
756 /* Entry into the IDT monitor is via fixed address vectors, and
757 not using machine instructions. To avoid clashing with use of
758 the MIPS TRAP system, we place our own (simulator specific)
759 "undefined" instructions into the relevant vector slots. */
760 for (loop
= 0; (loop
< monitor_size
); loop
+= 4) {
761 uword64 vaddr
= (monitor_base
+ loop
);
764 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
765 StoreMemory(cca
,AccessLength_WORD
,(RSVD_INSTRUCTION
| ((loop
>> 2) & RSVD_INSTRUCTION_AMASK
)),paddr
,vaddr
,isRAW
);
767 /* The PMON monitor uses the same address space, but rather than
768 branching into it the address of a routine is loaded. We can
769 cheat for the moment, and direct the PMON routine to IDT style
770 instructions within the monitor space. This relies on the IDT
771 monitor not using the locations from 0xBFC00500 onwards as its
773 for (loop
= 0; (loop
< 24); loop
++)
775 uword64 vaddr
= (monitor_base
+ 0x500 + (loop
* 4));
778 unsigned int value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
798 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
801 case 8: /* cliexit */
805 value
= (monitor_base
+ (value
* 8));
806 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
807 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
809 sim_error("Failed to write to monitor space 0x%08X%08X",WORD64HI(vaddr
),WORD64LO(vaddr
));
814 if (state
& simTRACE
) {
815 tracefh
= fopen(tracefile
,"wb+");
816 if (tracefh
== NULL
) {
817 sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile
);
826 /* For the profile writing, we write the data in the host
827 endianness. This unfortunately means we are assuming that the
828 profile file we create is processed on the same host executing the
829 simulator. The gmon.out file format should either have an explicit
830 endianness, or a method of encoding the endianness in the file
840 if (state
& simHOSTBE
) {
841 buff
[3] = ((val
>> 0) & 0xFF);
842 buff
[2] = ((val
>> 8) & 0xFF);
843 buff
[1] = ((val
>> 16) & 0xFF);
844 buff
[0] = ((val
>> 24) & 0xFF);
846 buff
[0] = ((val
>> 0) & 0xFF);
847 buff
[1] = ((val
>> 8) & 0xFF);
848 buff
[2] = ((val
>> 16) & 0xFF);
849 buff
[3] = ((val
>> 24) & 0xFF);
851 if (fwrite(buff
,4,1,fh
) != 1) {
852 sim_warning("Failed to write 4bytes to the profile file");
865 if (state
& simHOSTBE
) {
866 buff
[1] = ((val
>> 0) & 0xFF);
867 buff
[0] = ((val
>> 8) & 0xFF);
869 buff
[0] = ((val
>> 0) & 0xFF);
870 buff
[1] = ((val
>> 8) & 0xFF);
872 if (fwrite(buff
,2,1,fh
) != 1) {
873 sim_warning("Failed to write 2bytes to the profile file");
884 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
887 /* Cannot assume sim_kill() has been called */
888 /* "quitting" is non-zero if we cannot hang on errors */
890 /* Ensure that any resources allocated through the callback
891 mechanism are released: */
892 callback
->shutdown(callback
);
895 if ((state
& simPROFILE
) && (profile_hist
!= NULL
)) {
896 unsigned short *p
= profile_hist
;
897 FILE *pf
= fopen("gmon.out","wb");
901 sim_warning("Failed to open \"gmon.out\" profile file");
905 printf("DBG: minpc = 0x%08X\n",(unsigned int)profile_minpc
);
906 printf("DBG: maxpc = 0x%08X\n",(unsigned int)profile_maxpc
);
908 ok
= writeout32(pf
,(unsigned int)profile_minpc
);
910 ok
= writeout32(pf
,(unsigned int)profile_maxpc
);
912 ok
= writeout32(pf
,(profile_nsamples
* 2) + 12); /* size of sample buffer (+ header) */
914 printf("DBG: nsamples = %d (size = 0x%08X)\n",profile_nsamples
,((profile_nsamples
* 2) + 12));
916 for (loop
= 0; (ok
&& (loop
< profile_nsamples
)); loop
++) {
917 ok
= writeout16(pf
,profile_hist
[loop
]);
927 state
&= ~simPROFILE
;
932 if (tracefh
!= stderr
)
937 if (logfh
!= NULL
&& logfh
!= stdout
&& logfh
!= stderr
)
942 free(membank
); /* cfree not available on all hosts */
949 sim_resume (step
,signal
)
953 printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step
,signal
,membank
);
957 state
|= simSTEP
; /* execute only a single instruction */
959 state
&= ~(simSTOP
| simSTEP
); /* execute until event */
961 state
|= (simHALTEX
| simHALTIN
); /* treat interrupt event as exception */
963 /* Start executing instructions from the current state (set
964 explicitly by register updates, or by sim_create_inferior): */
971 sim_write (addr
,buffer
,size
)
973 unsigned char *buffer
;
977 uword64 vaddr
= (uword64
)addr
;
979 /* Return the number of bytes written, or zero if error. */
981 callback
->printf_filtered(callback
,"sim_write(0x%08X%08X,buffer,%d);\n",WORD64HI(addr
),WORD64LO(addr
),size
);
984 /* We provide raw read and write routines, since we do not want to
985 count the GDB memory accesses in our statistics gathering. */
987 /* There is a lot of code duplication in the individual blocks
988 below, but the variables are declared locally to a block to give
989 the optimiser the best chance of improving the code. We have to
990 perform slow byte reads from the host memory, to ensure that we
991 get the data into the correct endianness for the (simulated)
992 target memory world. */
994 /* Mask count to get odd byte, odd halfword, and odd word out of the
995 way. We can then perform doubleword transfers to and from the
996 simulator memory for optimum performance. */
997 if (index
&& (index
& 1)) {
1000 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1001 uword64 value
= ((uword64
)(*buffer
++));
1002 StoreMemory(cca
,AccessLength_BYTE
,value
,paddr
,vaddr
,isRAW
);
1005 index
&= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
1007 if (index
&& (index
& 2)) {
1010 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1012 /* We need to perform the following magic to ensure that that
1013 bytes are written into same byte positions in the target memory
1014 world, regardless of the endianness of the host. */
1016 value
= ((uword64
)(*buffer
++) << 8);
1017 value
|= ((uword64
)(*buffer
++) << 0);
1019 value
= ((uword64
)(*buffer
++) << 0);
1020 value
|= ((uword64
)(*buffer
++) << 8);
1022 StoreMemory(cca
,AccessLength_HALFWORD
,value
,paddr
,vaddr
,isRAW
);
1027 if (index
&& (index
& 4)) {
1030 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1033 value
= ((uword64
)(*buffer
++) << 24);
1034 value
|= ((uword64
)(*buffer
++) << 16);
1035 value
|= ((uword64
)(*buffer
++) << 8);
1036 value
|= ((uword64
)(*buffer
++) << 0);
1038 value
= ((uword64
)(*buffer
++) << 0);
1039 value
|= ((uword64
)(*buffer
++) << 8);
1040 value
|= ((uword64
)(*buffer
++) << 16);
1041 value
|= ((uword64
)(*buffer
++) << 24);
1043 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
1048 for (;index
; index
-= 8) {
1051 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1054 value
= ((uword64
)(*buffer
++) << 56);
1055 value
|= ((uword64
)(*buffer
++) << 48);
1056 value
|= ((uword64
)(*buffer
++) << 40);
1057 value
|= ((uword64
)(*buffer
++) << 32);
1058 value
|= ((uword64
)(*buffer
++) << 24);
1059 value
|= ((uword64
)(*buffer
++) << 16);
1060 value
|= ((uword64
)(*buffer
++) << 8);
1061 value
|= ((uword64
)(*buffer
++) << 0);
1063 value
= ((uword64
)(*buffer
++) << 0);
1064 value
|= ((uword64
)(*buffer
++) << 8);
1065 value
|= ((uword64
)(*buffer
++) << 16);
1066 value
|= ((uword64
)(*buffer
++) << 24);
1067 value
|= ((uword64
)(*buffer
++) << 32);
1068 value
|= ((uword64
)(*buffer
++) << 40);
1069 value
|= ((uword64
)(*buffer
++) << 48);
1070 value
|= ((uword64
)(*buffer
++) << 56);
1072 StoreMemory(cca
,AccessLength_DOUBLEWORD
,value
,paddr
,vaddr
,isRAW
);
1081 sim_read (addr
,buffer
,size
)
1083 unsigned char *buffer
;
1088 /* Return the number of bytes read, or zero if error. */
1090 callback
->printf_filtered(callback
,"sim_read(0x%08X%08X,buffer,%d);\n",WORD64HI(addr
),WORD64LO(addr
),size
);
1093 /* TODO: Perform same optimisation as the sim_write() code
1094 above. NOTE: This will require a bit more work since we will need
1095 to ensure that the source physical address is doubleword aligned
1096 before, and then deal with trailing bytes. */
1097 for (index
= 0; (index
< size
); index
++) {
1098 uword64 vaddr
,paddr
,value
;
1100 vaddr
= (uword64
)addr
+ index
;
1101 if (AddressTranslation(vaddr
,isDATA
,isLOAD
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1102 value
= LoadMemory(cca
,AccessLength_BYTE
,paddr
,vaddr
,isDATA
,isRAW
);
1103 buffer
[index
] = (unsigned char)(value
&0xFF);
1112 sim_store_register (rn
,memory
)
1114 unsigned char *memory
;
1117 callback
->printf_filtered(callback
,"sim_store_register(%d,*memory=0x%08X%08X);\n",rn
,*((unsigned int *)memory
),*((unsigned int *)(memory
+ 4)));
1120 /* Unfortunately this suffers from the same problem as the register
1121 numbering one. We need to know what the width of each logical
1122 register number is for the architecture being simulated. */
1123 if (register_widths
[rn
] == 0)
1124 sim_warning("Invalid register width for %d (register store ignored)",rn
);
1126 if (register_widths
[rn
] == 32)
1127 registers
[rn
] = host_read_word(memory
);
1129 registers
[rn
] = host_read_long(memory
);
1136 sim_fetch_register (rn
,memory
)
1138 unsigned char *memory
;
1141 callback
->printf_filtered(callback
,"sim_fetch_register(%d=0x%08X%08X,mem) : place simulator registers into memory\n",rn
,WORD64HI(registers
[rn
]),WORD64LO(registers
[rn
]));
1144 if (register_widths
[rn
] == 0)
1145 sim_warning("Invalid register width for %d (register fetch ignored)",rn
);
1147 if (register_widths
[rn
] == 32)
1148 *((unsigned int *)memory
) = host_swap_word(registers
[rn
] & 0xFFFFFFFF);
1149 else /* 64bit register */
1150 *((uword64
*)memory
) = host_swap_long(registers
[rn
]);
1156 sim_stop_reason (reason
,sigrc
)
1157 enum sim_stop
*reason
;
1160 /* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so
1161 sim_exited *sigrc = argument to exit()
1162 sim_stopped *sigrc = exception number
1163 sim_signalled *sigrc = signal number
1165 if (state
& simEXCEPTION
) {
1166 /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers,
1167 and not the MIPS specific exception codes. */
1169 /* For some reason, sending GDB a sim_signalled reason cause it to
1171 *reason
= sim_stopped
;
1173 *reason
= sim_signalled
;
1175 switch ((CAUSE
>> 2) & 0x1F) {
1177 *sigrc
= SIGINT
; /* wrong type of interrupt, but it will do for the moment */
1180 case TLBModification
:
1185 case InstructionFetch
:
1190 case ReservedInstruction
:
1191 case CoProcessorUnusable
:
1195 case IntegerOverflow
:
1207 default : /* Unknown internal exception */
1211 } else if (state
& simEXIT
) {
1213 printf("DBG: simEXIT (%d)\n",rcexit
);
1215 *reason
= sim_exited
;
1217 } else { /* assume single-stepping */
1218 *reason
= sim_stopped
;
1221 state
&= ~(simEXCEPTION
| simEXIT
);
1229 /* Accessed from the GDB "info files" command: */
1231 callback
->printf_filtered(callback
,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT
? 64 : 32));
1233 callback
->printf_filtered(callback
,"%s endian memory model\n",(BigEndianMem
? "Big" : "Little"));
1235 callback
->printf_filtered(callback
,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size
,WORD64HI(membank_base
),WORD64LO(membank_base
));
1237 #if !defined(FASTSIM)
1238 if (instruction_fetch_overflow
!= 0)
1239 callback
->printf_filtered(callback
,"Instruction fetches = 0x%08X%08X\n",instruction_fetch_overflow
,instruction_fetches
);
1241 callback
->printf_filtered(callback
,"Instruction fetches = %d\n",instruction_fetches
);
1242 callback
->printf_filtered(callback
,"Pipeline ticks = %d\n",pipeline_ticks
);
1243 /* It would be a useful feature, if when performing multi-cycle
1244 simulations (rather than single-stepping) we keep the start and
1245 end times of the execution, so that we can give a performance
1246 figure for the simulator. */
1247 #endif /* !FASTSIM */
1249 /* print information pertaining to MIPS ISA and architecture being simulated */
1250 /* things that may be interesting */
1251 /* instructions executed - if available */
1252 /* cycles executed - if available */
1253 /* pipeline stalls - if available */
1254 /* virtual time taken */
1255 /* profiling size */
1256 /* profiling frequency */
1264 sim_load (prog
,from_tty
)
1268 /* Return non-zero if the caller should handle the load. Zero if
1269 we have loaded the image. */
1274 sim_create_inferior (start_address
,argv
,env
)
1275 SIM_ADDR start_address
;
1280 printf("DBG: sim_create_inferior entered: start_address = 0x%08X\n",start_address
);
1283 /* Prepare to execute the program to be simulated */
1284 /* argv and env are NULL terminated lists of pointers */
1287 PC
= (uword64
)start_address
;
1289 /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
1290 PC
= SIGNEXTEND(start_address
,32);
1292 /* NOTE: GDB normally sets the PC explicitly. However, this call is
1293 used by other clients of the simulator. */
1296 #if 0 /* def DEBUG */
1297 callback
->printf_filtered(callback
,"sim_create_inferior() : passed arguments ignored\n");
1300 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1301 printf("DBG: arg \"%s\"\n",*cptr
);
1304 /* We should really place the argv slot values into the argument
1305 registers, and onto the stack as required. However, this
1306 assumes that we have a stack defined, which is not necessarily
1307 true at the moment. */
1317 /* This routine should be for terminating any existing simulation
1318 thread. Since we are single-threaded only at the moment, this is
1319 not an issue. It should *NOT* be used to terminate the
1321 #else /* do *NOT* call sim_close */
1322 sim_close(1); /* Do not hang on errors */
1323 /* This would also be the point where any memory mapped areas used
1324 by the simulator should be released. */
1330 sim_get_quit_code ()
1332 /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as
1333 the function return value. However, it may be more correct for
1334 this to return the argument to the exit() function (if
1340 sim_set_callbacks (p
)
1347 typedef enum {e_terminate
,e_help
,e_setmemsize
,e_reset
} e_cmds
;
1349 static struct t_sim_command
{
1353 } sim_commands
[] = {
1354 {e_help
, "help", ": Show MIPS simulator private commands"},
1355 {e_setmemsize
,"set-memory-size","<n> : Specify amount of memory simulated"},
1356 {e_reset
, "reset-system", ": Reset the simulated processor"},
1361 sim_do_command (cmd
)
1364 struct t_sim_command
*cptr
;
1366 if (callback
== NULL
) {
1367 fprintf(stderr
,"Simulator not enabled: \"target sim\" should be used to activate\n");
1371 if (!(cmd
&& *cmd
!= '\0'))
1374 /* NOTE: Accessed from the GDB "sim" commmand: */
1375 for (cptr
= sim_commands
; cptr
&& cptr
->name
; cptr
++)
1376 if (strncmp(cmd
,cptr
->name
,strlen(cptr
->name
)) == 0) {
1377 cmd
+= strlen(cptr
->name
);
1379 case e_help
: /* no arguments */
1380 { /* no arguments */
1381 struct t_sim_command
*lptr
;
1382 callback
->printf_filtered(callback
,"List of MIPS simulator commands:\n");
1383 for (lptr
= sim_commands
; lptr
->name
; lptr
++)
1384 callback
->printf_filtered(callback
,"%s %s\n",lptr
->name
,lptr
->help
);
1388 case e_setmemsize
: /* memory size argument */
1390 unsigned int newsize
= (unsigned int)getnum(cmd
);
1395 case e_reset
: /* no arguments */
1397 /* NOTE: See the comments in sim_open() relating to device
1402 callback
->printf_filtered(callback
,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd
,cptr
->id
);
1409 callback
->printf_filtered(callback
,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd
);
1414 /*---------------------------------------------------------------------------*/
1415 /* NOTE: The following routines do not seem to be used by GDB at the
1416 moment. However, they may be useful to the standalone simulator
1420 /* The profiling format is described in the "gmon_out.h" header file */
1425 #if defined(PROFILE)
1426 profile_frequency
= n
;
1427 state
|= simPROFILE
;
1428 #endif /* PROFILE */
1433 sim_set_profile_size (n
)
1436 #if defined(PROFILE)
1437 if (state
& simPROFILE
) {
1440 /* Since we KNOW that the memory banks are a power-of-2 in size: */
1441 profile_nsamples
= power2(n
);
1442 profile_minpc
= membank_base
;
1443 profile_maxpc
= (membank_base
+ membank_size
);
1445 /* Just in-case we are sampling every address: NOTE: The shift
1446 right of 2 is because we only have word-aligned PC addresses. */
1447 if (profile_nsamples
> (membank_size
>> 2))
1448 profile_nsamples
= (membank_size
>> 2);
1450 /* Since we are dealing with power-of-2 values: */
1451 profile_shift
= (((membank_size
>> 2) / profile_nsamples
) - 1);
1453 bsize
= (profile_nsamples
* sizeof(unsigned short));
1454 if (profile_hist
== NULL
)
1455 profile_hist
= (unsigned short *)calloc(64,(bsize
/ 64));
1457 profile_hist
= (unsigned short *)realloc(profile_hist
,bsize
);
1458 if (profile_hist
== NULL
) {
1459 sim_warning("Failed to allocate VM for profiling buffer (0x%08X bytes)",bsize
);
1460 state
&= ~simPROFILE
;
1463 #endif /* PROFILE */
1470 unsigned int newsize
;
1473 /* Used by "run", and internally, to set the simulated memory size */
1475 callback
->printf_filtered(callback
,"Zero not valid: Memory size still 0x%08X bytes\n",membank_size
);
1478 newsize
= power2(newsize
);
1479 if (membank
== NULL
)
1480 new = (char *)calloc(64,(membank_size
/ 64));
1482 new = (char *)realloc(membank
,newsize
);
1484 if (membank
== NULL
)
1485 sim_error("Not enough VM for simulation memory of 0x%08X bytes",membank_size
);
1487 sim_warning("Failed to resize memory (still 0x%08X bytes)",membank_size
);
1489 membank_size
= (unsigned)newsize
;
1491 #if defined(PROFILE)
1492 /* Ensure that we sample across the new memory range */
1493 sim_set_profile_size(profile_nsamples
);
1494 #endif /* PROFILE */
1503 /* This routine is called by the "run" program, when detailed
1504 execution information is required. Rather than executing a single
1505 instruction, and looping around externally... we just start
1506 simulating, returning TRUE when the simulator stops (for whatever
1510 /* Ensure tracing is enabled, if available */
1511 if (tracefh
!= NULL
)
1515 state
&= ~(simSTOP
| simSTEP
); /* execute until event */
1516 state
|= (simHALTEX
| simHALTIN
); /* treat interrupt event as exception */
1517 /* Start executing instructions from the current state (set
1518 explicitly by register updates, or by sim_create_inferior): */
1524 /*---------------------------------------------------------------------------*/
1525 /*-- Private simulator support interface ------------------------------------*/
1526 /*---------------------------------------------------------------------------*/
1528 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1531 unsigned int reason
;
1533 /* The IDT monitor actually allows two instructions per vector
1534 slot. However, the simulator currently causes a trap on each
1535 individual instruction. We cheat, and lose the bottom bit. */
1538 /* The following callback functions are available, however the
1539 monitor we are simulating does not make use of them: get_errno,
1540 isatty, lseek, rename, system, time and unlink */
1542 case 6: /* int open(char *path,int flags) */
1547 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1548 V0
= callback
->open(callback
,(char *)((int)paddr
),(int)A1
);
1550 sim_error("Attempt to pass pointer that does not reference simulated memory");
1554 case 7: /* int read(int file,char *ptr,int len) */
1559 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1560 V0
= callback
->read(callback
,(int)A0
,(char *)((int)paddr
),(int)A2
);
1562 sim_error("Attempt to pass pointer that does not reference simulated memory");
1566 case 8: /* int write(int file,char *ptr,int len) */
1571 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1572 V0
= callback
->write(callback
,(int)A0
,(const char *)((int)paddr
),(int)A2
);
1574 sim_error("Attempt to pass pointer that does not reference simulated memory");
1578 case 10: /* int close(int file) */
1579 V0
= callback
->close(callback
,(int)A0
);
1582 case 11: /* char inbyte(void) */
1585 if (callback
->read_stdin(callback
,&tmp
,sizeof(char)) != sizeof(char)) {
1586 sim_error("Invalid return from character read");
1594 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1596 char tmp
= (char)(A0
& 0xFF);
1597 callback
->write_stdout(callback
,&tmp
,sizeof(char));
1601 case 17: /* void _exit() */
1602 sim_warning("sim_monitor(17): _exit(int reason) to be coded");
1603 state
|= (simSTOP
| simEXIT
); /* stop executing code */
1604 rcexit
= (unsigned int)(A0
& 0xFFFFFFFF);
1607 case 55: /* void get_mem_info(unsigned int *ptr) */
1608 /* in: A0 = pointer to three word memory location */
1609 /* out: [A0 + 0] = size */
1610 /* [A0 + 4] = instruction cache size */
1611 /* [A0 + 8] = data cache size */
1614 uword64 paddr
, value
;
1618 /* NOTE: We use RAW memory writes here, but since we are not
1619 gathering statistics for the monitor calls we are simulating,
1620 it is not an issue. */
1623 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1624 value
= (uword64
)membank_size
;
1625 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
1626 /* We re-do the address translations, in-case the block
1627 overlaps a memory boundary: */
1629 vaddr
+= (AccessLength_WORD
+ 1);
1630 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1631 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
1632 vaddr
+= (AccessLength_WORD
+ 1);
1633 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
))
1634 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
1643 sim_error("Invalid pointer passed into monitor call");
1647 case 158 : /* PMON printf */
1648 /* in: A0 = pointer to format string */
1649 /* A1 = optional argument 1 */
1650 /* A2 = optional argument 2 */
1651 /* A3 = optional argument 3 */
1653 /* The following is based on the PMON printf source */
1657 /* This isn't the quickest way, since we call the host print
1658 routine for every character almost. But it does avoid
1659 having to allocate and manage a temporary string buffer. */
1660 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1661 char *s
= (char *)((int)paddr
);
1662 ut_reg
*ap
= &A1
; /* 1st argument */
1663 /* TODO: Include check that we only use three arguments (A1, A2 and A3) */
1667 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1668 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1672 if (strchr ("dobxXulscefg%", *s
))
1680 else if (*s
== '*') {
1685 } else if (*s
>= '1' && *s
<= '9') {
1688 for (t
= s
; isdigit (*s
); s
++);
1689 strncpy (tmp
, t
, s
- t
);
1691 n
= (unsigned int)strtol(tmp
,NULL
,10);
1697 } else if (*s
== '.')
1701 callback
->printf_filtered(callback
,"%%");
1702 } else if (*s
== 's') {
1703 if ((int)*ap
!= 0) {
1704 if (AddressTranslation(*ap
++,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1705 char *p
= (char *)((int)paddr
);;
1706 callback
->printf_filtered(callback
,p
);
1709 sim_error("Attempt to pass pointer that does not reference simulated memory");
1713 callback
->printf_filtered(callback
,"(null)");
1714 } else if (*s
== 'c') {
1716 callback
->printf_filtered(callback
,"%c",n
);
1724 if (strchr ("dobxXu", *s
)) {
1725 long long lv
= (long long)*ap
++;
1727 callback
->printf_filtered(callback
,"<binary not supported>");
1729 sprintf(tmp
,"%%%s%c",longlong
? "ll" : "",*s
);
1731 callback
->printf_filtered(callback
,tmp
,lv
);
1733 callback
->printf_filtered(callback
,tmp
,(int)lv
);
1735 } else if (strchr ("eEfgG", *s
)) {
1736 double dbl
= (double)*ap
++;
1737 sprintf(tmp
,"%%%d.%d%c",width
,trunc
,*s
);
1738 callback
->printf_filtered(callback
,tmp
,dbl
);
1744 callback
->printf_filtered(callback
,"%c",*s
++);
1747 sim_error("Attempt to pass pointer that does not reference simulated memory");
1752 sim_warning("TODO: sim_monitor(%d) : PC = 0x%08X%08X",reason
,WORD64HI(IPC
),WORD64LO(IPC
));
1753 sim_warning("(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)",WORD64HI(A0
),WORD64LO(A0
),WORD64HI(A1
),WORD64LO(A1
),WORD64HI(A2
),WORD64LO(A2
),WORD64HI(A3
),WORD64LO(A3
));
1765 if (logfh
!= NULL
) {
1767 fprintf(logfh
,"SIM Warning: ");
1768 fprintf(logfh
,fmt
,ap
);
1769 fprintf(logfh
,"\n");
1770 #else /* we should provide a method of routing log messages to the simulator output stream */
1771 callback
->printf_filtered(callback
,"SIM Warning: ");
1772 callback
->printf_filtered(callback
,fmt
,ap
);
1776 SignalException(SimulatorFault
,"");
1786 callback
->printf_filtered(callback
,"SIM Error: ");
1787 callback
->printf_filtered(callback
,fmt
,ap
);
1789 SignalException(SimulatorFault
,"");
1799 /* Round *UP* to the nearest power-of-2 if not already one */
1800 if (value
!= (value
& ~(value
- 1))) {
1801 for (tmp
= value
, loop
= 0; (tmp
!= 0); loop
++)
1803 value
= (1 << loop
);
1816 num
= strtol(value
,&end
,10);
1818 callback
->printf_filtered(callback
,"Warning: Invalid number \"%s\" ignored, using zero\n",value
);
1820 if (*end
&& ((tolower(*end
) == 'k') || (tolower(*end
) == 'm'))) {
1821 if (tolower(*end
) == 'k')
1828 callback
->printf_filtered(callback
,"Warning: Spurious characters \"%s\" at end of number ignored\n",end
);
1834 /*-- trace support ----------------------------------------------------------*/
1836 /* The TRACE support is provided (if required) in the memory accessing
1837 routines. Since we are also providing the architecture specific
1838 features, the architecture simulation code can also deal with
1839 notifying the TRACE world of cache flushes, etc. Similarly we do
1840 not need to provide profiling support in the simulator engine,
1841 since we can sample in the instruction fetch control loop. By
1842 defining the TRACE manifest, we add tracing as a run-time
1846 /* Tracing by default produces "din" format (as required by
1847 dineroIII). Each line of such a trace file *MUST* have a din label
1848 and address field. The rest of the line is ignored, so comments can
1849 be included if desired. The first field is the label which must be
1850 one of the following values:
1855 3 escape record (treated as unknown access type)
1856 4 escape record (causes cache flush)
1858 The address field is a 32bit (lower-case) hexadecimal address
1859 value. The address should *NOT* be preceded by "0x".
1861 The size of the memory transfer is not important when dealing with
1862 cache lines (as long as no more than a cache line can be
1863 transferred in a single operation :-), however more information
1864 could be given following the dineroIII requirement to allow more
1865 complete memory and cache simulators to provide better
1866 results. i.e. the University of Pisa has a cache simulator that can
1867 also take bus size and speed as (variable) inputs to calculate
1868 complete system performance (a much more useful ability when trying
1869 to construct an end product, rather than a processor). They
1870 currently have an ARM version of their tool called ChARM. */
1873 void dotrace(tracefh
,type
,address
,width
,comment
)
1876 unsigned int address
;
1880 if (state
& simTRACE
) {
1882 fprintf(tracefh
,"%d %08x ; width %d ; ",type
,address
,width
);
1883 va_start(ap
,comment
);
1884 fprintf(tracefh
,comment
,ap
);
1886 fprintf(tracefh
,"\n");
1888 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1889 we may be generating 64bit ones, we should put the hi-32bits of the
1890 address into the comment field. */
1892 /* TODO: Provide a buffer for the trace lines. We can then avoid
1893 performing writes until the buffer is filled, or the file is
1896 /* NOTE: We could consider adding a comment field to the "din" file
1897 produced using type 3 markers (unknown access). This would then
1898 allow information about the program that the "din" is for, and
1899 the MIPs world that was being simulated, to be placed into the
1906 /*---------------------------------------------------------------------------*/
1907 /*-- host<->target transfers ------------------------------------------------*/
1908 /*---------------------------------------------------------------------------*/
1909 /* The following routines allow conditionals to be avoided during the
1910 simulation, at the cost of increasing the image and source size. */
1913 xfer_direct_word(memory
)
1914 unsigned char *memory
;
1916 return *((unsigned int *)memory
);
1920 xfer_direct_long(memory
)
1921 unsigned char *memory
;
1923 return *((uword64
*)memory
);
1927 swap_direct_word(data
)
1934 swap_direct_long(data
)
1941 xfer_big_word(memory
)
1942 unsigned char *memory
;
1944 return ((memory
[0] << 24) | (memory
[1] << 16) | (memory
[2] << 8) | memory
[3]);
1948 xfer_big_long(memory
)
1949 unsigned char *memory
;
1951 return (((uword64
)memory
[0] << 56) | ((uword64
)memory
[1] << 48)
1952 | ((uword64
)memory
[2] << 40) | ((uword64
)memory
[3] << 32)
1953 | (memory
[4] << 24) | (memory
[5] << 16) | (memory
[6] << 8) | memory
[7]);
1957 xfer_little_word(memory
)
1958 unsigned char *memory
;
1960 return ((memory
[3] << 24) | (memory
[2] << 16) | (memory
[1] << 8) | memory
[0]);
1964 xfer_little_long(memory
)
1965 unsigned char *memory
;
1967 return (((uword64
)memory
[7] << 56) | ((uword64
)memory
[6] << 48)
1968 | ((uword64
)memory
[5] << 40) | ((uword64
)memory
[4] << 32)
1969 | (memory
[3] << 24) | (memory
[2] << 16) | (memory
[1] << 8) | memory
[0]);
1976 unsigned int result
;
1977 result
= data
^ ((data
<< 16) | (data
>> 16));
1978 result
&= ~0x00FF0000;
1979 data
= (data
<< 24) | (data
>> 8);
1980 return data
^ (result
>> 8);
1987 unsigned int tmphi
= WORD64HI(data
);
1988 unsigned int tmplo
= WORD64LO(data
);
1989 tmphi
= swap_word(tmphi
);
1990 tmplo
= swap_word(tmplo
);
1991 /* Now swap the HI and LO parts */
1992 return SET64LO(tmphi
) | SET64HI(tmplo
);
1995 /*---------------------------------------------------------------------------*/
1996 /*-- simulator engine -------------------------------------------------------*/
1997 /*---------------------------------------------------------------------------*/
2002 /* RESET: Fixed PC address: */
2003 PC
= (((uword64
)0xFFFFFFFF<<32) | 0xBFC00000);
2004 /* The reset vector address is in the unmapped, uncached memory space. */
2006 SR
&= ~(status_SR
| status_TS
| status_RP
);
2007 SR
|= (status_ERL
| status_BEV
);
2008 /* VR4300 starts in Big-Endian mode */
2009 CONFIG
&= ~(config_EP_mask
<< config_EP_shift
);
2010 CONFIG
|= ((config_EP_D
<< config_EP_shift
) | config_BE
);
2011 /* TODO: The VR4300 CONFIG register is not modelled fully at the moment */
2013 #if defined(HASFPU) && (GPRLEN == (64))
2014 /* Cheat and allow access to the complete register set immediately: */
2015 SR
|= status_FR
; /* 64bit registers */
2016 #endif /* HASFPU and 64bit FP registers */
2018 /* Ensure that any instructions with pending register updates are
2022 for (loop
= 0; (loop
< PSLOTS
); loop
++)
2023 pending_slot_reg
[loop
] = (LAST_EMBED_REGNUM
+ 1);
2024 pending_in
= pending_out
= pending_total
= 0;
2028 /* Initialise the FPU registers to the unknown state */
2031 for (rn
= 0; (rn
< 32); rn
++)
2032 fpr_state
[rn
] = fmt_uninterpreted
;
2036 /* In reality this check should be performed at various points
2037 within the simulation, since it is possible to change the
2038 endianness of user programs. However, we perform the check here
2039 to ensure that the start-of-day values agree: */
2040 state
|= (BigEndianCPU
? simBE
: 0);
2041 if ((target_byte_order
== 1234) != !(state
& simBE
)) {
2042 fprintf(stderr
,"ColdReset: GDB (%s) and simulator (%s) do not agree on target endianness\n",
2043 target_byte_order
== 1234 ? "little" : "big",
2044 state
& simBE
? "big" : "little");
2048 if (!(state
& simHOSTBE
) == !(state
& simBE
)) {
2049 host_read_word
= xfer_direct_word
;
2050 host_read_long
= xfer_direct_long
;
2051 host_swap_word
= swap_direct_word
;
2052 host_swap_long
= swap_direct_long
;
2053 } else if (state
& simHOSTBE
) {
2054 host_read_word
= xfer_little_word
;
2055 host_read_long
= xfer_little_long
;
2056 host_swap_word
= swap_word
;
2057 host_swap_long
= swap_long
;
2058 } else { /* HOST little-endian */
2059 host_read_word
= xfer_big_word
;
2060 host_read_long
= xfer_big_long
;
2061 host_swap_word
= swap_word
;
2062 host_swap_long
= swap_long
;
2068 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2069 /* Translate a virtual address to a physical address and cache
2070 coherence algorithm describing the mechanism used to resolve the
2071 memory reference. Given the virtual address vAddr, and whether the
2072 reference is to Instructions ot Data (IorD), find the corresponding
2073 physical address (pAddr) and the cache coherence algorithm (CCA)
2074 used to resolve the reference. If the virtual address is in one of
2075 the unmapped address spaces the physical address and the CCA are
2076 determined directly by the virtual address. If the virtual address
2077 is in one of the mapped address spaces then the TLB is used to
2078 determine the physical address and access type; if the required
2079 translation is not present in the TLB or the desired access is not
2080 permitted the function fails and an exception is taken.
2082 NOTE: This function is extended to return an exception state. This,
2083 along with the exception generation is used to notify whether a
2084 valid address translation occured */
2087 AddressTranslation(vAddr
,IorD
,LorS
,pAddr
,CCA
,host
,raw
)
2096 int res
= -1; /* TRUE : Assume good return */
2099 callback
->printf_filtered(callback
,"AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr
),WORD64LO(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
2102 /* Check that the address is valid for this memory model */
2104 /* For a simple (flat) memory model, we simply pass virtual
2105 addressess through (mostly) unchanged. */
2106 vAddr
&= 0xFFFFFFFF;
2108 /* Treat the kernel memory spaces identically for the moment: */
2109 if ((membank_base
== K1BASE
) && (vAddr
>= K0BASE
) && (vAddr
< (K0BASE
+ K0SIZE
)))
2110 vAddr
+= (K1BASE
- K0BASE
);
2112 /* Also assume that the K1BASE memory wraps. This is required to
2113 allow the PMON run-time __sizemem() routine to function (without
2114 having to provide exception simulation). NOTE: A kludge to work
2115 around the fact that the monitor memory is currently held in the
2117 if (((vAddr
< monitor_base
) || (vAddr
>= (monitor_base
+ monitor_size
))) && (vAddr
>= K1BASE
&& vAddr
< (K1BASE
+ K1SIZE
)))
2118 vAddr
= (K1BASE
| (vAddr
& (membank_size
- 1)));
2120 *pAddr
= vAddr
; /* default for isTARGET */
2121 *CCA
= Uncached
; /* not used for isHOST */
2123 /* NOTE: This is a duplicate of the code that appears in the
2124 LoadMemory and StoreMemory functions. They should be merged into
2125 a single function (that can be in-lined if required). */
2126 if ((vAddr
>= membank_base
) && (vAddr
< (membank_base
+ membank_size
))) {
2128 *pAddr
= (int)&membank
[((unsigned int)(vAddr
- membank_base
) & (membank_size
- 1))];
2129 } else if ((vAddr
>= monitor_base
) && (vAddr
< (monitor_base
+ monitor_size
))) {
2131 *pAddr
= (int)&monitor
[((unsigned int)(vAddr
- monitor_base
) & (monitor_size
- 1))];
2133 #if 1 /* def DEBUG */
2134 sim_warning("Failed: AddressTranslation(0x%08X%08X,%s,%s,...) IPC = 0x%08X%08X",WORD64HI(vAddr
),WORD64LO(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "isSTORE" : "isLOAD"),WORD64HI(IPC
),WORD64LO(IPC
));
2136 res
= 0; /* AddressTranslation has failed */
2138 if (!raw
) /* only generate exceptions on real memory transfers */
2139 SignalException((LorS
== isSTORE
) ? AddressStore
: AddressLoad
);
2141 sim_warning("AddressTranslation for %s %s from 0x%08X%08X failed",(IorD
? "data" : "instruction"),(LorS
? "store" : "load"),WORD64HI(vAddr
),WORD64LO(vAddr
));
2147 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2148 /* Prefetch data from memory. Prefetch is an advisory instruction for
2149 which an implementation specific action is taken. The action taken
2150 may increase performance, but must not change the meaning of the
2151 program, or alter architecturally-visible state. */
2153 Prefetch(CCA
,pAddr
,vAddr
,DATA
,hint
)
2161 callback
->printf_filtered(callback
,"Prefetch(%d,0x%08X%08X,0x%08X%08X,%d,%d);\n",CCA
,WORD64HI(pAddr
),WORD64LO(pAddr
),WORD64HI(vAddr
),WORD64LO(vAddr
),DATA
,hint
);
2164 /* For our simple memory model we do nothing */
2168 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2169 /* Load a value from memory. Use the cache and main memory as
2170 specified in the Cache Coherence Algorithm (CCA) and the sort of
2171 access (IorD) to find the contents of AccessLength memory bytes
2172 starting at physical location pAddr. The data is returned in the
2173 fixed width naturally-aligned memory element (MemElem). The
2174 low-order two (or three) bits of the address and the AccessLength
2175 indicate which of the bytes within MemElem needs to be given to the
2176 processor. If the memory access type of the reference is uncached
2177 then only the referenced bytes are read from memory and valid
2178 within the memory element. If the access type is cached, and the
2179 data is not present in cache, an implementation specific size and
2180 alignment block of memory is read and loaded into the cache to
2181 satisfy a load reference. At a minimum, the block is the entire
2184 LoadMemory(CCA
,AccessLength
,pAddr
,vAddr
,IorD
,raw
)
2195 if (membank
== NULL
)
2196 callback
->printf_filtered(callback
,"DBG: LoadMemory(%d,%d,0x%08X%08X,0x%08X%08X,%s,%s)\n",CCA
,AccessLength
,WORD64HI(pAddr
),WORD64LO(pAddr
),WORD64HI(vAddr
),WORD64LO(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(raw
? "isRAW" : "isREAL"));
2199 #if defined(WARN_MEM)
2200 if (CCA
!= uncached
)
2201 sim_warning("LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA
);
2203 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
) {
2204 /* In reality this should be a Bus Error */
2205 sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%08X%08X\n",AccessLength
,(LOADDRMASK
+ 1)<<2,WORD64HI(pAddr
),WORD64LO(pAddr
));
2207 #endif /* WARN_MEM */
2209 /* Decide which physical memory locations are being dealt with. At
2210 this point we should be able to split the pAddr bits into the
2211 relevant address map being simulated. If the "raw" variable is
2212 set, the memory read being performed should *NOT* update any I/O
2213 state or affect the CPU state. This also includes avoiding
2214 affecting statistics gathering. */
2216 /* If instruction fetch then we need to check that the two lo-order
2217 bits are zero, otherwise raise a InstructionFetch exception: */
2218 if ((IorD
== isINSTRUCTION
) && ((pAddr
& 0x3) != 0))
2219 SignalException(InstructionFetch
);
2222 unsigned char *mem
= NULL
;
2226 dotrace(tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
2229 /* NOTE: Quicker methods of decoding the address space can be used
2230 when a real memory map is being simulated (i.e. using hi-order
2231 address bits to select device). */
2232 if ((pAddr
>= membank_base
) && (pAddr
< (membank_base
+ membank_size
))) {
2233 index
= ((unsigned int)(pAddr
- membank_base
) & (membank_size
- 1));
2235 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
2236 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
2240 sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr
),WORD64LO(pAddr
));
2242 /* If we obtained the endianness of the host, and it is the same
2243 as the target memory system we can optimise the memory
2244 accesses. However, without that information we must perform
2245 slow transfer, and hope that the compiler optimisation will
2246 merge successive loads. */
2247 value
= 0; /* no data loaded yet */
2249 /* In reality we should always be loading a doubleword value (or
2250 word value in 32bit memory worlds). The external code then
2251 extracts the required bytes. However, to keep performance
2252 high we only load the required bytes into the relevant
2255 switch (AccessLength
) { /* big-endian memory */
2256 case AccessLength_DOUBLEWORD
:
2257 value
|= ((uword64
)mem
[index
++] << 56);
2258 case AccessLength_SEPTIBYTE
:
2259 value
|= ((uword64
)mem
[index
++] << 48);
2260 case AccessLength_SEXTIBYTE
:
2261 value
|= ((uword64
)mem
[index
++] << 40);
2262 case AccessLength_QUINTIBYTE
:
2263 value
|= ((uword64
)mem
[index
++] << 32);
2264 case AccessLength_WORD
:
2265 value
|= ((unsigned int)mem
[index
++] << 24);
2266 case AccessLength_TRIPLEBYTE
:
2267 value
|= ((unsigned int)mem
[index
++] << 16);
2268 case AccessLength_HALFWORD
:
2269 value
|= ((unsigned int)mem
[index
++] << 8);
2270 case AccessLength_BYTE
:
2271 value
|= mem
[index
];
2275 index
+= (AccessLength
+ 1);
2276 switch (AccessLength
) { /* little-endian memory */
2277 case AccessLength_DOUBLEWORD
:
2278 value
|= ((uword64
)mem
[--index
] << 56);
2279 case AccessLength_SEPTIBYTE
:
2280 value
|= ((uword64
)mem
[--index
] << 48);
2281 case AccessLength_SEXTIBYTE
:
2282 value
|= ((uword64
)mem
[--index
] << 40);
2283 case AccessLength_QUINTIBYTE
:
2284 value
|= ((uword64
)mem
[--index
] << 32);
2285 case AccessLength_WORD
:
2286 value
|= ((uword64
)mem
[--index
] << 24);
2287 case AccessLength_TRIPLEBYTE
:
2288 value
|= ((uword64
)mem
[--index
] << 16);
2289 case AccessLength_HALFWORD
:
2290 value
|= ((uword64
)mem
[--index
] << 8);
2291 case AccessLength_BYTE
:
2292 value
|= ((uword64
)mem
[--index
] << 0);
2298 printf("DBG: LoadMemory() : (offset %d) : value = 0x%08X%08X\n",(int)(pAddr
& LOADDRMASK
),WORD64HI(value
),WORD64LO(value
));
2301 /* TODO: We could try and avoid the shifts when dealing with raw
2302 memory accesses. This would mean updating the LoadMemory and
2303 StoreMemory routines to avoid shifting the data before
2304 returning or using it. */
2305 if (!raw
) { /* do nothing for raw accessess */
2307 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
2308 else /* little-endian only needs to be shifted up to the correct byte offset */
2309 value
<<= ((pAddr
& LOADDRMASK
) * 8);
2313 printf("DBG: LoadMemory() : shifted value = 0x%08X%08X\n",WORD64HI(value
),WORD64LO(value
));
2321 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2322 /* Store a value to memory. The specified data is stored into the
2323 physical location pAddr using the memory hierarchy (data caches and
2324 main memory) as specified by the Cache Coherence Algorithm
2325 (CCA). The MemElem contains the data for an aligned, fixed-width
2326 memory element (word for 32-bit processors, doubleword for 64-bit
2327 processors), though only the bytes that will actually be stored to
2328 memory need to be valid. The low-order two (or three) bits of pAddr
2329 and the AccessLength field indicates which of the bytes within the
2330 MemElem data should actually be stored; only these bytes in memory
2333 StoreMemory(CCA
,AccessLength
,MemElem
,pAddr
,vAddr
,raw
)
2342 callback
->printf_filtered(callback
,"DBG: StoreMemory(%d,%d,0x%08X%08X,0x%08X%08X,0x%08X%08X,%s)\n",CCA
,AccessLength
,WORD64HI(MemElem
),WORD64LO(MemElem
),WORD64HI(pAddr
),WORD64LO(pAddr
),WORD64HI(vAddr
),WORD64LO(vAddr
),(raw
? "isRAW" : "isREAL"));
2345 #if defined(WARN_MEM)
2346 if (CCA
!= uncached
)
2347 sim_warning("StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA
);
2349 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
2350 sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%08X%08X\n",AccessLength
,(LOADDRMASK
+ 1)<<2,WORD64HI(pAddr
),WORD64LO(pAddr
));
2351 #endif /* WARN_MEM */
2355 dotrace(tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
2358 /* See the comments in the LoadMemory routine about optimising
2359 memory accesses. Also if we wanted to make the simulator smaller,
2360 we could merge a lot of this code with the LoadMemory
2361 routine. However, this would slow the simulator down with
2362 run-time conditionals. */
2365 unsigned char *mem
= NULL
;
2367 if ((pAddr
>= membank_base
) && (pAddr
< (membank_base
+ membank_size
))) {
2368 index
= ((unsigned int)(pAddr
- membank_base
) & (membank_size
- 1));
2370 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
2371 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
2376 sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr
),WORD64LO(pAddr
));
2381 printf("DBG: StoreMemory: offset = %d MemElem = 0x%08X%08X\n",(unsigned int)(pAddr
& LOADDRMASK
),WORD64HI(MemElem
),WORD64LO(MemElem
));
2386 shift
= ((7 - AccessLength
) * 8);
2387 else /* real memory access */
2388 shift
= ((pAddr
& LOADDRMASK
) * 8);
2391 /* no need to shift raw little-endian data */
2393 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
2397 printf("DBG: StoreMemory: shift = %d MemElem = 0x%08X%08X\n",shift
,WORD64HI(MemElem
),WORD64LO(MemElem
));
2401 switch (AccessLength
) { /* big-endian memory */
2402 case AccessLength_DOUBLEWORD
:
2403 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2405 case AccessLength_SEPTIBYTE
:
2406 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2408 case AccessLength_SEXTIBYTE
:
2409 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2411 case AccessLength_QUINTIBYTE
:
2412 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2414 case AccessLength_WORD
:
2415 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2417 case AccessLength_TRIPLEBYTE
:
2418 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2420 case AccessLength_HALFWORD
:
2421 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2423 case AccessLength_BYTE
:
2424 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2428 index
+= (AccessLength
+ 1);
2429 switch (AccessLength
) { /* little-endian memory */
2430 case AccessLength_DOUBLEWORD
:
2431 mem
[--index
] = (unsigned char)(MemElem
>> 56);
2432 case AccessLength_SEPTIBYTE
:
2433 mem
[--index
] = (unsigned char)(MemElem
>> 48);
2434 case AccessLength_SEXTIBYTE
:
2435 mem
[--index
] = (unsigned char)(MemElem
>> 40);
2436 case AccessLength_QUINTIBYTE
:
2437 mem
[--index
] = (unsigned char)(MemElem
>> 32);
2438 case AccessLength_WORD
:
2439 mem
[--index
] = (unsigned char)(MemElem
>> 24);
2440 case AccessLength_TRIPLEBYTE
:
2441 mem
[--index
] = (unsigned char)(MemElem
>> 16);
2442 case AccessLength_HALFWORD
:
2443 mem
[--index
] = (unsigned char)(MemElem
>> 8);
2444 case AccessLength_BYTE
:
2445 mem
[--index
] = (unsigned char)(MemElem
>> 0);
2455 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2456 /* Order loads and stores to synchronise shared memory. Perform the
2457 action necessary to make the effects of groups of synchronizable
2458 loads and stores indicated by stype occur in the same order for all
2461 SyncOperation(stype
)
2465 callback
->printf_filtered(callback
,"SyncOperation(%d) : TODO\n",stype
);
2470 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2471 /* Signal an exception condition. This will result in an exception
2472 that aborts the instruction. The instruction operation pseudocode
2473 will never see a return from this function call. */
2475 SignalException(exception
)
2478 /* Ensure that any active atomic read/modify/write operation will fail: */
2481 switch (exception
) {
2482 /* TODO: For testing purposes I have been ignoring TRAPs. In
2483 reality we should either simulate them, or allow the user to
2484 ignore them at run-time. */
2486 sim_warning("Ignoring instruction TRAP (PC 0x%08X%08X)",WORD64HI(IPC
),WORD64LO(IPC
));
2489 case ReservedInstruction
:
2492 unsigned int instruction
;
2493 va_start(ap
,exception
);
2494 instruction
= va_arg(ap
,unsigned int);
2496 /* Provide simple monitor support using ReservedInstruction
2497 exceptions. The following code simulates the fixed vector
2498 entry points into the IDT monitor by causing a simulator
2499 trap, performing the monitor operation, and returning to
2500 the address held in the $ra register (standard PCS return
2501 address). This means we only need to pre-load the vector
2502 space with suitable instruction values. For systems were
2503 actual trap instructions are used, we would not need to
2504 perform this magic. */
2505 if ((instruction
& ~RSVD_INSTRUCTION_AMASK
) == RSVD_INSTRUCTION
) {
2506 sim_monitor(instruction
& RSVD_INSTRUCTION_AMASK
);
2507 PC
= RA
; /* simulate the return from the vector entry */
2508 /* NOTE: This assumes that a branch-and-link style
2509 instruction was used to enter the vector (which is the
2510 case with the current IDT monitor). */
2511 break; /* out of the switch statement */
2512 } /* else fall through to normal exception processing */
2513 sim_warning("ReservedInstruction 0x%08X at IPC = 0x%08X%08X",instruction
,WORD64HI(IPC
),WORD64LO(IPC
));
2517 #if 1 /* def DEBUG */
2518 if (exception
!= BreakPoint
)
2519 callback
->printf_filtered(callback
,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception
,WORD64HI(IPC
),WORD64LO(IPC
));
2521 /* Store exception code into current exception id variable (used
2524 /* TODO: If not simulating exceptions then stop the simulator
2525 execution. At the moment we always stop the simulation. */
2526 #if 1 /* bodge to allow exit() code to be returned, by assuming that a breakpoint exception after a monitor exit() call should be silent */
2527 /* further bodged since the standard libgloss/mips world doesn't use the _exit() monitor call, it just uses a break instruction */
2528 if (exception
== BreakPoint
/* && state & simEXIT */)
2531 #if 1 /* since the _exit() monitor call may not be called */
2533 rcexit
= (unsigned int)(A0
& 0xFFFFFFFF);
2537 state
|= (simSTOP
| simEXCEPTION
);
2539 state
|= (simSTOP
| simEXCEPTION
);
2541 CAUSE
= (exception
<< 2);
2542 if (state
& simDELAYSLOT
) {
2544 EPC
= (IPC
- 4); /* reference the branch instruction */
2547 /* The following is so that the simulator will continue from the
2548 exception address on breakpoint operations. */
2552 case SimulatorFault
:
2556 va_start(ap
,exception
);
2557 msg
= va_arg(ap
,char *);
2558 fprintf(stderr
,"FATAL: Simulator error \"%s\"\n",msg
);
2567 #if defined(WARN_RESULT)
2568 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2569 /* This function indicates that the result of the operation is
2570 undefined. However, this should not affect the instruction
2571 stream. All that is meant to happen is that the destination
2572 register is set to an undefined result. To keep the simulator
2573 simple, we just don't bother updating the destination register, so
2574 the overall result will be undefined. If desired we can stop the
2575 simulator by raising a pseudo-exception. */
2579 sim_warning("UndefinedResult: IPC = 0x%08X%08X",WORD64HI(IPC
),WORD64LO(IPC
));
2580 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2585 #endif /* WARN_RESULT */
2588 CacheOp(op
,pAddr
,vAddr
,instruction
)
2592 unsigned int instruction
;
2594 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2595 static int icache_warning
= 1;
2596 static int dcache_warning
= 1;
2598 static int icache_warning
= 0;
2599 static int dcache_warning
= 0;
2602 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2603 enable bit in the Status Register is clear - a coprocessor
2604 unusable exception is taken. */
2606 callback
->printf_filtered(callback
,"TODO: Cache availability checking (PC = 0x%08X%08X)\n",WORD64HI(IPC
),WORD64LO(IPC
));
2610 case 0: /* instruction cache */
2612 case 0: /* Index Invalidate */
2613 case 1: /* Index Load Tag */
2614 case 2: /* Index Store Tag */
2615 case 4: /* Hit Invalidate */
2617 case 6: /* Hit Writeback */
2618 if (!icache_warning
)
2620 sim_warning("Instruction CACHE operation %d to be coded",(op
>> 2));
2626 SignalException(ReservedInstruction
,instruction
);
2631 case 1: /* data cache */
2633 case 0: /* Index Writeback Invalidate */
2634 case 1: /* Index Load Tag */
2635 case 2: /* Index Store Tag */
2636 case 3: /* Create Dirty */
2637 case 4: /* Hit Invalidate */
2638 case 5: /* Hit Writeback Invalidate */
2639 case 6: /* Hit Writeback */
2640 if (!dcache_warning
)
2642 sim_warning("Data CACHE operation %d to be coded",(op
>> 2));
2648 SignalException(ReservedInstruction
,instruction
);
2653 default: /* unrecognised cache ID */
2654 SignalException(ReservedInstruction
,instruction
);
2661 /*-- FPU support routines ---------------------------------------------------*/
2663 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
2666 #define SizeFGR() (GPRLEN)
2668 /* They depend on the CPU being simulated */
2669 #define SizeFGR() ((PROCESSOR_64BIT && ((SR & status_FR) == 1)) ? 64 : 32)
2672 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2673 formats conform to ANSI/IEEE Std 754-1985. */
2674 /* SINGLE precision floating:
2675 * seeeeeeeefffffffffffffffffffffff
2677 * e = 8bits = exponent
2678 * f = 23bits = fraction
2680 /* SINGLE precision fixed:
2681 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2683 * i = 31bits = integer
2685 /* DOUBLE precision floating:
2686 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2688 * e = 11bits = exponent
2689 * f = 52bits = fraction
2691 /* DOUBLE precision fixed:
2692 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2694 * i = 63bits = integer
2697 /* Extract sign-bit: */
2698 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2699 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2700 /* Extract biased exponent: */
2701 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2702 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2703 /* Extract unbiased Exponent: */
2704 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2705 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2706 /* Extract complete fraction field: */
2707 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2708 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2709 /* Extract numbered fraction bit: */
2710 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2711 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2713 /* Explicit QNaN values used when value required: */
2714 #define FPQNaN_SINGLE (0x7FBFFFFF)
2715 #define FPQNaN_WORD (0x7FFFFFFF)
2716 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2717 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2719 /* Explicit Infinity values used when required: */
2720 #define FPINF_SINGLE (0x7F800000)
2721 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2723 #if 1 /* def DEBUG */
2724 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2725 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2736 /* Treat unused register values, as fixed-point 64bit values: */
2737 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2739 /* If request to read data as "uninterpreted", then use the current
2741 fmt
= fpr_state
[fpr
];
2746 /* For values not yet accessed, set to the desired format: */
2747 if (fpr_state
[fpr
] == fmt_uninterpreted
) {
2748 fpr_state
[fpr
] = fmt
;
2750 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2753 if (fmt
!= fpr_state
[fpr
]) {
2754 sim_warning("FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)",fpr
,DOFMT(fpr_state
[fpr
]),DOFMT(fmt
),WORD64HI(IPC
),WORD64LO(IPC
));
2755 fpr_state
[fpr
] = fmt_unknown
;
2758 if (fpr_state
[fpr
] == fmt_unknown
) {
2759 /* Set QNaN value: */
2762 value
= FPQNaN_SINGLE
;
2766 value
= FPQNaN_DOUBLE
;
2770 value
= FPQNaN_WORD
;
2774 value
= FPQNaN_LONG
;
2781 } else if (SizeFGR() == 64) {
2785 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2788 case fmt_uninterpreted
:
2798 } else if ((fpr
& 1) == 0) { /* even registers only */
2802 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2805 case fmt_uninterpreted
:
2808 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2818 SignalException(SimulatorFault
,"Unrecognised FP format in ValueFPR()");
2821 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),WORD64HI(value
),WORD64LO(value
),WORD64HI(IPC
),WORD64LO(IPC
),SizeFGR());
2828 StoreFPR(fpr
,fmt
,value
)
2836 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),WORD64HI(value
),WORD64LO(value
),WORD64HI(IPC
),WORD64LO(IPC
),SizeFGR());
2839 if (SizeFGR() == 64) {
2843 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2844 fpr_state
[fpr
] = fmt
;
2847 case fmt_uninterpreted
:
2851 fpr_state
[fpr
] = fmt
;
2855 fpr_state
[fpr
] = fmt_unknown
;
2859 } else if ((fpr
& 1) == 0) { /* even register number only */
2863 FGR
[fpr
+1] = 0xDEADC0DE;
2864 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2865 fpr_state
[fpr
+ 1] = fmt
;
2866 fpr_state
[fpr
] = fmt
;
2869 case fmt_uninterpreted
:
2872 FGR
[fpr
+1] = (value
>> 32);
2873 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2874 fpr_state
[fpr
+ 1] = fmt
;
2875 fpr_state
[fpr
] = fmt
;
2879 fpr_state
[fpr
] = fmt_unknown
;
2884 #if defined(WARN_RESULT)
2887 #endif /* WARN_RESULT */
2890 SignalException(SimulatorFault
,"Unrecognised FP format in StoreFPR()");
2893 printf("DBG: StoreFPR: fpr[%d] = 0x%08X%08X (format %s)\n",fpr
,WORD64HI(FGR
[fpr
]),WORD64LO(FGR
[fpr
]),DOFMT(fmt
));
2906 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
2907 know that the exponent field is biased... we we cheat and avoid
2908 removing the bias value. */
2911 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) != 0));
2912 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2913 dealing with a SNaN or QNaN */
2916 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) != 0));
2917 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2918 dealing with a SNaN or QNaN */
2921 boolean
= (op
== FPQNaN_WORD
);
2924 boolean
= (op
== FPQNaN_LONG
);
2929 printf("DBG: NaN: returning %d for 0x%08X%08X (format = %s)\n",boolean
,WORD64HI(op
),WORD64LO(op
),DOFMT(fmt
));
2943 printf("DBG: Infinity: format %s 0x%08X%08X (PC = 0x%08X%08X)\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
),WORD64HI(IPC
),WORD64LO(IPC
));
2946 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
2947 know that the exponent field is biased... we we cheat and avoid
2948 removing the bias value. */
2951 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) == 0));
2954 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) == 0));
2957 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2962 printf("DBG: Infinity: returning %d for 0x%08X%08X (format = %s)\n",boolean
,WORD64HI(op
),WORD64LO(op
),DOFMT(fmt
));
2976 /* Argument checking already performed by the FPCOMPARE code */
2979 printf("DBG: Less: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
2982 /* The format type should already have been checked: */
2986 unsigned int wop1
= (unsigned int)op1
;
2987 unsigned int wop2
= (unsigned int)op2
;
2988 boolean
= (*(float *)&wop1
< *(float *)&wop2
);
2992 boolean
= (*(double *)&op1
< *(double *)&op2
);
2997 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
3011 /* Argument checking already performed by the FPCOMPARE code */
3014 printf("DBG: Equal: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
3017 /* The format type should already have been checked: */
3020 boolean
= ((op1
& 0xFFFFFFFF) == (op2
& 0xFFFFFFFF));
3023 boolean
= (op1
== op2
);
3028 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
3035 AbsoluteValue(op
,fmt
)
3042 printf("DBG: AbsoluteValue: %s: op = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
));
3045 /* The format type should already have been checked: */
3049 unsigned int wop
= (unsigned int)op
;
3050 float tmp
= ((float)fabs((double)*(float *)&wop
));
3051 result
= (uword64
)*(unsigned int *)&tmp
;
3056 double tmp
= (fabs(*(double *)&op
));
3057 result
= *(uword64
*)&tmp
;
3072 printf("DBG: Negate: %s: op = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
));
3075 /* The format type should already have been checked: */
3079 unsigned int wop
= (unsigned int)op
;
3080 float tmp
= ((float)0.0 - *(float *)&wop
);
3081 result
= (uword64
)*(unsigned int *)&tmp
;
3086 double tmp
= ((double)0.0 - *(double *)&op
);
3087 result
= *(uword64
*)&tmp
;
3104 printf("DBG: Add: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
3107 /* The registers must specify FPRs valid for operands of type
3108 "fmt". If they are not valid, the result is undefined. */
3110 /* The format type should already have been checked: */
3114 unsigned int wop1
= (unsigned int)op1
;
3115 unsigned int wop2
= (unsigned int)op2
;
3116 float tmp
= (*(float *)&wop1
+ *(float *)&wop2
);
3117 result
= (uword64
)*(unsigned int *)&tmp
;
3122 double tmp
= (*(double *)&op1
+ *(double *)&op2
);
3123 result
= *(uword64
*)&tmp
;
3129 printf("DBG: Add: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
3144 printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
3147 /* The registers must specify FPRs valid for operands of type
3148 "fmt". If they are not valid, the result is undefined. */
3150 /* The format type should already have been checked: */
3154 unsigned int wop1
= (unsigned int)op1
;
3155 unsigned int wop2
= (unsigned int)op2
;
3156 float tmp
= (*(float *)&wop1
- *(float *)&wop2
);
3157 result
= (uword64
)*(unsigned int *)&tmp
;
3162 double tmp
= (*(double *)&op1
- *(double *)&op2
);
3163 result
= *(uword64
*)&tmp
;
3169 printf("DBG: Sub: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
3176 Multiply(op1
,op2
,fmt
)
3184 printf("DBG: Multiply: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
3187 /* The registers must specify FPRs valid for operands of type
3188 "fmt". If they are not valid, the result is undefined. */
3190 /* The format type should already have been checked: */
3194 unsigned int wop1
= (unsigned int)op1
;
3195 unsigned int wop2
= (unsigned int)op2
;
3196 float tmp
= (*(float *)&wop1
* *(float *)&wop2
);
3197 result
= (uword64
)*(unsigned int *)&tmp
;
3202 double tmp
= (*(double *)&op1
* *(double *)&op2
);
3203 result
= *(uword64
*)&tmp
;
3209 printf("DBG: Multiply: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
3224 printf("DBG: Divide: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
3227 /* The registers must specify FPRs valid for operands of type
3228 "fmt". If they are not valid, the result is undefined. */
3230 /* The format type should already have been checked: */
3234 unsigned int wop1
= (unsigned int)op1
;
3235 unsigned int wop2
= (unsigned int)op2
;
3236 float tmp
= (*(float *)&wop1
/ *(float *)&wop2
);
3237 result
= (uword64
)*(unsigned int *)&tmp
;
3242 double tmp
= (*(double *)&op1
/ *(double *)&op2
);
3243 result
= *(uword64
*)&tmp
;
3249 printf("DBG: Divide: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
3263 printf("DBG: Recip: %s: op = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
));
3266 /* The registers must specify FPRs valid for operands of type
3267 "fmt". If they are not valid, the result is undefined. */
3269 /* The format type should already have been checked: */
3273 unsigned int wop
= (unsigned int)op
;
3274 float tmp
= ((float)1.0 / *(float *)&wop
);
3275 result
= (uword64
)*(unsigned int *)&tmp
;
3280 double tmp
= ((double)1.0 / *(double *)&op
);
3281 result
= *(uword64
*)&tmp
;
3287 printf("DBG: Recip: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
3301 printf("DBG: SquareRoot: %s: op = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
));
3304 /* The registers must specify FPRs valid for operands of type
3305 "fmt". If they are not valid, the result is undefined. */
3307 /* The format type should already have been checked: */
3311 unsigned int wop
= (unsigned int)op
;
3312 float tmp
= ((float)sqrt((double)*(float *)&wop
));
3313 result
= (uword64
)*(unsigned int *)&tmp
;
3318 double tmp
= (sqrt(*(double *)&op
));
3319 result
= *(uword64
*)&tmp
;
3325 printf("DBG: SquareRoot: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
3332 Convert(rm
,op
,from
,to
)
3341 printf("DBG: Convert: mode %s : op 0x%08X%08X : from %s : to %s : (PC = 0x%08X%08X)\n",RMMODE(rm
),WORD64HI(op
),WORD64LO(op
),DOFMT(from
),DOFMT(to
),WORD64HI(IPC
),WORD64LO(IPC
));
3344 /* The value "op" is converted to the destination format, rounding
3345 using mode "rm". When the destination is a fixed-point format,
3346 then a source value of Infinity, NaN or one which would round to
3347 an integer outside the fixed point range then an IEEE Invalid
3348 Operation condition is raised. */
3355 tmp
= (float)(*(double *)&op
);
3359 tmp
= (float)((int)(op
& 0xFFFFFFFF));
3363 tmp
= (float)((int)op
);
3368 /* FIXME: This code is incorrect. The rounding mode does not
3369 round to integral values; it rounds to the nearest
3370 representable value in the format. */
3374 /* Round result to nearest representable value. When two
3375 representable values are equally near, round to the value
3376 that has a least significant bit of zero (i.e. is even). */
3378 tmp
= (float)anint((double)tmp
);
3380 /* TODO: Provide round-to-nearest */
3385 /* Round result to the value closest to, and not greater in
3386 magnitude than, the result. */
3388 tmp
= (float)aint((double)tmp
);
3390 /* TODO: Provide round-to-zero */
3395 /* Round result to the value closest to, and not less than,
3397 tmp
= (float)ceil((double)tmp
);
3401 /* Round result to the value closest to, and not greater than,
3403 tmp
= (float)floor((double)tmp
);
3408 result
= (uword64
)*(unsigned int *)&tmp
;
3420 unsigned int wop
= (unsigned int)op
;
3421 tmp
= (double)(*(float *)&wop
);
3426 xxx
= SIGNEXTEND((op
& 0xFFFFFFFF),32);
3431 tmp
= (double)((word64
)op
);
3436 /* FIXME: This code is incorrect. The rounding mode does not
3437 round to integral values; it rounds to the nearest
3438 representable value in the format. */
3443 tmp
= anint(*(double *)&tmp
);
3445 /* TODO: Provide round-to-nearest */
3451 tmp
= aint(*(double *)&tmp
);
3453 /* TODO: Provide round-to-zero */
3458 tmp
= ceil(*(double *)&tmp
);
3462 tmp
= floor(*(double *)&tmp
);
3467 result
= *(uword64
*)&tmp
;
3473 if (Infinity(op
,from
) || NaN(op
,from
) || (1 == 0/*TODO: check range */)) {
3474 printf("DBG: TODO: update FCSR\n");
3475 SignalException(FPE
);
3477 if (to
== fmt_word
) {
3482 unsigned int wop
= (unsigned int)op
;
3483 tmp
= (unsigned int)*((float *)&wop
);
3487 tmp
= (unsigned int)*((double *)&op
);
3489 printf("DBG: from double %.30f (0x%08X%08X) to word: 0x%08X\n",*((double *)&op
),WORD64HI(op
),WORD64LO(op
),tmp
);
3493 result
= (uword64
)tmp
;
3494 } else { /* fmt_long */
3498 unsigned int wop
= (unsigned int)op
;
3499 result
= (uword64
)*((float *)&wop
);
3503 result
= (uword64
)*((double *)&op
);
3512 printf("DBG: Convert: returning 0x%08X%08X (to format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(to
));
3519 /*-- co-processor support routines ------------------------------------------*/
3522 CoProcPresent(coproc_number
)
3523 unsigned int coproc_number
;
3525 /* Return TRUE if simulator provides a model for the given co-processor number */
3530 COP_LW(coproc_num
,coproc_reg
,memword
)
3531 int coproc_num
, coproc_reg
;
3532 unsigned int memword
;
3534 switch (coproc_num
) {
3538 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%08X%08X\n",memword
,WORD64HI(memword
),WORD64LO(memword
));
3540 StoreFPR(coproc_reg
,fmt_uninterpreted
,(uword64
)memword
);
3545 #if 0 /* this should be controlled by a configuration option */
3546 callback
->printf_filtered(callback
,"COP_LW(%d,%d,0x%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,WORD64HI(IPC
),WORD64LO(IPC
));
3555 COP_LD(coproc_num
,coproc_reg
,memword
)
3556 int coproc_num
, coproc_reg
;
3559 switch (coproc_num
) {
3562 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3567 #if 0 /* this message should be controlled by a configuration option */
3568 callback
->printf_filtered(callback
,"COP_LD(%d,%d,0x%08X%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,WORD64HI(memword
),WORD64LO(memword
),WORD64HI(IPC
),WORD64LO(IPC
));
3577 COP_SW(coproc_num
,coproc_reg
)
3578 int coproc_num
, coproc_reg
;
3580 unsigned int value
= 0;
3581 switch (coproc_num
) {
3585 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3588 value
= (unsigned int)ValueFPR(coproc_reg
,fpr_state
[coproc_reg
]);
3591 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(fpr_state
[coproc_reg
]));
3593 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
3600 #if 0 /* should be controlled by configuration option */
3601 callback
->printf_filtered(callback
,"COP_SW(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,WORD64HI(IPC
),WORD64LO(IPC
));
3610 COP_SD(coproc_num
,coproc_reg
)
3611 int coproc_num
, coproc_reg
;
3614 switch (coproc_num
) {
3618 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3621 value
= ValueFPR(coproc_reg
,fpr_state
[coproc_reg
]);
3624 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(fpr_state
[coproc_reg
]));
3626 value
= ValueFPR(coproc_reg
,fmt_double
);
3633 #if 0 /* should be controlled by configuration option */
3634 callback
->printf_filtered(callback
,"COP_SD(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,WORD64HI(IPC
),WORD64LO(IPC
));
3643 decode_coproc(instruction
)
3644 unsigned int instruction
;
3646 int coprocnum
= ((instruction
>> 26) & 3);
3648 switch (coprocnum
) {
3649 case 0: /* standard CPU control and cache registers */
3652 Standard CP0 registers
3653 0 = Index R4000 VR4100 VR4300
3654 1 = Random R4000 VR4100 VR4300
3655 2 = EntryLo0 R4000 VR4100 VR4300
3656 3 = EntryLo1 R4000 VR4100 VR4300
3657 4 = Context R4000 VR4100 VR4300
3658 5 = PageMask R4000 VR4100 VR4300
3659 6 = Wired R4000 VR4100 VR4300
3660 8 = BadVAddr R4000 VR4100 VR4300
3661 9 = Count R4000 VR4100 VR4300
3662 10 = EntryHi R4000 VR4100 VR4300
3663 11 = Compare R4000 VR4100 VR4300
3664 12 = SR R4000 VR4100 VR4300
3665 13 = Cause R4000 VR4100 VR4300
3666 14 = EPC R4000 VR4100 VR4300
3667 15 = PRId R4000 VR4100 VR4300
3668 16 = Config R4000 VR4100 VR4300
3669 17 = LLAddr R4000 VR4100 VR4300
3670 18 = WatchLo R4000 VR4100 VR4300
3671 19 = WatchHi R4000 VR4100 VR4300
3672 20 = XContext R4000 VR4100 VR4300
3673 26 = PErr or ECC R4000 VR4100 VR4300
3674 27 = CacheErr R4000 VR4100
3675 28 = TagLo R4000 VR4100 VR4300
3676 29 = TagHi R4000 VR4100 VR4300
3677 30 = ErrorEPC R4000 VR4100 VR4300
3679 int code
= ((instruction
>> 21) & 0x1F);
3680 /* R4000 Users Manual (second edition) lists the following CP0
3682 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3683 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3684 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3685 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3686 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3687 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3688 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3689 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3690 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3691 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3693 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0)) {
3694 int rt
= ((instruction
>> 16) & 0x1F);
3695 int rd
= ((instruction
>> 11) & 0x1F);
3696 if (code
== 0x00) { /* MF : move from */
3697 #if 0 /* message should be controlled by configuration option */
3698 callback
->printf_filtered(callback
,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt
,rd
);
3700 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3701 } else { /* MT : move to */
3702 /* CPR[0,rd] = GPR[rt]; */
3703 #if 0 /* should be controlled by configuration option */
3704 callback
->printf_filtered(callback
,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt
,rd
);
3708 sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present",instruction
,WORD64HI(IPC
),WORD64LO(IPC
));
3709 /* TODO: When executing an ERET or RFE instruction we should
3710 clear LLBIT, to ensure that any out-standing atomic
3711 read/modify/write sequence fails. */
3715 case 2: /* undefined co-processor */
3716 sim_warning("COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present",instruction
,WORD64HI(IPC
),WORD64LO(IPC
));
3719 case 1: /* should not occur (FPU co-processor) */
3720 case 3: /* should not occur (FPU co-processor) */
3721 SignalException(ReservedInstruction
,instruction
);
3728 /*-- instruction simulation -------------------------------------------------*/
3733 unsigned int pipeline_count
= 1;
3736 if (membank
== NULL
) {
3737 printf("DBG: simulate() entered with no memory\n");
3742 #if 0 /* Disabled to check that everything works OK */
3743 /* The VR4300 seems to sign-extend the PC on its first
3744 access. However, this may just be because it is currently
3745 configured in 32bit mode. However... */
3746 PC
= SIGNEXTEND(PC
,32);
3749 /* main controlling loop */
3751 /* Fetch the next instruction from the simulator memory: */
3752 uword64 vaddr
= (uword64
)PC
;
3755 unsigned int instruction
;
3756 int dsstate
= (state
& simDELAYSLOT
);
3760 printf("DBG: state = 0x%08X :",state
);
3761 if (state
& simSTOP
) printf(" simSTOP");
3762 if (state
& simSTEP
) printf(" simSTEP");
3763 if (state
& simHALTEX
) printf(" simHALTEX");
3764 if (state
& simHALTIN
) printf(" simHALTIN");
3765 if (state
& simBE
) printf(" simBE");
3771 callback
->printf_filtered(callback
,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC
),WORD64LO(DSPC
));
3774 if (AddressTranslation(PC
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) { /* Copy the action of the LW instruction */
3775 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3776 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3779 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3780 value
= LoadMemory(cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3781 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3782 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3784 fprintf(stderr
,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC
),WORD64LO(PC
));
3789 callback
->printf_filtered(callback
,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction
,WORD64HI(PC
),WORD64LO(PC
));
3792 #if !defined(FASTSIM) || defined(PROFILE)
3793 instruction_fetches
++;
3794 /* Since we increment above, the value should only ever be zero if
3795 we have just overflowed: */
3796 if (instruction_fetches
== 0)
3797 instruction_fetch_overflow
++;
3798 #if defined(PROFILE)
3799 if ((state
& simPROFILE
) && ((instruction_fetches
% profile_frequency
) == 0) && profile_hist
) {
3800 int n
= ((unsigned int)(PC
- profile_minpc
) >> (profile_shift
+ 2));
3801 if (n
< profile_nsamples
) {
3802 /* NOTE: The counts for the profiling bins are only 16bits wide */
3803 if (profile_hist
[n
] != USHRT_MAX
)
3804 (profile_hist
[n
])++;
3807 #endif /* PROFILE */
3808 #endif /* !FASTSIM && PROFILE */
3810 IPC
= PC
; /* copy PC for this instruction */
3811 /* This is required by exception processing, to ensure that we can
3812 cope with exceptions in the delay slots of branches that may
3813 already have changed the PC. */
3814 PC
+= 4; /* increment ready for the next fetch */
3815 /* NOTE: If we perform a delay slot change to the PC, this
3816 increment is not requuired. However, it would make the
3817 simulator more complicated to try and avoid this small hit. */
3819 /* Currently this code provides a simple model. For more
3820 complicated models we could perform exception status checks at
3821 this point, and set the simSTOP state as required. This could
3822 also include processing any hardware interrupts raised by any
3823 I/O model attached to the simulator context.
3825 Support for "asynchronous" I/O events within the simulated world
3826 could be providing by managing a counter, and calling a I/O
3827 specific handler when a particular threshold is reached. On most
3828 architectures a decrement and check for zero operation is
3829 usually quicker than an increment and compare. However, the
3830 process of managing a known value decrement to zero, is higher
3831 than the cost of using an explicit value UINT_MAX into the
3832 future. Which system is used will depend on how complicated the
3833 I/O model is, and how much it is likely to affect the simulator
3836 If events need to be scheduled further in the future than
3837 UINT_MAX event ticks, then the I/O model should just provide its
3838 own counter, triggered from the event system. */
3840 /* MIPS pipeline ticks. To allow for future support where the
3841 pipeline hit of individual instructions is known, this control
3842 loop manages a "pipeline_count" variable. It is initialised to
3843 1 (one), and will only be changed by the simulator engine when
3844 executing an instruction. If the engine does not have access to
3845 pipeline cycle count information then all instructions will be
3846 treated as using a single cycle. NOTE: A standard system is not
3847 provided by the default simulator because different MIPS
3848 architectures have different cycle counts for the same
3852 /* Set previous flag, depending on current: */
3853 if (state
& simPCOC0
)
3857 /* and update the current value: */
3864 /* NOTE: For multi-context simulation environments the "instruction"
3865 variable should be local to this routine. */
3867 /* Shorthand accesses for engine. Note: If we wanted to use global
3868 variables (and a single-threaded simulator engine), then we can
3869 create the actual variables with these names. */
3871 if (!(state
& simSKIPNEXT
)) {
3872 /* Include the simulator engine */
3874 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3875 #error "Mismatch between run-time simulator code and simulation engine"
3878 #if defined(WARN_LOHI)
3879 /* Decrement the HI/LO validity ticks */
3884 #endif /* WARN_LOHI */
3886 #if defined(WARN_ZERO)
3887 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3888 should check for it being changed. It is better doing it here,
3889 than within the simulator, since it will help keep the simulator
3892 sim_warning("The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X) (reset back to zero)",WORD64HI(ZERO
),WORD64LO(ZERO
),WORD64HI(IPC
),WORD64LO(IPC
));
3893 ZERO
= 0; /* reset back to zero before next instruction */
3895 #endif /* WARN_ZERO */
3896 } else /* simSKIPNEXT check */
3897 state
&= ~simSKIPNEXT
;
3899 /* If the delay slot was active before the instruction is
3900 executed, then update the PC to its new value: */
3903 printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC
),WORD64LO(DSPC
));
3906 state
&= ~simDELAYSLOT
;
3909 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3910 /* Deal with pending register updates: */
3912 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3914 if (pending_out
!= pending_in
) {
3916 int index
= pending_out
;
3917 int total
= pending_total
;
3918 if (pending_total
== 0) {
3919 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3922 for (loop
= 0; (loop
< total
); loop
++) {
3924 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3926 if (pending_slot_reg
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3928 printf("pending_slot_count[%d] = %d\n",index
,pending_slot_count
[index
]);
3930 if (--(pending_slot_count
[index
]) == 0) {
3932 printf("pending_slot_reg[%d] = %d\n",index
,pending_slot_reg
[index
]);
3933 printf("pending_slot_value[%d] = 0x%08X%08X\n",index
,WORD64HI(pending_slot_value
[index
]),WORD64LO(pending_slot_value
[index
]));
3935 if (pending_slot_reg
[index
] == COCIDX
) {
3936 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3938 registers
[pending_slot_reg
[index
]] = pending_slot_value
[index
];
3940 /* The only time we have PENDING updates to FPU
3941 registers, is when performing binary transfers. This
3942 means we should update the register type field. */
3943 if ((pending_slot_reg
[index
] >= FGRIDX
) && (pending_slot_reg
[index
] < (FGRIDX
+ 32)))
3944 fpr_state
[pending_slot_reg
[index
]] = fmt_uninterpreted
;
3948 printf("registers[%d] = 0x%08X%08X\n",pending_slot_reg
[index
],WORD64HI(registers
[pending_slot_reg
[index
]]),WORD64LO(registers
[pending_slot_reg
[index
]]));
3950 pending_slot_reg
[index
] = (LAST_EMBED_REGNUM
+ 1);
3952 if (pending_out
== PSLOTS
)
3958 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3961 if (index
== PSLOTS
)
3966 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3970 #if !defined(FASTSIM)
3971 pipeline_ticks
+= pipeline_count
;
3972 #endif /* FASTSIM */
3974 if (state
& simSTEP
)
3976 } while (!(state
& simSTOP
));
3979 if (membank
== NULL
) {
3980 printf("DBG: simulate() LEAVING with no memory\n");
3988 /*---------------------------------------------------------------------------*/
3989 /*> EOF interp.c <*/