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IGEN likes to cache the current instruction address (CIA). Change the
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
18 $Date$
19
20 NOTEs:
21
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 code on the hardware.
26
27 */
28
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
33 #define TRACE (1)
34 #endif
35
36 #include "bfd.h"
37 #include "sim-main.h"
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
41
42 #include "config.h"
43
44 #include <stdio.h>
45 #include <stdarg.h>
46 #include <ansidecl.h>
47 #include <ctype.h>
48 #include <limits.h>
49 #include <math.h>
50 #ifdef HAVE_STDLIB_H
51 #include <stdlib.h>
52 #endif
53 #ifdef HAVE_STRING_H
54 #include <string.h>
55 #else
56 #ifdef HAVE_STRINGS_H
57 #include <strings.h>
58 #endif
59 #endif
60
61 #include "getopt.h"
62 #include "libiberty.h"
63 #include "bfd.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
66
67 #include "sysdep.h"
68
69 #ifndef PARAMS
70 #define PARAMS(x)
71 #endif
72
73 char* pr_addr PARAMS ((SIM_ADDR addr));
74 char* pr_uword64 PARAMS ((uword64 addr));
75
76
77 /* Get the simulator engine description, without including the code: */
78 #define SIM_MANIFESTS
79 #include "oengine.c"
80 #undef SIM_MANIFESTS
81
82
83 /* The following reserved instruction value is used when a simulator
84 trap is required. NOTE: Care must be taken, since this value may be
85 used in later revisions of the MIPS ISA. */
86 #define RSVD_INSTRUCTION (0x00000005)
87 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
88
89 #define RSVD_INSTRUCTION_ARG_SHIFT 6
90 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
91
92
93 /* Bits in the Debug register */
94 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
95 #define Debug_DM 0x40000000 /* Debug Mode */
96 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
97
98
99
100
101
102 /*---------------------------------------------------------------------------*/
103 /*-- GDB simulator interface ------------------------------------------------*/
104 /*---------------------------------------------------------------------------*/
105
106 static void dotrace PARAMS((SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...));
107 static void ColdReset PARAMS((SIM_DESC sd));
108
109 /*---------------------------------------------------------------------------*/
110
111
112
113 #define DELAYSLOT() {\
114 if (STATE & simDELAYSLOT)\
115 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
116 STATE |= simDELAYSLOT;\
117 }
118
119 #define JALDELAYSLOT() {\
120 DELAYSLOT ();\
121 STATE |= simJALDELAYSLOT;\
122 }
123
124 #define NULLIFY() {\
125 STATE &= ~simDELAYSLOT;\
126 STATE |= simSKIPNEXT;\
127 }
128
129 #define CANCELDELAYSLOT() {\
130 DSSTATE = 0;\
131 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
132 }
133
134 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
135 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
136
137 #define K0BASE (0x80000000)
138 #define K0SIZE (0x20000000)
139 #define K1BASE (0xA0000000)
140 #define K1SIZE (0x20000000)
141 #define MONITOR_BASE (0xBFC00000)
142 #define MONITOR_SIZE (1 << 11)
143 #define MEM_SIZE (2 << 20)
144
145 #if defined(TRACE)
146 static char *tracefile = "trace.din"; /* default filename for trace log */
147 static FILE *tracefh = NULL;
148 static void open_trace PARAMS((SIM_DESC sd));
149 #endif /* TRACE */
150
151 #define OPTION_DINERO_TRACE 200
152 #define OPTION_DINERO_FILE 201
153
154 static SIM_RC
155 mips_option_handler (sd, opt, arg)
156 SIM_DESC sd;
157 int opt;
158 char *arg;
159 {
160 switch (opt)
161 {
162 case OPTION_DINERO_TRACE: /* ??? */
163 #if defined(TRACE)
164 /* Eventually the simTRACE flag could be treated as a toggle, to
165 allow external control of the program points being traced
166 (i.e. only from main onwards, excluding the run-time setup,
167 etc.). */
168 if (arg == NULL)
169 STATE |= simTRACE;
170 else if (strcmp (arg, "yes") == 0)
171 STATE |= simTRACE;
172 else if (strcmp (arg, "no") == 0)
173 STATE &= ~simTRACE;
174 else if (strcmp (arg, "on") == 0)
175 STATE |= simTRACE;
176 else if (strcmp (arg, "off") == 0)
177 STATE &= ~simTRACE;
178 else
179 {
180 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
181 return SIM_RC_FAIL;
182 }
183 return SIM_RC_OK;
184 #else /* !TRACE */
185 fprintf(stderr,"\
186 Simulator constructed without dinero tracing support (for performance).\n\
187 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
188 return SIM_RC_FAIL;
189 #endif /* !TRACE */
190
191 case OPTION_DINERO_FILE:
192 #if defined(TRACE)
193 if (optarg != NULL) {
194 char *tmp;
195 tmp = (char *)malloc(strlen(optarg) + 1);
196 if (tmp == NULL)
197 {
198 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
199 return SIM_RC_FAIL;
200 }
201 else {
202 strcpy(tmp,optarg);
203 tracefile = tmp;
204 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
205 }
206 }
207 #endif /* TRACE */
208 return SIM_RC_OK;
209
210 }
211
212 return SIM_RC_OK;
213 }
214
215 static const OPTION mips_options[] =
216 {
217 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
218 '\0', "on|off", "Enable dinero tracing",
219 mips_option_handler },
220 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
221 '\0', "FILE", "Write dinero trace to FILE",
222 mips_option_handler },
223 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
224 };
225
226
227 int interrupt_pending;
228
229 static void
230 interrupt_event (SIM_DESC sd, void *data)
231 {
232 if (SR & status_IE)
233 {
234 interrupt_pending = 0;
235 SignalExceptionInterrupt ();
236 }
237 else if (!interrupt_pending)
238 sim_events_schedule (sd, 1, interrupt_event, data);
239 }
240
241
242
243 /*---------------------------------------------------------------------------*/
244 /*-- GDB simulator interface ------------------------------------------------*/
245 /*---------------------------------------------------------------------------*/
246
247 SIM_DESC
248 sim_open (kind, cb, abfd, argv)
249 SIM_OPEN_KIND kind;
250 host_callback *cb;
251 struct _bfd *abfd;
252 char **argv;
253 {
254 SIM_DESC sd = sim_state_alloc (kind, cb);
255 sim_cpu *cpu = STATE_CPU (sd, 0);
256
257 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
258
259 /* FIXME: watchpoints code shouldn't need this */
260 STATE_WATCHPOINTS (sd)->pc = &(PC);
261 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
262 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
263
264 STATE = 0;
265
266 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
267 return 0;
268 sim_add_option_table (sd, mips_options);
269
270 /* Allocate core managed memory */
271
272 /* the monitor */
273 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
274 /* For compatibility with the old code - under this (at level one)
275 are the kernel spaces K0 & K1. Both of these map to a single
276 smaller sub region */
277 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
278 K1BASE, K0SIZE,
279 MEM_SIZE, /* actual size */
280 K0BASE);
281
282 /* getopt will print the error message so we just have to exit if this fails.
283 FIXME: Hmmm... in the case of gdb we need getopt to call
284 print_filtered. */
285 if (sim_parse_args (sd, argv) != SIM_RC_OK)
286 {
287 /* Uninstall the modules to avoid memory leaks,
288 file descriptor leaks, etc. */
289 sim_module_uninstall (sd);
290 return 0;
291 }
292
293 /* check for/establish the a reference program image */
294 if (sim_analyze_program (sd,
295 (STATE_PROG_ARGV (sd) != NULL
296 ? *STATE_PROG_ARGV (sd)
297 : NULL),
298 abfd) != SIM_RC_OK)
299 {
300 sim_module_uninstall (sd);
301 return 0;
302 }
303
304 /* Configure/verify the target byte order and other runtime
305 configuration options */
306 if (sim_config (sd) != SIM_RC_OK)
307 {
308 sim_module_uninstall (sd);
309 return 0;
310 }
311
312 if (sim_post_argv_init (sd) != SIM_RC_OK)
313 {
314 /* Uninstall the modules to avoid memory leaks,
315 file descriptor leaks, etc. */
316 sim_module_uninstall (sd);
317 return 0;
318 }
319
320 /* verify assumptions the simulator made about the host type system.
321 This macro does not return if there is a problem */
322 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
323 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
324
325 #if defined(HASFPU)
326 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
327 and DOUBLE binary formats. This is a bit nasty, requiring that we
328 trust the explicit manifests held in the source: */
329 /* TODO: We need to cope with the simulated target and the host not
330 having the same endianness. This will require the high and low
331 words of a (double) to be swapped when converting between the
332 host and the simulated target. */
333 {
334 union {
335 unsigned int i[2];
336 double d;
337 float f[2];
338 } s;
339
340 s.d = (double)523.2939453125;
341
342 if ((s.i[0] == 0 && (s.f[1] != (float)4.01102924346923828125
343 || s.i[1] != 0x40805A5A))
344 || (s.i[1] == 0 && (s.f[0] != (float)4.01102924346923828125
345 || s.i[0] != 0x40805A5A)))
346 {
347 fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
348 return 0;
349 }
350 }
351 #endif /* HASFPU */
352
353 /* This is NASTY, in that we are assuming the size of specific
354 registers: */
355 {
356 int rn;
357 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
358 if (rn < 32)
359 cpu->register_widths[rn] = GPRLEN;
360 else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
361 cpu->register_widths[rn] = GPRLEN;
362 else if ((rn >= 33) && (rn <= 37))
363 cpu->register_widths[rn] = GPRLEN;
364 else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
365 cpu->register_widths[rn] = 32;
366 else
367 cpu->register_widths[rn] = 0;
368 }
369 /* start-sanitize-r5900 */
370
371 /* set the 5900 "upper" registers to 64 bits */
372 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
373 cpu->register_widths[rn] = 64;
374 /* end-sanitize-r5900 */
375 }
376
377 #if defined(TRACE)
378 if (STATE & simTRACE)
379 open_trace(sd);
380 #endif /* TRACE */
381
382 /* Write the monitor trap address handlers into the monitor (eeprom)
383 address space. This can only be done once the target endianness
384 has been determined. */
385 {
386 unsigned loop;
387 /* Entry into the IDT monitor is via fixed address vectors, and
388 not using machine instructions. To avoid clashing with use of
389 the MIPS TRAP system, we place our own (simulator specific)
390 "undefined" instructions into the relevant vector slots. */
391 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
392 {
393 address_word vaddr = (MONITOR_BASE + loop);
394 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
395 H2T (insn);
396 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
397 }
398 /* The PMON monitor uses the same address space, but rather than
399 branching into it the address of a routine is loaded. We can
400 cheat for the moment, and direct the PMON routine to IDT style
401 instructions within the monitor space. This relies on the IDT
402 monitor not using the locations from 0xBFC00500 onwards as its
403 entry points.*/
404 for (loop = 0; (loop < 24); loop++)
405 {
406 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
407 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
408 switch (loop)
409 {
410 case 0: /* read */
411 value = 7;
412 break;
413 case 1: /* write */
414 value = 8;
415 break;
416 case 2: /* open */
417 value = 6;
418 break;
419 case 3: /* close */
420 value = 10;
421 break;
422 case 5: /* printf */
423 value = ((0x500 - 16) / 8); /* not an IDT reason code */
424 break;
425 case 8: /* cliexit */
426 value = 17;
427 break;
428 case 11: /* flush_cache */
429 value = 28;
430 break;
431 }
432 /* FIXME - should monitor_base be SIM_ADDR?? */
433 value = ((unsigned int)MONITOR_BASE + (value * 8));
434 H2T (value);
435 sim_write (sd, vaddr, (char *)&value, sizeof (value));
436
437 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
438 vaddr -= 0x300;
439 sim_write (sd, vaddr, (char *)&value, sizeof (value));
440 }
441 }
442
443 return sd;
444 }
445
446 #if defined(TRACE)
447 static void
448 open_trace(sd)
449 SIM_DESC sd;
450 {
451 tracefh = fopen(tracefile,"wb+");
452 if (tracefh == NULL)
453 {
454 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
455 tracefh = stderr;
456 }
457 }
458 #endif /* TRACE */
459
460 void
461 sim_close (sd, quitting)
462 SIM_DESC sd;
463 int quitting;
464 {
465 #ifdef DEBUG
466 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
467 #endif
468
469 /* "quitting" is non-zero if we cannot hang on errors */
470
471 /* Ensure that any resources allocated through the callback
472 mechanism are released: */
473 sim_io_shutdown (sd);
474
475 #if defined(TRACE)
476 if (tracefh != NULL && tracefh != stderr)
477 fclose(tracefh);
478 tracefh = NULL;
479 STATE &= ~simTRACE;
480 #endif /* TRACE */
481
482 return;
483 }
484
485
486 int
487 sim_write (sd,addr,buffer,size)
488 SIM_DESC sd;
489 SIM_ADDR addr;
490 unsigned char *buffer;
491 int size;
492 {
493 int index;
494
495 /* Return the number of bytes written, or zero if error. */
496 #ifdef DEBUG
497 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
498 #endif
499
500 /* We use raw read and write routines, since we do not want to count
501 the GDB memory accesses in our statistics gathering. */
502
503 for (index = 0; index < size; index++)
504 {
505 address_word vaddr = (address_word)addr + index;
506 address_word paddr;
507 int cca;
508 if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
509 break;
510 if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
511 break;
512 }
513
514 return(index);
515 }
516
517 int
518 sim_read (sd,addr,buffer,size)
519 SIM_DESC sd;
520 SIM_ADDR addr;
521 unsigned char *buffer;
522 int size;
523 {
524 int index;
525
526 /* Return the number of bytes read, or zero if error. */
527 #ifdef DEBUG
528 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
529 #endif /* DEBUG */
530
531 for (index = 0; (index < size); index++)
532 {
533 address_word vaddr = (address_word)addr + index;
534 address_word paddr;
535 int cca;
536 if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
537 break;
538 if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
539 break;
540 }
541
542 return(index);
543 }
544
545 void
546 sim_store_register (sd,rn,memory)
547 SIM_DESC sd;
548 int rn;
549 unsigned char *memory;
550 {
551 sim_cpu *cpu = STATE_CPU (sd, 0);
552 /* NOTE: gdb (the client) stores registers in target byte order
553 while the simulator uses host byte order */
554 #ifdef DEBUG
555 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
556 #endif /* DEBUG */
557
558 /* Unfortunately this suffers from the same problem as the register
559 numbering one. We need to know what the width of each logical
560 register number is for the architecture being simulated. */
561
562 if (cpu->register_widths[rn] == 0)
563 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
564 /* start-sanitize-r5900 */
565 else if (rn == REGISTER_SA)
566 SA = T2H_8(*(uword64*)memory);
567 else if (rn > LAST_EMBED_REGNUM)
568 cpu->registers1[rn - LAST_EMBED_REGNUM - 1] = T2H_8(*(uword64*)memory);
569 /* end-sanitize-r5900 */
570 else if (cpu->register_widths[rn] == 32)
571 cpu->registers[rn] = T2H_4 (*(unsigned int*)memory);
572 else
573 cpu->registers[rn] = T2H_8 (*(uword64*)memory);
574
575 return;
576 }
577
578 void
579 sim_fetch_register (sd,rn,memory)
580 SIM_DESC sd;
581 int rn;
582 unsigned char *memory;
583 {
584 sim_cpu *cpu = STATE_CPU (sd, 0);
585 /* NOTE: gdb (the client) stores registers in target byte order
586 while the simulator uses host byte order */
587 #ifdef DEBUG
588 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
589 #endif /* DEBUG */
590
591 if (cpu->register_widths[rn] == 0)
592 sim_io_eprintf(sd,"Invalid register width for %d (register fetch ignored)\n",rn);
593 /* start-sanitize-r5900 */
594 else if (rn == REGISTER_SA)
595 *((uword64 *)memory) = H2T_8(SA);
596 else if (rn > LAST_EMBED_REGNUM)
597 *((uword64 *)memory) = H2T_8(cpu->registers1[rn - LAST_EMBED_REGNUM - 1]);
598 /* end-sanitize-r5900 */
599 else if (cpu->register_widths[rn] == 32)
600 *((unsigned int *)memory) = H2T_4 ((unsigned int)(cpu->registers[rn] & 0xFFFFFFFF));
601 else /* 64bit register */
602 *((uword64 *)memory) = H2T_8 (cpu->registers[rn]);
603
604 return;
605 }
606
607
608 void
609 sim_info (sd,verbose)
610 SIM_DESC sd;
611 int verbose;
612 {
613 /* Accessed from the GDB "info files" command: */
614 if (STATE_VERBOSE_P (sd) || verbose)
615 {
616
617 sim_io_printf (sd, "MIPS %d-bit %s endian simulator\n",
618 (PROCESSOR_64BIT ? 64 : 32),
619 (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN ? "Big" : "Little"));
620
621 #if !defined(FASTSIM)
622 /* It would be a useful feature, if when performing multi-cycle
623 simulations (rather than single-stepping) we keep the start and
624 end times of the execution, so that we can give a performance
625 figure for the simulator. */
626 #endif /* !FASTSIM */
627 sim_io_printf (sd, "Number of execution cycles = %ld\n",
628 (long) sim_events_time (sd));
629
630 /* print information pertaining to MIPS ISA and architecture being simulated */
631 /* things that may be interesting */
632 /* instructions executed - if available */
633 /* cycles executed - if available */
634 /* pipeline stalls - if available */
635 /* virtual time taken */
636 /* profiling size */
637 /* profiling frequency */
638 /* profile minpc */
639 /* profile maxpc */
640 }
641 profile_print (sd, STATE_VERBOSE_P (sd), NULL, NULL);
642 }
643
644
645 SIM_RC
646 sim_create_inferior (sd, abfd, argv,env)
647 SIM_DESC sd;
648 struct _bfd *abfd;
649 char **argv;
650 char **env;
651 {
652
653 #ifdef DEBUG
654 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
655 pr_addr(PC));
656 #endif /* DEBUG */
657
658 ColdReset(sd);
659
660 if (abfd != NULL)
661 /* override PC value set by ColdReset () */
662 PC = (unsigned64) bfd_get_start_address (abfd);
663
664 #if 0 /* def DEBUG */
665 if (argv || env)
666 {
667 /* We should really place the argv slot values into the argument
668 registers, and onto the stack as required. However, this
669 assumes that we have a stack defined, which is not
670 necessarily true at the moment. */
671 char **cptr;
672 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
673 for (cptr = argv; (cptr && *cptr); cptr++)
674 printf("DBG: arg \"%s\"\n",*cptr);
675 }
676 #endif /* DEBUG */
677
678 return SIM_RC_OK;
679 }
680
681 void
682 sim_do_command (sd,cmd)
683 SIM_DESC sd;
684 char *cmd;
685 {
686 if (sim_args_command (sd, cmd) != SIM_RC_OK)
687 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
688 cmd);
689 }
690
691 /*---------------------------------------------------------------------------*/
692 /*-- Private simulator support interface ------------------------------------*/
693 /*---------------------------------------------------------------------------*/
694
695 /* Read a null terminated string from memory, return in a buffer */
696 static char *
697 fetch_str (sd, addr)
698 SIM_DESC sd;
699 address_word addr;
700 {
701 char *buf;
702 int nr = 0;
703 char null;
704 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
705 nr++;
706 buf = NZALLOC (char, nr + 1);
707 sim_read (sd, addr, buf, nr);
708 return buf;
709 }
710
711 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
712 static void
713 sim_monitor(sd,reason)
714 SIM_DESC sd;
715 unsigned int reason;
716 {
717 #ifdef DEBUG
718 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
719 #endif /* DEBUG */
720
721 /* The IDT monitor actually allows two instructions per vector
722 slot. However, the simulator currently causes a trap on each
723 individual instruction. We cheat, and lose the bottom bit. */
724 reason >>= 1;
725
726 /* The following callback functions are available, however the
727 monitor we are simulating does not make use of them: get_errno,
728 isatty, lseek, rename, system, time and unlink */
729 switch (reason)
730 {
731
732 case 6: /* int open(char *path,int flags) */
733 {
734 char *path = fetch_str (sd, A0);
735 V0 = sim_io_open (sd, path, (int)A1);
736 zfree (path);
737 break;
738 }
739
740 case 7: /* int read(int file,char *ptr,int len) */
741 {
742 int fd = A0;
743 int nr = A2;
744 char *buf = zalloc (nr);
745 V0 = sim_io_read (sd, fd, buf, nr);
746 sim_write (sd, A1, buf, nr);
747 zfree (buf);
748 }
749 break;
750
751 case 8: /* int write(int file,char *ptr,int len) */
752 {
753 int fd = A0;
754 int nr = A2;
755 char *buf = zalloc (nr);
756 sim_read (sd, A1, buf, nr);
757 V0 = sim_io_write (sd, fd, buf, nr);
758 zfree (buf);
759 break;
760 }
761
762 case 10: /* int close(int file) */
763 {
764 V0 = sim_io_close (sd, (int)A0);
765 break;
766 }
767
768 case 11: /* char inbyte(void) */
769 {
770 char tmp;
771 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
772 {
773 sim_io_error(sd,"Invalid return from character read");
774 V0 = (ut_reg)-1;
775 }
776 else
777 V0 = (ut_reg)tmp;
778 break;
779 }
780
781 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
782 {
783 char tmp = (char)(A0 & 0xFF);
784 sim_io_write_stdout (sd, &tmp, sizeof(char));
785 break;
786 }
787
788 case 17: /* void _exit() */
789 {
790 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
791 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited,
792 (unsigned int)(A0 & 0xFFFFFFFF));
793 break;
794 }
795
796 case 28 : /* PMON flush_cache */
797 break;
798
799 case 55: /* void get_mem_info(unsigned int *ptr) */
800 /* in: A0 = pointer to three word memory location */
801 /* out: [A0 + 0] = size */
802 /* [A0 + 4] = instruction cache size */
803 /* [A0 + 8] = data cache size */
804 {
805 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
806 H2T (value);
807 sim_write (sd, A0, (char *)&value, sizeof (value));
808 sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n");
809 break;
810 }
811
812 case 158 : /* PMON printf */
813 /* in: A0 = pointer to format string */
814 /* A1 = optional argument 1 */
815 /* A2 = optional argument 2 */
816 /* A3 = optional argument 3 */
817 /* out: void */
818 /* The following is based on the PMON printf source */
819 {
820 address_word s = A0;
821 char c;
822 signed_word *ap = &A1; /* 1st argument */
823 /* This isn't the quickest way, since we call the host print
824 routine for every character almost. But it does avoid
825 having to allocate and manage a temporary string buffer. */
826 /* TODO: Include check that we only use three arguments (A1,
827 A2 and A3) */
828 while (sim_read (sd, s++, &c, 1) && c != '\0')
829 {
830 if (c == '%')
831 {
832 char tmp[40];
833 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
834 int width = 0, trunc = 0, haddot = 0, longlong = 0;
835 while (sim_read (sd, s++, &c, 1) && c != '\0')
836 {
837 if (strchr ("dobxXulscefg%", s))
838 break;
839 else if (c == '-')
840 fmt = FMT_LJUST;
841 else if (c == '0')
842 fmt = FMT_RJUST0;
843 else if (c == '~')
844 fmt = FMT_CENTER;
845 else if (c == '*')
846 {
847 if (haddot)
848 trunc = (int)*ap++;
849 else
850 width = (int)*ap++;
851 }
852 else if (c >= '1' && c <= '9')
853 {
854 address_word t = s;
855 unsigned int n;
856 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
857 tmp[s - t] = c;
858 tmp[s - t] = '\0';
859 n = (unsigned int)strtol(tmp,NULL,10);
860 if (haddot)
861 trunc = n;
862 else
863 width = n;
864 s--;
865 }
866 else if (c == '.')
867 haddot = 1;
868 }
869 switch (c)
870 {
871 case '%':
872 sim_io_printf (sd, "%%");
873 break;
874 case 's':
875 if ((int)*ap != 0)
876 {
877 address_word p = *ap++;
878 char ch;
879 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
880 sim_io_printf(sd, "%c", ch);
881 }
882 else
883 sim_io_printf(sd,"(null)");
884 break;
885 case 'c':
886 sim_io_printf (sd, "%c", (int)*ap++);
887 break;
888 default:
889 if (c == 'l')
890 {
891 sim_read (sd, s++, &c, 1);
892 if (c == 'l')
893 {
894 longlong = 1;
895 sim_read (sd, s++, &c, 1);
896 }
897 }
898 if (strchr ("dobxXu", c))
899 {
900 word64 lv = (word64) *ap++;
901 if (c == 'b')
902 sim_io_printf(sd,"<binary not supported>");
903 else
904 {
905 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
906 if (longlong)
907 sim_io_printf(sd, tmp, lv);
908 else
909 sim_io_printf(sd, tmp, (int)lv);
910 }
911 }
912 else if (strchr ("eEfgG", c))
913 {
914 double dbl = *(double*)(ap++);
915 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
916 sim_io_printf (sd, tmp, dbl);
917 trunc = 0;
918 }
919 }
920 }
921 else
922 sim_io_printf(sd, "%c", c);
923 }
924 break;
925 }
926
927 default:
928 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
929 reason, pr_addr(IPC));
930 break;
931 }
932 return;
933 }
934
935 /* Store a word into memory. */
936
937 static void
938 store_word (sd, cia, vaddr, val)
939 SIM_DESC sd;
940 address_word cia;
941 uword64 vaddr;
942 t_reg val;
943 {
944 address_word paddr;
945 int uncached;
946
947 if ((vaddr & 3) != 0)
948 SignalExceptionAddressStore ();
949 else
950 {
951 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
952 isTARGET, isREAL))
953 {
954 const uword64 mask = 7;
955 uword64 memval;
956 unsigned int byte;
957
958 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
959 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
960 memval = ((uword64) val) << (8 * byte);
961 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
962 isREAL);
963 }
964 }
965 }
966
967 /* Load a word from memory. */
968
969 static t_reg
970 load_word (sd, cia, vaddr)
971 SIM_DESC sd;
972 address_word cia;
973 uword64 vaddr;
974 {
975 if ((vaddr & 3) != 0)
976 SignalExceptionAddressLoad ();
977 else
978 {
979 address_word paddr;
980 int uncached;
981
982 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
983 isTARGET, isREAL))
984 {
985 const uword64 mask = 0x7;
986 const unsigned int reverse = ReverseEndian ? 1 : 0;
987 const unsigned int bigend = BigEndianCPU ? 1 : 0;
988 uword64 memval;
989 unsigned int byte;
990
991 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
992 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
993 isDATA, isREAL);
994 byte = (vaddr & mask) ^ (bigend << 2);
995 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
996 }
997 }
998
999 return 0;
1000 }
1001
1002 /* Simulate the mips16 entry and exit pseudo-instructions. These
1003 would normally be handled by the reserved instruction exception
1004 code, but for ease of simulation we just handle them directly. */
1005
1006 static void
1007 mips16_entry (sd,insn)
1008 SIM_DESC sd;
1009 unsigned int insn;
1010 {
1011 int aregs, sregs, rreg;
1012
1013 #ifdef DEBUG
1014 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1015 #endif /* DEBUG */
1016
1017 aregs = (insn & 0x700) >> 8;
1018 sregs = (insn & 0x0c0) >> 6;
1019 rreg = (insn & 0x020) >> 5;
1020
1021 /* This should be checked by the caller. */
1022 if (sregs == 3)
1023 abort ();
1024
1025 if (aregs < 5)
1026 {
1027 int i;
1028 t_reg tsp;
1029
1030 /* This is the entry pseudo-instruction. */
1031
1032 for (i = 0; i < aregs; i++)
1033 store_word ((uword64) (SP + 4 * i), GPR[i + 4]);
1034
1035 tsp = SP;
1036 SP -= 32;
1037
1038 if (rreg)
1039 {
1040 tsp -= 4;
1041 store_word ((uword64) tsp, RA);
1042 }
1043
1044 for (i = 0; i < sregs; i++)
1045 {
1046 tsp -= 4;
1047 store_word ((uword64) tsp, GPR[16 + i]);
1048 }
1049 }
1050 else
1051 {
1052 int i;
1053 t_reg tsp;
1054
1055 /* This is the exit pseudo-instruction. */
1056
1057 tsp = SP + 32;
1058
1059 if (rreg)
1060 {
1061 tsp -= 4;
1062 RA = load_word ((uword64) tsp);
1063 }
1064
1065 for (i = 0; i < sregs; i++)
1066 {
1067 tsp -= 4;
1068 GPR[i + 16] = load_word ((uword64) tsp);
1069 }
1070
1071 SP += 32;
1072
1073 #if defined(HASFPU)
1074 if (aregs == 5)
1075 {
1076 FGR[0] = WORD64LO (GPR[4]);
1077 FPR_STATE[0] = fmt_uninterpreted;
1078 }
1079 else if (aregs == 6)
1080 {
1081 FGR[0] = WORD64LO (GPR[5]);
1082 FGR[1] = WORD64LO (GPR[4]);
1083 FPR_STATE[0] = fmt_uninterpreted;
1084 FPR_STATE[1] = fmt_uninterpreted;
1085 }
1086 #endif /* defined(HASFPU) */
1087
1088 PC = RA;
1089 }
1090 }
1091
1092 /*-- trace support ----------------------------------------------------------*/
1093
1094 /* The TRACE support is provided (if required) in the memory accessing
1095 routines. Since we are also providing the architecture specific
1096 features, the architecture simulation code can also deal with
1097 notifying the TRACE world of cache flushes, etc. Similarly we do
1098 not need to provide profiling support in the simulator engine,
1099 since we can sample in the instruction fetch control loop. By
1100 defining the TRACE manifest, we add tracing as a run-time
1101 option. */
1102
1103 #if defined(TRACE)
1104 /* Tracing by default produces "din" format (as required by
1105 dineroIII). Each line of such a trace file *MUST* have a din label
1106 and address field. The rest of the line is ignored, so comments can
1107 be included if desired. The first field is the label which must be
1108 one of the following values:
1109
1110 0 read data
1111 1 write data
1112 2 instruction fetch
1113 3 escape record (treated as unknown access type)
1114 4 escape record (causes cache flush)
1115
1116 The address field is a 32bit (lower-case) hexadecimal address
1117 value. The address should *NOT* be preceded by "0x".
1118
1119 The size of the memory transfer is not important when dealing with
1120 cache lines (as long as no more than a cache line can be
1121 transferred in a single operation :-), however more information
1122 could be given following the dineroIII requirement to allow more
1123 complete memory and cache simulators to provide better
1124 results. i.e. the University of Pisa has a cache simulator that can
1125 also take bus size and speed as (variable) inputs to calculate
1126 complete system performance (a much more useful ability when trying
1127 to construct an end product, rather than a processor). They
1128 currently have an ARM version of their tool called ChARM. */
1129
1130
1131 static
1132 void dotrace(SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
1133 {
1134 if (STATE & simTRACE) {
1135 va_list ap;
1136 fprintf(tracefh,"%d %s ; width %d ; ",
1137 type,
1138 pr_addr(address),
1139 width);
1140 va_start(ap,comment);
1141 vfprintf(tracefh,comment,ap);
1142 va_end(ap);
1143 fprintf(tracefh,"\n");
1144 }
1145 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1146 we may be generating 64bit ones, we should put the hi-32bits of the
1147 address into the comment field. */
1148
1149 /* TODO: Provide a buffer for the trace lines. We can then avoid
1150 performing writes until the buffer is filled, or the file is
1151 being closed. */
1152
1153 /* NOTE: We could consider adding a comment field to the "din" file
1154 produced using type 3 markers (unknown access). This would then
1155 allow information about the program that the "din" is for, and
1156 the MIPs world that was being simulated, to be placed into the
1157 trace file. */
1158
1159 return;
1160 }
1161 #endif /* TRACE */
1162
1163 /*---------------------------------------------------------------------------*/
1164 /*-- simulator engine -------------------------------------------------------*/
1165 /*---------------------------------------------------------------------------*/
1166
1167 static void
1168 ColdReset (sd)
1169 SIM_DESC sd;
1170 {
1171 /* RESET: Fixed PC address: */
1172 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
1173 /* The reset vector address is in the unmapped, uncached memory space. */
1174
1175 SR &= ~(status_SR | status_TS | status_RP);
1176 SR |= (status_ERL | status_BEV);
1177
1178 /* Cheat and allow access to the complete register set immediately */
1179 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1180 && WITH_TARGET_WORD_BITSIZE == 64)
1181 SR |= status_FR; /* 64bit registers */
1182
1183 /* Ensure that any instructions with pending register updates are
1184 cleared: */
1185 {
1186 int loop;
1187 for (loop = 0; (loop < PSLOTS); loop++)
1188 PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1);
1189 PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
1190 }
1191
1192 /* Initialise the FPU registers to the unknown state */
1193 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1194 {
1195 int rn;
1196 for (rn = 0; (rn < 32); rn++)
1197 FPR_STATE[rn] = fmt_uninterpreted;
1198 }
1199
1200 return;
1201 }
1202
1203 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1204 (revision 3.1) */
1205 /* Translate a virtual address to a physical address and cache
1206 coherence algorithm describing the mechanism used to resolve the
1207 memory reference. Given the virtual address vAddr, and whether the
1208 reference is to Instructions ot Data (IorD), find the corresponding
1209 physical address (pAddr) and the cache coherence algorithm (CCA)
1210 used to resolve the reference. If the virtual address is in one of
1211 the unmapped address spaces the physical address and the CCA are
1212 determined directly by the virtual address. If the virtual address
1213 is in one of the mapped address spaces then the TLB is used to
1214 determine the physical address and access type; if the required
1215 translation is not present in the TLB or the desired access is not
1216 permitted the function fails and an exception is taken.
1217
1218 NOTE: Normally (RAW == 0), when address translation fails, this
1219 function raises an exception and does not return. */
1220
1221 int
1222 address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
1223 SIM_DESC sd;
1224 address_word cia;
1225 address_word vAddr;
1226 int IorD;
1227 int LorS;
1228 address_word *pAddr;
1229 int *CCA;
1230 int raw;
1231 {
1232 int res = -1; /* TRUE : Assume good return */
1233
1234 #ifdef DEBUG
1235 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
1236 #endif
1237
1238 /* Check that the address is valid for this memory model */
1239
1240 /* For a simple (flat) memory model, we simply pass virtual
1241 addressess through (mostly) unchanged. */
1242 vAddr &= 0xFFFFFFFF;
1243
1244 *pAddr = vAddr; /* default for isTARGET */
1245 *CCA = Uncached; /* not used for isHOST */
1246
1247 return(res);
1248 }
1249
1250 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1251 (revision 3.1) */
1252 /* Prefetch data from memory. Prefetch is an advisory instruction for
1253 which an implementation specific action is taken. The action taken
1254 may increase performance, but must not change the meaning of the
1255 program, or alter architecturally-visible state. */
1256
1257 void
1258 prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
1259 SIM_DESC sd;
1260 address_word cia;
1261 int CCA;
1262 address_word pAddr;
1263 address_word vAddr;
1264 int DATA;
1265 int hint;
1266 {
1267 #ifdef DEBUG
1268 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
1269 #endif /* DEBUG */
1270
1271 /* For our simple memory model we do nothing */
1272 return;
1273 }
1274
1275 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1276 (revision 3.1) */
1277 /* Load a value from memory. Use the cache and main memory as
1278 specified in the Cache Coherence Algorithm (CCA) and the sort of
1279 access (IorD) to find the contents of AccessLength memory bytes
1280 starting at physical location pAddr. The data is returned in the
1281 fixed width naturally-aligned memory element (MemElem). The
1282 low-order two (or three) bits of the address and the AccessLength
1283 indicate which of the bytes within MemElem needs to be given to the
1284 processor. If the memory access type of the reference is uncached
1285 then only the referenced bytes are read from memory and valid
1286 within the memory element. If the access type is cached, and the
1287 data is not present in cache, an implementation specific size and
1288 alignment block of memory is read and loaded into the cache to
1289 satisfy a load reference. At a minimum, the block is the entire
1290 memory element. */
1291 void
1292 load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
1293 SIM_DESC sd;
1294 address_word cia;
1295 uword64* memvalp;
1296 uword64* memval1p;
1297 int CCA;
1298 int AccessLength;
1299 address_word pAddr;
1300 address_word vAddr;
1301 int IorD;
1302 {
1303 uword64 value = 0;
1304 uword64 value1 = 0;
1305
1306 #ifdef DEBUG
1307 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
1308 #endif /* DEBUG */
1309
1310 #if defined(WARN_MEM)
1311 if (CCA != uncached)
1312 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1313 #endif /* WARN_MEM */
1314
1315 /* If instruction fetch then we need to check that the two lo-order
1316 bits are zero, otherwise raise a InstructionFetch exception: */
1317 if ((IorD == isINSTRUCTION)
1318 && ((pAddr & 0x3) != 0)
1319 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
1320 SignalExceptionInstructionFetch ();
1321
1322 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1323 {
1324 /* In reality this should be a Bus Error */
1325 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1326 AccessLength,
1327 (LOADDRMASK + 1) << 2,
1328 pr_addr (pAddr));
1329 }
1330
1331 #if defined(TRACE)
1332 dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
1333 #endif /* TRACE */
1334
1335 /* Read the specified number of bytes from memory. Adjust for
1336 host/target byte ordering/ Align the least significant byte
1337 read. */
1338
1339 switch (AccessLength)
1340 {
1341 case AccessLength_QUADWORD :
1342 {
1343 unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
1344 sim_core_read_map, pAddr);
1345 value1 = VH8_16 (val);
1346 value = VL8_16 (val);
1347 break;
1348 }
1349 case AccessLength_DOUBLEWORD :
1350 value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
1351 sim_core_read_map, pAddr);
1352 break;
1353 case AccessLength_SEPTIBYTE :
1354 value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
1355 sim_core_read_map, pAddr);
1356 case AccessLength_SEXTIBYTE :
1357 value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
1358 sim_core_read_map, pAddr);
1359 case AccessLength_QUINTIBYTE :
1360 value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
1361 sim_core_read_map, pAddr);
1362 case AccessLength_WORD :
1363 value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
1364 sim_core_read_map, pAddr);
1365 break;
1366 case AccessLength_TRIPLEBYTE :
1367 value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
1368 sim_core_read_map, pAddr);
1369 case AccessLength_HALFWORD :
1370 value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
1371 sim_core_read_map, pAddr);
1372 break;
1373 case AccessLength_BYTE :
1374 value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
1375 sim_core_read_map, pAddr);
1376 break;
1377 default:
1378 abort ();
1379 }
1380
1381 #ifdef DEBUG
1382 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1383 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
1384 #endif /* DEBUG */
1385
1386 /* See also store_memory. */
1387 if (AccessLength <= AccessLength_DOUBLEWORD)
1388 {
1389 if (BigEndianMem)
1390 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1391 shifted to the most significant byte position. */
1392 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1393 else
1394 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1395 is already in the correct postition. */
1396 value <<= ((pAddr & LOADDRMASK) * 8);
1397 }
1398
1399 #ifdef DEBUG
1400 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1401 pr_uword64(value1),pr_uword64(value));
1402 #endif /* DEBUG */
1403
1404 *memvalp = value;
1405 if (memval1p) *memval1p = value1;
1406 }
1407
1408
1409 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1410 (revision 3.1) */
1411 /* Store a value to memory. The specified data is stored into the
1412 physical location pAddr using the memory hierarchy (data caches and
1413 main memory) as specified by the Cache Coherence Algorithm
1414 (CCA). The MemElem contains the data for an aligned, fixed-width
1415 memory element (word for 32-bit processors, doubleword for 64-bit
1416 processors), though only the bytes that will actually be stored to
1417 memory need to be valid. The low-order two (or three) bits of pAddr
1418 and the AccessLength field indicates which of the bytes within the
1419 MemElem data should actually be stored; only these bytes in memory
1420 will be changed. */
1421
1422 void
1423 store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
1424 SIM_DESC sd;
1425 address_word cia;
1426 int CCA;
1427 int AccessLength;
1428 uword64 MemElem;
1429 uword64 MemElem1; /* High order 64 bits */
1430 address_word pAddr;
1431 address_word vAddr;
1432 {
1433 #ifdef DEBUG
1434 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
1435 #endif /* DEBUG */
1436
1437 #if defined(WARN_MEM)
1438 if (CCA != uncached)
1439 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1440 #endif /* WARN_MEM */
1441
1442 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1443 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1444
1445 #if defined(TRACE)
1446 dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
1447 #endif /* TRACE */
1448
1449 #ifdef DEBUG
1450 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
1451 #endif /* DEBUG */
1452
1453 /* See also load_memory */
1454 if (AccessLength <= AccessLength_DOUBLEWORD)
1455 {
1456 if (BigEndianMem)
1457 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1458 shifted to the most significant byte position. */
1459 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1460 else
1461 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1462 is already in the correct postition. */
1463 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1464 }
1465
1466 #ifdef DEBUG
1467 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
1468 #endif /* DEBUG */
1469
1470 switch (AccessLength)
1471 {
1472 case AccessLength_QUADWORD :
1473 {
1474 unsigned_16 val = U16_8 (MemElem1, MemElem);
1475 sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
1476 sim_core_write_map, pAddr, val);
1477 break;
1478 }
1479 case AccessLength_DOUBLEWORD :
1480 sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
1481 sim_core_write_map, pAddr, MemElem);
1482 break;
1483 case AccessLength_SEPTIBYTE :
1484 sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
1485 sim_core_write_map, pAddr, MemElem);
1486 break;
1487 case AccessLength_SEXTIBYTE :
1488 sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
1489 sim_core_write_map, pAddr, MemElem);
1490 break;
1491 case AccessLength_QUINTIBYTE :
1492 sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
1493 sim_core_write_map, pAddr, MemElem);
1494 break;
1495 case AccessLength_WORD :
1496 sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
1497 sim_core_write_map, pAddr, MemElem);
1498 break;
1499 case AccessLength_TRIPLEBYTE :
1500 sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
1501 sim_core_write_map, pAddr, MemElem);
1502 break;
1503 case AccessLength_HALFWORD :
1504 sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
1505 sim_core_write_map, pAddr, MemElem);
1506 break;
1507 case AccessLength_BYTE :
1508 sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
1509 sim_core_write_map, pAddr, MemElem);
1510 break;
1511 default:
1512 abort ();
1513 }
1514
1515 return;
1516 }
1517
1518
1519 unsigned32
1520 ifetch32 (SIM_DESC sd,
1521 address_word cia,
1522 address_word vaddr)
1523 {
1524 /* Copy the action of the LW instruction */
1525 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1526 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1527 unsigned64 value;
1528 address_word paddr;
1529 unsigned32 instruction;
1530 unsigned byte;
1531 int cca;
1532 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1533 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1534 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1535 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1536 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1537 return instruction;
1538 }
1539
1540
1541 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1542 /* Order loads and stores to synchronise shared memory. Perform the
1543 action necessary to make the effects of groups of synchronizable
1544 loads and stores indicated by stype occur in the same order for all
1545 processors. */
1546 void
1547 sync_operation(sd,cia,stype)
1548 SIM_DESC sd;
1549 address_word cia;
1550 int stype;
1551 {
1552 #ifdef DEBUG
1553 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
1554 #endif /* DEBUG */
1555 return;
1556 }
1557
1558 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1559 /* Signal an exception condition. This will result in an exception
1560 that aborts the instruction. The instruction operation pseudocode
1561 will never see a return from this function call. */
1562
1563 void
1564 signal_exception (SIM_DESC sd,
1565 address_word cia,
1566 int exception,...)
1567 {
1568 int vector;
1569
1570 #ifdef DEBUG
1571 sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC));
1572 #endif /* DEBUG */
1573
1574 /* Ensure that any active atomic read/modify/write operation will fail: */
1575 LLBIT = 0;
1576
1577 switch (exception) {
1578 /* TODO: For testing purposes I have been ignoring TRAPs. In
1579 reality we should either simulate them, or allow the user to
1580 ignore them at run-time.
1581 Same for SYSCALL */
1582 case Trap :
1583 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(IPC));
1584 break;
1585
1586 case SystemCall :
1587 {
1588 va_list ap;
1589 unsigned int instruction;
1590 unsigned int code;
1591
1592 va_start(ap,exception);
1593 instruction = va_arg(ap,unsigned int);
1594 va_end(ap);
1595
1596 code = (instruction >> 6) & 0xFFFFF;
1597
1598 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1599 code, pr_addr(IPC));
1600 }
1601 break;
1602
1603 case DebugBreakPoint :
1604 if (! (Debug & Debug_DM))
1605 {
1606 if (INDELAYSLOT())
1607 {
1608 CANCELDELAYSLOT();
1609
1610 Debug |= Debug_DBD; /* signaled from within in delay slot */
1611 DEPC = IPC - 4; /* reference the branch instruction */
1612 }
1613 else
1614 {
1615 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1616 DEPC = IPC;
1617 }
1618
1619 Debug |= Debug_DM; /* in debugging mode */
1620 Debug |= Debug_DBp; /* raising a DBp exception */
1621 PC = 0xBFC00200;
1622 sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
1623 }
1624 break;
1625
1626 case ReservedInstruction :
1627 {
1628 va_list ap;
1629 unsigned int instruction;
1630 va_start(ap,exception);
1631 instruction = va_arg(ap,unsigned int);
1632 va_end(ap);
1633 /* Provide simple monitor support using ReservedInstruction
1634 exceptions. The following code simulates the fixed vector
1635 entry points into the IDT monitor by causing a simulator
1636 trap, performing the monitor operation, and returning to
1637 the address held in the $ra register (standard PCS return
1638 address). This means we only need to pre-load the vector
1639 space with suitable instruction values. For systems were
1640 actual trap instructions are used, we would not need to
1641 perform this magic. */
1642 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1643 {
1644 sim_monitor(sd, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1645 /* NOTE: This assumes that a branch-and-link style
1646 instruction was used to enter the vector (which is the
1647 case with the current IDT monitor). */
1648 sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA);
1649 }
1650 /* Look for the mips16 entry and exit instructions, and
1651 simulate a handler for them. */
1652 else if ((IPC & 1) != 0
1653 && (instruction & 0xf81f) == 0xe809
1654 && (instruction & 0x0c0) != 0x0c0)
1655 {
1656 mips16_entry (instruction);
1657 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1658 }
1659 /* else fall through to normal exception processing */
1660 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at IPC = 0x%s\n",instruction,pr_addr(IPC));
1661 }
1662
1663 case BreakPoint:
1664 #ifdef DEBUG
1665 sim_io_printf(sd,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC));
1666 #endif /* DEBUG */
1667 /* Keep a copy of the current A0 in-case this is the program exit
1668 breakpoint: */
1669 {
1670 va_list ap;
1671 unsigned int instruction;
1672 va_start(ap,exception);
1673 instruction = va_arg(ap,unsigned int);
1674 va_end(ap);
1675 /* Check for our special terminating BREAK: */
1676 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
1677 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia,
1678 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1679 }
1680 }
1681 if (STATE & simDELAYSLOT)
1682 PC = IPC - 4; /* reference the branch instruction */
1683 else
1684 PC = IPC;
1685 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1686 sim_stopped, SIGTRAP);
1687
1688 default:
1689 /* Store exception code into current exception id variable (used
1690 by exit code): */
1691
1692 /* TODO: If not simulating exceptions then stop the simulator
1693 execution. At the moment we always stop the simulation. */
1694
1695 /* See figure 5-17 for an outline of the code below */
1696 if (! (SR & status_EXL))
1697 {
1698 CAUSE = (exception << 2);
1699 if (STATE & simDELAYSLOT)
1700 {
1701 STATE &= ~simDELAYSLOT;
1702 CAUSE |= cause_BD;
1703 EPC = (IPC - 4); /* reference the branch instruction */
1704 }
1705 else
1706 EPC = IPC;
1707 /* FIXME: TLB et.al. */
1708 vector = 0x180;
1709 }
1710 else
1711 {
1712 CAUSE = (exception << 2);
1713 vector = 0x180;
1714 }
1715 SR |= status_EXL;
1716 /* Store exception code into current exception id variable (used
1717 by exit code): */
1718 if (SR & status_BEV)
1719 PC = (signed)0xBFC00200 + 0x180;
1720 else
1721 PC = (signed)0x80000000 + 0x180;
1722
1723 switch ((CAUSE >> 2) & 0x1F)
1724 {
1725 case Interrupt:
1726 /* Interrupts arrive during event processing, no need to
1727 restart */
1728 return;
1729
1730 case TLBModification:
1731 case TLBLoad:
1732 case TLBStore:
1733 case AddressLoad:
1734 case AddressStore:
1735 case InstructionFetch:
1736 case DataReference:
1737 /* The following is so that the simulator will continue from the
1738 exception address on breakpoint operations. */
1739 PC = EPC;
1740 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1741 sim_stopped, SIGBUS);
1742
1743 case ReservedInstruction:
1744 case CoProcessorUnusable:
1745 PC = EPC;
1746 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1747 sim_stopped, SIGILL);
1748
1749 case IntegerOverflow:
1750 case FPE:
1751 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1752 sim_stopped, SIGFPE);
1753
1754 case Trap:
1755 case Watch:
1756 case SystemCall:
1757 PC = EPC;
1758 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1759 sim_stopped, SIGTRAP);
1760
1761 case BreakPoint:
1762 PC = EPC;
1763 sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
1764 "FATAL: Should not encounter a breakpoint\n");
1765
1766 default : /* Unknown internal exception */
1767 PC = EPC;
1768 sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA,
1769 sim_stopped, SIGQUIT);
1770
1771 }
1772
1773 case SimulatorFault:
1774 {
1775 va_list ap;
1776 char *msg;
1777 va_start(ap,exception);
1778 msg = va_arg(ap,char *);
1779 va_end(ap);
1780 sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA,
1781 "FATAL: Simulator error \"%s\"\n",msg);
1782 }
1783 }
1784
1785 return;
1786 }
1787
1788 #if defined(WARN_RESULT)
1789 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1790 /* This function indicates that the result of the operation is
1791 undefined. However, this should not affect the instruction
1792 stream. All that is meant to happen is that the destination
1793 register is set to an undefined result. To keep the simulator
1794 simple, we just don't bother updating the destination register, so
1795 the overall result will be undefined. If desired we can stop the
1796 simulator by raising a pseudo-exception. */
1797 static void
1798 UndefinedResult()
1799 {
1800 sim_io_eprintf(sd,"UndefinedResult: IPC = 0x%s\n",pr_addr(IPC));
1801 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1802 state |= simSTOP;
1803 #endif
1804 return;
1805 }
1806 #endif /* WARN_RESULT */
1807
1808 void
1809 cache_op(sd,cia,op,pAddr,vAddr,instruction)
1810 SIM_DESC sd;
1811 address_word cia;
1812 int op;
1813 address_word pAddr;
1814 address_word vAddr;
1815 unsigned int instruction;
1816 {
1817 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1818 static int icache_warning = 1;
1819 static int dcache_warning = 1;
1820 #else
1821 static int icache_warning = 0;
1822 static int dcache_warning = 0;
1823 #endif
1824
1825 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1826 enable bit in the Status Register is clear - a coprocessor
1827 unusable exception is taken. */
1828 #if 0
1829 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC));
1830 #endif
1831
1832 switch (op & 0x3) {
1833 case 0: /* instruction cache */
1834 switch (op >> 2) {
1835 case 0: /* Index Invalidate */
1836 case 1: /* Index Load Tag */
1837 case 2: /* Index Store Tag */
1838 case 4: /* Hit Invalidate */
1839 case 5: /* Fill */
1840 case 6: /* Hit Writeback */
1841 if (!icache_warning)
1842 {
1843 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
1844 icache_warning = 1;
1845 }
1846 break;
1847
1848 default:
1849 SignalException(ReservedInstruction,instruction);
1850 break;
1851 }
1852 break;
1853
1854 case 1: /* data cache */
1855 switch (op >> 2) {
1856 case 0: /* Index Writeback Invalidate */
1857 case 1: /* Index Load Tag */
1858 case 2: /* Index Store Tag */
1859 case 3: /* Create Dirty */
1860 case 4: /* Hit Invalidate */
1861 case 5: /* Hit Writeback Invalidate */
1862 case 6: /* Hit Writeback */
1863 if (!dcache_warning)
1864 {
1865 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
1866 dcache_warning = 1;
1867 }
1868 break;
1869
1870 default:
1871 SignalException(ReservedInstruction,instruction);
1872 break;
1873 }
1874 break;
1875
1876 default: /* unrecognised cache ID */
1877 SignalException(ReservedInstruction,instruction);
1878 break;
1879 }
1880
1881 return;
1882 }
1883
1884 /*-- FPU support routines ---------------------------------------------------*/
1885
1886 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
1887
1888 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1889 formats conform to ANSI/IEEE Std 754-1985. */
1890 /* SINGLE precision floating:
1891 * seeeeeeeefffffffffffffffffffffff
1892 * s = 1bit = sign
1893 * e = 8bits = exponent
1894 * f = 23bits = fraction
1895 */
1896 /* SINGLE precision fixed:
1897 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1898 * s = 1bit = sign
1899 * i = 31bits = integer
1900 */
1901 /* DOUBLE precision floating:
1902 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1903 * s = 1bit = sign
1904 * e = 11bits = exponent
1905 * f = 52bits = fraction
1906 */
1907 /* DOUBLE precision fixed:
1908 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1909 * s = 1bit = sign
1910 * i = 63bits = integer
1911 */
1912
1913 /* Extract sign-bit: */
1914 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1915 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1916 /* Extract biased exponent: */
1917 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1918 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1919 /* Extract unbiased Exponent: */
1920 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1921 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1922 /* Extract complete fraction field: */
1923 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1924 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1925 /* Extract numbered fraction bit: */
1926 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1927 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1928
1929 /* Explicit QNaN values used when value required: */
1930 #define FPQNaN_SINGLE (0x7FBFFFFF)
1931 #define FPQNaN_WORD (0x7FFFFFFF)
1932 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1933 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1934
1935 /* Explicit Infinity values used when required: */
1936 #define FPINF_SINGLE (0x7F800000)
1937 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1938
1939 #if 1 /* def DEBUG */
1940 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1941 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1942 #endif /* DEBUG */
1943
1944 uword64
1945 value_fpr(sd,cia,fpr,fmt)
1946 SIM_DESC sd;
1947 address_word cia;
1948 int fpr;
1949 FP_formats fmt;
1950 {
1951 uword64 value = 0;
1952 int err = 0;
1953
1954 /* Treat unused register values, as fixed-point 64bit values: */
1955 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
1956 #if 1
1957 /* If request to read data as "uninterpreted", then use the current
1958 encoding: */
1959 fmt = FPR_STATE[fpr];
1960 #else
1961 fmt = fmt_long;
1962 #endif
1963
1964 /* For values not yet accessed, set to the desired format: */
1965 if (FPR_STATE[fpr] == fmt_uninterpreted) {
1966 FPR_STATE[fpr] = fmt;
1967 #ifdef DEBUG
1968 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
1969 #endif /* DEBUG */
1970 }
1971 if (fmt != FPR_STATE[fpr]) {
1972 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(IPC));
1973 FPR_STATE[fpr] = fmt_unknown;
1974 }
1975
1976 if (FPR_STATE[fpr] == fmt_unknown) {
1977 /* Set QNaN value: */
1978 switch (fmt) {
1979 case fmt_single:
1980 value = FPQNaN_SINGLE;
1981 break;
1982
1983 case fmt_double:
1984 value = FPQNaN_DOUBLE;
1985 break;
1986
1987 case fmt_word:
1988 value = FPQNaN_WORD;
1989 break;
1990
1991 case fmt_long:
1992 value = FPQNaN_LONG;
1993 break;
1994
1995 default:
1996 err = -1;
1997 break;
1998 }
1999 } else if (SizeFGR() == 64) {
2000 switch (fmt) {
2001 case fmt_single:
2002 case fmt_word:
2003 value = (FGR[fpr] & 0xFFFFFFFF);
2004 break;
2005
2006 case fmt_uninterpreted:
2007 case fmt_double:
2008 case fmt_long:
2009 value = FGR[fpr];
2010 break;
2011
2012 default :
2013 err = -1;
2014 break;
2015 }
2016 } else {
2017 switch (fmt) {
2018 case fmt_single:
2019 case fmt_word:
2020 value = (FGR[fpr] & 0xFFFFFFFF);
2021 break;
2022
2023 case fmt_uninterpreted:
2024 case fmt_double:
2025 case fmt_long:
2026 if ((fpr & 1) == 0) { /* even registers only */
2027 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2028 } else {
2029 SignalException(ReservedInstruction,0);
2030 }
2031 break;
2032
2033 default :
2034 err = -1;
2035 break;
2036 }
2037 }
2038
2039 if (err)
2040 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2041
2042 #ifdef DEBUG
2043 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR());
2044 #endif /* DEBUG */
2045
2046 return(value);
2047 }
2048
2049 void
2050 store_fpr(sd,cia,fpr,fmt,value)
2051 SIM_DESC sd;
2052 address_word cia;
2053 int fpr;
2054 FP_formats fmt;
2055 uword64 value;
2056 {
2057 int err = 0;
2058
2059 #ifdef DEBUG
2060 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(IPC),SizeFGR());
2061 #endif /* DEBUG */
2062
2063 if (SizeFGR() == 64) {
2064 switch (fmt) {
2065 case fmt_single :
2066 case fmt_word :
2067 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2068 FPR_STATE[fpr] = fmt;
2069 break;
2070
2071 case fmt_uninterpreted:
2072 case fmt_double :
2073 case fmt_long :
2074 FGR[fpr] = value;
2075 FPR_STATE[fpr] = fmt;
2076 break;
2077
2078 default :
2079 FPR_STATE[fpr] = fmt_unknown;
2080 err = -1;
2081 break;
2082 }
2083 } else {
2084 switch (fmt) {
2085 case fmt_single :
2086 case fmt_word :
2087 FGR[fpr] = (value & 0xFFFFFFFF);
2088 FPR_STATE[fpr] = fmt;
2089 break;
2090
2091 case fmt_uninterpreted:
2092 case fmt_double :
2093 case fmt_long :
2094 if ((fpr & 1) == 0) { /* even register number only */
2095 FGR[fpr+1] = (value >> 32);
2096 FGR[fpr] = (value & 0xFFFFFFFF);
2097 FPR_STATE[fpr + 1] = fmt;
2098 FPR_STATE[fpr] = fmt;
2099 } else {
2100 FPR_STATE[fpr] = fmt_unknown;
2101 FPR_STATE[fpr + 1] = fmt_unknown;
2102 SignalException(ReservedInstruction,0);
2103 }
2104 break;
2105
2106 default :
2107 FPR_STATE[fpr] = fmt_unknown;
2108 err = -1;
2109 break;
2110 }
2111 }
2112 #if defined(WARN_RESULT)
2113 else
2114 UndefinedResult();
2115 #endif /* WARN_RESULT */
2116
2117 if (err)
2118 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2119
2120 #ifdef DEBUG
2121 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2122 #endif /* DEBUG */
2123
2124 return;
2125 }
2126
2127 int
2128 NaN(op,fmt)
2129 uword64 op;
2130 FP_formats fmt;
2131 {
2132 int boolean = 0;
2133
2134 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
2135 know that the exponent field is biased... we we cheat and avoid
2136 removing the bias value. */
2137 switch (fmt) {
2138 case fmt_single:
2139 boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0));
2140 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2141 dealing with a SNaN or QNaN */
2142 break;
2143 case fmt_double:
2144 boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0));
2145 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2146 dealing with a SNaN or QNaN */
2147 break;
2148 case fmt_word:
2149 boolean = (op == FPQNaN_WORD);
2150 break;
2151 case fmt_long:
2152 boolean = (op == FPQNaN_LONG);
2153 break;
2154 default:
2155 fprintf (stderr, "Bad switch\n");
2156 abort ();
2157 }
2158
2159 #ifdef DEBUG
2160 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2161 #endif /* DEBUG */
2162
2163 return(boolean);
2164 }
2165
2166 int
2167 Infinity(op,fmt)
2168 uword64 op;
2169 FP_formats fmt;
2170 {
2171 int boolean = 0;
2172
2173 #ifdef DEBUG
2174 printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt),pr_addr(op),pr_addr(IPC));
2175 #endif /* DEBUG */
2176
2177 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
2178 know that the exponent field is biased... we we cheat and avoid
2179 removing the bias value. */
2180 switch (fmt) {
2181 case fmt_single:
2182 boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0));
2183 break;
2184 case fmt_double:
2185 boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0));
2186 break;
2187 default:
2188 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2189 break;
2190 }
2191
2192 #ifdef DEBUG
2193 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2194 #endif /* DEBUG */
2195
2196 return(boolean);
2197 }
2198
2199 int
2200 Less(op1,op2,fmt)
2201 uword64 op1;
2202 uword64 op2;
2203 FP_formats fmt;
2204 {
2205 int boolean = 0;
2206
2207 /* Argument checking already performed by the FPCOMPARE code */
2208
2209 #ifdef DEBUG
2210 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2211 #endif /* DEBUG */
2212
2213 /* The format type should already have been checked: */
2214 switch (fmt) {
2215 case fmt_single:
2216 {
2217 unsigned int wop1 = (unsigned int)op1;
2218 unsigned int wop2 = (unsigned int)op2;
2219 boolean = (*(float *)&wop1 < *(float *)&wop2);
2220 }
2221 break;
2222 case fmt_double:
2223 boolean = (*(double *)&op1 < *(double *)&op2);
2224 break;
2225 default:
2226 fprintf (stderr, "Bad switch\n");
2227 abort ();
2228 }
2229
2230 #ifdef DEBUG
2231 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2232 #endif /* DEBUG */
2233
2234 return(boolean);
2235 }
2236
2237 int
2238 Equal(op1,op2,fmt)
2239 uword64 op1;
2240 uword64 op2;
2241 FP_formats fmt;
2242 {
2243 int boolean = 0;
2244
2245 /* Argument checking already performed by the FPCOMPARE code */
2246
2247 #ifdef DEBUG
2248 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2249 #endif /* DEBUG */
2250
2251 /* The format type should already have been checked: */
2252 switch (fmt) {
2253 case fmt_single:
2254 boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF));
2255 break;
2256 case fmt_double:
2257 boolean = (op1 == op2);
2258 break;
2259 default:
2260 fprintf (stderr, "Bad switch\n");
2261 abort ();
2262 }
2263
2264 #ifdef DEBUG
2265 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2266 #endif /* DEBUG */
2267
2268 return(boolean);
2269 }
2270
2271 uword64
2272 AbsoluteValue(op,fmt)
2273 uword64 op;
2274 FP_formats fmt;
2275 {
2276 uword64 result = 0;
2277
2278 #ifdef DEBUG
2279 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2280 #endif /* DEBUG */
2281
2282 /* The format type should already have been checked: */
2283 switch (fmt) {
2284 case fmt_single:
2285 {
2286 unsigned int wop = (unsigned int)op;
2287 float tmp = ((float)fabs((double)*(float *)&wop));
2288 result = (uword64)*(unsigned int *)&tmp;
2289 }
2290 break;
2291 case fmt_double:
2292 {
2293 double tmp = (fabs(*(double *)&op));
2294 result = *(uword64 *)&tmp;
2295 }
2296 default:
2297 fprintf (stderr, "Bad switch\n");
2298 abort ();
2299 }
2300
2301 return(result);
2302 }
2303
2304 uword64
2305 Negate(op,fmt)
2306 uword64 op;
2307 FP_formats fmt;
2308 {
2309 uword64 result = 0;
2310
2311 #ifdef DEBUG
2312 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2313 #endif /* DEBUG */
2314
2315 /* The format type should already have been checked: */
2316 switch (fmt) {
2317 case fmt_single:
2318 {
2319 unsigned int wop = (unsigned int)op;
2320 float tmp = ((float)0.0 - *(float *)&wop);
2321 result = (uword64)*(unsigned int *)&tmp;
2322 }
2323 break;
2324 case fmt_double:
2325 {
2326 double tmp = ((double)0.0 - *(double *)&op);
2327 result = *(uword64 *)&tmp;
2328 }
2329 break;
2330 default:
2331 fprintf (stderr, "Bad switch\n");
2332 abort ();
2333 }
2334
2335 return(result);
2336 }
2337
2338 uword64
2339 Add(op1,op2,fmt)
2340 uword64 op1;
2341 uword64 op2;
2342 FP_formats fmt;
2343 {
2344 uword64 result = 0;
2345
2346 #ifdef DEBUG
2347 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2348 #endif /* DEBUG */
2349
2350 /* The registers must specify FPRs valid for operands of type
2351 "fmt". If they are not valid, the result is undefined. */
2352
2353 /* The format type should already have been checked: */
2354 switch (fmt) {
2355 case fmt_single:
2356 {
2357 unsigned int wop1 = (unsigned int)op1;
2358 unsigned int wop2 = (unsigned int)op2;
2359 float tmp = (*(float *)&wop1 + *(float *)&wop2);
2360 result = (uword64)*(unsigned int *)&tmp;
2361 }
2362 break;
2363 case fmt_double:
2364 {
2365 double tmp = (*(double *)&op1 + *(double *)&op2);
2366 result = *(uword64 *)&tmp;
2367 }
2368 break;
2369 default:
2370 fprintf (stderr, "Bad switch\n");
2371 abort ();
2372 }
2373
2374 #ifdef DEBUG
2375 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2376 #endif /* DEBUG */
2377
2378 return(result);
2379 }
2380
2381 uword64
2382 Sub(op1,op2,fmt)
2383 uword64 op1;
2384 uword64 op2;
2385 FP_formats fmt;
2386 {
2387 uword64 result = 0;
2388
2389 #ifdef DEBUG
2390 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2391 #endif /* DEBUG */
2392
2393 /* The registers must specify FPRs valid for operands of type
2394 "fmt". If they are not valid, the result is undefined. */
2395
2396 /* The format type should already have been checked: */
2397 switch (fmt) {
2398 case fmt_single:
2399 {
2400 unsigned int wop1 = (unsigned int)op1;
2401 unsigned int wop2 = (unsigned int)op2;
2402 float tmp = (*(float *)&wop1 - *(float *)&wop2);
2403 result = (uword64)*(unsigned int *)&tmp;
2404 }
2405 break;
2406 case fmt_double:
2407 {
2408 double tmp = (*(double *)&op1 - *(double *)&op2);
2409 result = *(uword64 *)&tmp;
2410 }
2411 break;
2412 default:
2413 fprintf (stderr, "Bad switch\n");
2414 abort ();
2415 }
2416
2417 #ifdef DEBUG
2418 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2419 #endif /* DEBUG */
2420
2421 return(result);
2422 }
2423
2424 uword64
2425 Multiply(op1,op2,fmt)
2426 uword64 op1;
2427 uword64 op2;
2428 FP_formats fmt;
2429 {
2430 uword64 result = 0;
2431
2432 #ifdef DEBUG
2433 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2434 #endif /* DEBUG */
2435
2436 /* The registers must specify FPRs valid for operands of type
2437 "fmt". If they are not valid, the result is undefined. */
2438
2439 /* The format type should already have been checked: */
2440 switch (fmt) {
2441 case fmt_single:
2442 {
2443 unsigned int wop1 = (unsigned int)op1;
2444 unsigned int wop2 = (unsigned int)op2;
2445 float tmp = (*(float *)&wop1 * *(float *)&wop2);
2446 result = (uword64)*(unsigned int *)&tmp;
2447 }
2448 break;
2449 case fmt_double:
2450 {
2451 double tmp = (*(double *)&op1 * *(double *)&op2);
2452 result = *(uword64 *)&tmp;
2453 }
2454 break;
2455 default:
2456 fprintf (stderr, "Bad switch\n");
2457 abort ();
2458 }
2459
2460 #ifdef DEBUG
2461 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2462 #endif /* DEBUG */
2463
2464 return(result);
2465 }
2466
2467 uword64
2468 Divide(op1,op2,fmt)
2469 uword64 op1;
2470 uword64 op2;
2471 FP_formats fmt;
2472 {
2473 uword64 result = 0;
2474
2475 #ifdef DEBUG
2476 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2477 #endif /* DEBUG */
2478
2479 /* The registers must specify FPRs valid for operands of type
2480 "fmt". If they are not valid, the result is undefined. */
2481
2482 /* The format type should already have been checked: */
2483 switch (fmt) {
2484 case fmt_single:
2485 {
2486 unsigned int wop1 = (unsigned int)op1;
2487 unsigned int wop2 = (unsigned int)op2;
2488 float tmp = (*(float *)&wop1 / *(float *)&wop2);
2489 result = (uword64)*(unsigned int *)&tmp;
2490 }
2491 break;
2492 case fmt_double:
2493 {
2494 double tmp = (*(double *)&op1 / *(double *)&op2);
2495 result = *(uword64 *)&tmp;
2496 }
2497 break;
2498 default:
2499 fprintf (stderr, "Bad switch\n");
2500 abort ();
2501 }
2502
2503 #ifdef DEBUG
2504 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2505 #endif /* DEBUG */
2506
2507 return(result);
2508 }
2509
2510 uword64 UNUSED
2511 Recip(op,fmt)
2512 uword64 op;
2513 FP_formats fmt;
2514 {
2515 uword64 result = 0;
2516
2517 #ifdef DEBUG
2518 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2519 #endif /* DEBUG */
2520
2521 /* The registers must specify FPRs valid for operands of type
2522 "fmt". If they are not valid, the result is undefined. */
2523
2524 /* The format type should already have been checked: */
2525 switch (fmt) {
2526 case fmt_single:
2527 {
2528 unsigned int wop = (unsigned int)op;
2529 float tmp = ((float)1.0 / *(float *)&wop);
2530 result = (uword64)*(unsigned int *)&tmp;
2531 }
2532 break;
2533 case fmt_double:
2534 {
2535 double tmp = ((double)1.0 / *(double *)&op);
2536 result = *(uword64 *)&tmp;
2537 }
2538 break;
2539 default:
2540 fprintf (stderr, "Bad switch\n");
2541 abort ();
2542 }
2543
2544 #ifdef DEBUG
2545 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2546 #endif /* DEBUG */
2547
2548 return(result);
2549 }
2550
2551 uword64
2552 SquareRoot(op,fmt)
2553 uword64 op;
2554 FP_formats fmt;
2555 {
2556 uword64 result = 0;
2557
2558 #ifdef DEBUG
2559 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2560 #endif /* DEBUG */
2561
2562 /* The registers must specify FPRs valid for operands of type
2563 "fmt". If they are not valid, the result is undefined. */
2564
2565 /* The format type should already have been checked: */
2566 switch (fmt) {
2567 case fmt_single:
2568 {
2569 unsigned int wop = (unsigned int)op;
2570 #ifdef HAVE_SQRT
2571 float tmp = ((float)sqrt((double)*(float *)&wop));
2572 result = (uword64)*(unsigned int *)&tmp;
2573 #else
2574 /* TODO: Provide square-root */
2575 result = (uword64)0;
2576 #endif
2577 }
2578 break;
2579 case fmt_double:
2580 {
2581 #ifdef HAVE_SQRT
2582 double tmp = (sqrt(*(double *)&op));
2583 result = *(uword64 *)&tmp;
2584 #else
2585 /* TODO: Provide square-root */
2586 result = (uword64)0;
2587 #endif
2588 }
2589 break;
2590 default:
2591 fprintf (stderr, "Bad switch\n");
2592 abort ();
2593 }
2594
2595 #ifdef DEBUG
2596 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2597 #endif /* DEBUG */
2598
2599 return(result);
2600 }
2601
2602 uword64
2603 convert(sd,cia,rm,op,from,to)
2604 SIM_DESC sd;
2605 address_word cia;
2606 int rm;
2607 uword64 op;
2608 FP_formats from;
2609 FP_formats to;
2610 {
2611 uword64 result = 0;
2612
2613 #ifdef DEBUG
2614 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
2615 #endif /* DEBUG */
2616
2617 /* The value "op" is converted to the destination format, rounding
2618 using mode "rm". When the destination is a fixed-point format,
2619 then a source value of Infinity, NaN or one which would round to
2620 an integer outside the fixed point range then an IEEE Invalid
2621 Operation condition is raised. */
2622 switch (to) {
2623 case fmt_single:
2624 {
2625 float tmp;
2626 switch (from) {
2627 case fmt_double:
2628 tmp = (float)(*(double *)&op);
2629 break;
2630
2631 case fmt_word:
2632 tmp = (float)((int)(op & 0xFFFFFFFF));
2633 break;
2634
2635 case fmt_long:
2636 tmp = (float)((word64)op);
2637 break;
2638 default:
2639 fprintf (stderr, "Bad switch\n");
2640 abort ();
2641 }
2642
2643 #if 0
2644 /* FIXME: This code is incorrect. The rounding mode does not
2645 round to integral values; it rounds to the nearest
2646 representable value in the format. */
2647
2648 switch (rm) {
2649 case FP_RM_NEAREST:
2650 /* Round result to nearest representable value. When two
2651 representable values are equally near, round to the value
2652 that has a least significant bit of zero (i.e. is even). */
2653 #ifdef HAVE_ANINT
2654 tmp = (float)anint((double)tmp);
2655 #else
2656 /* TODO: Provide round-to-nearest */
2657 #endif
2658 break;
2659
2660 case FP_RM_TOZERO:
2661 /* Round result to the value closest to, and not greater in
2662 magnitude than, the result. */
2663 #ifdef HAVE_AINT
2664 tmp = (float)aint((double)tmp);
2665 #else
2666 /* TODO: Provide round-to-zero */
2667 #endif
2668 break;
2669
2670 case FP_RM_TOPINF:
2671 /* Round result to the value closest to, and not less than,
2672 the result. */
2673 tmp = (float)ceil((double)tmp);
2674 break;
2675
2676 case FP_RM_TOMINF:
2677 /* Round result to the value closest to, and not greater than,
2678 the result. */
2679 tmp = (float)floor((double)tmp);
2680 break;
2681 }
2682 #endif /* 0 */
2683
2684 result = (uword64)*(unsigned int *)&tmp;
2685 }
2686 break;
2687
2688 case fmt_double:
2689 {
2690 double tmp;
2691 word64 xxx;
2692
2693 switch (from) {
2694 case fmt_single:
2695 {
2696 unsigned int wop = (unsigned int)op;
2697 tmp = (double)(*(float *)&wop);
2698 }
2699 break;
2700
2701 case fmt_word:
2702 xxx = SIGNEXTEND((op & 0xFFFFFFFF),32);
2703 tmp = (double)xxx;
2704 break;
2705
2706 case fmt_long:
2707 tmp = (double)((word64)op);
2708 break;
2709
2710 default:
2711 fprintf (stderr, "Bad switch\n");
2712 abort ();
2713 }
2714
2715 #if 0
2716 /* FIXME: This code is incorrect. The rounding mode does not
2717 round to integral values; it rounds to the nearest
2718 representable value in the format. */
2719
2720 switch (rm) {
2721 case FP_RM_NEAREST:
2722 #ifdef HAVE_ANINT
2723 tmp = anint(*(double *)&tmp);
2724 #else
2725 /* TODO: Provide round-to-nearest */
2726 #endif
2727 break;
2728
2729 case FP_RM_TOZERO:
2730 #ifdef HAVE_AINT
2731 tmp = aint(*(double *)&tmp);
2732 #else
2733 /* TODO: Provide round-to-zero */
2734 #endif
2735 break;
2736
2737 case FP_RM_TOPINF:
2738 tmp = ceil(*(double *)&tmp);
2739 break;
2740
2741 case FP_RM_TOMINF:
2742 tmp = floor(*(double *)&tmp);
2743 break;
2744 }
2745 #endif /* 0 */
2746
2747 result = *(uword64 *)&tmp;
2748 }
2749 break;
2750
2751 case fmt_word:
2752 case fmt_long:
2753 if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) {
2754 printf("DBG: TODO: update FCSR\n");
2755 SignalExceptionFPE ();
2756 } else {
2757 if (to == fmt_word) {
2758 int tmp = 0;
2759 switch (from) {
2760 case fmt_single:
2761 {
2762 unsigned int wop = (unsigned int)op;
2763 tmp = (int)*((float *)&wop);
2764 }
2765 break;
2766 case fmt_double:
2767 tmp = (int)*((double *)&op);
2768 #ifdef DEBUG
2769 printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op),pr_addr(op),tmp);
2770 #endif /* DEBUG */
2771 break;
2772 default:
2773 fprintf (stderr, "Bad switch\n");
2774 abort ();
2775 }
2776 result = (uword64)tmp;
2777 } else { /* fmt_long */
2778 word64 tmp = 0;
2779 switch (from) {
2780 case fmt_single:
2781 {
2782 unsigned int wop = (unsigned int)op;
2783 tmp = (word64)*((float *)&wop);
2784 }
2785 break;
2786 case fmt_double:
2787 tmp = (word64)*((double *)&op);
2788 break;
2789 default:
2790 fprintf (stderr, "Bad switch\n");
2791 abort ();
2792 }
2793 result = (uword64)tmp;
2794 }
2795 }
2796 break;
2797 default:
2798 fprintf (stderr, "Bad switch\n");
2799 abort ();
2800 }
2801
2802 #ifdef DEBUG
2803 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result),DOFMT(to));
2804 #endif /* DEBUG */
2805
2806 return(result);
2807 }
2808 #endif /* HASFPU */
2809
2810 /*-- co-processor support routines ------------------------------------------*/
2811
2812 static int UNUSED
2813 CoProcPresent(coproc_number)
2814 unsigned int coproc_number;
2815 {
2816 /* Return TRUE if simulator provides a model for the given co-processor number */
2817 return(0);
2818 }
2819
2820 void
2821 cop_lw(sd,cia,coproc_num,coproc_reg,memword)
2822 SIM_DESC sd;
2823 address_word cia;
2824 int coproc_num, coproc_reg;
2825 unsigned int memword;
2826 {
2827 switch (coproc_num) {
2828 #if defined(HASFPU)
2829 case 1:
2830 #ifdef DEBUG
2831 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2832 #endif
2833 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
2834 FPR_STATE[coproc_reg] = fmt_uninterpreted;
2835 break;
2836 #endif /* HASFPU */
2837
2838 default:
2839 #if 0 /* this should be controlled by a configuration option */
2840 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(IPC));
2841 #endif
2842 break;
2843 }
2844
2845 return;
2846 }
2847
2848 void
2849 cop_ld(sd,cia,coproc_num,coproc_reg,memword)
2850 SIM_DESC sd;
2851 address_word cia;
2852 int coproc_num, coproc_reg;
2853 uword64 memword;
2854 {
2855 switch (coproc_num) {
2856 #if defined(HASFPU)
2857 case 1:
2858 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
2859 break;
2860 #endif /* HASFPU */
2861
2862 default:
2863 #if 0 /* this message should be controlled by a configuration option */
2864 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(IPC));
2865 #endif
2866 break;
2867 }
2868
2869 return;
2870 }
2871
2872 unsigned int
2873 cop_sw(sd,cia,coproc_num,coproc_reg)
2874 SIM_DESC sd;
2875 address_word cia;
2876 int coproc_num, coproc_reg;
2877 {
2878 unsigned int value = 0;
2879
2880 switch (coproc_num) {
2881 #if defined(HASFPU)
2882 case 1:
2883 #if 1
2884 {
2885 FP_formats hold;
2886 hold = FPR_STATE[coproc_reg];
2887 FPR_STATE[coproc_reg] = fmt_word;
2888 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
2889 FPR_STATE[coproc_reg] = hold;
2890 }
2891 #else
2892 #if 1
2893 value = (unsigned int)ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
2894 #else
2895 #ifdef DEBUG
2896 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE[coproc_reg]));
2897 #endif /* DEBUG */
2898 value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
2899 #endif
2900 #endif
2901 break;
2902 #endif /* HASFPU */
2903
2904 default:
2905 #if 0 /* should be controlled by configuration option */
2906 sim_io_printf(sd,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC));
2907 #endif
2908 break;
2909 }
2910
2911 return(value);
2912 }
2913
2914 uword64
2915 cop_sd(sd,cia,coproc_num,coproc_reg)
2916 SIM_DESC sd;
2917 address_word cia;
2918 int coproc_num, coproc_reg;
2919 {
2920 uword64 value = 0;
2921 switch (coproc_num) {
2922 #if defined(HASFPU)
2923 case 1:
2924 #if 1
2925 value = ValueFPR(coproc_reg,fmt_uninterpreted);
2926 #else
2927 #if 1
2928 value = ValueFPR(coproc_reg,FPR_STATE[coproc_reg]);
2929 #else
2930 #ifdef DEBUG
2931 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE[coproc_reg]));
2932 #endif /* DEBUG */
2933 value = ValueFPR(coproc_reg,fmt_double);
2934 #endif
2935 #endif
2936 break;
2937 #endif /* HASFPU */
2938
2939 default:
2940 #if 0 /* should be controlled by configuration option */
2941 sim_io_printf(sd,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(IPC));
2942 #endif
2943 break;
2944 }
2945
2946 return(value);
2947 }
2948
2949 void
2950 decode_coproc(sd,cia,instruction)
2951 SIM_DESC sd;
2952 address_word cia;
2953 unsigned int instruction;
2954 {
2955 int coprocnum = ((instruction >> 26) & 3);
2956
2957 switch (coprocnum)
2958 {
2959 case 0: /* standard CPU control and cache registers */
2960 {
2961 int code = ((instruction >> 21) & 0x1F);
2962 /* R4000 Users Manual (second edition) lists the following CP0
2963 instructions:
2964 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2965 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2966 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2967 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2968 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2969 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2970 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2971 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2972 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2973 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2974 */
2975 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
2976 {
2977 int rt = ((instruction >> 16) & 0x1F);
2978 int rd = ((instruction >> 11) & 0x1F);
2979
2980 switch (rd) /* NOTEs: Standard CP0 registers */
2981 {
2982 /* 0 = Index R4000 VR4100 VR4300 */
2983 /* 1 = Random R4000 VR4100 VR4300 */
2984 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2985 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2986 /* 4 = Context R4000 VR4100 VR4300 */
2987 /* 5 = PageMask R4000 VR4100 VR4300 */
2988 /* 6 = Wired R4000 VR4100 VR4300 */
2989 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2990 /* 9 = Count R4000 VR4100 VR4300 */
2991 /* 10 = EntryHi R4000 VR4100 VR4300 */
2992 /* 11 = Compare R4000 VR4100 VR4300 */
2993 /* 12 = SR R4000 VR4100 VR4300 */
2994 case 12:
2995 if (code == 0x00)
2996 GPR[rt] = SR;
2997 else
2998 SR = GPR[rt];
2999 break;
3000 /* 13 = Cause R4000 VR4100 VR4300 */
3001 case 13:
3002 if (code == 0x00)
3003 GPR[rt] = CAUSE;
3004 else
3005 CAUSE = GPR[rt];
3006 break;
3007 /* 14 = EPC R4000 VR4100 VR4300 */
3008 /* 15 = PRId R4000 VR4100 VR4300 */
3009 #ifdef SUBTARGET_R3900
3010 /* 16 = Debug */
3011 case 16:
3012 if (code == 0x00)
3013 GPR[rt] = Debug;
3014 else
3015 Debug = GPR[rt];
3016 break;
3017 #else
3018 /* 16 = Config R4000 VR4100 VR4300 */
3019 #endif
3020 #ifdef SUBTARGET_R3900
3021 /* 17 = Debug */
3022 case 17:
3023 if (code == 0x00)
3024 GPR[rt] = DEPC;
3025 else
3026 DEPC = GPR[rt];
3027 break;
3028 #else
3029 /* 17 = LLAddr R4000 VR4100 VR4300 */
3030 #endif
3031 /* 18 = WatchLo R4000 VR4100 VR4300 */
3032 /* 19 = WatchHi R4000 VR4100 VR4300 */
3033 /* 20 = XContext R4000 VR4100 VR4300 */
3034 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3035 /* 27 = CacheErr R4000 VR4100 */
3036 /* 28 = TagLo R4000 VR4100 VR4300 */
3037 /* 29 = TagHi R4000 VR4100 VR4300 */
3038 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3039 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3040 /* CPR[0,rd] = GPR[rt]; */
3041 default:
3042 if (code == 0x00)
3043 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3044 else
3045 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3046 }
3047 }
3048 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3049 {
3050 /* ERET */
3051 if (SR & status_ERL)
3052 {
3053 /* Oops, not yet available */
3054 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3055 PC = EPC;
3056 SR &= ~status_ERL;
3057 }
3058 else
3059 {
3060 PC = EPC;
3061 SR &= ~status_EXL;
3062 }
3063 }
3064 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3065 {
3066 /* RFE */
3067 }
3068 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3069 {
3070 /* DERET */
3071 Debug &= ~Debug_DM;
3072 DELAYSLOT();
3073 DSPC = DEPC;
3074 }
3075 else
3076 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC));
3077 /* TODO: When executing an ERET or RFE instruction we should
3078 clear LLBIT, to ensure that any out-standing atomic
3079 read/modify/write sequence fails. */
3080 }
3081 break;
3082
3083 case 2: /* undefined co-processor */
3084 sim_io_eprintf(sd,"COP2 instruction 0x%08X at IPC = 0x%s : No handler present\n",instruction,pr_addr(IPC));
3085 break;
3086
3087 case 1: /* should not occur (FPU co-processor) */
3088 case 3: /* should not occur (FPU co-processor) */
3089 SignalException(ReservedInstruction,instruction);
3090 break;
3091 }
3092
3093 return;
3094 }
3095
3096 /*-- instruction simulation -------------------------------------------------*/
3097
3098 /* When the IGEN simulator is being built, the function below is be
3099 replaced by a generated version. However, WITH_IGEN == 2 indicates
3100 that the fubction below should be compiled but under a different
3101 name (to allow backward compatibility) */
3102
3103 #if (WITH_IGEN != 1)
3104 #if (WITH_IGEN > 1)
3105 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3106 void
3107 old_engine_run (sd, next_cpu_nr, siggnal)
3108 #else
3109 void
3110 sim_engine_run (sd, next_cpu_nr, siggnal)
3111 #endif
3112 SIM_DESC sd;
3113 int next_cpu_nr; /* ignore */
3114 int siggnal; /* ignore */
3115 {
3116 #if !defined(FASTSIM)
3117 unsigned int pipeline_count = 1;
3118 #endif
3119
3120 #ifdef DEBUG
3121 if (STATE_MEMORY (sd) == NULL) {
3122 printf("DBG: simulate() entered with no memory\n");
3123 exit(1);
3124 }
3125 #endif /* DEBUG */
3126
3127 #if 0 /* Disabled to check that everything works OK */
3128 /* The VR4300 seems to sign-extend the PC on its first
3129 access. However, this may just be because it is currently
3130 configured in 32bit mode. However... */
3131 PC = SIGNEXTEND(PC,32);
3132 #endif
3133
3134 /* main controlling loop */
3135 while (1) {
3136 /* vaddr is slowly being replaced with cia - current instruction
3137 address */
3138 address_word cia = (uword64)PC;
3139 address_word vaddr = cia;
3140 address_word paddr;
3141 int cca;
3142 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3143
3144 #ifdef DEBUG
3145 {
3146 printf("DBG: state = 0x%08X :",state);
3147 if (state & simHALTEX) printf(" simHALTEX");
3148 if (state & simHALTIN) printf(" simHALTIN");
3149 printf("\n");
3150 }
3151 #endif /* DEBUG */
3152
3153 DSSTATE = (STATE & simDELAYSLOT);
3154 #ifdef DEBUG
3155 if (dsstate)
3156 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3157 #endif /* DEBUG */
3158
3159 /* Fetch the next instruction from the simulator memory: */
3160 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3161 if ((vaddr & 1) == 0) {
3162 /* Copy the action of the LW instruction */
3163 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3164 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3165 uword64 value;
3166 unsigned int byte;
3167 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3168 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3169 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3170 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3171 } else {
3172 /* Copy the action of the LH instruction */
3173 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3174 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3175 uword64 value;
3176 unsigned int byte;
3177 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3178 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3179 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3180 paddr & ~ (uword64) 1,
3181 vaddr, isINSTRUCTION, isREAL);
3182 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3183 instruction = ((value >> (8 * byte)) & 0xFFFF);
3184 }
3185 } else {
3186 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3187 exit(1);
3188 }
3189
3190 #ifdef DEBUG
3191 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3192 #endif /* DEBUG */
3193
3194 IPC = PC; /* copy PC for this instruction */
3195 /* This is required by exception processing, to ensure that we can
3196 cope with exceptions in the delay slots of branches that may
3197 already have changed the PC. */
3198 if ((vaddr & 1) == 0)
3199 PC += 4; /* increment ready for the next fetch */
3200 else
3201 PC += 2;
3202 /* NOTE: If we perform a delay slot change to the PC, this
3203 increment is not requuired. However, it would make the
3204 simulator more complicated to try and avoid this small hit. */
3205
3206 /* Currently this code provides a simple model. For more
3207 complicated models we could perform exception status checks at
3208 this point, and set the simSTOP state as required. This could
3209 also include processing any hardware interrupts raised by any
3210 I/O model attached to the simulator context.
3211
3212 Support for "asynchronous" I/O events within the simulated world
3213 could be providing by managing a counter, and calling a I/O
3214 specific handler when a particular threshold is reached. On most
3215 architectures a decrement and check for zero operation is
3216 usually quicker than an increment and compare. However, the
3217 process of managing a known value decrement to zero, is higher
3218 than the cost of using an explicit value UINT_MAX into the
3219 future. Which system is used will depend on how complicated the
3220 I/O model is, and how much it is likely to affect the simulator
3221 bandwidth.
3222
3223 If events need to be scheduled further in the future than
3224 UINT_MAX event ticks, then the I/O model should just provide its
3225 own counter, triggered from the event system. */
3226
3227 /* MIPS pipeline ticks. To allow for future support where the
3228 pipeline hit of individual instructions is known, this control
3229 loop manages a "pipeline_count" variable. It is initialised to
3230 1 (one), and will only be changed by the simulator engine when
3231 executing an instruction. If the engine does not have access to
3232 pipeline cycle count information then all instructions will be
3233 treated as using a single cycle. NOTE: A standard system is not
3234 provided by the default simulator because different MIPS
3235 architectures have different cycle counts for the same
3236 instructions.
3237
3238 [NOTE: pipeline_count has been replaced the event queue] */
3239
3240 #if defined(HASFPU)
3241 /* Set previous flag, depending on current: */
3242 if (STATE & simPCOC0)
3243 STATE |= simPCOC1;
3244 else
3245 STATE &= ~simPCOC1;
3246 /* and update the current value: */
3247 if (GETFCC(0))
3248 STATE |= simPCOC0;
3249 else
3250 STATE &= ~simPCOC0;
3251 #endif /* HASFPU */
3252
3253 /* NOTE: For multi-context simulation environments the "instruction"
3254 variable should be local to this routine. */
3255
3256 /* Shorthand accesses for engine. Note: If we wanted to use global
3257 variables (and a single-threaded simulator engine), then we can
3258 create the actual variables with these names. */
3259
3260 if (!(STATE & simSKIPNEXT)) {
3261 /* Include the simulator engine */
3262 #include "oengine.c"
3263 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3264 #error "Mismatch between run-time simulator code and simulation engine"
3265 #endif
3266 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3267 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3268 #endif
3269 #if (WITH_FLOATING_POINT == HARD_FLOATING_POINT != defined (HASFPU))
3270 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3271 #endif
3272
3273 #if defined(WARN_LOHI)
3274 /* Decrement the HI/LO validity ticks */
3275 if (HIACCESS > 0)
3276 HIACCESS--;
3277 if (LOACCESS > 0)
3278 LOACCESS--;
3279 /* start-sanitize-r5900 */
3280 if (HI1ACCESS > 0)
3281 HI1ACCESS--;
3282 if (LO1ACCESS > 0)
3283 LO1ACCESS--;
3284 /* end-sanitize-r5900 */
3285 #endif /* WARN_LOHI */
3286
3287 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3288 should check for it being changed. It is better doing it here,
3289 than within the simulator, since it will help keep the simulator
3290 small. */
3291 if (ZERO != 0) {
3292 #if defined(WARN_ZERO)
3293 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(IPC));
3294 #endif /* WARN_ZERO */
3295 ZERO = 0; /* reset back to zero before next instruction */
3296 }
3297 } else /* simSKIPNEXT check */
3298 STATE &= ~simSKIPNEXT;
3299
3300 /* If the delay slot was active before the instruction is
3301 executed, then update the PC to its new value: */
3302 if (DSSTATE) {
3303 #ifdef DEBUG
3304 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3305 #endif /* DEBUG */
3306 PC = DSPC;
3307 CANCELDELAYSLOT();
3308 }
3309
3310 if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
3311 /* Deal with pending register updates: */
3312 #ifdef DEBUG
3313 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
3314 #endif /* DEBUG */
3315 if (PENDING_OUT != PENDING_IN) {
3316 int loop;
3317 int index = PENDING_OUT;
3318 int total = PENDING_TOTAL;
3319 if (PENDING_TOTAL == 0) {
3320 fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
3321 exit(1);
3322 }
3323 for (loop = 0; (loop < total); loop++) {
3324 #ifdef DEBUG
3325 printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
3326 #endif /* DEBUG */
3327 if (PENDING_SLOT_REG[index] != (LAST_EMBED_REGNUM + 1)) {
3328 #ifdef DEBUG
3329 printf("pending_slot_count[%d] = %d\n",index,PENDING_SLOT_COUNT[index]);
3330 #endif /* DEBUG */
3331 if (--(PENDING_SLOT_COUNT[index]) == 0) {
3332 #ifdef DEBUG
3333 printf("pending_slot_reg[%d] = %d\n",index,PENDING_SLOT_REG[index]);
3334 printf("pending_slot_value[%d] = 0x%s\n",index,pr_addr(PENDING_SLOT_VALUE[index]));
3335 #endif /* DEBUG */
3336 if (PENDING_SLOT_REG[index] == COCIDX) {
3337 #if defined(HASFPU)
3338 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3339 #else
3340 ;
3341 #endif
3342 } else {
3343 REGISTERS[PENDING_SLOT_REG[index]] = PENDING_SLOT_VALUE[index];
3344 #if defined(HASFPU)
3345 /* The only time we have PENDING updates to FPU
3346 registers, is when performing binary transfers. This
3347 means we should update the register type field. */
3348 if ((PENDING_SLOT_REG[index] >= FGRIDX) && (PENDING_SLOT_REG[index] < (FGRIDX + 32)))
3349 FPR_STATE[PENDING_SLOT_REG[index] - FGRIDX] = fmt_uninterpreted;
3350 #endif /* HASFPU */
3351 }
3352 #ifdef DEBUG
3353 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG[index],pr_addr(REGISTERS[PENDING_SLOT_REG[index]]));
3354 #endif /* DEBUG */
3355 PENDING_SLOT_REG[index] = (LAST_EMBED_REGNUM + 1);
3356 PENDING_OUT++;
3357 if (PENDING_OUT == PSLOTS)
3358 PENDING_OUT = 0;
3359 PENDING_TOTAL--;
3360 }
3361 }
3362 #ifdef DEBUG
3363 printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
3364 #endif /* DEBUG */
3365 index++;
3366 if (index == PSLOTS)
3367 index = 0;
3368 }
3369 }
3370 #ifdef DEBUG
3371 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);
3372 #endif /* DEBUG */
3373 }
3374
3375 #if !defined(FASTSIM)
3376 if (sim_events_tickn (sd, pipeline_count))
3377 {
3378 /* cpu->cia = cia; */
3379 sim_events_process (sd);
3380 }
3381 #else
3382 if (sim_events_tick (sd))
3383 {
3384 /* cpu->cia = cia; */
3385 sim_events_process (sd);
3386 }
3387 #endif /* FASTSIM */
3388 }
3389 }
3390 #endif
3391
3392
3393 /* This code copied from gdb's utils.c. Would like to share this code,
3394 but don't know of a common place where both could get to it. */
3395
3396 /* Temporary storage using circular buffer */
3397 #define NUMCELLS 16
3398 #define CELLSIZE 32
3399 static char*
3400 get_cell()
3401 {
3402 static char buf[NUMCELLS][CELLSIZE];
3403 static int cell=0;
3404 if (++cell>=NUMCELLS) cell=0;
3405 return buf[cell];
3406 }
3407
3408 /* Print routines to handle variable size regs, etc */
3409
3410 /* Eliminate warning from compiler on 32-bit systems */
3411 static int thirty_two = 32;
3412
3413 char*
3414 pr_addr(addr)
3415 SIM_ADDR addr;
3416 {
3417 char *paddr_str=get_cell();
3418 switch (sizeof(addr))
3419 {
3420 case 8:
3421 sprintf(paddr_str,"%08lx%08lx",
3422 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3423 break;
3424 case 4:
3425 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3426 break;
3427 case 2:
3428 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3429 break;
3430 default:
3431 sprintf(paddr_str,"%x",addr);
3432 }
3433 return paddr_str;
3434 }
3435
3436 char*
3437 pr_uword64(addr)
3438 uword64 addr;
3439 {
3440 char *paddr_str=get_cell();
3441 sprintf(paddr_str,"%08lx%08lx",
3442 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3443 return paddr_str;
3444 }
3445
3446
3447 /*---------------------------------------------------------------------------*/
3448 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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