2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 We only need to take account of the target endianness when moving data
23 between the simulator and the host. We do not need to worry about the
24 endianness of the host, since this sim code and GDB are executing in
27 The IDT monitor (found on the VR4300 board), seems to lie about
28 register contents. It seems to treat the registers as sign-extended
29 32-bit values. This cause *REAL* problems when single-stepping 64-bit
34 /* The TRACE and PROFILE manifests enable the provision of extra
35 features. If they are not defined then a simpler (quicker)
36 simulator is constructed without the required run-time checks,
38 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
64 #include "libiberty.h"
66 #include "callback.h" /* GDB simulator callback interface */
67 #include "remote-sim.h" /* GDB simulator interface */
69 #include "support.h" /* internal support manifests */
77 char* pr_addr
PARAMS ((SIM_ADDR addr
));
78 char* pr_uword64
PARAMS ((uword64 addr
));
81 #define SIGBUS SIGSEGV
84 /* Get the simulator engine description, without including the code: */
89 static SIM_OPEN_KIND sim_kind
;
91 static int big_endian_p
;
93 /* The following reserved instruction value is used when a simulator
94 trap is required. NOTE: Care must be taken, since this value may be
95 used in later revisions of the MIPS ISA. */
96 #define RSVD_INSTRUCTION (0x00000005)
97 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
99 #define RSVD_INSTRUCTION_ARG_SHIFT 6
100 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
103 /* NOTE: These numbers depend on the processor architecture being
105 #define Interrupt (0)
106 #define TLBModification (1)
109 #define AddressLoad (4)
110 #define AddressStore (5)
111 #define InstructionFetch (6)
112 #define DataReference (7)
113 #define SystemCall (8)
114 #define BreakPoint (9)
115 #define ReservedInstruction (10)
116 #define CoProcessorUnusable (11)
117 #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
122 /* The following exception code is actually private to the simulator
123 world. It is *NOT* a processor feature, and is used to signal
124 run-time errors in the simulator. */
125 #define SimulatorFault (0xFFFFFFFF)
127 /* The following are generic to all versions of the MIPS architecture
129 /* Memory Access Types (for CCA): */
131 #define CachedNoncoherent (1)
132 #define CachedCoherent (2)
135 #define isINSTRUCTION (1 == 0) /* FALSE */
136 #define isDATA (1 == 1) /* TRUE */
138 #define isLOAD (1 == 0) /* FALSE */
139 #define isSTORE (1 == 1) /* TRUE */
141 #define isREAL (1 == 0) /* FALSE */
142 #define isRAW (1 == 1) /* TRUE */
144 #define isTARGET (1 == 0) /* FALSE */
145 #define isHOST (1 == 1) /* TRUE */
147 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
148 is the number of bytes minus 1. */
149 #define AccessLength_BYTE (0)
150 #define AccessLength_HALFWORD (1)
151 #define AccessLength_TRIPLEBYTE (2)
152 #define AccessLength_WORD (3)
153 #define AccessLength_QUINTIBYTE (4)
154 #define AccessLength_SEXTIBYTE (5)
155 #define AccessLength_SEPTIBYTE (6)
156 #define AccessLength_DOUBLEWORD (7)
157 #define AccessLength_QUADWORD (15)
160 /* FPU registers must be one of the following types. All other values
161 are reserved (and undefined). */
167 /* The following are well outside the normal acceptable format
168 range, and are used in the register status vector. */
169 fmt_unknown
= 0x10000000,
170 fmt_uninterpreted
= 0x20000000,
174 /* NOTE: We cannot avoid globals, since the GDB "sim_" interface does
175 not allow a private variable to be passed around. This means that
176 simulators under GDB can only be single-threaded. However, it would
177 be possible for the simulators to be multi-threaded if GDB allowed
178 for a private pointer to be maintained. i.e. a general "void **ptr"
179 variable that GDB passed around in the argument list to all of
180 sim_xxx() routines. It could be initialised to NULL by GDB, and
181 then updated by sim_open() and used by the other sim_xxx() support
182 functions. This would allow new features in the simulator world,
183 like storing a context - continuing execution to gather a result,
184 and then going back to the point where the context was saved and
185 changing some state before continuing. i.e. the ability to perform
186 UNDOs on simulations. It would also allow the simulation of
187 shared-memory multi-processor systems. */
189 static host_callback
*callback
= NULL
; /* handle onto the current callback structure */
191 /* This is nasty, since we have to rely on matching the register
192 numbers used by GDB. Unfortunately, depending on the MIPS target
193 GDB uses different register numbers. We cannot just include the
194 relevant "gdb/tm.h" link, since GDB may not be configured before
195 the sim world, and also the GDB header file requires too much other
197 /* TODO: Sort out a scheme for *KNOWING* the mapping between real
198 registers, and the numbers that GDB uses. At the moment due to the
199 order that the tools are built, we cannot rely on a configured GDB
200 world whilst constructing the simulator. This means we have to
201 assume the GDB register number mapping. */
203 #define LAST_EMBED_REGNUM (89)
206 /* To keep this default simulator simple, and fast, we use a direct
207 vector of registers. The internal simulator engine then uses
208 manifests to access the correct slot. */
209 static ut_reg registers
[LAST_EMBED_REGNUM
+ 1];
210 static int register_widths
[LAST_EMBED_REGNUM
+ 1];
212 #define GPR (®isters[0])
215 #define FGR (®isters[FGRIDX])
217 #define LO (registers[33])
218 #define HI (registers[34])
219 #define PC (registers[37])
220 #define CAUSE (registers[36])
222 #define SR (registers[SRIDX]) /* CPU status register */
224 #define FCR0 (registers[FCR0IDX]) /* really a 32bit register */
225 #define FCR31IDX (70)
226 #define FCR31 (registers[FCR31IDX]) /* really a 32bit register */
228 #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
230 /* The following are pseudonyms for standard registers */
231 #define ZERO (registers[0])
232 #define V0 (registers[2])
233 #define A0 (registers[4])
234 #define A1 (registers[5])
235 #define A2 (registers[6])
236 #define A3 (registers[7])
237 #define SP (registers[29])
238 #define RA (registers[31])
241 /* start-sanitize-r5900 */
243 The R5900 has 128 bit registers, but the hi 64 bits are only touched by
244 multimedia (MMI) instructions. The normal mips instructions just use the
245 lower 64 bits. To avoid changing the older parts of the simulator to
246 handle this weirdness, the high 64 bits of each register are kept in
247 a separate array (registers1). The high 64 bits of any register are by
248 convention refered by adding a '1' to the end of the normal register's
249 name. So LO still refers to the low 64 bits of the LO register, LO1
250 refers to the high 64 bits of that same register.
253 /* The high part of each register */
254 static ut_reg registers1
[LAST_EMBED_REGNUM
+ 1];
256 #define GPR1 (®isters1[0])
258 #define LO1 (registers1[33])
259 #define HI1 (registers1[34])
261 #define BYTES_IN_MMI_REGS (sizeof(registers[0])+sizeof(registers1[0]))
262 #define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
263 #define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
264 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
266 #define BYTES_IN_MIPS_REGS (sizeof(registers[0]))
267 #define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
268 #define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
269 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
273 SUB_REG_FETCH - return as lvalue some sub-part of a "register"
274 T - type of the sub part
275 TC - # of T's in the mips part of the "register"
276 I - index (from 0) of desired sub part
277 A - low part of "register"
278 A1 - high part of register
280 #define SUB_REG_FETCH(T,TC,A,A1,I) (*(((T*)(((I) < (TC)) ? (A) : (A1))) + ((I) % (TC))))
283 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
284 where <type> has two letters:
285 1 is S=signed or U=unsigned
286 2 is B=byte H=halfword W=word D=doubleword
289 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed char, BYTES_IN_MIPS_REGS, A, A1, I)
290 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed short, HALFWORDS_IN_MIPS_REGS, A, A1, I)
291 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed int, WORDS_IN_MIPS_REGS, A, A1, I)
292 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed long long, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
294 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned char, BYTES_IN_MIPS_REGS, A, A1, I)
295 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned short, HALFWORDS_IN_MIPS_REGS, A, A1, I)
296 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned int, WORDS_IN_MIPS_REGS, A, A1, I)
297 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned long long,DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
301 #define GPR_SB(R,I) SUB_REG_SB(®isters[R], ®isters1[R], I)
302 #define GPR_SH(R,I) SUB_REG_SH(®isters[R], ®isters1[R], I)
303 #define GPR_SW(R,I) SUB_REG_SW(®isters[R], ®isters1[R], I)
304 #define GPR_SD(R,I) SUB_REG_SD(®isters[R], ®isters1[R], I)
306 #define GPR_UB(R,I) SUB_REG_UB(®isters[R], ®isters1[R], I)
307 #define GPR_UH(R,I) SUB_REG_UH(®isters[R], ®isters1[R], I)
308 #define GPR_UW(R,I) SUB_REG_UW(®isters[R], ®isters1[R], I)
309 #define GPR_UD(R,I) SUB_REG_UD(®isters[R], ®isters1[R], I)
312 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
313 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
314 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
315 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
317 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
318 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
319 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
320 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
322 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
323 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
324 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
325 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
327 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
328 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
329 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
330 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
334 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
335 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
336 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
337 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
339 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
340 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
341 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
342 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
344 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
345 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
346 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
347 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
349 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
350 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
351 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
352 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
353 /* end-sanitize-r5900 */
356 /* start-sanitize-r5900 */
357 static ut_reg SA
; /* the shift amount register */
358 /* end-sanitize-r5900 */
360 static ut_reg EPC
= 0; /* Exception PC */
363 /* Keep the current format state for each register: */
364 static FP_formats fpr_state
[32];
367 /* The following are internal simulator state variables: */
368 static ut_reg IPC
= 0; /* internal Instruction PC */
369 static ut_reg DSPC
= 0; /* delay-slot PC */
372 /* TODO : these should be the bitmasks for these bits within the
373 status register. At the moment the following are VR4300
375 #define status_KSU_mask (0x3) /* mask for KSU bits */
376 #define status_KSU_shift (3) /* shift for field */
377 #define ksu_kernel (0x0)
378 #define ksu_supervisor (0x1)
379 #define ksu_user (0x2)
380 #define ksu_unknown (0x3)
382 #define status_RE (1 << 25) /* Reverse Endian in user mode */
383 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
384 #define status_SR (1 << 20) /* soft reset or NMI */
385 #define status_BEV (1 << 22) /* Location of general exception vectors */
386 #define status_TS (1 << 21) /* TLB shutdown has occurred */
387 #define status_ERL (1 << 2) /* Error level */
388 #define status_RP (1 << 27) /* Reduced Power mode */
390 #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
393 /* Macro to update FPSR condition-code field. This is complicated by
394 the fact that there is a hole in the index range of the bits within
395 the FCSR register. Also, the number of bits visible depends on the
396 MIPS ISA version being supported. */
397 #define SETFCC(cc,v) {\
398 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
399 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
401 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
403 /* This should be the COC1 value at the start of the preceding
405 #define PREVCOC1() ((state & simPCOC1) ? 1 : 0)
408 /* Standard FCRS bits: */
409 #define IR (0) /* Inexact Result */
410 #define UF (1) /* UnderFlow */
411 #define OF (2) /* OverFlow */
412 #define DZ (3) /* Division by Zero */
413 #define IO (4) /* Invalid Operation */
414 #define UO (5) /* Unimplemented Operation */
416 /* Get masks for individual flags: */
417 #if 1 /* SAFE version */
418 #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
419 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
420 #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
422 #define FP_FLAGS(b) (1 << ((b) + 2))
423 #define FP_ENABLE(b) (1 << ((b) + 7))
424 #define FP_CAUSE(b) (1 << ((b) + 12))
427 #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
429 #define FP_MASK_RM (0x3)
431 #define FP_RM_NEAREST (0) /* Round to nearest (Round) */
432 #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
433 #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
434 #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
435 #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
437 /* Slots for delayed register updates. For the moment we just have a
438 fixed number of slots (rather than a more generic, dynamic
439 system). This keeps the simulator fast. However, we only allow for
440 the register update to be delayed for a single instruction
442 #define PSLOTS (5) /* Maximum number of instruction cycles */
443 static int pending_in
;
444 static int pending_out
;
445 static int pending_total
;
446 static int pending_slot_count
[PSLOTS
];
447 static int pending_slot_reg
[PSLOTS
];
448 static ut_reg pending_slot_value
[PSLOTS
];
450 /*---------------------------------------------------------------------------*/
451 /*-- GDB simulator interface ------------------------------------------------*/
452 /*---------------------------------------------------------------------------*/
454 static void dotrace
PARAMS((FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...));
455 static void sim_warning
PARAMS((char *fmt
,...));
456 extern void sim_error
PARAMS((char *fmt
,...));
457 static void set_endianness
PARAMS((void));
458 static void ColdReset
PARAMS((void));
459 static int AddressTranslation
PARAMS((uword64 vAddr
,int IorD
,int LorS
,uword64
*pAddr
,int *CCA
,int host
,int raw
));
460 static void StoreMemory
PARAMS((int CCA
,int AccessLength
,uword64 MemElem
,uword64 MemElem1
,uword64 pAddr
,uword64 vAddr
,int raw
));
461 static void LoadMemory
PARAMS((uword64
*memvalp
,uword64
*memval1p
,int CCA
,int AccessLength
,uword64 pAddr
,uword64 vAddr
,int IorD
,int raw
));
462 static void SignalException
PARAMS((int exception
,...));
463 static void simulate
PARAMS((void));
464 static long getnum
PARAMS((char *value
));
465 extern void sim_set_profile
PARAMS((int frequency
));
466 static unsigned int power2
PARAMS((unsigned int value
));
468 /*---------------------------------------------------------------------------*/
470 /* The following are not used for MIPS IV onwards: */
471 #define PENDING_FILL(r,v) {\
472 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total); */\
473 if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\
474 sim_warning("Attempt to over-write pending value");\
475 pending_slot_count[pending_in] = 2;\
476 pending_slot_reg[pending_in] = (r);\
477 pending_slot_value[pending_in] = (uword64)(v);\
478 /*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
481 if (pending_in == PSLOTS)\
483 /*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);*/\
486 static int LLBIT
= 0;
487 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
488 read-write instructions. It is set when a linked load occurs. It is
489 tested and cleared by the conditional store. It is cleared (during
490 other CPU operations) when a store to the location would no longer
491 be atomic. In particular, it is cleared by exception return
494 static int HIACCESS
= 0;
495 static int LOACCESS
= 0;
496 static int HI1ACCESS
= 0;
497 static int LO1ACCESS
= 0;
498 /* The HIACCESS and LOACCESS counts are used to ensure that
499 corruptions caused by using the HI or LO register to close to a
500 following operation are spotted. */
501 static ut_reg HLPC
= 0;
503 /* ??? The 4300 and a few other processors have interlocks on hi/lo register
504 reads, and hence do not have this problem. To avoid spurious warnings,
505 we just disable this always. */
509 /* If either of the preceding two instructions have accessed the HI or
510 LO registers, then the values they see should be
511 undefined. However, to keep the simulator world simple, we just let
512 them use the value read and raise a warning to notify the user: */
513 #define CHECKHILO(s) {\
514 if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
515 sim_warning("%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
519 /* NOTE: We keep the following status flags as bit values (1 for true,
520 0 for false). This allows them to be used in binary boolean
521 operations without worrying about what exactly the non-zero true
525 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
528 /* Hardware configuration. Affects endianness of LoadMemory and
529 StoreMemory and the endianness of Kernel and Supervisor mode
530 execution. The value is 0 for little-endian; 1 for big-endian. */
531 #define BigEndianMem ((state & simBE) ? 1 : 0)
534 /* This is true if the host and target have different endianness. */
535 #define ByteSwapMem (!(state & simHOSTBE) != !(state & simBE))
538 /* This mode is selected if in User mode with the RE bit being set in
539 SR (Status Register). It reverses the endianness of load and store
541 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
544 /* The endianness for load and store instructions (0=little;1=big). In
545 User mode this endianness may be switched by setting the state_RE
546 bit in the SR register. Thus, BigEndianCPU may be computed as
547 (BigEndianMem EOR ReverseEndian). */
548 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
550 #if !defined(FASTSIM) || defined(PROFILE)
551 /* At the moment these values will be the same, since we do not have
552 access to the pipeline cycle count information from the simulator
554 static unsigned int instruction_fetches
= 0;
555 static unsigned int instruction_fetch_overflow
= 0;
556 static unsigned int pipeline_ticks
= 0;
559 /* Flags in the "state" variable: */
560 #define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */
561 #define simSTEP (1 << 1) /* 0 = run; 1 = single-step */
562 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
563 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
564 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
565 #define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */
566 #define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */
567 /* Whilst simSTOP is not set, the simulator control loop should just
568 keep simulating instructions. The simSTEP flag is used to force
569 single-step execution. */
570 #define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */
571 #define simPCOC0 (1 << 17) /* COC[1] from current */
572 #define simPCOC1 (1 << 18) /* COC[1] from previous */
573 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
574 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
575 #define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
576 #define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
577 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
578 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
580 static unsigned int state
= 0;
581 static unsigned int rcexit
= 0; /* _exit() reason code holder */
583 #define DELAYSLOT() {\
584 if (state & simDELAYSLOT)\
585 sim_warning("Delay slot already activated (branch in delay slot?)");\
586 state |= simDELAYSLOT;\
589 #define JALDELAYSLOT() {\
591 state |= simJALDELAYSLOT;\
595 state &= ~simDELAYSLOT;\
596 state |= simSKIPNEXT;\
599 #define INDELAYSLOT() ((state & simDELAYSLOT) != 0)
600 #define INJALDELAYSLOT() ((state & simJALDELAYSLOT) != 0)
602 #define K0BASE (0x80000000)
603 #define K0SIZE (0x20000000)
604 #define K1BASE (0xA0000000)
605 #define K1SIZE (0x20000000)
607 /* Very simple memory model to start with: */
608 static unsigned char *membank
= NULL
;
609 static ut_reg membank_base
= K1BASE
;
610 /* The ddb.ld linker script loads text at K1BASE+1MB, and the idt.ld linker
611 script loads text at K1BASE+128KB. We allocate 2MB, so that we have a
612 minimum of 1 MB available for the user process. We must have memory
613 above _end in order for sbrk to work. */
614 static unsigned membank_size
= (2 << 20);
616 /* Simple run-time monitor support */
617 static unsigned char *monitor
= NULL
;
618 static ut_reg monitor_base
= 0xBFC00000;
619 static unsigned monitor_size
= (1 << 11); /* power-of-2 */
621 static char *logfile
= NULL
; /* logging disabled by default */
622 static FILE *logfh
= NULL
;
625 static char *tracefile
= "trace.din"; /* default filename for trace log */
626 static FILE *tracefh
= NULL
;
627 static void open_trace
PARAMS((void));
631 static unsigned profile_frequency
= 256;
632 static unsigned profile_nsamples
= (128 << 10);
633 static unsigned short *profile_hist
= NULL
;
634 static ut_reg profile_minpc
;
635 static ut_reg profile_maxpc
;
636 static int profile_shift
= 0; /* address shift amount */
639 /* The following are used to provide shortcuts to the required version
640 of host<->target copying. This avoids run-time conditionals, which
641 would slow the simulator throughput. */
642 typedef unsigned int (*fnptr_read_word
) PARAMS((unsigned char *memory
));
643 typedef unsigned int (*fnptr_swap_word
) PARAMS((unsigned int data
));
644 typedef uword64 (*fnptr_read_long
) PARAMS((unsigned char *memory
));
645 typedef uword64 (*fnptr_swap_long
) PARAMS((uword64 data
));
647 static fnptr_read_word host_read_word
;
648 static fnptr_read_long host_read_long
;
649 static fnptr_swap_word host_swap_word
;
650 static fnptr_swap_long host_swap_long
;
652 /*---------------------------------------------------------------------------*/
653 /*-- GDB simulator interface ------------------------------------------------*/
654 /*---------------------------------------------------------------------------*/
661 if (callback
== NULL
) {
662 fprintf(stderr
,"SIM Error: sim_open() called without callbacks attached\n");
666 /* The following ensures that the standard file handles for stdin,
667 stdout and stderr are initialised: */
668 callback
->init(callback
);
675 if (state
& simEXCEPTION
) {
676 fprintf(stderr
,"This simulator is not suitable for this host configuration\n");
682 if (*((char *)&data
) != 0x12)
683 state
|= simHOSTBE
; /* big-endian host */
687 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
688 and DOUBLE binary formats. This is a bit nasty, requiring that we
689 trust the explicit manifests held in the source: */
692 s
[state
& simHOSTBE
? 0 : 1] = 0x40805A5A;
693 s
[state
& simHOSTBE
? 1 : 0] = 0x00000000;
695 /* TODO: We need to cope with the simulated target and the host
696 not having the same endianness. This will require the high and
697 low words of a (double) to be swapped when converting between
698 the host and the simulated target. */
700 if (((float)4.01102924346923828125 != *(float *)(s
+ ((state
& simHOSTBE
) ? 0 : 1))) || ((double)523.2939453125 != *(double *)s
)) {
701 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
702 fprintf(stderr
,"*(float *)s = %.20f (4.01102924346923828125)\n",*(float *)s
);
703 fprintf(stderr
,"*(double *)s = %.20f (523.2939453125)\n",*(double *)s
);
709 /* This is NASTY, in that we are assuming the size of specific
713 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
715 register_widths
[rn
] = GPRLEN
;
716 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
717 register_widths
[rn
] = GPRLEN
;
718 else if ((rn
>= 33) && (rn
<= 37))
719 register_widths
[rn
] = GPRLEN
;
720 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
721 register_widths
[rn
] = 32;
723 register_widths
[rn
] = 0;
727 /* It would be good if we could select particular named MIPS
728 architecture simulators. However, having a pre-built, fixed
729 engine would mean including multiple engines. If the simulator is
730 changed to a run-time conditional version, then the ability to
731 select a particular architecture would be straightforward. */
736 static struct option cmdline
[] = {
740 {"profile", 0,0,'p'},
743 {"tracefile",1,0,'z'},
744 {"frequency",1,0,'y'},
745 {"samples", 1,0,'x'},
749 for (argc
= 0; argv
[argc
]; argc
++);
751 /* Ensure getopt is reset [don't know whether caller used it]. */
755 int option_index
= 0;
757 c
= getopt_long(argc
,argv
,"E:hn:s:tp",cmdline
,&option_index
);
763 big_endian_p
= strcmp (optarg
, "big") == 0;
767 callback
->printf_filtered(callback
,"Usage:\n\t\
768 target sim [-h] [--log=<file>] [--name=<model>] [--size=<amount>]");
770 callback
->printf_filtered(callback
," [-t [--tracefile=<name>]]");
773 callback
->printf_filtered(callback
," [-p [--frequency=<count>] [--samples=<count>]]");
775 callback
->printf_filtered(callback
,"\n");
779 if (optarg
!= NULL
) {
781 tmp
= (char *)malloc(strlen(optarg
) + 1);
783 callback
->printf_filtered(callback
,"Failed to allocate buffer for logfile name \"%s\"\n",optarg
);
792 callback
->printf_filtered(callback
,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg
);
796 membank_size
= (unsigned)getnum(optarg
);
801 /* Eventually the simTRACE flag could be treated as a toggle, to
802 allow external control of the program points being traced
803 (i.e. only from main onwards, excluding the run-time setup,
808 Simulator constructed without tracing support (for performance).\n\
809 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
815 if (optarg
!= NULL
) {
817 tmp
= (char *)malloc(strlen(optarg
) + 1);
819 callback
->printf_filtered(callback
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
823 callback
->printf_filtered(callback
,"Placing trace information into file \"%s\"\n",tracefile
);
834 Simulator constructed without profiling support (for performance).\n\
835 Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
836 #endif /* !PROFILE */
841 profile_nsamples
= (unsigned)getnum(optarg
);
847 sim_set_profile((int)getnum(optarg
));
852 callback
->printf_filtered(callback
,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c
);
860 callback
->printf_filtered(callback
,"Warning: Ignoring spurious non-option arguments ");
861 while (optind
< argc
)
862 callback
->printf_filtered(callback
,"\"%s\" ",argv
[optind
++]);
863 callback
->printf_filtered(callback
,"\n");
868 if (logfile
!= NULL
) {
869 if (strcmp(logfile
,"-") == 0)
872 logfh
= fopen(logfile
,"wb+");
874 callback
->printf_filtered(callback
,"Failed to create file \"%s\", writing log information to stderr.\n",tracefile
);
882 /* If the host has "mmap" available we could use it to provide a
883 very large virtual address space for the simulator, since memory
884 would only be allocated within the "mmap" space as it is
885 accessed. This can also be linked to the architecture specific
886 support, required to simulate the MMU. */
887 sim_size(membank_size
);
888 /* NOTE: The above will also have enabled any profiling state */
891 /* If we were providing a more complete I/O, co-processor or memory
892 simulation, we should perform any "device" initialisation at this
893 point. This can include pre-loading memory areas with particular
894 patterns (e.g. simulating ROM monitors). */
896 /* We can start writing to the memory, now that the processor has
898 monitor
= (unsigned char *)calloc(1,monitor_size
);
900 fprintf(stderr
,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size
);
903 /* Entry into the IDT monitor is via fixed address vectors, and
904 not using machine instructions. To avoid clashing with use of
905 the MIPS TRAP system, we place our own (simulator specific)
906 "undefined" instructions into the relevant vector slots. */
907 for (loop
= 0; (loop
< monitor_size
); loop
+= 4) {
908 uword64 vaddr
= (monitor_base
+ loop
);
911 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
912 StoreMemory(cca
,AccessLength_WORD
,(RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
)),0,paddr
,vaddr
,isRAW
);
914 /* The PMON monitor uses the same address space, but rather than
915 branching into it the address of a routine is loaded. We can
916 cheat for the moment, and direct the PMON routine to IDT style
917 instructions within the monitor space. This relies on the IDT
918 monitor not using the locations from 0xBFC00500 onwards as its
920 for (loop
= 0; (loop
< 24); loop
++)
922 uword64 vaddr
= (monitor_base
+ 0x500 + (loop
* 4));
925 unsigned int value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
945 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
948 case 8: /* cliexit */
952 case 11: /* flush_cache */
956 /* FIXME - should monitor_base be SIM_ADDR?? */
957 value
= ((unsigned int)monitor_base
+ (value
* 8));
958 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
959 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
961 sim_error("Failed to write to monitor space 0x%s",pr_addr(vaddr
));
963 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
965 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
966 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
968 sim_error("Failed to write to monitor space 0x%s",pr_addr(vaddr
));
973 if (state
& simTRACE
)
977 /* fudge our descriptor for now */
985 tracefh
= fopen(tracefile
,"wb+");
988 sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile
);
994 /* For the profile writing, we write the data in the host
995 endianness. This unfortunately means we are assuming that the
996 profile file we create is processed on the same host executing the
997 simulator. The gmon.out file format should either have an explicit
998 endianness, or a method of encoding the endianness in the file
1008 if (state
& simHOSTBE
) {
1009 buff
[3] = ((val
>> 0) & 0xFF);
1010 buff
[2] = ((val
>> 8) & 0xFF);
1011 buff
[1] = ((val
>> 16) & 0xFF);
1012 buff
[0] = ((val
>> 24) & 0xFF);
1014 buff
[0] = ((val
>> 0) & 0xFF);
1015 buff
[1] = ((val
>> 8) & 0xFF);
1016 buff
[2] = ((val
>> 16) & 0xFF);
1017 buff
[3] = ((val
>> 24) & 0xFF);
1019 if (fwrite(buff
,4,1,fh
) != 1) {
1020 sim_warning("Failed to write 4bytes to the profile file");
1033 if (state
& simHOSTBE
) {
1034 buff
[1] = ((val
>> 0) & 0xFF);
1035 buff
[0] = ((val
>> 8) & 0xFF);
1037 buff
[0] = ((val
>> 0) & 0xFF);
1038 buff
[1] = ((val
>> 8) & 0xFF);
1040 if (fwrite(buff
,2,1,fh
) != 1) {
1041 sim_warning("Failed to write 2bytes to the profile file");
1048 sim_close (sd
, quitting
)
1053 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
1056 /* Cannot assume sim_kill() has been called */
1057 /* "quitting" is non-zero if we cannot hang on errors */
1059 /* Ensure that any resources allocated through the callback
1060 mechanism are released: */
1061 callback
->shutdown(callback
);
1063 #if defined(PROFILE)
1064 if ((state
& simPROFILE
) && (profile_hist
!= NULL
)) {
1065 unsigned short *p
= profile_hist
;
1066 FILE *pf
= fopen("gmon.out","wb");
1070 sim_warning("Failed to open \"gmon.out\" profile file");
1074 printf("DBG: minpc = 0x%s\n",pr_addr(profile_minpc
));
1075 printf("DBG: maxpc = 0x%s\n",pr_addr(profile_maxpc
));
1077 ok
= writeout32(pf
,(unsigned int)profile_minpc
);
1079 ok
= writeout32(pf
,(unsigned int)profile_maxpc
);
1081 ok
= writeout32(pf
,(profile_nsamples
* 2) + 12); /* size of sample buffer (+ header) */
1083 printf("DBG: nsamples = %d (size = 0x%08X)\n",profile_nsamples
,((profile_nsamples
* 2) + 12));
1085 for (loop
= 0; (ok
&& (loop
< profile_nsamples
)); loop
++) {
1086 ok
= writeout16(pf
,profile_hist
[loop
]);
1095 profile_hist
= NULL
;
1096 state
&= ~simPROFILE
;
1098 #endif /* PROFILE */
1101 if (tracefh
!= NULL
&& tracefh
!= stderr
)
1107 if (logfh
!= NULL
&& logfh
!= stdout
&& logfh
!= stderr
)
1112 free(membank
); /* cfree not available on all hosts */
1119 control_c (sig
, code
, scp
, addr
)
1125 state
|= (simSTOP
| simSIGINT
);
1129 sim_resume (sd
,step
,signal_number
)
1131 int step
, signal_number
;
1136 printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step
,signal_number
,membank
);
1140 state
|= simSTEP
; /* execute only a single instruction */
1142 state
&= ~(simSTOP
| simSTEP
); /* execute until event */
1144 state
|= (simHALTEX
| simHALTIN
); /* treat interrupt event as exception */
1146 /* Start executing instructions from the current state (set
1147 explicitly by register updates, or by sim_create_inferior): */
1149 prev
= signal (SIGINT
, control_c
);
1153 signal (SIGINT
, prev
);
1159 sim_write (sd
,addr
,buffer
,size
)
1162 unsigned char *buffer
;
1166 uword64 vaddr
= (uword64
)addr
;
1168 /* Return the number of bytes written, or zero if error. */
1170 callback
->printf_filtered(callback
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
1173 /* We provide raw read and write routines, since we do not want to
1174 count the GDB memory accesses in our statistics gathering. */
1176 /* There is a lot of code duplication in the individual blocks
1177 below, but the variables are declared locally to a block to give
1178 the optimiser the best chance of improving the code. We have to
1179 perform slow byte reads from the host memory, to ensure that we
1180 get the data into the correct endianness for the (simulated)
1181 target memory world. */
1183 /* Mask count to get odd byte, odd halfword, and odd word out of the
1184 way. We can then perform doubleword transfers to and from the
1185 simulator memory for optimum performance. */
1186 if (index
&& (index
& 1)) {
1189 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1190 uword64 value
= ((uword64
)(*buffer
++));
1191 StoreMemory(cca
,AccessLength_BYTE
,value
,0,paddr
,vaddr
,isRAW
);
1194 index
&= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
1196 if (index
&& (index
& 2)) {
1199 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1201 /* We need to perform the following magic to ensure that that
1202 bytes are written into same byte positions in the target memory
1203 world, regardless of the endianness of the host. */
1205 value
= ((uword64
)(*buffer
++) << 8);
1206 value
|= ((uword64
)(*buffer
++) << 0);
1208 value
= ((uword64
)(*buffer
++) << 0);
1209 value
|= ((uword64
)(*buffer
++) << 8);
1211 StoreMemory(cca
,AccessLength_HALFWORD
,value
,0,paddr
,vaddr
,isRAW
);
1216 if (index
&& (index
& 4)) {
1219 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1222 value
= ((uword64
)(*buffer
++) << 24);
1223 value
|= ((uword64
)(*buffer
++) << 16);
1224 value
|= ((uword64
)(*buffer
++) << 8);
1225 value
|= ((uword64
)(*buffer
++) << 0);
1227 value
= ((uword64
)(*buffer
++) << 0);
1228 value
|= ((uword64
)(*buffer
++) << 8);
1229 value
|= ((uword64
)(*buffer
++) << 16);
1230 value
|= ((uword64
)(*buffer
++) << 24);
1232 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1237 for (;index
; index
-= 8) {
1240 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1243 value
= ((uword64
)(*buffer
++) << 56);
1244 value
|= ((uword64
)(*buffer
++) << 48);
1245 value
|= ((uword64
)(*buffer
++) << 40);
1246 value
|= ((uword64
)(*buffer
++) << 32);
1247 value
|= ((uword64
)(*buffer
++) << 24);
1248 value
|= ((uword64
)(*buffer
++) << 16);
1249 value
|= ((uword64
)(*buffer
++) << 8);
1250 value
|= ((uword64
)(*buffer
++) << 0);
1252 value
= ((uword64
)(*buffer
++) << 0);
1253 value
|= ((uword64
)(*buffer
++) << 8);
1254 value
|= ((uword64
)(*buffer
++) << 16);
1255 value
|= ((uword64
)(*buffer
++) << 24);
1256 value
|= ((uword64
)(*buffer
++) << 32);
1257 value
|= ((uword64
)(*buffer
++) << 40);
1258 value
|= ((uword64
)(*buffer
++) << 48);
1259 value
|= ((uword64
)(*buffer
++) << 56);
1261 StoreMemory(cca
,AccessLength_DOUBLEWORD
,value
,0,paddr
,vaddr
,isRAW
);
1270 sim_read (sd
,addr
,buffer
,size
)
1273 unsigned char *buffer
;
1278 /* Return the number of bytes read, or zero if error. */
1280 callback
->printf_filtered(callback
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
1283 /* TODO: Perform same optimisation as the sim_write() code
1284 above. NOTE: This will require a bit more work since we will need
1285 to ensure that the source physical address is doubleword aligned
1286 before, and then deal with trailing bytes. */
1287 for (index
= 0; (index
< size
); index
++) {
1288 uword64 vaddr
,paddr
,value
;
1290 vaddr
= (uword64
)addr
+ index
;
1291 if (AddressTranslation(vaddr
,isDATA
,isLOAD
,&paddr
,&cca
,isTARGET
,isRAW
)) {
1292 LoadMemory(&value
,NULL
,cca
,AccessLength_BYTE
,paddr
,vaddr
,isDATA
,isRAW
);
1293 buffer
[index
] = (unsigned char)(value
&0xFF);
1302 sim_store_register (sd
,rn
,memory
)
1305 unsigned char *memory
;
1308 callback
->printf_filtered(callback
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
1311 /* Unfortunately this suffers from the same problem as the register
1312 numbering one. We need to know what the width of each logical
1313 register number is for the architecture being simulated. */
1314 if (register_widths
[rn
] == 0)
1315 sim_warning("Invalid register width for %d (register store ignored)",rn
);
1317 if (register_widths
[rn
] == 32)
1318 registers
[rn
] = host_read_word(memory
);
1320 registers
[rn
] = host_read_long(memory
);
1327 sim_fetch_register (sd
,rn
,memory
)
1330 unsigned char *memory
;
1333 callback
->printf_filtered(callback
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
1336 if (register_widths
[rn
] == 0)
1337 sim_warning("Invalid register width for %d (register fetch ignored)",rn
);
1339 if (register_widths
[rn
] == 32)
1340 *((unsigned int *)memory
) = host_swap_word((unsigned int)(registers
[rn
] & 0xFFFFFFFF));
1341 else /* 64bit register */
1342 *((uword64
*)memory
) = host_swap_long(registers
[rn
]);
1348 sim_stop_reason (sd
,reason
,sigrc
)
1350 enum sim_stop
*reason
;
1353 /* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so
1354 sim_exited *sigrc = argument to exit()
1355 sim_stopped *sigrc = exception number
1356 sim_signalled *sigrc = signal number
1358 if (state
& simEXCEPTION
) {
1359 /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers,
1360 and not the MIPS specific exception codes. */
1362 /* For some reason, sending GDB a sim_signalled reason cause it to
1364 *reason
= sim_stopped
;
1366 *reason
= sim_signalled
;
1368 switch ((CAUSE
>> 2) & 0x1F) {
1370 *sigrc
= SIGINT
; /* wrong type of interrupt, but it will do for the moment */
1373 case TLBModification
:
1378 case InstructionFetch
:
1383 case ReservedInstruction
:
1384 case CoProcessorUnusable
:
1388 case IntegerOverflow
:
1400 default : /* Unknown internal exception */
1404 } else if (state
& simEXIT
) {
1406 printf("DBG: simEXIT (%d)\n",rcexit
);
1408 *reason
= sim_exited
;
1410 } else if (state
& simSIGINT
) {
1411 *reason
= sim_stopped
;
1413 } else { /* assume single-stepping */
1414 *reason
= sim_stopped
;
1417 state
&= ~(simEXCEPTION
| simEXIT
| simSIGINT
);
1422 sim_info (sd
,verbose
)
1426 /* Accessed from the GDB "info files" command: */
1428 callback
->printf_filtered(callback
,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT
? 64 : 32));
1430 callback
->printf_filtered(callback
,"%s endian memory model\n",(state
& simBE
? "Big" : "Little"));
1432 callback
->printf_filtered(callback
,"0x%08X bytes of memory at 0x%s\n",(unsigned int)membank_size
,pr_addr(membank_base
));
1434 #if !defined(FASTSIM)
1435 if (instruction_fetch_overflow
!= 0)
1436 callback
->printf_filtered(callback
,"Instruction fetches = 0x%08X%08X\n",instruction_fetch_overflow
,instruction_fetches
);
1438 callback
->printf_filtered(callback
,"Instruction fetches = %d\n",instruction_fetches
);
1439 callback
->printf_filtered(callback
,"Pipeline ticks = %d\n",pipeline_ticks
);
1440 /* It would be a useful feature, if when performing multi-cycle
1441 simulations (rather than single-stepping) we keep the start and
1442 end times of the execution, so that we can give a performance
1443 figure for the simulator. */
1444 #endif /* !FASTSIM */
1446 /* print information pertaining to MIPS ISA and architecture being simulated */
1447 /* things that may be interesting */
1448 /* instructions executed - if available */
1449 /* cycles executed - if available */
1450 /* pipeline stalls - if available */
1451 /* virtual time taken */
1452 /* profiling size */
1453 /* profiling frequency */
1461 sim_load (sd
,prog
,abfd
,from_tty
)
1467 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
1470 prog_bfd
= sim_load_file (sd
, myname
, callback
, prog
, abfd
,
1471 sim_kind
== SIM_OPEN_DEBUG
);
1472 if (prog_bfd
== NULL
)
1475 PC
= (uword64
) bfd_get_start_address (prog_bfd
);
1477 /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
1478 PC
= SIGNEXTEND(bfd_get_start_address(prog_bfd
),32);
1481 bfd_close (prog_bfd
);
1486 sim_create_inferior (sd
, argv
,env
)
1492 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1496 /* Prepare to execute the program to be simulated */
1497 /* argv and env are NULL terminated lists of pointers */
1500 #if 0 /* def DEBUG */
1501 callback
->printf_filtered(callback
,"sim_create_inferior() : passed arguments ignored\n");
1504 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1505 printf("DBG: arg \"%s\"\n",*cptr
);
1508 /* We should really place the argv slot values into the argument
1509 registers, and onto the stack as required. However, this
1510 assumes that we have a stack defined, which is not necessarily
1511 true at the moment. */
1522 /* This routine should be for terminating any existing simulation
1523 thread. Since we are single-threaded only at the moment, this is
1524 not an issue. It should *NOT* be used to terminate the
1526 #else /* do *NOT* call sim_close */
1527 sim_close(sd
, 1); /* Do not hang on errors */
1528 /* This would also be the point where any memory mapped areas used
1529 by the simulator should be released. */
1535 sim_get_quit_code ()
1537 /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as
1538 the function return value. However, it may be more correct for
1539 this to return the argument to the exit() function (if
1545 sim_set_callbacks (sd
,p
)
1553 typedef enum {e_terminate
,e_help
,e_setmemsize
,e_reset
} e_cmds
;
1555 static struct t_sim_command
{
1559 } sim_commands
[] = {
1560 {e_help
, "help", ": Show MIPS simulator private commands"},
1561 {e_setmemsize
,"set-memory-size","<n> : Specify amount of memory simulated"},
1562 {e_reset
, "reset-system", ": Reset the simulated processor"},
1567 sim_do_command (sd
,cmd
)
1571 struct t_sim_command
*cptr
;
1573 if (callback
== NULL
) {
1574 fprintf(stderr
,"Simulator not enabled: \"target sim\" should be used to activate\n");
1578 if (!(cmd
&& *cmd
!= '\0'))
1581 /* NOTE: Accessed from the GDB "sim" commmand: */
1582 for (cptr
= sim_commands
; cptr
&& cptr
->name
; cptr
++)
1583 if (strncmp(cmd
,cptr
->name
,strlen(cptr
->name
)) == 0) {
1584 cmd
+= strlen(cptr
->name
);
1586 case e_help
: /* no arguments */
1587 { /* no arguments */
1588 struct t_sim_command
*lptr
;
1589 callback
->printf_filtered(callback
,"List of MIPS simulator commands:\n");
1590 for (lptr
= sim_commands
; lptr
->name
; lptr
++)
1591 callback
->printf_filtered(callback
,"%s %s\n",lptr
->name
,lptr
->help
);
1595 case e_setmemsize
: /* memory size argument */
1597 unsigned int newsize
= (unsigned int)getnum(cmd
);
1602 case e_reset
: /* no arguments */
1604 /* NOTE: See the comments in sim_open() relating to device
1609 callback
->printf_filtered(callback
,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd
,cptr
->id
);
1616 callback
->printf_filtered(callback
,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd
);
1621 /*---------------------------------------------------------------------------*/
1622 /* NOTE: The following routines do not seem to be used by GDB at the
1623 moment. However, they may be useful to the standalone simulator
1627 /* The profiling format is described in the "gmon_out.h" header file */
1632 #if defined(PROFILE)
1633 profile_frequency
= n
;
1634 state
|= simPROFILE
;
1635 #endif /* PROFILE */
1640 sim_set_profile_size (n
)
1643 #if defined(PROFILE)
1644 if (state
& simPROFILE
) {
1647 /* Since we KNOW that the memory banks are a power-of-2 in size: */
1648 profile_nsamples
= power2(n
);
1649 profile_minpc
= membank_base
;
1650 profile_maxpc
= (membank_base
+ membank_size
);
1652 /* Just in-case we are sampling every address: NOTE: The shift
1653 right of 2 is because we only have word-aligned PC addresses. */
1654 if (profile_nsamples
> (membank_size
>> 2))
1655 profile_nsamples
= (membank_size
>> 2);
1657 /* Since we are dealing with power-of-2 values: */
1658 profile_shift
= (((membank_size
>> 2) / profile_nsamples
) - 1);
1660 bsize
= (profile_nsamples
* sizeof(unsigned short));
1661 if (profile_hist
== NULL
)
1662 profile_hist
= (unsigned short *)calloc(64,(bsize
/ 64));
1664 profile_hist
= (unsigned short *)realloc(profile_hist
,bsize
);
1665 if (profile_hist
== NULL
) {
1666 sim_warning("Failed to allocate VM for profiling buffer (0x%08X bytes)",bsize
);
1667 state
&= ~simPROFILE
;
1670 #endif /* PROFILE */
1680 /* Used by "run", and internally, to set the simulated memory size */
1682 callback
->printf_filtered(callback
,"Zero not valid: Memory size still 0x%08X bytes\n",membank_size
);
1685 newsize
= power2(newsize
);
1686 if (membank
== NULL
)
1687 new = (char *)calloc(64,(membank_size
/ 64));
1689 new = (char *)realloc(membank
,newsize
);
1691 if (membank
== NULL
)
1692 sim_error("Not enough VM for simulation memory of 0x%08X bytes",membank_size
);
1694 sim_warning("Failed to resize memory (still 0x%08X bytes)",membank_size
);
1696 membank_size
= (unsigned)newsize
;
1698 #if defined(PROFILE)
1699 /* Ensure that we sample across the new memory range */
1700 sim_set_profile_size(profile_nsamples
);
1701 #endif /* PROFILE */
1711 /* This routine is called by the "run" program, when detailed
1712 execution information is required. Rather than executing a single
1713 instruction, and looping around externally... we just start
1714 simulating, returning TRUE when the simulator stops (for whatever
1718 /* Ensure tracing is enabled, if available */
1719 if (tracefh
== NULL
)
1726 state
&= ~(simSTOP
| simSTEP
); /* execute until event */
1727 state
|= (simHALTEX
| simHALTIN
); /* treat interrupt event as exception */
1728 /* Start executing instructions from the current state (set
1729 explicitly by register updates, or by sim_create_inferior): */
1735 /*---------------------------------------------------------------------------*/
1736 /*-- Private simulator support interface ------------------------------------*/
1737 /*---------------------------------------------------------------------------*/
1739 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1742 unsigned int reason
;
1745 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
1748 /* The IDT monitor actually allows two instructions per vector
1749 slot. However, the simulator currently causes a trap on each
1750 individual instruction. We cheat, and lose the bottom bit. */
1753 /* The following callback functions are available, however the
1754 monitor we are simulating does not make use of them: get_errno,
1755 isatty, lseek, rename, system, time and unlink */
1757 case 6: /* int open(char *path,int flags) */
1761 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1762 V0
= callback
->open(callback
,(char *)((int)paddr
),(int)A1
);
1764 sim_error("Attempt to pass pointer that does not reference simulated memory");
1768 case 7: /* int read(int file,char *ptr,int len) */
1772 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1773 V0
= callback
->read(callback
,(int)A0
,(char *)((int)paddr
),(int)A2
);
1775 sim_error("Attempt to pass pointer that does not reference simulated memory");
1779 case 8: /* int write(int file,char *ptr,int len) */
1783 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1784 V0
= callback
->write(callback
,(int)A0
,(const char *)((int)paddr
),(int)A2
);
1786 sim_error("Attempt to pass pointer that does not reference simulated memory");
1790 case 10: /* int close(int file) */
1791 V0
= callback
->close(callback
,(int)A0
);
1794 case 11: /* char inbyte(void) */
1797 if (callback
->read_stdin(callback
,&tmp
,sizeof(char)) != sizeof(char)) {
1798 sim_error("Invalid return from character read");
1806 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1808 char tmp
= (char)(A0
& 0xFF);
1809 callback
->write_stdout(callback
,&tmp
,sizeof(char));
1813 case 17: /* void _exit() */
1814 sim_warning("sim_monitor(17): _exit(int reason) to be coded");
1815 state
|= (simSTOP
| simEXIT
); /* stop executing code */
1816 rcexit
= (unsigned int)(A0
& 0xFFFFFFFF);
1819 case 28 : /* PMON flush_cache */
1822 case 55: /* void get_mem_info(unsigned int *ptr) */
1823 /* in: A0 = pointer to three word memory location */
1824 /* out: [A0 + 0] = size */
1825 /* [A0 + 4] = instruction cache size */
1826 /* [A0 + 8] = data cache size */
1829 uword64 paddr
, value
;
1833 /* NOTE: We use RAW memory writes here, but since we are not
1834 gathering statistics for the monitor calls we are simulating,
1835 it is not an issue. */
1838 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1839 value
= (uword64
)membank_size
;
1840 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1841 /* We re-do the address translations, in-case the block
1842 overlaps a memory boundary: */
1844 vaddr
+= (AccessLength_WORD
+ 1);
1845 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1846 StoreMemory(cca
,AccessLength_WORD
,0,value
,paddr
,vaddr
,isRAW
);
1847 vaddr
+= (AccessLength_WORD
+ 1);
1848 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
))
1849 StoreMemory(cca
,AccessLength_WORD
,value
,0,paddr
,vaddr
,isRAW
);
1858 sim_error("Invalid pointer passed into monitor call");
1862 case 158 : /* PMON printf */
1863 /* in: A0 = pointer to format string */
1864 /* A1 = optional argument 1 */
1865 /* A2 = optional argument 2 */
1866 /* A3 = optional argument 3 */
1868 /* The following is based on the PMON printf source */
1872 /* This isn't the quickest way, since we call the host print
1873 routine for every character almost. But it does avoid
1874 having to allocate and manage a temporary string buffer. */
1875 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1876 char *s
= (char *)((int)paddr
);
1877 ut_reg
*ap
= &A1
; /* 1st argument */
1878 /* TODO: Include check that we only use three arguments (A1, A2 and A3) */
1882 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1883 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1887 if (strchr ("dobxXulscefg%", *s
))
1895 else if (*s
== '*') {
1900 } else if (*s
>= '1' && *s
<= '9') {
1903 for (t
= s
; isdigit (*s
); s
++);
1904 strncpy (tmp
, t
, s
- t
);
1906 n
= (unsigned int)strtol(tmp
,NULL
,10);
1912 } else if (*s
== '.')
1916 callback
->printf_filtered(callback
,"%%");
1917 } else if (*s
== 's') {
1918 if ((int)*ap
!= 0) {
1919 if (AddressTranslation(*ap
++,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
)) {
1920 char *p
= (char *)((int)paddr
);;
1921 callback
->printf_filtered(callback
,p
);
1924 sim_error("Attempt to pass pointer that does not reference simulated memory");
1928 callback
->printf_filtered(callback
,"(null)");
1929 } else if (*s
== 'c') {
1931 callback
->printf_filtered(callback
,"%c",n
);
1939 if (strchr ("dobxXu", *s
)) {
1940 word64 lv
= (word64
) *ap
++;
1942 callback
->printf_filtered(callback
,"<binary not supported>");
1944 sprintf(tmp
,"%%%s%c",longlong
? "ll" : "",*s
);
1946 callback
->printf_filtered(callback
,tmp
,lv
);
1948 callback
->printf_filtered(callback
,tmp
,(int)lv
);
1950 } else if (strchr ("eEfgG", *s
)) {
1951 #ifdef _MSC_VER /* MSVC version 2.x can't convert from uword64 directly */
1952 double dbl
= (double)((word64
)*ap
++);
1954 double dbl
= (double)*ap
++;
1956 sprintf(tmp
,"%%%d.%d%c",width
,trunc
,*s
);
1957 callback
->printf_filtered(callback
,tmp
,dbl
);
1963 callback
->printf_filtered(callback
,"%c",*s
++);
1966 sim_error("Attempt to pass pointer that does not reference simulated memory");
1971 sim_warning("TODO: sim_monitor(%d) : PC = 0x%s",reason
,pr_addr(IPC
));
1972 sim_warning("(Arguments : A0 = 0x%s : A1 = 0x%s : A2 = 0x%s : A3 = 0x%s)",pr_addr(A0
),pr_addr(A1
),pr_addr(A2
),pr_addr(A3
));
1978 /* Store a word into memory. */
1981 store_word (vaddr
, val
)
1988 if ((vaddr
& 3) != 0)
1989 SignalException (AddressStore
);
1992 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1995 const uword64 mask
= 7;
1999 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
2000 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
2001 memval
= ((uword64
) val
) << (8 * byte
);
2002 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
2008 /* Load a word from memory. */
2014 if ((vaddr
& 3) != 0)
2015 SignalException (AddressLoad
);
2021 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
2024 const uword64 mask
= 0x7;
2025 const unsigned int reverse
= ReverseEndian
? 1 : 0;
2026 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
2030 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
2031 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
2033 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
2034 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
2041 /* Simulate the mips16 entry and exit pseudo-instructions. These
2042 would normally be handled by the reserved instruction exception
2043 code, but for ease of simulation we just handle them directly. */
2049 int aregs
, sregs
, rreg
;
2052 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
2055 aregs
= (insn
& 0x700) >> 8;
2056 sregs
= (insn
& 0x0c0) >> 6;
2057 rreg
= (insn
& 0x020) >> 5;
2059 /* This should be checked by the caller. */
2068 /* This is the entry pseudo-instruction. */
2070 for (i
= 0; i
< aregs
; i
++)
2071 store_word ((uword64
) (SP
+ 4 * i
), registers
[i
+ 4]);
2079 store_word ((uword64
) tsp
, RA
);
2082 for (i
= 0; i
< sregs
; i
++)
2085 store_word ((uword64
) tsp
, registers
[16 + i
]);
2093 /* This is the exit pseudo-instruction. */
2100 RA
= load_word ((uword64
) tsp
);
2103 for (i
= 0; i
< sregs
; i
++)
2106 registers
[i
+ 16] = load_word ((uword64
) tsp
);
2113 FGR
[0] = WORD64LO (GPR
[4]);
2114 fpr_state
[0] = fmt_uninterpreted
;
2116 else if (aregs
== 6)
2118 FGR
[0] = WORD64LO (GPR
[5]);
2119 FGR
[1] = WORD64LO (GPR
[4]);
2120 fpr_state
[0] = fmt_uninterpreted
;
2121 fpr_state
[1] = fmt_uninterpreted
;
2129 sim_warning(char *fmt
,...)
2135 vsprintf (buf
, fmt
, ap
);
2138 if (logfh
!= NULL
) {
2139 fprintf(logfh
,"SIM Warning: %s\n", buf
);
2141 callback
->printf_filtered(callback
,"SIM Warning: %s\n", buf
);
2143 /* This used to call SignalException with a SimulatorFault, but that causes
2144 the simulator to exit, and that is inappropriate for a warning. */
2149 sim_error(char *fmt
,...)
2155 vsprintf (buf
, fmt
, ap
);
2158 callback
->printf_filtered(callback
,"SIM Error: %s", buf
);
2159 SignalException (SimulatorFault
, buf
);
2169 /* Round *UP* to the nearest power-of-2 if not already one */
2170 if (value
!= (value
& ~(value
- 1))) {
2171 for (tmp
= value
, loop
= 0; (tmp
!= 0); loop
++)
2173 value
= (1 << loop
);
2186 num
= strtol(value
,&end
,10);
2188 callback
->printf_filtered(callback
,"Warning: Invalid number \"%s\" ignored, using zero\n",value
);
2190 if (*end
&& ((tolower(*end
) == 'k') || (tolower(*end
) == 'm'))) {
2191 if (tolower(*end
) == 'k')
2198 callback
->printf_filtered(callback
,"Warning: Spurious characters \"%s\" at end of number ignored\n",end
);
2204 /*-- trace support ----------------------------------------------------------*/
2206 /* The TRACE support is provided (if required) in the memory accessing
2207 routines. Since we are also providing the architecture specific
2208 features, the architecture simulation code can also deal with
2209 notifying the TRACE world of cache flushes, etc. Similarly we do
2210 not need to provide profiling support in the simulator engine,
2211 since we can sample in the instruction fetch control loop. By
2212 defining the TRACE manifest, we add tracing as a run-time
2216 /* Tracing by default produces "din" format (as required by
2217 dineroIII). Each line of such a trace file *MUST* have a din label
2218 and address field. The rest of the line is ignored, so comments can
2219 be included if desired. The first field is the label which must be
2220 one of the following values:
2225 3 escape record (treated as unknown access type)
2226 4 escape record (causes cache flush)
2228 The address field is a 32bit (lower-case) hexadecimal address
2229 value. The address should *NOT* be preceded by "0x".
2231 The size of the memory transfer is not important when dealing with
2232 cache lines (as long as no more than a cache line can be
2233 transferred in a single operation :-), however more information
2234 could be given following the dineroIII requirement to allow more
2235 complete memory and cache simulators to provide better
2236 results. i.e. the University of Pisa has a cache simulator that can
2237 also take bus size and speed as (variable) inputs to calculate
2238 complete system performance (a much more useful ability when trying
2239 to construct an end product, rather than a processor). They
2240 currently have an ARM version of their tool called ChARM. */
2244 void dotrace(FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...)
2246 if (state
& simTRACE
) {
2248 fprintf(tracefh
,"%d %s ; width %d ; ",
2252 va_start(ap
,comment
);
2253 vfprintf(tracefh
,comment
,ap
);
2255 fprintf(tracefh
,"\n");
2257 /* NOTE: Since the "din" format will only accept 32bit addresses, and
2258 we may be generating 64bit ones, we should put the hi-32bits of the
2259 address into the comment field. */
2261 /* TODO: Provide a buffer for the trace lines. We can then avoid
2262 performing writes until the buffer is filled, or the file is
2265 /* NOTE: We could consider adding a comment field to the "din" file
2266 produced using type 3 markers (unknown access). This would then
2267 allow information about the program that the "din" is for, and
2268 the MIPs world that was being simulated, to be placed into the
2275 /*---------------------------------------------------------------------------*/
2276 /*-- host<->target transfers ------------------------------------------------*/
2277 /*---------------------------------------------------------------------------*/
2278 /* The following routines allow conditionals to be avoided during the
2279 simulation, at the cost of increasing the image and source size. */
2282 xfer_direct_word(unsigned char *memory
)
2284 return *((unsigned int *)memory
);
2288 xfer_direct_long(unsigned char *memory
)
2290 return *((uword64
*)memory
);
2294 swap_direct_word(unsigned int data
)
2300 swap_direct_long(uword64 data
)
2306 xfer_big_word(unsigned char *memory
)
2308 return ((memory
[0] << 24) | (memory
[1] << 16) | (memory
[2] << 8) | memory
[3]);
2312 xfer_big_long(unsigned char *memory
)
2314 return (((uword64
)memory
[0] << 56) | ((uword64
)memory
[1] << 48)
2315 | ((uword64
)memory
[2] << 40) | ((uword64
)memory
[3] << 32)
2316 | ((uword64
)memory
[4] << 24) | ((uword64
)memory
[5] << 16)
2317 | ((uword64
)memory
[6] << 8) | ((uword64
)memory
[7]));
2321 xfer_little_word(unsigned char *memory
)
2323 return ((memory
[3] << 24) | (memory
[2] << 16) | (memory
[1] << 8) | memory
[0]);
2327 xfer_little_long(unsigned char *memory
)
2329 return (((uword64
)memory
[7] << 56) | ((uword64
)memory
[6] << 48)
2330 | ((uword64
)memory
[5] << 40) | ((uword64
)memory
[4] << 32)
2331 | ((uword64
)memory
[3] << 24) | ((uword64
)memory
[2] << 16)
2332 | ((uword64
)memory
[1] << 8) | (uword64
)memory
[0]);
2336 swap_word(unsigned int data
)
2338 unsigned int result
;
2339 result
= (((data
& 0xff) << 24) | ((data
& 0xff00) << 8)
2340 | ((data
>> 8) & 0xff00) | ((data
>> 24) & 0xff));
2345 swap_long(uword64 data
)
2347 unsigned int tmphi
= WORD64HI(data
);
2348 unsigned int tmplo
= WORD64LO(data
);
2349 tmphi
= swap_word(tmphi
);
2350 tmplo
= swap_word(tmplo
);
2351 /* Now swap the HI and LO parts */
2352 return SET64LO(tmphi
) | SET64HI(tmplo
);
2355 /*---------------------------------------------------------------------------*/
2356 /*-- simulator engine -------------------------------------------------------*/
2357 /*---------------------------------------------------------------------------*/
2362 /* In reality this check should be performed at various points
2363 within the simulation, since it is possible to change the
2364 endianness of user programs. However, we perform the check here
2365 to ensure that the start-of-day values agree. */
2369 /* ??? This is a lot more code than is necessary to solve the problem.
2370 It would be simpler to handle this like the SH simulator. */
2372 host_read_word
= xfer_direct_word
;
2373 host_read_long
= xfer_direct_long
;
2374 host_swap_word
= swap_direct_word
;
2375 host_swap_long
= swap_direct_long
;
2376 } else if (state
& simHOSTBE
) {
2377 host_read_word
= xfer_little_word
;
2378 host_read_long
= xfer_little_long
;
2379 host_swap_word
= swap_word
;
2380 host_swap_long
= swap_long
;
2381 } else { /* HOST little-endian */
2382 host_read_word
= xfer_big_word
;
2383 host_read_long
= xfer_big_long
;
2384 host_swap_word
= swap_word
;
2385 host_swap_long
= swap_long
;
2392 /* RESET: Fixed PC address: */
2393 PC
= (((uword64
)0xFFFFFFFF<<32) | 0xBFC00000);
2394 /* The reset vector address is in the unmapped, uncached memory space. */
2396 SR
&= ~(status_SR
| status_TS
| status_RP
);
2397 SR
|= (status_ERL
| status_BEV
);
2399 #if defined(HASFPU) && (GPRLEN == (64))
2400 /* Cheat and allow access to the complete register set immediately: */
2401 SR
|= status_FR
; /* 64bit registers */
2402 #endif /* HASFPU and 64bit FP registers */
2404 /* Ensure that any instructions with pending register updates are
2408 for (loop
= 0; (loop
< PSLOTS
); loop
++)
2409 pending_slot_reg
[loop
] = (LAST_EMBED_REGNUM
+ 1);
2410 pending_in
= pending_out
= pending_total
= 0;
2414 /* Initialise the FPU registers to the unknown state */
2417 for (rn
= 0; (rn
< 32); rn
++)
2418 fpr_state
[rn
] = fmt_uninterpreted
;
2425 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2426 /* Translate a virtual address to a physical address and cache
2427 coherence algorithm describing the mechanism used to resolve the
2428 memory reference. Given the virtual address vAddr, and whether the
2429 reference is to Instructions ot Data (IorD), find the corresponding
2430 physical address (pAddr) and the cache coherence algorithm (CCA)
2431 used to resolve the reference. If the virtual address is in one of
2432 the unmapped address spaces the physical address and the CCA are
2433 determined directly by the virtual address. If the virtual address
2434 is in one of the mapped address spaces then the TLB is used to
2435 determine the physical address and access type; if the required
2436 translation is not present in the TLB or the desired access is not
2437 permitted the function fails and an exception is taken.
2439 NOTE: This function is extended to return an exception state. This,
2440 along with the exception generation is used to notify whether a
2441 valid address translation occured */
2444 AddressTranslation(vAddr
,IorD
,LorS
,pAddr
,CCA
,host
,raw
)
2453 int res
= -1; /* TRUE : Assume good return */
2456 callback
->printf_filtered(callback
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
2459 /* Check that the address is valid for this memory model */
2461 /* For a simple (flat) memory model, we simply pass virtual
2462 addressess through (mostly) unchanged. */
2463 vAddr
&= 0xFFFFFFFF;
2465 /* Treat the kernel memory spaces identically for the moment: */
2466 if ((membank_base
== K1BASE
) && (vAddr
>= K0BASE
) && (vAddr
< (K0BASE
+ K0SIZE
)))
2467 vAddr
+= (K1BASE
- K0BASE
);
2469 /* Also assume that the K1BASE memory wraps. This is required to
2470 allow the PMON run-time __sizemem() routine to function (without
2471 having to provide exception simulation). NOTE: A kludge to work
2472 around the fact that the monitor memory is currently held in the
2474 if (((vAddr
< monitor_base
) || (vAddr
>= (monitor_base
+ monitor_size
))) && (vAddr
>= K1BASE
&& vAddr
< (K1BASE
+ K1SIZE
)))
2475 vAddr
= (K1BASE
| (vAddr
& (membank_size
- 1)));
2477 *pAddr
= vAddr
; /* default for isTARGET */
2478 *CCA
= Uncached
; /* not used for isHOST */
2480 /* NOTE: This is a duplicate of the code that appears in the
2481 LoadMemory and StoreMemory functions. They should be merged into
2482 a single function (that can be in-lined if required). */
2483 if ((vAddr
>= membank_base
) && (vAddr
< (membank_base
+ membank_size
))) {
2485 *pAddr
= (int)&membank
[((unsigned int)(vAddr
- membank_base
) & (membank_size
- 1))];
2486 } else if ((vAddr
>= monitor_base
) && (vAddr
< (monitor_base
+ monitor_size
))) {
2488 *pAddr
= (int)&monitor
[((unsigned int)(vAddr
- monitor_base
) & (monitor_size
- 1))];
2491 sim_warning("Failed: AddressTranslation(0x%s,%s,%s,...) IPC = 0x%s",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "isSTORE" : "isLOAD"),pr_addr(IPC
));
2493 res
= 0; /* AddressTranslation has failed */
2494 *pAddr
= (SIM_ADDR
)-1;
2495 if (!raw
) /* only generate exceptions on real memory transfers */
2496 SignalException((LorS
== isSTORE
) ? AddressStore
: AddressLoad
);
2499 /* This is a normal occurance during gdb operation, for instance trying
2500 to print parameters at function start before they have been setup,
2501 and hence we should not print a warning except when debugging the
2503 sim_warning("AddressTranslation for %s %s from 0x%s failed",(IorD
? "data" : "instruction"),(LorS
? "store" : "load"),pr_addr(vAddr
));
2510 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2511 /* Prefetch data from memory. Prefetch is an advisory instruction for
2512 which an implementation specific action is taken. The action taken
2513 may increase performance, but must not change the meaning of the
2514 program, or alter architecturally-visible state. */
2516 Prefetch(CCA
,pAddr
,vAddr
,DATA
,hint
)
2524 callback
->printf_filtered(callback
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
2527 /* For our simple memory model we do nothing */
2531 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2532 /* Load a value from memory. Use the cache and main memory as
2533 specified in the Cache Coherence Algorithm (CCA) and the sort of
2534 access (IorD) to find the contents of AccessLength memory bytes
2535 starting at physical location pAddr. The data is returned in the
2536 fixed width naturally-aligned memory element (MemElem). The
2537 low-order two (or three) bits of the address and the AccessLength
2538 indicate which of the bytes within MemElem needs to be given to the
2539 processor. If the memory access type of the reference is uncached
2540 then only the referenced bytes are read from memory and valid
2541 within the memory element. If the access type is cached, and the
2542 data is not present in cache, an implementation specific size and
2543 alignment block of memory is read and loaded into the cache to
2544 satisfy a load reference. At a minimum, the block is the entire
2547 LoadMemory(memvalp
,memval1p
,CCA
,AccessLength
,pAddr
,vAddr
,IorD
,raw
)
2561 if (membank
== NULL
)
2562 callback
->printf_filtered(callback
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(raw
? "isRAW" : "isREAL"));
2565 #if defined(WARN_MEM)
2566 if (CCA
!= uncached
)
2567 sim_warning("LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA
);
2569 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
) {
2570 /* In reality this should be a Bus Error */
2571 sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
2573 #endif /* WARN_MEM */
2575 /* Decide which physical memory locations are being dealt with. At
2576 this point we should be able to split the pAddr bits into the
2577 relevant address map being simulated. If the "raw" variable is
2578 set, the memory read being performed should *NOT* update any I/O
2579 state or affect the CPU state. This also includes avoiding
2580 affecting statistics gathering. */
2582 /* If instruction fetch then we need to check that the two lo-order
2583 bits are zero, otherwise raise a InstructionFetch exception: */
2584 if ((IorD
== isINSTRUCTION
)
2585 && ((pAddr
& 0x3) != 0)
2586 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
2587 SignalException(InstructionFetch
);
2590 unsigned char *mem
= NULL
;
2594 dotrace(tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
2597 /* NOTE: Quicker methods of decoding the address space can be used
2598 when a real memory map is being simulated (i.e. using hi-order
2599 address bits to select device). */
2600 if ((pAddr
>= membank_base
) && (pAddr
< (membank_base
+ membank_size
))) {
2601 index
= ((unsigned int)(pAddr
- membank_base
) & (membank_size
- 1));
2603 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
2604 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
2608 sim_error("Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
2610 /* If we obtained the endianness of the host, and it is the same
2611 as the target memory system we can optimise the memory
2612 accesses. However, without that information we must perform
2613 slow transfer, and hope that the compiler optimisation will
2614 merge successive loads. */
2615 value
= 0; /* no data loaded yet */
2618 /* In reality we should always be loading a doubleword value (or
2619 word value in 32bit memory worlds). The external code then
2620 extracts the required bytes. However, to keep performance
2621 high we only load the required bytes into the relevant
2624 switch (AccessLength
) { /* big-endian memory */
2625 case AccessLength_QUADWORD
:
2626 value1
|= ((uword64
)mem
[index
++] << 56);
2627 case 14: /* AccessLength is one less than datalen */
2628 value1
|= ((uword64
)mem
[index
++] << 48);
2630 value1
|= ((uword64
)mem
[index
++] << 40);
2632 value1
|= ((uword64
)mem
[index
++] << 32);
2634 value1
|= ((unsigned int)mem
[index
++] << 24);
2636 value1
|= ((unsigned int)mem
[index
++] << 16);
2638 value1
|= ((unsigned int)mem
[index
++] << 8);
2640 value1
|= mem
[index
];
2642 case AccessLength_DOUBLEWORD
:
2643 value
|= ((uword64
)mem
[index
++] << 56);
2644 case AccessLength_SEPTIBYTE
:
2645 value
|= ((uword64
)mem
[index
++] << 48);
2646 case AccessLength_SEXTIBYTE
:
2647 value
|= ((uword64
)mem
[index
++] << 40);
2648 case AccessLength_QUINTIBYTE
:
2649 value
|= ((uword64
)mem
[index
++] << 32);
2650 case AccessLength_WORD
:
2651 value
|= ((unsigned int)mem
[index
++] << 24);
2652 case AccessLength_TRIPLEBYTE
:
2653 value
|= ((unsigned int)mem
[index
++] << 16);
2654 case AccessLength_HALFWORD
:
2655 value
|= ((unsigned int)mem
[index
++] << 8);
2656 case AccessLength_BYTE
:
2657 value
|= mem
[index
];
2661 index
+= (AccessLength
+ 1);
2662 switch (AccessLength
) { /* little-endian memory */
2663 case AccessLength_QUADWORD
:
2664 value1
|= ((uword64
)mem
[--index
] << 56);
2665 case 14: /* AccessLength is one less than datalen */
2666 value1
|= ((uword64
)mem
[--index
] << 48);
2668 value1
|= ((uword64
)mem
[--index
] << 40);
2670 value1
|= ((uword64
)mem
[--index
] << 32);
2672 value1
|= ((uword64
)mem
[--index
] << 24);
2674 value1
|= ((uword64
)mem
[--index
] << 16);
2676 value1
|= ((uword64
)mem
[--index
] << 8);
2678 value1
|= ((uword64
)mem
[--index
] << 0);
2680 case AccessLength_DOUBLEWORD
:
2681 value
|= ((uword64
)mem
[--index
] << 56);
2682 case AccessLength_SEPTIBYTE
:
2683 value
|= ((uword64
)mem
[--index
] << 48);
2684 case AccessLength_SEXTIBYTE
:
2685 value
|= ((uword64
)mem
[--index
] << 40);
2686 case AccessLength_QUINTIBYTE
:
2687 value
|= ((uword64
)mem
[--index
] << 32);
2688 case AccessLength_WORD
:
2689 value
|= ((uword64
)mem
[--index
] << 24);
2690 case AccessLength_TRIPLEBYTE
:
2691 value
|= ((uword64
)mem
[--index
] << 16);
2692 case AccessLength_HALFWORD
:
2693 value
|= ((uword64
)mem
[--index
] << 8);
2694 case AccessLength_BYTE
:
2695 value
|= ((uword64
)mem
[--index
] << 0);
2701 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
2702 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
2705 /* TODO: We could try and avoid the shifts when dealing with raw
2706 memory accesses. This would mean updating the LoadMemory and
2707 StoreMemory routines to avoid shifting the data before
2708 returning or using it. */
2709 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
2710 if (!raw
) { /* do nothing for raw accessess */
2712 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
2713 else /* little-endian only needs to be shifted up to the correct byte offset */
2714 value
<<= ((pAddr
& LOADDRMASK
) * 8);
2719 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
2720 pr_uword64(value1
),pr_uword64(value
));
2726 if (memval1p
) *memval1p
= value1
;
2730 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2731 /* Store a value to memory. The specified data is stored into the
2732 physical location pAddr using the memory hierarchy (data caches and
2733 main memory) as specified by the Cache Coherence Algorithm
2734 (CCA). The MemElem contains the data for an aligned, fixed-width
2735 memory element (word for 32-bit processors, doubleword for 64-bit
2736 processors), though only the bytes that will actually be stored to
2737 memory need to be valid. The low-order two (or three) bits of pAddr
2738 and the AccessLength field indicates which of the bytes within the
2739 MemElem data should actually be stored; only these bytes in memory
2743 StoreMemory(CCA
,AccessLength
,MemElem
,MemElem1
,pAddr
,vAddr
,raw
)
2747 uword64 MemElem1
; /* High order 64 bits */
2753 callback
->printf_filtered(callback
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s,%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
),(raw
? "isRAW" : "isREAL"));
2756 #if defined(WARN_MEM)
2757 if (CCA
!= uncached
)
2758 sim_warning("StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)",CCA
);
2760 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
2761 sim_error("AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
2762 #endif /* WARN_MEM */
2766 dotrace(tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
2769 /* See the comments in the LoadMemory routine about optimising
2770 memory accesses. Also if we wanted to make the simulator smaller,
2771 we could merge a lot of this code with the LoadMemory
2772 routine. However, this would slow the simulator down with
2773 run-time conditionals. */
2776 unsigned char *mem
= NULL
;
2778 if ((pAddr
>= membank_base
) && (pAddr
< (membank_base
+ membank_size
))) {
2779 index
= ((unsigned int)(pAddr
- membank_base
) & (membank_size
- 1));
2781 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
2782 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
2787 sim_error("Simulator memory not found for physical address 0x%s\n",pr_addr(pAddr
));
2792 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
2795 if (AccessLength
<= AccessLength_DOUBLEWORD
) {
2798 shift
= ((7 - AccessLength
) * 8);
2799 else /* real memory access */
2800 shift
= ((pAddr
& LOADDRMASK
) * 8);
2803 /* no need to shift raw little-endian data */
2805 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
2810 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
2814 switch (AccessLength
) { /* big-endian memory */
2815 case AccessLength_QUADWORD
:
2816 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2819 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2822 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2825 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2828 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2831 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2834 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2837 mem
[index
++] = (unsigned char)(MemElem1
>> 56);
2839 case AccessLength_DOUBLEWORD
:
2840 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2842 case AccessLength_SEPTIBYTE
:
2843 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2845 case AccessLength_SEXTIBYTE
:
2846 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2848 case AccessLength_QUINTIBYTE
:
2849 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2851 case AccessLength_WORD
:
2852 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2854 case AccessLength_TRIPLEBYTE
:
2855 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2857 case AccessLength_HALFWORD
:
2858 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2860 case AccessLength_BYTE
:
2861 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2865 index
+= (AccessLength
+ 1);
2866 switch (AccessLength
) { /* little-endian memory */
2867 case AccessLength_QUADWORD
:
2868 mem
[--index
] = (unsigned char)(MemElem1
>> 56);
2870 mem
[--index
] = (unsigned char)(MemElem1
>> 48);
2872 mem
[--index
] = (unsigned char)(MemElem1
>> 40);
2874 mem
[--index
] = (unsigned char)(MemElem1
>> 32);
2876 mem
[--index
] = (unsigned char)(MemElem1
>> 24);
2878 mem
[--index
] = (unsigned char)(MemElem1
>> 16);
2880 mem
[--index
] = (unsigned char)(MemElem1
>> 8);
2882 mem
[--index
] = (unsigned char)(MemElem1
>> 0);
2884 case AccessLength_DOUBLEWORD
:
2885 mem
[--index
] = (unsigned char)(MemElem
>> 56);
2886 case AccessLength_SEPTIBYTE
:
2887 mem
[--index
] = (unsigned char)(MemElem
>> 48);
2888 case AccessLength_SEXTIBYTE
:
2889 mem
[--index
] = (unsigned char)(MemElem
>> 40);
2890 case AccessLength_QUINTIBYTE
:
2891 mem
[--index
] = (unsigned char)(MemElem
>> 32);
2892 case AccessLength_WORD
:
2893 mem
[--index
] = (unsigned char)(MemElem
>> 24);
2894 case AccessLength_TRIPLEBYTE
:
2895 mem
[--index
] = (unsigned char)(MemElem
>> 16);
2896 case AccessLength_HALFWORD
:
2897 mem
[--index
] = (unsigned char)(MemElem
>> 8);
2898 case AccessLength_BYTE
:
2899 mem
[--index
] = (unsigned char)(MemElem
>> 0);
2910 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2911 /* Order loads and stores to synchronise shared memory. Perform the
2912 action necessary to make the effects of groups of synchronizable
2913 loads and stores indicated by stype occur in the same order for all
2916 SyncOperation(stype
)
2920 callback
->printf_filtered(callback
,"SyncOperation(%d) : TODO\n",stype
);
2925 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2926 /* Signal an exception condition. This will result in an exception
2927 that aborts the instruction. The instruction operation pseudocode
2928 will never see a return from this function call. */
2930 SignalException (int exception
,...)
2932 /* Ensure that any active atomic read/modify/write operation will fail: */
2935 switch (exception
) {
2936 /* TODO: For testing purposes I have been ignoring TRAPs. In
2937 reality we should either simulate them, or allow the user to
2938 ignore them at run-time. */
2940 sim_warning("Ignoring instruction TRAP (PC 0x%s)",pr_addr(IPC
));
2943 case ReservedInstruction
:
2946 unsigned int instruction
;
2947 va_start(ap
,exception
);
2948 instruction
= va_arg(ap
,unsigned int);
2950 /* Provide simple monitor support using ReservedInstruction
2951 exceptions. The following code simulates the fixed vector
2952 entry points into the IDT monitor by causing a simulator
2953 trap, performing the monitor operation, and returning to
2954 the address held in the $ra register (standard PCS return
2955 address). This means we only need to pre-load the vector
2956 space with suitable instruction values. For systems were
2957 actual trap instructions are used, we would not need to
2958 perform this magic. */
2959 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
) {
2960 sim_monitor( ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
2961 PC
= RA
; /* simulate the return from the vector entry */
2962 /* NOTE: This assumes that a branch-and-link style
2963 instruction was used to enter the vector (which is the
2964 case with the current IDT monitor). */
2965 break; /* out of the switch statement */
2967 /* Look for the mips16 entry and exit instructions, and
2968 simulate a handler for them. */
2969 else if ((IPC
& 1) != 0
2970 && (instruction
& 0xf81f) == 0xe809
2971 && (instruction
& 0x0c0) != 0x0c0) {
2972 mips16_entry (instruction
);
2974 } /* else fall through to normal exception processing */
2975 sim_warning("ReservedInstruction 0x%08X at IPC = 0x%s",instruction
,pr_addr(IPC
));
2980 if (exception
!= BreakPoint
)
2981 callback
->printf_filtered(callback
,"DBG: SignalException(%d) IPC = 0x%s\n",exception
,pr_addr(IPC
));
2983 /* Store exception code into current exception id variable (used
2986 /* TODO: If not simulating exceptions then stop the simulator
2987 execution. At the moment we always stop the simulation. */
2988 state
|= (simSTOP
| simEXCEPTION
);
2990 /* Keep a copy of the current A0 in-case this is the program exit
2992 if (exception
== BreakPoint
) {
2994 unsigned int instruction
;
2995 va_start(ap
,exception
);
2996 instruction
= va_arg(ap
,unsigned int);
2998 /* Check for our special terminating BREAK: */
2999 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
3000 rcexit
= (unsigned int)(A0
& 0xFFFFFFFF);
3001 state
&= ~simEXCEPTION
;
3006 /* Store exception code into current exception id variable (used
3008 CAUSE
= (exception
<< 2);
3009 if (state
& simDELAYSLOT
) {
3011 EPC
= (IPC
- 4); /* reference the branch instruction */
3014 /* The following is so that the simulator will continue from the
3015 exception address on breakpoint operations. */
3019 case SimulatorFault
:
3023 va_start(ap
,exception
);
3024 msg
= va_arg(ap
,char *);
3025 fprintf(stderr
,"FATAL: Simulator error \"%s\"\n",msg
);
3034 #if defined(WARN_RESULT)
3035 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
3036 /* This function indicates that the result of the operation is
3037 undefined. However, this should not affect the instruction
3038 stream. All that is meant to happen is that the destination
3039 register is set to an undefined result. To keep the simulator
3040 simple, we just don't bother updating the destination register, so
3041 the overall result will be undefined. If desired we can stop the
3042 simulator by raising a pseudo-exception. */
3046 sim_warning("UndefinedResult: IPC = 0x%s",pr_addr(IPC
));
3047 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
3052 #endif /* WARN_RESULT */
3055 CacheOp(op
,pAddr
,vAddr
,instruction
)
3059 unsigned int instruction
;
3061 #if 1 /* stop warning message being displayed (we should really just remove the code) */
3062 static int icache_warning
= 1;
3063 static int dcache_warning
= 1;
3065 static int icache_warning
= 0;
3066 static int dcache_warning
= 0;
3069 /* If CP0 is not useable (User or Supervisor mode) and the CP0
3070 enable bit in the Status Register is clear - a coprocessor
3071 unusable exception is taken. */
3073 callback
->printf_filtered(callback
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(IPC
));
3077 case 0: /* instruction cache */
3079 case 0: /* Index Invalidate */
3080 case 1: /* Index Load Tag */
3081 case 2: /* Index Store Tag */
3082 case 4: /* Hit Invalidate */
3084 case 6: /* Hit Writeback */
3085 if (!icache_warning
)
3087 sim_warning("Instruction CACHE operation %d to be coded",(op
>> 2));
3093 SignalException(ReservedInstruction
,instruction
);
3098 case 1: /* data cache */
3100 case 0: /* Index Writeback Invalidate */
3101 case 1: /* Index Load Tag */
3102 case 2: /* Index Store Tag */
3103 case 3: /* Create Dirty */
3104 case 4: /* Hit Invalidate */
3105 case 5: /* Hit Writeback Invalidate */
3106 case 6: /* Hit Writeback */
3107 if (!dcache_warning
)
3109 sim_warning("Data CACHE operation %d to be coded",(op
>> 2));
3115 SignalException(ReservedInstruction
,instruction
);
3120 default: /* unrecognised cache ID */
3121 SignalException(ReservedInstruction
,instruction
);
3128 /*-- FPU support routines ---------------------------------------------------*/
3130 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
3133 #define SizeFGR() (GPRLEN)
3135 /* They depend on the CPU being simulated */
3136 #define SizeFGR() ((PROCESSOR_64BIT && ((SR & status_FR) == 1)) ? 64 : 32)
3139 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
3140 formats conform to ANSI/IEEE Std 754-1985. */
3141 /* SINGLE precision floating:
3142 * seeeeeeeefffffffffffffffffffffff
3144 * e = 8bits = exponent
3145 * f = 23bits = fraction
3147 /* SINGLE precision fixed:
3148 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
3150 * i = 31bits = integer
3152 /* DOUBLE precision floating:
3153 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
3155 * e = 11bits = exponent
3156 * f = 52bits = fraction
3158 /* DOUBLE precision fixed:
3159 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
3161 * i = 63bits = integer
3164 /* Extract sign-bit: */
3165 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
3166 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
3167 /* Extract biased exponent: */
3168 #define FP_S_be(v) (((v) >> 23) & 0xFF)
3169 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
3170 /* Extract unbiased Exponent: */
3171 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
3172 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
3173 /* Extract complete fraction field: */
3174 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
3175 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
3176 /* Extract numbered fraction bit: */
3177 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
3178 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
3180 /* Explicit QNaN values used when value required: */
3181 #define FPQNaN_SINGLE (0x7FBFFFFF)
3182 #define FPQNaN_WORD (0x7FFFFFFF)
3183 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
3184 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
3186 /* Explicit Infinity values used when required: */
3187 #define FPINF_SINGLE (0x7F800000)
3188 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
3190 #if 1 /* def DEBUG */
3191 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
3192 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
3203 /* Treat unused register values, as fixed-point 64bit values: */
3204 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
3206 /* If request to read data as "uninterpreted", then use the current
3208 fmt
= fpr_state
[fpr
];
3213 /* For values not yet accessed, set to the desired format: */
3214 if (fpr_state
[fpr
] == fmt_uninterpreted
) {
3215 fpr_state
[fpr
] = fmt
;
3217 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
3220 if (fmt
!= fpr_state
[fpr
]) {
3221 sim_warning("FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)",fpr
,DOFMT(fpr_state
[fpr
]),DOFMT(fmt
),pr_addr(IPC
));
3222 fpr_state
[fpr
] = fmt_unknown
;
3225 if (fpr_state
[fpr
] == fmt_unknown
) {
3226 /* Set QNaN value: */
3229 value
= FPQNaN_SINGLE
;
3233 value
= FPQNaN_DOUBLE
;
3237 value
= FPQNaN_WORD
;
3241 value
= FPQNaN_LONG
;
3248 } else if (SizeFGR() == 64) {
3252 value
= (FGR
[fpr
] & 0xFFFFFFFF);
3255 case fmt_uninterpreted
:
3269 value
= (FGR
[fpr
] & 0xFFFFFFFF);
3272 case fmt_uninterpreted
:
3275 if ((fpr
& 1) == 0) { /* even registers only */
3276 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
3278 SignalException (ReservedInstruction
, 0);
3289 SignalException(SimulatorFault
,"Unrecognised FP format in ValueFPR()");
3292 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
3299 StoreFPR(fpr
,fmt
,value
)
3307 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(IPC
),SizeFGR());
3310 if (SizeFGR() == 64) {
3314 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
3315 fpr_state
[fpr
] = fmt
;
3318 case fmt_uninterpreted
:
3322 fpr_state
[fpr
] = fmt
;
3326 fpr_state
[fpr
] = fmt_unknown
;
3334 FGR
[fpr
] = (value
& 0xFFFFFFFF);
3335 fpr_state
[fpr
] = fmt
;
3338 case fmt_uninterpreted
:
3341 if ((fpr
& 1) == 0) { /* even register number only */
3342 FGR
[fpr
+1] = (value
>> 32);
3343 FGR
[fpr
] = (value
& 0xFFFFFFFF);
3344 fpr_state
[fpr
+ 1] = fmt
;
3345 fpr_state
[fpr
] = fmt
;
3347 fpr_state
[fpr
] = fmt_unknown
;
3348 fpr_state
[fpr
+ 1] = fmt_unknown
;
3349 SignalException (ReservedInstruction
, 0);
3354 fpr_state
[fpr
] = fmt_unknown
;
3359 #if defined(WARN_RESULT)
3362 #endif /* WARN_RESULT */
3365 SignalException(SimulatorFault
,"Unrecognised FP format in StoreFPR()");
3368 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
3381 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
3382 know that the exponent field is biased... we we cheat and avoid
3383 removing the bias value. */
3386 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) != 0));
3387 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
3388 dealing with a SNaN or QNaN */
3391 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) != 0));
3392 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
3393 dealing with a SNaN or QNaN */
3396 boolean
= (op
== FPQNaN_WORD
);
3399 boolean
= (op
== FPQNaN_LONG
);
3404 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
3418 printf("DBG: Infinity: format %s 0x%s (PC = 0x%s)\n",DOFMT(fmt
),pr_addr(op
),pr_addr(IPC
));
3421 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
3422 know that the exponent field is biased... we we cheat and avoid
3423 removing the bias value. */
3426 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) == 0));
3429 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) == 0));
3432 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
3437 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
3451 /* Argument checking already performed by the FPCOMPARE code */
3454 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3457 /* The format type should already have been checked: */
3461 unsigned int wop1
= (unsigned int)op1
;
3462 unsigned int wop2
= (unsigned int)op2
;
3463 boolean
= (*(float *)&wop1
< *(float *)&wop2
);
3467 boolean
= (*(double *)&op1
< *(double *)&op2
);
3472 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
3486 /* Argument checking already performed by the FPCOMPARE code */
3489 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3492 /* The format type should already have been checked: */
3495 boolean
= ((op1
& 0xFFFFFFFF) == (op2
& 0xFFFFFFFF));
3498 boolean
= (op1
== op2
);
3503 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
3510 AbsoluteValue(op
,fmt
)
3517 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3520 /* The format type should already have been checked: */
3524 unsigned int wop
= (unsigned int)op
;
3525 float tmp
= ((float)fabs((double)*(float *)&wop
));
3526 result
= (uword64
)*(unsigned int *)&tmp
;
3531 double tmp
= (fabs(*(double *)&op
));
3532 result
= *(uword64
*)&tmp
;
3547 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3550 /* The format type should already have been checked: */
3554 unsigned int wop
= (unsigned int)op
;
3555 float tmp
= ((float)0.0 - *(float *)&wop
);
3556 result
= (uword64
)*(unsigned int *)&tmp
;
3561 double tmp
= ((double)0.0 - *(double *)&op
);
3562 result
= *(uword64
*)&tmp
;
3579 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3582 /* The registers must specify FPRs valid for operands of type
3583 "fmt". If they are not valid, the result is undefined. */
3585 /* The format type should already have been checked: */
3589 unsigned int wop1
= (unsigned int)op1
;
3590 unsigned int wop2
= (unsigned int)op2
;
3591 float tmp
= (*(float *)&wop1
+ *(float *)&wop2
);
3592 result
= (uword64
)*(unsigned int *)&tmp
;
3597 double tmp
= (*(double *)&op1
+ *(double *)&op2
);
3598 result
= *(uword64
*)&tmp
;
3604 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3619 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3622 /* The registers must specify FPRs valid for operands of type
3623 "fmt". If they are not valid, the result is undefined. */
3625 /* The format type should already have been checked: */
3629 unsigned int wop1
= (unsigned int)op1
;
3630 unsigned int wop2
= (unsigned int)op2
;
3631 float tmp
= (*(float *)&wop1
- *(float *)&wop2
);
3632 result
= (uword64
)*(unsigned int *)&tmp
;
3637 double tmp
= (*(double *)&op1
- *(double *)&op2
);
3638 result
= *(uword64
*)&tmp
;
3644 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3651 Multiply(op1
,op2
,fmt
)
3659 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3662 /* The registers must specify FPRs valid for operands of type
3663 "fmt". If they are not valid, the result is undefined. */
3665 /* The format type should already have been checked: */
3669 unsigned int wop1
= (unsigned int)op1
;
3670 unsigned int wop2
= (unsigned int)op2
;
3671 float tmp
= (*(float *)&wop1
* *(float *)&wop2
);
3672 result
= (uword64
)*(unsigned int *)&tmp
;
3677 double tmp
= (*(double *)&op1
* *(double *)&op2
);
3678 result
= *(uword64
*)&tmp
;
3684 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3699 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3702 /* The registers must specify FPRs valid for operands of type
3703 "fmt". If they are not valid, the result is undefined. */
3705 /* The format type should already have been checked: */
3709 unsigned int wop1
= (unsigned int)op1
;
3710 unsigned int wop2
= (unsigned int)op2
;
3711 float tmp
= (*(float *)&wop1
/ *(float *)&wop2
);
3712 result
= (uword64
)*(unsigned int *)&tmp
;
3717 double tmp
= (*(double *)&op1
/ *(double *)&op2
);
3718 result
= *(uword64
*)&tmp
;
3724 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3738 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3741 /* The registers must specify FPRs valid for operands of type
3742 "fmt". If they are not valid, the result is undefined. */
3744 /* The format type should already have been checked: */
3748 unsigned int wop
= (unsigned int)op
;
3749 float tmp
= ((float)1.0 / *(float *)&wop
);
3750 result
= (uword64
)*(unsigned int *)&tmp
;
3755 double tmp
= ((double)1.0 / *(double *)&op
);
3756 result
= *(uword64
*)&tmp
;
3762 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3776 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
3779 /* The registers must specify FPRs valid for operands of type
3780 "fmt". If they are not valid, the result is undefined. */
3782 /* The format type should already have been checked: */
3786 unsigned int wop
= (unsigned int)op
;
3788 float tmp
= ((float)sqrt((double)*(float *)&wop
));
3789 result
= (uword64
)*(unsigned int *)&tmp
;
3791 /* TODO: Provide square-root */
3792 result
= (uword64
)0;
3799 double tmp
= (sqrt(*(double *)&op
));
3800 result
= *(uword64
*)&tmp
;
3802 /* TODO: Provide square-root */
3803 result
= (uword64
)0;
3810 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3817 Convert(rm
,op
,from
,to
)
3826 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3829 /* The value "op" is converted to the destination format, rounding
3830 using mode "rm". When the destination is a fixed-point format,
3831 then a source value of Infinity, NaN or one which would round to
3832 an integer outside the fixed point range then an IEEE Invalid
3833 Operation condition is raised. */
3840 tmp
= (float)(*(double *)&op
);
3844 tmp
= (float)((int)(op
& 0xFFFFFFFF));
3848 tmp
= (float)((word64
)op
);
3853 /* FIXME: This code is incorrect. The rounding mode does not
3854 round to integral values; it rounds to the nearest
3855 representable value in the format. */
3859 /* Round result to nearest representable value. When two
3860 representable values are equally near, round to the value
3861 that has a least significant bit of zero (i.e. is even). */
3863 tmp
= (float)anint((double)tmp
);
3865 /* TODO: Provide round-to-nearest */
3870 /* Round result to the value closest to, and not greater in
3871 magnitude than, the result. */
3873 tmp
= (float)aint((double)tmp
);
3875 /* TODO: Provide round-to-zero */
3880 /* Round result to the value closest to, and not less than,
3882 tmp
= (float)ceil((double)tmp
);
3886 /* Round result to the value closest to, and not greater than,
3888 tmp
= (float)floor((double)tmp
);
3893 result
= (uword64
)*(unsigned int *)&tmp
;
3905 unsigned int wop
= (unsigned int)op
;
3906 tmp
= (double)(*(float *)&wop
);
3911 xxx
= SIGNEXTEND((op
& 0xFFFFFFFF),32);
3916 tmp
= (double)((word64
)op
);
3921 /* FIXME: This code is incorrect. The rounding mode does not
3922 round to integral values; it rounds to the nearest
3923 representable value in the format. */
3928 tmp
= anint(*(double *)&tmp
);
3930 /* TODO: Provide round-to-nearest */
3936 tmp
= aint(*(double *)&tmp
);
3938 /* TODO: Provide round-to-zero */
3943 tmp
= ceil(*(double *)&tmp
);
3947 tmp
= floor(*(double *)&tmp
);
3952 result
= *(uword64
*)&tmp
;
3958 if (Infinity(op
,from
) || NaN(op
,from
) || (1 == 0/*TODO: check range */)) {
3959 printf("DBG: TODO: update FCSR\n");
3960 SignalException(FPE
);
3962 if (to
== fmt_word
) {
3967 unsigned int wop
= (unsigned int)op
;
3968 tmp
= (int)*((float *)&wop
);
3972 tmp
= (int)*((double *)&op
);
3974 printf("DBG: from double %.30f (0x%s) to word: 0x%08X\n",*((double *)&op
),pr_addr(op
),tmp
);
3978 result
= (uword64
)tmp
;
3979 } else { /* fmt_long */
3984 unsigned int wop
= (unsigned int)op
;
3985 tmp
= (word64
)*((float *)&wop
);
3989 tmp
= (word64
)*((double *)&op
);
3992 result
= (uword64
)tmp
;
3999 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result
),DOFMT(to
));
4006 /*-- co-processor support routines ------------------------------------------*/
4009 CoProcPresent(coproc_number
)
4010 unsigned int coproc_number
;
4012 /* Return TRUE if simulator provides a model for the given co-processor number */
4017 COP_LW(coproc_num
,coproc_reg
,memword
)
4018 int coproc_num
, coproc_reg
;
4019 unsigned int memword
;
4021 switch (coproc_num
) {
4025 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
4027 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
4028 fpr_state
[coproc_reg
] = fmt_uninterpreted
;
4033 #if 0 /* this should be controlled by a configuration option */
4034 callback
->printf_filtered(callback
,"COP_LW(%d,%d,0x%08X) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(IPC
));
4043 COP_LD(coproc_num
,coproc_reg
,memword
)
4044 int coproc_num
, coproc_reg
;
4047 switch (coproc_num
) {
4050 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
4055 #if 0 /* this message should be controlled by a configuration option */
4056 callback
->printf_filtered(callback
,"COP_LD(%d,%d,0x%s) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(IPC
));
4065 COP_SW(coproc_num
,coproc_reg
)
4066 int coproc_num
, coproc_reg
;
4068 unsigned int value
= 0;
4071 switch (coproc_num
) {
4075 hold
= fpr_state
[coproc_reg
];
4076 fpr_state
[coproc_reg
] = fmt_word
;
4077 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
4078 fpr_state
[coproc_reg
] = hold
;
4081 value
= (unsigned int)ValueFPR(coproc_reg
,fpr_state
[coproc_reg
]);
4084 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(fpr_state
[coproc_reg
]));
4086 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
4093 #if 0 /* should be controlled by configuration option */
4094 callback
->printf_filtered(callback
,"COP_SW(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
4103 COP_SD(coproc_num
,coproc_reg
)
4104 int coproc_num
, coproc_reg
;
4107 switch (coproc_num
) {
4111 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
4114 value
= ValueFPR(coproc_reg
,fpr_state
[coproc_reg
]);
4117 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(fpr_state
[coproc_reg
]));
4119 value
= ValueFPR(coproc_reg
,fmt_double
);
4126 #if 0 /* should be controlled by configuration option */
4127 callback
->printf_filtered(callback
,"COP_SD(%d,%d) at IPC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(IPC
));
4136 decode_coproc(instruction
)
4137 unsigned int instruction
;
4139 int coprocnum
= ((instruction
>> 26) & 3);
4141 switch (coprocnum
) {
4142 case 0: /* standard CPU control and cache registers */
4145 Standard CP0 registers
4146 0 = Index R4000 VR4100 VR4300
4147 1 = Random R4000 VR4100 VR4300
4148 2 = EntryLo0 R4000 VR4100 VR4300
4149 3 = EntryLo1 R4000 VR4100 VR4300
4150 4 = Context R4000 VR4100 VR4300
4151 5 = PageMask R4000 VR4100 VR4300
4152 6 = Wired R4000 VR4100 VR4300
4153 8 = BadVAddr R4000 VR4100 VR4300
4154 9 = Count R4000 VR4100 VR4300
4155 10 = EntryHi R4000 VR4100 VR4300
4156 11 = Compare R4000 VR4100 VR4300
4157 12 = SR R4000 VR4100 VR4300
4158 13 = Cause R4000 VR4100 VR4300
4159 14 = EPC R4000 VR4100 VR4300
4160 15 = PRId R4000 VR4100 VR4300
4161 16 = Config R4000 VR4100 VR4300
4162 17 = LLAddr R4000 VR4100 VR4300
4163 18 = WatchLo R4000 VR4100 VR4300
4164 19 = WatchHi R4000 VR4100 VR4300
4165 20 = XContext R4000 VR4100 VR4300
4166 26 = PErr or ECC R4000 VR4100 VR4300
4167 27 = CacheErr R4000 VR4100
4168 28 = TagLo R4000 VR4100 VR4300
4169 29 = TagHi R4000 VR4100 VR4300
4170 30 = ErrorEPC R4000 VR4100 VR4300
4172 int code
= ((instruction
>> 21) & 0x1F);
4173 /* R4000 Users Manual (second edition) lists the following CP0
4175 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
4176 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
4177 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
4178 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
4179 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
4180 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
4181 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
4182 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
4183 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
4184 ERET Exception return (VR4100 = 01000010000000000000000000011000)
4186 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0)) {
4187 int rt
= ((instruction
>> 16) & 0x1F);
4188 int rd
= ((instruction
>> 11) & 0x1F);
4189 if (code
== 0x00) { /* MF : move from */
4190 #if 0 /* message should be controlled by configuration option */
4191 callback
->printf_filtered(callback
,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt
,rd
);
4193 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
4194 } else { /* MT : move to */
4195 /* CPR[0,rd] = GPR[rt]; */
4196 #if 0 /* should be controlled by configuration option */
4197 callback
->printf_filtered(callback
,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt
,rd
);
4201 sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present",instruction
,pr_addr(IPC
));
4202 /* TODO: When executing an ERET or RFE instruction we should
4203 clear LLBIT, to ensure that any out-standing atomic
4204 read/modify/write sequence fails. */
4208 case 2: /* undefined co-processor */
4209 sim_warning("COP2 instruction 0x%08X at IPC = 0x%s : No handler present",instruction
,pr_addr(IPC
));
4212 case 1: /* should not occur (FPU co-processor) */
4213 case 3: /* should not occur (FPU co-processor) */
4214 SignalException(ReservedInstruction
,instruction
);
4221 /*-- instruction simulation -------------------------------------------------*/
4226 unsigned int pipeline_count
= 1;
4229 if (membank
== NULL
) {
4230 printf("DBG: simulate() entered with no memory\n");
4235 #if 0 /* Disabled to check that everything works OK */
4236 /* The VR4300 seems to sign-extend the PC on its first
4237 access. However, this may just be because it is currently
4238 configured in 32bit mode. However... */
4239 PC
= SIGNEXTEND(PC
,32);
4242 /* main controlling loop */
4244 /* Fetch the next instruction from the simulator memory: */
4245 uword64 vaddr
= (uword64
)PC
;
4248 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
4249 int dsstate
= (state
& simDELAYSLOT
);
4253 printf("DBG: state = 0x%08X :",state
);
4254 if (state
& simSTOP
) printf(" simSTOP");
4255 if (state
& simSTEP
) printf(" simSTEP");
4256 if (state
& simHALTEX
) printf(" simHALTEX");
4257 if (state
& simHALTIN
) printf(" simHALTIN");
4258 if (state
& simBE
) printf(" simBE");
4265 callback
->printf_filtered(callback
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
4268 if (AddressTranslation(PC
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
4269 if ((vaddr
& 1) == 0) {
4270 /* Copy the action of the LW instruction */
4271 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
4272 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
4275 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
4276 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
4277 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
4278 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
4280 /* Copy the action of the LH instruction */
4281 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
4282 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
4285 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
4286 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
4287 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
4288 paddr
& ~ (uword64
) 1,
4289 vaddr
, isINSTRUCTION
, isREAL
);
4290 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
4291 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
4294 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
4299 callback
->printf_filtered(callback
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
4302 #if !defined(FASTSIM) || defined(PROFILE)
4303 instruction_fetches
++;
4304 /* Since we increment above, the value should only ever be zero if
4305 we have just overflowed: */
4306 if (instruction_fetches
== 0)
4307 instruction_fetch_overflow
++;
4308 #if defined(PROFILE)
4309 if ((state
& simPROFILE
) && ((instruction_fetches
% profile_frequency
) == 0) && profile_hist
) {
4310 unsigned n
= ((unsigned int)(PC
- profile_minpc
) >> (profile_shift
+ 2));
4311 if (n
< profile_nsamples
) {
4312 /* NOTE: The counts for the profiling bins are only 16bits wide */
4313 if (profile_hist
[n
] != USHRT_MAX
)
4314 (profile_hist
[n
])++;
4317 #endif /* PROFILE */
4318 #endif /* !FASTSIM && PROFILE */
4320 IPC
= PC
; /* copy PC for this instruction */
4321 /* This is required by exception processing, to ensure that we can
4322 cope with exceptions in the delay slots of branches that may
4323 already have changed the PC. */
4324 if ((vaddr
& 1) == 0)
4325 PC
+= 4; /* increment ready for the next fetch */
4328 /* NOTE: If we perform a delay slot change to the PC, this
4329 increment is not requuired. However, it would make the
4330 simulator more complicated to try and avoid this small hit. */
4332 /* Currently this code provides a simple model. For more
4333 complicated models we could perform exception status checks at
4334 this point, and set the simSTOP state as required. This could
4335 also include processing any hardware interrupts raised by any
4336 I/O model attached to the simulator context.
4338 Support for "asynchronous" I/O events within the simulated world
4339 could be providing by managing a counter, and calling a I/O
4340 specific handler when a particular threshold is reached. On most
4341 architectures a decrement and check for zero operation is
4342 usually quicker than an increment and compare. However, the
4343 process of managing a known value decrement to zero, is higher
4344 than the cost of using an explicit value UINT_MAX into the
4345 future. Which system is used will depend on how complicated the
4346 I/O model is, and how much it is likely to affect the simulator
4349 If events need to be scheduled further in the future than
4350 UINT_MAX event ticks, then the I/O model should just provide its
4351 own counter, triggered from the event system. */
4353 /* MIPS pipeline ticks. To allow for future support where the
4354 pipeline hit of individual instructions is known, this control
4355 loop manages a "pipeline_count" variable. It is initialised to
4356 1 (one), and will only be changed by the simulator engine when
4357 executing an instruction. If the engine does not have access to
4358 pipeline cycle count information then all instructions will be
4359 treated as using a single cycle. NOTE: A standard system is not
4360 provided by the default simulator because different MIPS
4361 architectures have different cycle counts for the same
4365 /* Set previous flag, depending on current: */
4366 if (state
& simPCOC0
)
4370 /* and update the current value: */
4377 /* NOTE: For multi-context simulation environments the "instruction"
4378 variable should be local to this routine. */
4380 /* Shorthand accesses for engine. Note: If we wanted to use global
4381 variables (and a single-threaded simulator engine), then we can
4382 create the actual variables with these names. */
4384 if (!(state
& simSKIPNEXT
)) {
4385 /* Include the simulator engine */
4387 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
4388 #error "Mismatch between run-time simulator code and simulation engine"
4391 #if defined(WARN_LOHI)
4392 /* Decrement the HI/LO validity ticks */
4401 #endif /* WARN_LOHI */
4403 #if defined(WARN_ZERO)
4404 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
4405 should check for it being changed. It is better doing it here,
4406 than within the simulator, since it will help keep the simulator
4409 sim_warning("The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)",pr_addr(ZERO
),pr_addr(IPC
));
4410 ZERO
= 0; /* reset back to zero before next instruction */
4412 #endif /* WARN_ZERO */
4413 } else /* simSKIPNEXT check */
4414 state
&= ~simSKIPNEXT
;
4416 /* If the delay slot was active before the instruction is
4417 executed, then update the PC to its new value: */
4420 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
4423 state
&= ~(simDELAYSLOT
| simJALDELAYSLOT
);
4426 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
4427 /* Deal with pending register updates: */
4429 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
4431 if (pending_out
!= pending_in
) {
4433 int index
= pending_out
;
4434 int total
= pending_total
;
4435 if (pending_total
== 0) {
4436 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
4439 for (loop
= 0; (loop
< total
); loop
++) {
4441 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
4443 if (pending_slot_reg
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
4445 printf("pending_slot_count[%d] = %d\n",index
,pending_slot_count
[index
]);
4447 if (--(pending_slot_count
[index
]) == 0) {
4449 printf("pending_slot_reg[%d] = %d\n",index
,pending_slot_reg
[index
]);
4450 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(pending_slot_value
[index
]));
4452 if (pending_slot_reg
[index
] == COCIDX
) {
4453 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
4455 registers
[pending_slot_reg
[index
]] = pending_slot_value
[index
];
4457 /* The only time we have PENDING updates to FPU
4458 registers, is when performing binary transfers. This
4459 means we should update the register type field. */
4460 if ((pending_slot_reg
[index
] >= FGRIDX
) && (pending_slot_reg
[index
] < (FGRIDX
+ 32)))
4461 fpr_state
[pending_slot_reg
[index
] - FGRIDX
] = fmt_uninterpreted
;
4465 printf("registers[%d] = 0x%s\n",pending_slot_reg
[index
],pr_addr(registers
[pending_slot_reg
[index
]]));
4467 pending_slot_reg
[index
] = (LAST_EMBED_REGNUM
+ 1);
4469 if (pending_out
== PSLOTS
)
4475 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
4478 if (index
== PSLOTS
)
4483 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
4487 #if !defined(FASTSIM)
4488 pipeline_ticks
+= pipeline_count
;
4489 #endif /* FASTSIM */
4491 if (state
& simSTEP
)
4493 } while (!(state
& simSTOP
));
4496 if (membank
== NULL
) {
4497 printf("DBG: simulate() LEAVING with no memory\n");
4505 /* This code copied from gdb's utils.c. Would like to share this code,
4506 but don't know of a common place where both could get to it. */
4508 /* Temporary storage using circular buffer */
4514 static char buf
[NUMCELLS
][CELLSIZE
];
4516 if (++cell
>=NUMCELLS
) cell
=0;
4520 /* Print routines to handle variable size regs, etc */
4522 /* Eliminate warning from compiler on 32-bit systems */
4523 static int thirty_two
= 32;
4529 char *paddr_str
=get_cell();
4530 switch (sizeof(addr
))
4533 sprintf(paddr_str
,"%08x%08x",
4534 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
4537 sprintf(paddr_str
,"%08x",(unsigned long)addr
);
4540 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
4543 sprintf(paddr_str
,"%x",addr
);
4552 char *paddr_str
=get_cell();
4553 sprintf(paddr_str
,"%08x%08x",
4554 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
4559 /*---------------------------------------------------------------------------*/
4560 /*> EOF interp.c <*/