2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
114 static void ColdReset
PARAMS((SIM_DESC sd
));
116 /*---------------------------------------------------------------------------*/
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
126 #define JALDELAYSLOT() {\
128 STATE |= simJALDELAYSLOT;\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
136 #define CANCELDELAYSLOT() {\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
153 static char *tracefile
= "trace.din"; /* default filename for trace log */
154 FILE *tracefh
= NULL
;
155 static void open_trace
PARAMS((SIM_DESC sd
));
158 #define OPTION_DINERO_TRACE 200
159 #define OPTION_DINERO_FILE 201
162 mips_option_handler (sd
, opt
, arg
)
170 case OPTION_DINERO_TRACE
: /* ??? */
172 /* Eventually the simTRACE flag could be treated as a toggle, to
173 allow external control of the program points being traced
174 (i.e. only from main onwards, excluding the run-time setup,
176 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
178 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
181 else if (strcmp (arg
, "yes") == 0)
183 else if (strcmp (arg
, "no") == 0)
185 else if (strcmp (arg
, "on") == 0)
187 else if (strcmp (arg
, "off") == 0)
191 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
198 Simulator constructed without dinero tracing support (for performance).\n\
199 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
203 case OPTION_DINERO_FILE
:
205 if (optarg
!= NULL
) {
207 tmp
= (char *)malloc(strlen(optarg
) + 1);
210 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
216 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
227 static const OPTION mips_options
[] =
229 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
230 '\0', "on|off", "Enable dinero tracing",
231 mips_option_handler
},
232 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
233 '\0', "FILE", "Write dinero trace to FILE",
234 mips_option_handler
},
235 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
239 int interrupt_pending
;
242 interrupt_event (SIM_DESC sd
, void *data
)
244 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
247 interrupt_pending
= 0;
248 SignalExceptionInterrupt ();
250 else if (!interrupt_pending
)
251 sim_events_schedule (sd
, 1, interrupt_event
, data
);
256 /*---------------------------------------------------------------------------*/
257 /*-- GDB simulator interface ------------------------------------------------*/
258 /*---------------------------------------------------------------------------*/
261 sim_open (kind
, cb
, abfd
, argv
)
267 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
268 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
270 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
272 /* FIXME: watchpoints code shouldn't need this */
273 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
274 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
275 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
279 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
281 sim_add_option_table (sd
, mips_options
);
283 /* Allocate core managed memory */
286 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
287 /* For compatibility with the old code - under this (at level one)
288 are the kernel spaces K0 & K1. Both of these map to a single
289 smaller sub region */
290 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
292 MEM_SIZE
, /* actual size */
295 /* getopt will print the error message so we just have to exit if this fails.
296 FIXME: Hmmm... in the case of gdb we need getopt to call
298 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
300 /* Uninstall the modules to avoid memory leaks,
301 file descriptor leaks, etc. */
302 sim_module_uninstall (sd
);
306 /* check for/establish the a reference program image */
307 if (sim_analyze_program (sd
,
308 (STATE_PROG_ARGV (sd
) != NULL
309 ? *STATE_PROG_ARGV (sd
)
313 sim_module_uninstall (sd
);
317 /* Configure/verify the target byte order and other runtime
318 configuration options */
319 if (sim_config (sd
) != SIM_RC_OK
)
321 sim_module_uninstall (sd
);
325 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
327 /* Uninstall the modules to avoid memory leaks,
328 file descriptor leaks, etc. */
329 sim_module_uninstall (sd
);
333 /* verify assumptions the simulator made about the host type system.
334 This macro does not return if there is a problem */
335 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
336 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
338 /* This is NASTY, in that we are assuming the size of specific
343 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
346 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
347 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
348 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
349 else if ((rn
>= 33) && (rn
<= 37))
350 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
351 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
352 cpu
->register_widths
[rn
] = 32;
354 cpu
->register_widths
[rn
] = 0;
357 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
359 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
360 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
361 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
362 else if ((rn
>= 33) && (rn
<= 37))
363 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
364 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
365 cpu
->register_widths
[rn
] = 32;
367 cpu
->register_widths
[rn
] = 0;
370 /* start-sanitize-r5900 */
372 /* set the 5900 "upper" registers to 64 bits */
373 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
374 cpu
->register_widths
[rn
] = 64;
375 /* end-sanitize-r5900 */
379 if (STATE
& simTRACE
)
383 /* Write the monitor trap address handlers into the monitor (eeprom)
384 address space. This can only be done once the target endianness
385 has been determined. */
388 /* Entry into the IDT monitor is via fixed address vectors, and
389 not using machine instructions. To avoid clashing with use of
390 the MIPS TRAP system, we place our own (simulator specific)
391 "undefined" instructions into the relevant vector slots. */
392 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
394 address_word vaddr
= (MONITOR_BASE
+ loop
);
395 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
397 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
399 /* The PMON monitor uses the same address space, but rather than
400 branching into it the address of a routine is loaded. We can
401 cheat for the moment, and direct the PMON routine to IDT style
402 instructions within the monitor space. This relies on the IDT
403 monitor not using the locations from 0xBFC00500 onwards as its
405 for (loop
= 0; (loop
< 24); loop
++)
407 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
408 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
424 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
426 case 8: /* cliexit */
429 case 11: /* flush_cache */
433 /* FIXME - should monitor_base be SIM_ADDR?? */
434 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
436 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
438 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
440 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
452 tracefh
= fopen(tracefile
,"wb+");
455 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
462 sim_close (sd
, quitting
)
467 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
470 /* "quitting" is non-zero if we cannot hang on errors */
472 /* Ensure that any resources allocated through the callback
473 mechanism are released: */
474 sim_io_shutdown (sd
);
477 if (tracefh
!= NULL
&& tracefh
!= stderr
)
482 /* FIXME - free SD */
489 sim_write (sd
,addr
,buffer
,size
)
492 unsigned char *buffer
;
496 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
498 /* Return the number of bytes written, or zero if error. */
500 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
503 /* We use raw read and write routines, since we do not want to count
504 the GDB memory accesses in our statistics gathering. */
506 for (index
= 0; index
< size
; index
++)
508 address_word vaddr
= (address_word
)addr
+ index
;
511 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
513 if (sim_core_write_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
521 sim_read (sd
,addr
,buffer
,size
)
524 unsigned char *buffer
;
528 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
530 /* Return the number of bytes read, or zero if error. */
532 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
535 for (index
= 0; (index
< size
); index
++)
537 address_word vaddr
= (address_word
)addr
+ index
;
540 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
542 if (sim_core_read_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
550 sim_store_register (sd
,rn
,memory
)
553 unsigned char *memory
;
555 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
556 /* NOTE: gdb (the client) stores registers in target byte order
557 while the simulator uses host byte order */
559 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
562 /* Unfortunately this suffers from the same problem as the register
563 numbering one. We need to know what the width of each logical
564 register number is for the architecture being simulated. */
566 if (cpu
->register_widths
[rn
] == 0)
567 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
568 /* start-sanitize-r5900 */
569 else if (rn
== REGISTER_SA
)
570 SA
= T2H_8(*(unsigned64
*)memory
);
571 else if (rn
> LAST_EMBED_REGNUM
)
572 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(unsigned64
*)memory
);
573 /* end-sanitize-r5900 */
574 else if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
576 if (cpu
->register_widths
[rn
] == 32)
577 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
579 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
581 else if (cpu
->register_widths
[rn
] == 32)
582 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
584 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
590 sim_fetch_register (sd
,rn
,memory
)
593 unsigned char *memory
;
595 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
596 /* NOTE: gdb (the client) stores registers in target byte order
597 while the simulator uses host byte order */
599 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
602 if (cpu
->register_widths
[rn
] == 0)
603 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
604 /* start-sanitize-r5900 */
605 else if (rn
== REGISTER_SA
)
606 *((unsigned64
*)memory
) = H2T_8(SA
);
607 else if (rn
> LAST_EMBED_REGNUM
)
608 *((unsigned64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
609 /* end-sanitize-r5900 */
610 else if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
612 if (cpu
->register_widths
[rn
] == 32)
613 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
615 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
617 else if (cpu
->register_widths
[rn
] == 32)
618 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
619 else /* 64bit register */
620 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
627 sim_info (sd
,verbose
)
631 /* Accessed from the GDB "info files" command: */
632 if (STATE_VERBOSE_P (sd
) || verbose
)
635 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
636 WITH_TARGET_WORD_BITSIZE
,
637 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
639 #if !defined(FASTSIM)
640 /* It would be a useful feature, if when performing multi-cycle
641 simulations (rather than single-stepping) we keep the start and
642 end times of the execution, so that we can give a performance
643 figure for the simulator. */
644 #endif /* !FASTSIM */
645 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
646 (long) sim_events_time (sd
));
648 /* print information pertaining to MIPS ISA and architecture being simulated */
649 /* things that may be interesting */
650 /* instructions executed - if available */
651 /* cycles executed - if available */
652 /* pipeline stalls - if available */
653 /* virtual time taken */
655 /* profiling frequency */
659 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
664 sim_create_inferior (sd
, abfd
, argv
,env
)
672 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
680 /* override PC value set by ColdReset () */
682 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
684 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
685 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
689 #if 0 /* def DEBUG */
692 /* We should really place the argv slot values into the argument
693 registers, and onto the stack as required. However, this
694 assumes that we have a stack defined, which is not
695 necessarily true at the moment. */
697 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
698 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
699 printf("DBG: arg \"%s\"\n",*cptr
);
707 sim_do_command (sd
,cmd
)
711 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
712 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
716 /*---------------------------------------------------------------------------*/
717 /*-- Private simulator support interface ------------------------------------*/
718 /*---------------------------------------------------------------------------*/
720 /* Read a null terminated string from memory, return in a buffer */
729 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
731 buf
= NZALLOC (char, nr
+ 1);
732 sim_read (sd
, addr
, buf
, nr
);
736 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
738 sim_monitor (SIM_DESC sd
,
744 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
747 /* The IDT monitor actually allows two instructions per vector
748 slot. However, the simulator currently causes a trap on each
749 individual instruction. We cheat, and lose the bottom bit. */
752 /* The following callback functions are available, however the
753 monitor we are simulating does not make use of them: get_errno,
754 isatty, lseek, rename, system, time and unlink */
758 case 6: /* int open(char *path,int flags) */
760 char *path
= fetch_str (sd
, A0
);
761 V0
= sim_io_open (sd
, path
, (int)A1
);
766 case 7: /* int read(int file,char *ptr,int len) */
770 char *buf
= zalloc (nr
);
771 V0
= sim_io_read (sd
, fd
, buf
, nr
);
772 sim_write (sd
, A1
, buf
, nr
);
777 case 8: /* int write(int file,char *ptr,int len) */
781 char *buf
= zalloc (nr
);
782 sim_read (sd
, A1
, buf
, nr
);
783 V0
= sim_io_write (sd
, fd
, buf
, nr
);
788 case 10: /* int close(int file) */
790 V0
= sim_io_close (sd
, (int)A0
);
794 case 2: /* Densan monitor: char inbyte(int waitflag) */
796 if (A0
== 0) /* waitflag == NOWAIT */
797 V0
= (unsigned_word
)-1;
799 /* Drop through to case 11 */
801 case 11: /* char inbyte(void) */
804 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
806 sim_io_error(sd
,"Invalid return from character read");
807 V0
= (unsigned_word
)-1;
810 V0
= (unsigned_word
)tmp
;
814 case 3: /* Densan monitor: void co(char chr) */
815 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
817 char tmp
= (char)(A0
& 0xFF);
818 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
822 case 17: /* void _exit() */
824 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
825 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
826 (unsigned int)(A0
& 0xFFFFFFFF));
830 case 28 : /* PMON flush_cache */
833 case 55: /* void get_mem_info(unsigned int *ptr) */
834 /* in: A0 = pointer to three word memory location */
835 /* out: [A0 + 0] = size */
836 /* [A0 + 4] = instruction cache size */
837 /* [A0 + 8] = data cache size */
839 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
841 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
842 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
846 case 158 : /* PMON printf */
847 /* in: A0 = pointer to format string */
848 /* A1 = optional argument 1 */
849 /* A2 = optional argument 2 */
850 /* A3 = optional argument 3 */
852 /* The following is based on the PMON printf source */
856 signed_word
*ap
= &A1
; /* 1st argument */
857 /* This isn't the quickest way, since we call the host print
858 routine for every character almost. But it does avoid
859 having to allocate and manage a temporary string buffer. */
860 /* TODO: Include check that we only use three arguments (A1,
862 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
867 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
868 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
869 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
871 if (strchr ("dobxXulscefg%", s
))
886 else if (c
>= '1' && c
<= '9')
890 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
893 n
= (unsigned int)strtol(tmp
,NULL
,10);
906 sim_io_printf (sd
, "%%");
911 address_word p
= *ap
++;
913 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
914 sim_io_printf(sd
, "%c", ch
);
917 sim_io_printf(sd
,"(null)");
920 sim_io_printf (sd
, "%c", (int)*ap
++);
925 sim_read (sd
, s
++, &c
, 1);
929 sim_read (sd
, s
++, &c
, 1);
932 if (strchr ("dobxXu", c
))
934 word64 lv
= (word64
) *ap
++;
936 sim_io_printf(sd
,"<binary not supported>");
939 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
941 sim_io_printf(sd
, tmp
, lv
);
943 sim_io_printf(sd
, tmp
, (int)lv
);
946 else if (strchr ("eEfgG", c
))
948 double dbl
= *(double*)(ap
++);
949 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
950 sim_io_printf (sd
, tmp
, dbl
);
956 sim_io_printf(sd
, "%c", c
);
962 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
963 reason
, pr_addr(cia
));
969 /* Store a word into memory. */
972 store_word (SIM_DESC sd
,
981 if ((vaddr
& 3) != 0)
982 SignalExceptionAddressStore ();
985 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
988 const uword64 mask
= 7;
992 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
993 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
994 memval
= ((uword64
) val
) << (8 * byte
);
995 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1001 /* Load a word from memory. */
1004 load_word (SIM_DESC sd
,
1009 if ((vaddr
& 3) != 0)
1010 SignalExceptionAddressLoad ();
1016 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1019 const uword64 mask
= 0x7;
1020 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1021 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1025 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1026 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1028 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1029 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1036 /* Simulate the mips16 entry and exit pseudo-instructions. These
1037 would normally be handled by the reserved instruction exception
1038 code, but for ease of simulation we just handle them directly. */
1041 mips16_entry (SIM_DESC sd
,
1046 int aregs
, sregs
, rreg
;
1049 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1052 aregs
= (insn
& 0x700) >> 8;
1053 sregs
= (insn
& 0x0c0) >> 6;
1054 rreg
= (insn
& 0x020) >> 5;
1056 /* This should be checked by the caller. */
1065 /* This is the entry pseudo-instruction. */
1067 for (i
= 0; i
< aregs
; i
++)
1068 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1076 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1079 for (i
= 0; i
< sregs
; i
++)
1082 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1090 /* This is the exit pseudo-instruction. */
1097 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1100 for (i
= 0; i
< sregs
; i
++)
1103 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1108 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1112 FGR
[0] = WORD64LO (GPR
[4]);
1113 FPR_STATE
[0] = fmt_uninterpreted
;
1115 else if (aregs
== 6)
1117 FGR
[0] = WORD64LO (GPR
[5]);
1118 FGR
[1] = WORD64LO (GPR
[4]);
1119 FPR_STATE
[0] = fmt_uninterpreted
;
1120 FPR_STATE
[1] = fmt_uninterpreted
;
1129 /*-- trace support ----------------------------------------------------------*/
1131 /* The TRACE support is provided (if required) in the memory accessing
1132 routines. Since we are also providing the architecture specific
1133 features, the architecture simulation code can also deal with
1134 notifying the TRACE world of cache flushes, etc. Similarly we do
1135 not need to provide profiling support in the simulator engine,
1136 since we can sample in the instruction fetch control loop. By
1137 defining the TRACE manifest, we add tracing as a run-time
1141 /* Tracing by default produces "din" format (as required by
1142 dineroIII). Each line of such a trace file *MUST* have a din label
1143 and address field. The rest of the line is ignored, so comments can
1144 be included if desired. The first field is the label which must be
1145 one of the following values:
1150 3 escape record (treated as unknown access type)
1151 4 escape record (causes cache flush)
1153 The address field is a 32bit (lower-case) hexadecimal address
1154 value. The address should *NOT* be preceded by "0x".
1156 The size of the memory transfer is not important when dealing with
1157 cache lines (as long as no more than a cache line can be
1158 transferred in a single operation :-), however more information
1159 could be given following the dineroIII requirement to allow more
1160 complete memory and cache simulators to provide better
1161 results. i.e. the University of Pisa has a cache simulator that can
1162 also take bus size and speed as (variable) inputs to calculate
1163 complete system performance (a much more useful ability when trying
1164 to construct an end product, rather than a processor). They
1165 currently have an ARM version of their tool called ChARM. */
1169 dotrace (SIM_DESC sd
,
1177 if (STATE
& simTRACE
) {
1179 fprintf(tracefh
,"%d %s ; width %d ; ",
1183 va_start(ap
,comment
);
1184 vfprintf(tracefh
,comment
,ap
);
1186 fprintf(tracefh
,"\n");
1188 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1189 we may be generating 64bit ones, we should put the hi-32bits of the
1190 address into the comment field. */
1192 /* TODO: Provide a buffer for the trace lines. We can then avoid
1193 performing writes until the buffer is filled, or the file is
1196 /* NOTE: We could consider adding a comment field to the "din" file
1197 produced using type 3 markers (unknown access). This would then
1198 allow information about the program that the "din" is for, and
1199 the MIPs world that was being simulated, to be placed into the
1206 /*---------------------------------------------------------------------------*/
1207 /*-- simulator engine -------------------------------------------------------*/
1208 /*---------------------------------------------------------------------------*/
1211 ColdReset (SIM_DESC sd
)
1214 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1216 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1217 /* RESET: Fixed PC address: */
1218 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1219 /* The reset vector address is in the unmapped, uncached memory space. */
1221 SR
&= ~(status_SR
| status_TS
| status_RP
);
1222 SR
|= (status_ERL
| status_BEV
);
1224 /* Cheat and allow access to the complete register set immediately */
1225 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1226 && WITH_TARGET_WORD_BITSIZE
== 64)
1227 SR
|= status_FR
; /* 64bit registers */
1229 /* Ensure that any instructions with pending register updates are
1231 PENDING_INVALIDATE();
1233 /* Initialise the FPU registers to the unknown state */
1234 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1237 for (rn
= 0; (rn
< 32); rn
++)
1238 FPR_STATE
[rn
] = fmt_uninterpreted
;
1244 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1246 /* Translate a virtual address to a physical address and cache
1247 coherence algorithm describing the mechanism used to resolve the
1248 memory reference. Given the virtual address vAddr, and whether the
1249 reference is to Instructions ot Data (IorD), find the corresponding
1250 physical address (pAddr) and the cache coherence algorithm (CCA)
1251 used to resolve the reference. If the virtual address is in one of
1252 the unmapped address spaces the physical address and the CCA are
1253 determined directly by the virtual address. If the virtual address
1254 is in one of the mapped address spaces then the TLB is used to
1255 determine the physical address and access type; if the required
1256 translation is not present in the TLB or the desired access is not
1257 permitted the function fails and an exception is taken.
1259 NOTE: Normally (RAW == 0), when address translation fails, this
1260 function raises an exception and does not return. */
1263 address_translation (SIM_DESC sd
,
1269 address_word
*pAddr
,
1273 int res
= -1; /* TRUE : Assume good return */
1276 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1279 /* Check that the address is valid for this memory model */
1281 /* For a simple (flat) memory model, we simply pass virtual
1282 addressess through (mostly) unchanged. */
1283 vAddr
&= 0xFFFFFFFF;
1285 *pAddr
= vAddr
; /* default for isTARGET */
1286 *CCA
= Uncached
; /* not used for isHOST */
1291 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1293 /* Prefetch data from memory. Prefetch is an advisory instruction for
1294 which an implementation specific action is taken. The action taken
1295 may increase performance, but must not change the meaning of the
1296 program, or alter architecturally-visible state. */
1299 prefetch (SIM_DESC sd
,
1309 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1312 /* For our simple memory model we do nothing */
1316 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1318 /* Load a value from memory. Use the cache and main memory as
1319 specified in the Cache Coherence Algorithm (CCA) and the sort of
1320 access (IorD) to find the contents of AccessLength memory bytes
1321 starting at physical location pAddr. The data is returned in the
1322 fixed width naturally-aligned memory element (MemElem). The
1323 low-order two (or three) bits of the address and the AccessLength
1324 indicate which of the bytes within MemElem needs to be given to the
1325 processor. If the memory access type of the reference is uncached
1326 then only the referenced bytes are read from memory and valid
1327 within the memory element. If the access type is cached, and the
1328 data is not present in cache, an implementation specific size and
1329 alignment block of memory is read and loaded into the cache to
1330 satisfy a load reference. At a minimum, the block is the entire
1333 load_memory (SIM_DESC sd
,
1348 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1351 #if defined(WARN_MEM)
1352 if (CCA
!= uncached
)
1353 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1354 #endif /* WARN_MEM */
1356 /* If instruction fetch then we need to check that the two lo-order
1357 bits are zero, otherwise raise a InstructionFetch exception: */
1358 if ((IorD
== isINSTRUCTION
)
1359 && ((pAddr
& 0x3) != 0)
1360 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1361 SignalExceptionInstructionFetch ();
1363 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1365 /* In reality this should be a Bus Error */
1366 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1368 (LOADDRMASK
+ 1) << 2,
1373 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1376 /* Read the specified number of bytes from memory. Adjust for
1377 host/target byte ordering/ Align the least significant byte
1380 switch (AccessLength
)
1382 case AccessLength_QUADWORD
:
1384 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
,
1385 sim_core_read_map
, pAddr
);
1386 value1
= VH8_16 (val
);
1387 value
= VL8_16 (val
);
1390 case AccessLength_DOUBLEWORD
:
1391 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1392 sim_core_read_map
, pAddr
);
1394 case AccessLength_SEPTIBYTE
:
1395 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1396 sim_core_read_map
, pAddr
);
1397 case AccessLength_SEXTIBYTE
:
1398 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1399 sim_core_read_map
, pAddr
);
1400 case AccessLength_QUINTIBYTE
:
1401 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1402 sim_core_read_map
, pAddr
);
1403 case AccessLength_WORD
:
1404 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1405 sim_core_read_map
, pAddr
);
1407 case AccessLength_TRIPLEBYTE
:
1408 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1409 sim_core_read_map
, pAddr
);
1410 case AccessLength_HALFWORD
:
1411 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1412 sim_core_read_map
, pAddr
);
1414 case AccessLength_BYTE
:
1415 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1416 sim_core_read_map
, pAddr
);
1423 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1424 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1427 /* See also store_memory. */
1428 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1431 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1432 shifted to the most significant byte position. */
1433 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1435 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1436 is already in the correct postition. */
1437 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1441 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1442 pr_uword64(value1
),pr_uword64(value
));
1446 if (memval1p
) *memval1p
= value1
;
1450 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1452 /* Store a value to memory. The specified data is stored into the
1453 physical location pAddr using the memory hierarchy (data caches and
1454 main memory) as specified by the Cache Coherence Algorithm
1455 (CCA). The MemElem contains the data for an aligned, fixed-width
1456 memory element (word for 32-bit processors, doubleword for 64-bit
1457 processors), though only the bytes that will actually be stored to
1458 memory need to be valid. The low-order two (or three) bits of pAddr
1459 and the AccessLength field indicates which of the bytes within the
1460 MemElem data should actually be stored; only these bytes in memory
1464 store_memory (SIM_DESC sd
,
1470 uword64 MemElem1
, /* High order 64 bits */
1475 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1478 #if defined(WARN_MEM)
1479 if (CCA
!= uncached
)
1480 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1481 #endif /* WARN_MEM */
1483 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1484 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1487 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1491 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1494 /* See also load_memory */
1495 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1498 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1499 shifted to the most significant byte position. */
1500 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1502 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1503 is already in the correct postition. */
1504 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1508 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1511 switch (AccessLength
)
1513 case AccessLength_QUADWORD
:
1515 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1516 sim_core_write_aligned_16 (cpu
, NULL_CIA
,
1517 sim_core_write_map
, pAddr
, val
);
1520 case AccessLength_DOUBLEWORD
:
1521 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1522 sim_core_write_map
, pAddr
, MemElem
);
1524 case AccessLength_SEPTIBYTE
:
1525 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1526 sim_core_write_map
, pAddr
, MemElem
);
1528 case AccessLength_SEXTIBYTE
:
1529 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1530 sim_core_write_map
, pAddr
, MemElem
);
1532 case AccessLength_QUINTIBYTE
:
1533 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1534 sim_core_write_map
, pAddr
, MemElem
);
1536 case AccessLength_WORD
:
1537 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1538 sim_core_write_map
, pAddr
, MemElem
);
1540 case AccessLength_TRIPLEBYTE
:
1541 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1542 sim_core_write_map
, pAddr
, MemElem
);
1544 case AccessLength_HALFWORD
:
1545 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1546 sim_core_write_map
, pAddr
, MemElem
);
1548 case AccessLength_BYTE
:
1549 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1550 sim_core_write_map
, pAddr
, MemElem
);
1561 ifetch32 (SIM_DESC sd
,
1566 /* Copy the action of the LW instruction */
1567 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1568 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1571 unsigned32 instruction
;
1574 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1575 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1576 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1577 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1578 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1583 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1584 /* Order loads and stores to synchronise shared memory. Perform the
1585 action necessary to make the effects of groups of synchronizable
1586 loads and stores indicated by stype occur in the same order for all
1589 sync_operation (SIM_DESC sd
,
1595 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1600 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1601 /* Signal an exception condition. This will result in an exception
1602 that aborts the instruction. The instruction operation pseudocode
1603 will never see a return from this function call. */
1606 signal_exception (SIM_DESC sd
,
1614 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1617 /* Ensure that any active atomic read/modify/write operation will fail: */
1620 switch (exception
) {
1621 /* TODO: For testing purposes I have been ignoring TRAPs. In
1622 reality we should either simulate them, or allow the user to
1623 ignore them at run-time.
1626 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1632 unsigned int instruction
;
1635 va_start(ap
,exception
);
1636 instruction
= va_arg(ap
,unsigned int);
1639 code
= (instruction
>> 6) & 0xFFFFF;
1641 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1642 code
, pr_addr(cia
));
1646 case DebugBreakPoint
:
1647 if (! (Debug
& Debug_DM
))
1653 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1654 DEPC
= cia
- 4; /* reference the branch instruction */
1658 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1662 Debug
|= Debug_DM
; /* in debugging mode */
1663 Debug
|= Debug_DBp
; /* raising a DBp exception */
1665 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1669 case ReservedInstruction
:
1672 unsigned int instruction
;
1673 va_start(ap
,exception
);
1674 instruction
= va_arg(ap
,unsigned int);
1676 /* Provide simple monitor support using ReservedInstruction
1677 exceptions. The following code simulates the fixed vector
1678 entry points into the IDT monitor by causing a simulator
1679 trap, performing the monitor operation, and returning to
1680 the address held in the $ra register (standard PCS return
1681 address). This means we only need to pre-load the vector
1682 space with suitable instruction values. For systems were
1683 actual trap instructions are used, we would not need to
1684 perform this magic. */
1685 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1687 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1688 /* NOTE: This assumes that a branch-and-link style
1689 instruction was used to enter the vector (which is the
1690 case with the current IDT monitor). */
1691 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1693 /* Look for the mips16 entry and exit instructions, and
1694 simulate a handler for them. */
1695 else if ((cia
& 1) != 0
1696 && (instruction
& 0xf81f) == 0xe809
1697 && (instruction
& 0x0c0) != 0x0c0)
1699 mips16_entry (SD
, CPU
, cia
, instruction
);
1700 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1702 /* else fall through to normal exception processing */
1703 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1708 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1710 /* Keep a copy of the current A0 in-case this is the program exit
1714 unsigned int instruction
;
1715 va_start(ap
,exception
);
1716 instruction
= va_arg(ap
,unsigned int);
1718 /* Check for our special terminating BREAK: */
1719 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1720 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1721 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1724 if (STATE
& simDELAYSLOT
)
1725 PC
= cia
- 4; /* reference the branch instruction */
1728 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1729 sim_stopped
, SIM_SIGTRAP
);
1732 /* Store exception code into current exception id variable (used
1735 /* TODO: If not simulating exceptions then stop the simulator
1736 execution. At the moment we always stop the simulation. */
1738 /* See figure 5-17 for an outline of the code below */
1739 if (! (SR
& status_EXL
))
1741 CAUSE
= (exception
<< 2);
1742 if (STATE
& simDELAYSLOT
)
1744 STATE
&= ~simDELAYSLOT
;
1746 EPC
= (cia
- 4); /* reference the branch instruction */
1750 /* FIXME: TLB et.al. */
1755 CAUSE
= (exception
<< 2);
1759 /* Store exception code into current exception id variable (used
1761 if (SR
& status_BEV
)
1762 PC
= (signed)0xBFC00200 + 0x180;
1764 PC
= (signed)0x80000000 + 0x180;
1766 switch ((CAUSE
>> 2) & 0x1F)
1769 /* Interrupts arrive during event processing, no need to
1773 case TLBModification
:
1778 case InstructionFetch
:
1780 /* The following is so that the simulator will continue from the
1781 exception address on breakpoint operations. */
1783 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1784 sim_stopped
, SIM_SIGBUS
);
1786 case ReservedInstruction
:
1787 case CoProcessorUnusable
:
1789 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1790 sim_stopped
, SIM_SIGILL
);
1792 case IntegerOverflow
:
1794 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1795 sim_stopped
, SIM_SIGFPE
);
1801 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1802 sim_stopped
, SIM_SIGTRAP
);
1806 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1807 "FATAL: Should not encounter a breakpoint\n");
1809 default : /* Unknown internal exception */
1811 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1812 sim_stopped
, SIM_SIGABRT
);
1816 case SimulatorFault
:
1820 va_start(ap
,exception
);
1821 msg
= va_arg(ap
,char *);
1823 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1824 "FATAL: Simulator error \"%s\"\n",msg
);
1831 #if defined(WARN_RESULT)
1832 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1833 /* This function indicates that the result of the operation is
1834 undefined. However, this should not affect the instruction
1835 stream. All that is meant to happen is that the destination
1836 register is set to an undefined result. To keep the simulator
1837 simple, we just don't bother updating the destination register, so
1838 the overall result will be undefined. If desired we can stop the
1839 simulator by raising a pseudo-exception. */
1840 #define UndefinedResult() undefined_result (sd,cia)
1842 undefined_result(sd
,cia
)
1846 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1847 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1852 #endif /* WARN_RESULT */
1855 cache_op (SIM_DESC sd
,
1861 unsigned int instruction
)
1863 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1864 static int icache_warning
= 1;
1865 static int dcache_warning
= 1;
1867 static int icache_warning
= 0;
1868 static int dcache_warning
= 0;
1871 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1872 enable bit in the Status Register is clear - a coprocessor
1873 unusable exception is taken. */
1875 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
1879 case 0: /* instruction cache */
1881 case 0: /* Index Invalidate */
1882 case 1: /* Index Load Tag */
1883 case 2: /* Index Store Tag */
1884 case 4: /* Hit Invalidate */
1886 case 6: /* Hit Writeback */
1887 if (!icache_warning
)
1889 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
1895 SignalException(ReservedInstruction
,instruction
);
1900 case 1: /* data cache */
1902 case 0: /* Index Writeback Invalidate */
1903 case 1: /* Index Load Tag */
1904 case 2: /* Index Store Tag */
1905 case 3: /* Create Dirty */
1906 case 4: /* Hit Invalidate */
1907 case 5: /* Hit Writeback Invalidate */
1908 case 6: /* Hit Writeback */
1909 if (!dcache_warning
)
1911 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
1917 SignalException(ReservedInstruction
,instruction
);
1922 default: /* unrecognised cache ID */
1923 SignalException(ReservedInstruction
,instruction
);
1930 /*-- FPU support routines ---------------------------------------------------*/
1932 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1933 formats conform to ANSI/IEEE Std 754-1985. */
1934 /* SINGLE precision floating:
1935 * seeeeeeeefffffffffffffffffffffff
1937 * e = 8bits = exponent
1938 * f = 23bits = fraction
1940 /* SINGLE precision fixed:
1941 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1943 * i = 31bits = integer
1945 /* DOUBLE precision floating:
1946 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1948 * e = 11bits = exponent
1949 * f = 52bits = fraction
1951 /* DOUBLE precision fixed:
1952 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1954 * i = 63bits = integer
1957 /* Extract sign-bit: */
1958 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1959 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1960 /* Extract biased exponent: */
1961 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1962 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1963 /* Extract unbiased Exponent: */
1964 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1965 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1966 /* Extract complete fraction field: */
1967 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1968 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1969 /* Extract numbered fraction bit: */
1970 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1971 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1973 /* Explicit QNaN values used when value required: */
1974 #define FPQNaN_SINGLE (0x7FBFFFFF)
1975 #define FPQNaN_WORD (0x7FFFFFFF)
1976 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1977 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1979 /* Explicit Infinity values used when required: */
1980 #define FPINF_SINGLE (0x7F800000)
1981 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1983 #if 1 /* def DEBUG */
1984 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1985 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1989 value_fpr (SIM_DESC sd
,
1998 /* Treat unused register values, as fixed-point 64bit values: */
1999 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2001 /* If request to read data as "uninterpreted", then use the current
2003 fmt
= FPR_STATE
[fpr
];
2008 /* For values not yet accessed, set to the desired format: */
2009 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2010 FPR_STATE
[fpr
] = fmt
;
2012 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2015 if (fmt
!= FPR_STATE
[fpr
]) {
2016 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2017 FPR_STATE
[fpr
] = fmt_unknown
;
2020 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2021 /* Set QNaN value: */
2024 value
= FPQNaN_SINGLE
;
2028 value
= FPQNaN_DOUBLE
;
2032 value
= FPQNaN_WORD
;
2036 value
= FPQNaN_LONG
;
2043 } else if (SizeFGR() == 64) {
2047 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2050 case fmt_uninterpreted
:
2064 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2067 case fmt_uninterpreted
:
2070 if ((fpr
& 1) == 0) { /* even registers only */
2071 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2073 SignalException(ReservedInstruction
,0);
2084 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2087 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2094 store_fpr (SIM_DESC sd
,
2104 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2107 if (SizeFGR() == 64) {
2109 case fmt_uninterpreted_32
:
2110 fmt
= fmt_uninterpreted
;
2113 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2114 FPR_STATE
[fpr
] = fmt
;
2117 case fmt_uninterpreted_64
:
2118 fmt
= fmt_uninterpreted
;
2119 case fmt_uninterpreted
:
2123 FPR_STATE
[fpr
] = fmt
;
2127 FPR_STATE
[fpr
] = fmt_unknown
;
2133 case fmt_uninterpreted_32
:
2134 fmt
= fmt_uninterpreted
;
2137 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2138 FPR_STATE
[fpr
] = fmt
;
2141 case fmt_uninterpreted_64
:
2142 fmt
= fmt_uninterpreted
;
2143 case fmt_uninterpreted
:
2146 if ((fpr
& 1) == 0) { /* even register number only */
2147 FGR
[fpr
+1] = (value
>> 32);
2148 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2149 FPR_STATE
[fpr
+ 1] = fmt
;
2150 FPR_STATE
[fpr
] = fmt
;
2152 FPR_STATE
[fpr
] = fmt_unknown
;
2153 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2154 SignalException(ReservedInstruction
,0);
2159 FPR_STATE
[fpr
] = fmt_unknown
;
2164 #if defined(WARN_RESULT)
2167 #endif /* WARN_RESULT */
2170 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2173 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2190 sim_fpu_32to (&wop
, op
);
2191 boolean
= sim_fpu_is_nan (&wop
);
2198 sim_fpu_64to (&wop
, op
);
2199 boolean
= sim_fpu_is_nan (&wop
);
2203 fprintf (stderr
, "Bad switch\n");
2208 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2222 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2229 sim_fpu_32to (&wop
, op
);
2230 boolean
= sim_fpu_is_infinity (&wop
);
2236 sim_fpu_64to (&wop
, op
);
2237 boolean
= sim_fpu_is_infinity (&wop
);
2241 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2246 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2260 /* Argument checking already performed by the FPCOMPARE code */
2263 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2266 /* The format type should already have been checked: */
2272 sim_fpu_32to (&wop1
, op1
);
2273 sim_fpu_32to (&wop2
, op2
);
2274 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2281 sim_fpu_64to (&wop1
, op1
);
2282 sim_fpu_64to (&wop2
, op2
);
2283 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2287 fprintf (stderr
, "Bad switch\n");
2292 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2306 /* Argument checking already performed by the FPCOMPARE code */
2309 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2312 /* The format type should already have been checked: */
2318 sim_fpu_32to (&wop1
, op1
);
2319 sim_fpu_32to (&wop2
, op2
);
2320 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2327 sim_fpu_64to (&wop1
, op1
);
2328 sim_fpu_64to (&wop2
, op2
);
2329 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2333 fprintf (stderr
, "Bad switch\n");
2338 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2345 AbsoluteValue(op
,fmt
)
2352 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2355 /* The format type should already have been checked: */
2361 sim_fpu_32to (&wop
, op
);
2362 sim_fpu_abs (&wop
, &wop
);
2363 sim_fpu_to32 (&ans
, &wop
);
2371 sim_fpu_64to (&wop
, op
);
2372 sim_fpu_abs (&wop
, &wop
);
2373 sim_fpu_to64 (&ans
, &wop
);
2378 fprintf (stderr
, "Bad switch\n");
2393 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2396 /* The format type should already have been checked: */
2402 sim_fpu_32to (&wop
, op
);
2403 sim_fpu_neg (&wop
, &wop
);
2404 sim_fpu_to32 (&ans
, &wop
);
2412 sim_fpu_64to (&wop
, op
);
2413 sim_fpu_neg (&wop
, &wop
);
2414 sim_fpu_to64 (&ans
, &wop
);
2419 fprintf (stderr
, "Bad switch\n");
2435 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2438 /* The registers must specify FPRs valid for operands of type
2439 "fmt". If they are not valid, the result is undefined. */
2441 /* The format type should already have been checked: */
2449 sim_fpu_32to (&wop1
, op1
);
2450 sim_fpu_32to (&wop2
, op2
);
2451 sim_fpu_add (&ans
, &wop1
, &wop2
);
2452 sim_fpu_to32 (&res
, &ans
);
2462 sim_fpu_64to (&wop1
, op1
);
2463 sim_fpu_64to (&wop2
, op2
);
2464 sim_fpu_add (&ans
, &wop1
, &wop2
);
2465 sim_fpu_to64 (&res
, &ans
);
2470 fprintf (stderr
, "Bad switch\n");
2475 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2490 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2493 /* The registers must specify FPRs valid for operands of type
2494 "fmt". If they are not valid, the result is undefined. */
2496 /* The format type should already have been checked: */
2504 sim_fpu_32to (&wop1
, op1
);
2505 sim_fpu_32to (&wop2
, op2
);
2506 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2507 sim_fpu_to32 (&res
, &ans
);
2517 sim_fpu_64to (&wop1
, op1
);
2518 sim_fpu_64to (&wop2
, op2
);
2519 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2520 sim_fpu_to64 (&res
, &ans
);
2525 fprintf (stderr
, "Bad switch\n");
2530 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2537 Multiply(op1
,op2
,fmt
)
2545 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2548 /* The registers must specify FPRs valid for operands of type
2549 "fmt". If they are not valid, the result is undefined. */
2551 /* The format type should already have been checked: */
2559 sim_fpu_32to (&wop1
, op1
);
2560 sim_fpu_32to (&wop2
, op2
);
2561 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2562 sim_fpu_to32 (&res
, &ans
);
2572 sim_fpu_64to (&wop1
, op1
);
2573 sim_fpu_64to (&wop2
, op2
);
2574 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2575 sim_fpu_to64 (&res
, &ans
);
2580 fprintf (stderr
, "Bad switch\n");
2585 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2600 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2603 /* The registers must specify FPRs valid for operands of type
2604 "fmt". If they are not valid, the result is undefined. */
2606 /* The format type should already have been checked: */
2614 sim_fpu_32to (&wop1
, op1
);
2615 sim_fpu_32to (&wop2
, op2
);
2616 sim_fpu_div (&ans
, &wop1
, &wop2
);
2617 sim_fpu_to32 (&res
, &ans
);
2627 sim_fpu_64to (&wop1
, op1
);
2628 sim_fpu_64to (&wop2
, op2
);
2629 sim_fpu_div (&ans
, &wop1
, &wop2
);
2630 sim_fpu_to64 (&res
, &ans
);
2635 fprintf (stderr
, "Bad switch\n");
2640 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2654 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2657 /* The registers must specify FPRs valid for operands of type
2658 "fmt". If they are not valid, the result is undefined. */
2660 /* The format type should already have been checked: */
2667 sim_fpu_32to (&wop
, op
);
2668 sim_fpu_inv (&ans
, &wop
);
2669 sim_fpu_to32 (&res
, &ans
);
2678 sim_fpu_64to (&wop
, op
);
2679 sim_fpu_inv (&ans
, &wop
);
2680 sim_fpu_to64 (&res
, &ans
);
2685 fprintf (stderr
, "Bad switch\n");
2690 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2704 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2707 /* The registers must specify FPRs valid for operands of type
2708 "fmt". If they are not valid, the result is undefined. */
2710 /* The format type should already have been checked: */
2717 sim_fpu_32to (&wop
, op
);
2718 sim_fpu_sqrt (&ans
, &wop
);
2719 sim_fpu_to32 (&res
, &ans
);
2728 sim_fpu_64to (&wop
, op
);
2729 sim_fpu_sqrt (&ans
, &wop
);
2730 sim_fpu_to64 (&res
, &ans
);
2735 fprintf (stderr
, "Bad switch\n");
2740 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2747 convert (SIM_DESC sd
,
2756 sim_fpu_round round
;
2757 unsigned32 result32
;
2758 unsigned64 result64
;
2761 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2767 /* Round result to nearest representable value. When two
2768 representable values are equally near, round to the value
2769 that has a least significant bit of zero (i.e. is even). */
2770 round
= sim_fpu_round_near
;
2773 /* Round result to the value closest to, and not greater in
2774 magnitude than, the result. */
2775 round
= sim_fpu_round_zero
;
2778 /* Round result to the value closest to, and not less than,
2780 round
= sim_fpu_round_up
;
2784 /* Round result to the value closest to, and not greater than,
2786 round
= sim_fpu_round_down
;
2790 fprintf (stderr
, "Bad switch\n");
2794 /* Convert the input to sim_fpu internal format */
2798 sim_fpu_64to (&wop
, op
);
2801 sim_fpu_32to (&wop
, op
);
2804 sim_fpu_i32to (&wop
, op
, round
);
2807 sim_fpu_i64to (&wop
, op
, round
);
2810 fprintf (stderr
, "Bad switch\n");
2814 /* Convert sim_fpu format into the output */
2815 /* The value WOP is converted to the destination format, rounding
2816 using mode RM. When the destination is a fixed-point format, then
2817 a source value of Infinity, NaN or one which would round to an
2818 integer outside the fixed point range then an IEEE Invalid
2819 Operation condition is raised. */
2823 sim_fpu_round_32 (&wop
, round
, 0);
2824 sim_fpu_to32 (&result32
, &wop
);
2825 result64
= result32
;
2828 sim_fpu_round_64 (&wop
, round
, 0);
2829 sim_fpu_to64 (&result64
, &wop
);
2832 sim_fpu_to32i (&result32
, &wop
, round
);
2833 result64
= result32
;
2836 sim_fpu_to64i (&result64
, &wop
, round
);
2840 fprintf (stderr
, "Bad switch\n");
2845 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2852 /*-- co-processor support routines ------------------------------------------*/
2855 CoProcPresent(coproc_number
)
2856 unsigned int coproc_number
;
2858 /* Return TRUE if simulator provides a model for the given co-processor number */
2863 cop_lw (SIM_DESC sd
,
2868 unsigned int memword
)
2873 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2876 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2878 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2879 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2884 #if 0 /* this should be controlled by a configuration option */
2885 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2894 cop_ld (SIM_DESC sd
,
2901 switch (coproc_num
) {
2903 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2905 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2910 #if 0 /* this message should be controlled by a configuration option */
2911 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2920 cop_sw (SIM_DESC sd
,
2926 unsigned int value
= 0;
2931 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2934 hold
= FPR_STATE
[coproc_reg
];
2935 FPR_STATE
[coproc_reg
] = fmt_word
;
2936 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
2937 FPR_STATE
[coproc_reg
] = hold
;
2942 #if 0 /* should be controlled by configuration option */
2943 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2952 cop_sd (SIM_DESC sd
,
2962 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
2964 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
2969 #if 0 /* should be controlled by configuration option */
2970 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2979 decode_coproc (SIM_DESC sd
,
2982 unsigned int instruction
)
2984 int coprocnum
= ((instruction
>> 26) & 3);
2988 case 0: /* standard CPU control and cache registers */
2990 int code
= ((instruction
>> 21) & 0x1F);
2991 /* R4000 Users Manual (second edition) lists the following CP0
2993 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2994 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2995 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2996 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2997 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2998 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2999 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3000 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3001 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3002 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3004 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3006 int rt
= ((instruction
>> 16) & 0x1F);
3007 int rd
= ((instruction
>> 11) & 0x1F);
3009 switch (rd
) /* NOTEs: Standard CP0 registers */
3011 /* 0 = Index R4000 VR4100 VR4300 */
3012 /* 1 = Random R4000 VR4100 VR4300 */
3013 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3014 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3015 /* 4 = Context R4000 VR4100 VR4300 */
3016 /* 5 = PageMask R4000 VR4100 VR4300 */
3017 /* 6 = Wired R4000 VR4100 VR4300 */
3018 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3019 /* 9 = Count R4000 VR4100 VR4300 */
3020 /* 10 = EntryHi R4000 VR4100 VR4300 */
3021 /* 11 = Compare R4000 VR4100 VR4300 */
3022 /* 12 = SR R4000 VR4100 VR4300 */
3029 /* 13 = Cause R4000 VR4100 VR4300 */
3036 /* 14 = EPC R4000 VR4100 VR4300 */
3037 /* 15 = PRId R4000 VR4100 VR4300 */
3038 #ifdef SUBTARGET_R3900
3047 /* 16 = Config R4000 VR4100 VR4300 */
3050 GPR
[rt
] = C0_CONFIG
;
3052 C0_CONFIG
= GPR
[rt
];
3055 #ifdef SUBTARGET_R3900
3064 /* 17 = LLAddr R4000 VR4100 VR4300 */
3066 /* 18 = WatchLo R4000 VR4100 VR4300 */
3067 /* 19 = WatchHi R4000 VR4100 VR4300 */
3068 /* 20 = XContext R4000 VR4100 VR4300 */
3069 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3070 /* 27 = CacheErr R4000 VR4100 */
3071 /* 28 = TagLo R4000 VR4100 VR4300 */
3072 /* 29 = TagHi R4000 VR4100 VR4300 */
3073 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3074 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3075 /* CPR[0,rd] = GPR[rt]; */
3078 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3080 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3083 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3086 if (SR
& status_ERL
)
3088 /* Oops, not yet available */
3089 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3099 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3103 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3111 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3112 /* TODO: When executing an ERET or RFE instruction we should
3113 clear LLBIT, to ensure that any out-standing atomic
3114 read/modify/write sequence fails. */
3118 case 2: /* undefined co-processor */
3119 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3122 case 1: /* should not occur (FPU co-processor) */
3123 case 3: /* should not occur (FPU co-processor) */
3124 SignalException(ReservedInstruction
,instruction
);
3131 /*-- instruction simulation -------------------------------------------------*/
3133 /* When the IGEN simulator is being built, the function below is be
3134 replaced by a generated version. However, WITH_IGEN == 2 indicates
3135 that the fubction below should be compiled but under a different
3136 name (to allow backward compatibility) */
3138 #if (WITH_IGEN != 1)
3140 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3142 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3145 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3148 int next_cpu_nr
; /* ignore */
3149 int nr_cpus
; /* ignore */
3150 int siggnal
; /* ignore */
3152 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3153 #if !defined(FASTSIM)
3154 unsigned int pipeline_count
= 1;
3158 if (STATE_MEMORY (sd
) == NULL
) {
3159 printf("DBG: simulate() entered with no memory\n");
3164 #if 0 /* Disabled to check that everything works OK */
3165 /* The VR4300 seems to sign-extend the PC on its first
3166 access. However, this may just be because it is currently
3167 configured in 32bit mode. However... */
3168 PC
= SIGNEXTEND(PC
,32);
3171 /* main controlling loop */
3173 /* vaddr is slowly being replaced with cia - current instruction
3175 address_word cia
= (uword64
)PC
;
3176 address_word vaddr
= cia
;
3179 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3183 printf("DBG: state = 0x%08X :",state
);
3184 if (state
& simHALTEX
) printf(" simHALTEX");
3185 if (state
& simHALTIN
) printf(" simHALTIN");
3190 DSSTATE
= (STATE
& simDELAYSLOT
);
3193 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3196 /* Fetch the next instruction from the simulator memory: */
3197 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3198 if ((vaddr
& 1) == 0) {
3199 /* Copy the action of the LW instruction */
3200 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3201 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3204 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3205 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3206 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3207 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3209 /* Copy the action of the LH instruction */
3210 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3211 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3214 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3215 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3216 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3217 paddr
& ~ (uword64
) 1,
3218 vaddr
, isINSTRUCTION
, isREAL
);
3219 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3220 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3223 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3228 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3231 /* This is required by exception processing, to ensure that we can
3232 cope with exceptions in the delay slots of branches that may
3233 already have changed the PC. */
3234 if ((vaddr
& 1) == 0)
3235 PC
+= 4; /* increment ready for the next fetch */
3238 /* NOTE: If we perform a delay slot change to the PC, this
3239 increment is not requuired. However, it would make the
3240 simulator more complicated to try and avoid this small hit. */
3242 /* Currently this code provides a simple model. For more
3243 complicated models we could perform exception status checks at
3244 this point, and set the simSTOP state as required. This could
3245 also include processing any hardware interrupts raised by any
3246 I/O model attached to the simulator context.
3248 Support for "asynchronous" I/O events within the simulated world
3249 could be providing by managing a counter, and calling a I/O
3250 specific handler when a particular threshold is reached. On most
3251 architectures a decrement and check for zero operation is
3252 usually quicker than an increment and compare. However, the
3253 process of managing a known value decrement to zero, is higher
3254 than the cost of using an explicit value UINT_MAX into the
3255 future. Which system is used will depend on how complicated the
3256 I/O model is, and how much it is likely to affect the simulator
3259 If events need to be scheduled further in the future than
3260 UINT_MAX event ticks, then the I/O model should just provide its
3261 own counter, triggered from the event system. */
3263 /* MIPS pipeline ticks. To allow for future support where the
3264 pipeline hit of individual instructions is known, this control
3265 loop manages a "pipeline_count" variable. It is initialised to
3266 1 (one), and will only be changed by the simulator engine when
3267 executing an instruction. If the engine does not have access to
3268 pipeline cycle count information then all instructions will be
3269 treated as using a single cycle. NOTE: A standard system is not
3270 provided by the default simulator because different MIPS
3271 architectures have different cycle counts for the same
3274 [NOTE: pipeline_count has been replaced the event queue] */
3276 /* shuffle the floating point status pipeline state */
3277 ENGINE_ISSUE_PREFIX_HOOK();
3279 /* NOTE: For multi-context simulation environments the "instruction"
3280 variable should be local to this routine. */
3282 /* Shorthand accesses for engine. Note: If we wanted to use global
3283 variables (and a single-threaded simulator engine), then we can
3284 create the actual variables with these names. */
3286 if (!(STATE
& simSKIPNEXT
)) {
3287 /* Include the simulator engine */
3288 #include "oengine.c"
3289 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3290 #error "Mismatch between run-time simulator code and simulation engine"
3292 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3293 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3295 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3296 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3299 #if defined(WARN_LOHI)
3300 /* Decrement the HI/LO validity ticks */
3305 /* start-sanitize-r5900 */
3310 /* end-sanitize-r5900 */
3311 #endif /* WARN_LOHI */
3313 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3314 should check for it being changed. It is better doing it here,
3315 than within the simulator, since it will help keep the simulator
3318 #if defined(WARN_ZERO)
3319 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3320 #endif /* WARN_ZERO */
3321 ZERO
= 0; /* reset back to zero before next instruction */
3323 } else /* simSKIPNEXT check */
3324 STATE
&= ~simSKIPNEXT
;
3326 /* If the delay slot was active before the instruction is
3327 executed, then update the PC to its new value: */
3330 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3339 #if !defined(FASTSIM)
3340 if (sim_events_tickn (sd
, pipeline_count
))
3342 /* cpu->cia = cia; */
3343 sim_events_process (sd
);
3346 if (sim_events_tick (sd
))
3348 /* cpu->cia = cia; */
3349 sim_events_process (sd
);
3351 #endif /* FASTSIM */
3357 /* This code copied from gdb's utils.c. Would like to share this code,
3358 but don't know of a common place where both could get to it. */
3360 /* Temporary storage using circular buffer */
3366 static char buf
[NUMCELLS
][CELLSIZE
];
3368 if (++cell
>=NUMCELLS
) cell
=0;
3372 /* Print routines to handle variable size regs, etc */
3374 /* Eliminate warning from compiler on 32-bit systems */
3375 static int thirty_two
= 32;
3381 char *paddr_str
=get_cell();
3382 switch (sizeof(addr
))
3385 sprintf(paddr_str
,"%08lx%08lx",
3386 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3389 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3392 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3395 sprintf(paddr_str
,"%x",addr
);
3404 char *paddr_str
=get_cell();
3405 sprintf(paddr_str
,"%08lx%08lx",
3406 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3412 pending_tick (SIM_DESC sd
,
3417 sim_io_printf (sd
, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN
, PENDING_OUT
, PENDING_TOTAL
);
3418 if (PENDING_OUT
!= PENDING_IN
)
3421 int index
= PENDING_OUT
;
3422 int total
= PENDING_TOTAL
;
3423 if (PENDING_TOTAL
== 0)
3424 sim_engine_abort (SD
, CPU
, cia
, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3425 for (loop
= 0; (loop
< total
); loop
++)
3427 if (PENDING_SLOT_DEST
[index
] != NULL
)
3429 PENDING_SLOT_DELAY
[index
] -= 1;
3430 if (PENDING_SLOT_DELAY
[index
] == 0)
3432 if (PENDING_SLOT_BIT
[index
] >= 0)
3433 switch (PENDING_SLOT_SIZE
[index
])
3436 if (PENDING_SLOT_VALUE
[index
])
3437 *(unsigned32
*)PENDING_SLOT_DEST
[index
] |=
3438 BIT32 (PENDING_SLOT_BIT
[index
]);
3440 *(unsigned32
*)PENDING_SLOT_DEST
[index
] &=
3441 BIT32 (PENDING_SLOT_BIT
[index
]);
3444 if (PENDING_SLOT_VALUE
[index
])
3445 *(unsigned64
*)PENDING_SLOT_DEST
[index
] |=
3446 BIT64 (PENDING_SLOT_BIT
[index
]);
3448 *(unsigned64
*)PENDING_SLOT_DEST
[index
] &=
3449 BIT64 (PENDING_SLOT_BIT
[index
]);
3454 switch (PENDING_SLOT_SIZE
[index
])
3457 *(unsigned32
*)PENDING_SLOT_DEST
[index
] =
3458 PENDING_SLOT_VALUE
[index
];
3461 *(unsigned64
*)PENDING_SLOT_DEST
[index
] =
3462 PENDING_SLOT_VALUE
[index
];
3466 if (PENDING_OUT
== index
)
3468 PENDING_SLOT_DEST
[index
] = NULL
;
3469 PENDING_OUT
= (PENDING_OUT
+ 1) % PSLOTS
;
3474 index
= (index
+ 1) % PSLOTS
;
3478 /*---------------------------------------------------------------------------*/
3479 /*> EOF interp.c <*/