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* sim-main.h: shadow NUM_CORE_REGS from tm-txvu.h
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Date$
18
19 NOTEs:
20
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
24 code on the hardware.
25
26 */
27
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
32 #define TRACE (1)
33 #endif
34
35 #include "bfd.h"
36 #include "sim-main.h"
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
40 #include "sim-hw.h"
41
42 /* start-sanitize-sky */
43 #ifdef TARGET_SKY
44 #include "sky-vu.h"
45 #include "sky-vpe.h"
46 #include "sky-libvpe.h"
47 #include "sky-pke.h"
48 #include "idecode.h"
49 #include "sky-gdb.h"
50 #endif
51 /* end-sanitize-sky */
52
53 #include "config.h"
54
55 #include <stdio.h>
56 #include <stdarg.h>
57 #include <ansidecl.h>
58 #include <ctype.h>
59 #include <limits.h>
60 #include <math.h>
61 #ifdef HAVE_STDLIB_H
62 #include <stdlib.h>
63 #endif
64 #ifdef HAVE_STRING_H
65 #include <string.h>
66 #else
67 #ifdef HAVE_STRINGS_H
68 #include <strings.h>
69 #endif
70 #endif
71
72 #include "getopt.h"
73 #include "libiberty.h"
74 #include "bfd.h"
75 #include "callback.h" /* GDB simulator callback interface */
76 #include "remote-sim.h" /* GDB simulator interface */
77
78 #include "sysdep.h"
79
80 #ifndef PARAMS
81 #define PARAMS(x)
82 #endif
83
84 char* pr_addr PARAMS ((SIM_ADDR addr));
85 char* pr_uword64 PARAMS ((uword64 addr));
86
87
88 /* Get the simulator engine description, without including the code: */
89 #if !(WITH_IGEN)
90 #define SIM_MANIFESTS
91 #include "oengine.c"
92 #undef SIM_MANIFESTS
93 #endif
94
95 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
96 #define CPU cpu
97 #define SD sd
98
99
100 /* The following reserved instruction value is used when a simulator
101 trap is required. NOTE: Care must be taken, since this value may be
102 used in later revisions of the MIPS ISA. */
103
104 #define RSVD_INSTRUCTION (0x00000005)
105 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
106
107 #define RSVD_INSTRUCTION_ARG_SHIFT 6
108 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
109
110
111 /* Bits in the Debug register */
112 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
113 #define Debug_DM 0x40000000 /* Debug Mode */
114 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
115
116 /*---------------------------------------------------------------------------*/
117 /*-- GDB simulator interface ------------------------------------------------*/
118 /*---------------------------------------------------------------------------*/
119
120 static void ColdReset PARAMS((SIM_DESC sd));
121
122 /*---------------------------------------------------------------------------*/
123
124
125
126 #define DELAYSLOT() {\
127 if (STATE & simDELAYSLOT)\
128 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
129 STATE |= simDELAYSLOT;\
130 }
131
132 #define JALDELAYSLOT() {\
133 DELAYSLOT ();\
134 STATE |= simJALDELAYSLOT;\
135 }
136
137 #define NULLIFY() {\
138 STATE &= ~simDELAYSLOT;\
139 STATE |= simSKIPNEXT;\
140 }
141
142 #define CANCELDELAYSLOT() {\
143 DSSTATE = 0;\
144 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
145 }
146
147 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
148 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
149
150 #define K0BASE (0x80000000)
151 #define K0SIZE (0x20000000)
152 #define K1BASE (0xA0000000)
153 #define K1SIZE (0x20000000)
154 #define MONITOR_BASE (0xBFC00000)
155 #define MONITOR_SIZE (1 << 11)
156 #define MEM_SIZE (2 << 20)
157
158 /* start-sanitize-sky */
159 #ifdef TARGET_SKY
160 #undef MEM_SIZE
161 #define MEM_SIZE (16 << 20) /* 16 MB */
162 #endif
163 /* end-sanitize-sky */
164
165 #if defined(TRACE)
166 static char *tracefile = "trace.din"; /* default filename for trace log */
167 FILE *tracefh = NULL;
168 static void open_trace PARAMS((SIM_DESC sd));
169 #endif /* TRACE */
170
171 /* simulation target board. NULL=canonical */
172 static char* board = NULL;
173
174
175 static DECLARE_OPTION_HANDLER (mips_option_handler);
176
177 enum {
178 OPTION_DINERO_TRACE = OPTION_START,
179 OPTION_DINERO_FILE,
180 /* start-stanitize-branchbug4011 */
181 OPTION_BRANCH_BUG_4011,
182 /* end-stanitize-branchbug4011 */
183 OPTION_BOARD
184 };
185
186
187 static SIM_RC
188 mips_option_handler (sd, cpu, opt, arg, is_command)
189 SIM_DESC sd;
190 sim_cpu *cpu;
191 int opt;
192 char *arg;
193 int is_command;
194 {
195 int cpu_nr;
196 switch (opt)
197 {
198 /* start-sanitize-branchbug4011 */
199 case OPTION_BRANCH_BUG_4011:
200 {
201 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
202 {
203 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
204 if (arg == NULL)
205 BRANCHBUG4011_OPTION = 1;
206 else if (strcmp (arg, "yes") == 0)
207 BRANCHBUG4011_OPTION = 1;
208 else if (strcmp (arg, "no") == 0)
209 BRANCHBUG4011_OPTION = 0;
210 else if (strcmp (arg, "on") == 0)
211 BRANCHBUG4011_OPTION = 1;
212 else if (strcmp (arg, "off") == 0)
213 BRANCHBUG4011_OPTION = 0;
214 else
215 {
216 fprintf (stderr, "Unrecognized check-4011-branch-bug option `%s'\n", arg);
217 return SIM_RC_FAIL;
218 }
219 }
220 return SIM_RC_OK;
221 }
222
223 /* end-sanitize-branchbug4011 */
224 case OPTION_DINERO_TRACE: /* ??? */
225 #if defined(TRACE)
226 /* Eventually the simTRACE flag could be treated as a toggle, to
227 allow external control of the program points being traced
228 (i.e. only from main onwards, excluding the run-time setup,
229 etc.). */
230 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
231 {
232 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
233 if (arg == NULL)
234 STATE |= simTRACE;
235 else if (strcmp (arg, "yes") == 0)
236 STATE |= simTRACE;
237 else if (strcmp (arg, "no") == 0)
238 STATE &= ~simTRACE;
239 else if (strcmp (arg, "on") == 0)
240 STATE |= simTRACE;
241 else if (strcmp (arg, "off") == 0)
242 STATE &= ~simTRACE;
243 else
244 {
245 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
246 return SIM_RC_FAIL;
247 }
248 }
249 return SIM_RC_OK;
250 #else /* !TRACE */
251 fprintf(stderr,"\
252 Simulator constructed without dinero tracing support (for performance).\n\
253 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
254 return SIM_RC_FAIL;
255 #endif /* !TRACE */
256
257 case OPTION_DINERO_FILE:
258 #if defined(TRACE)
259 if (optarg != NULL) {
260 char *tmp;
261 tmp = (char *)malloc(strlen(optarg) + 1);
262 if (tmp == NULL)
263 {
264 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
265 return SIM_RC_FAIL;
266 }
267 else {
268 strcpy(tmp,optarg);
269 tracefile = tmp;
270 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
271 }
272 }
273 #endif /* TRACE */
274 return SIM_RC_OK;
275
276 case OPTION_BOARD:
277 {
278 if (arg)
279 {
280 board = zalloc(strlen(arg) + 1);
281 strcpy(board, arg);
282 }
283 return SIM_RC_OK;
284 }
285 }
286
287 return SIM_RC_OK;
288 }
289
290
291 static const OPTION mips_options[] =
292 {
293 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
294 '\0', "on|off", "Enable dinero tracing",
295 mips_option_handler },
296 /* start-sanitize-branchbug4011 */
297 { {"check-4011-branch-bug", optional_argument, NULL, OPTION_BRANCH_BUG_4011},
298 '\0', "on|off", "Enable checking for 4011 branch bug",
299 mips_option_handler },
300 /* end-sanitize-branchbug4011 */
301 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
302 '\0', "FILE", "Write dinero trace to FILE",
303 mips_option_handler },
304 { {"board", required_argument, NULL, OPTION_BOARD},
305 '\0', "none" /* rely on compile-time string concatenation for other options */
306
307 /* start-sanitize-tx3904 */
308 #define BOARD_JMR3904 "jmr3904"
309 "|" BOARD_JMR3904
310 #define BOARD_JMR3904_PAL "jmr3904pal"
311 "|" BOARD_JMR3904_PAL
312 #define BOARD_JMR3904_DEBUG "jmr3904debug"
313 "|" BOARD_JMR3904_DEBUG
314 /* end-sanitize-tx3904 */
315
316 , "Customize simulation for a particular board.", mips_option_handler },
317
318 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
319 };
320
321
322 int interrupt_pending;
323
324 void
325 interrupt_event (SIM_DESC sd, void *data)
326 {
327 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
328 address_word cia = CIA_GET (cpu);
329 if (SR & status_IE)
330 {
331 interrupt_pending = 0;
332 SignalExceptionInterrupt ();
333 }
334 else if (!interrupt_pending)
335 sim_events_schedule (sd, 1, interrupt_event, data);
336 }
337
338
339 /*---------------------------------------------------------------------------*/
340 /*-- Device registration hook -----------------------------------------------*/
341 /*---------------------------------------------------------------------------*/
342 static void device_init(SIM_DESC sd) {
343 #ifdef DEVICE_INIT
344 extern void register_devices(SIM_DESC);
345 register_devices(sd);
346 #endif
347 }
348
349 /*---------------------------------------------------------------------------*/
350 /*-- GDB simulator interface ------------------------------------------------*/
351 /*---------------------------------------------------------------------------*/
352
353 SIM_DESC
354 sim_open (kind, cb, abfd, argv)
355 SIM_OPEN_KIND kind;
356 host_callback *cb;
357 struct _bfd *abfd;
358 char **argv;
359 {
360 SIM_DESC sd = sim_state_alloc (kind, cb);
361 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
362
363 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
364
365 /* FIXME: watchpoints code shouldn't need this */
366 STATE_WATCHPOINTS (sd)->pc = &(PC);
367 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
368 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
369
370 STATE = 0;
371
372 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
373 return 0;
374 sim_add_option_table (sd, NULL, mips_options);
375
376 /* start-sanitize-sky */
377 #ifdef TARGET_SKY
378 sky_command_options_open (sd);
379 #endif
380 /* end-sanitize-sky */
381
382 /* getopt will print the error message so we just have to exit if this fails.
383 FIXME: Hmmm... in the case of gdb we need getopt to call
384 print_filtered. */
385 if (sim_parse_args (sd, argv) != SIM_RC_OK)
386 {
387 /* Uninstall the modules to avoid memory leaks,
388 file descriptor leaks, etc. */
389 sim_module_uninstall (sd);
390 return 0;
391 }
392
393 /* handle board-specific memory maps */
394 if (board == NULL)
395 {
396 /* Allocate core managed memory */
397
398 /* start-sanitize-sky */
399 #ifndef TARGET_SKY
400 /* end-sanitize-sky */
401 /* the monitor */
402 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
403 /* For compatibility with the old code - under this (at level one)
404 are the kernel spaces K0 & K1. Both of these map to a single
405 smaller sub region */
406 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
407 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
408 K1BASE, K0SIZE,
409 MEM_SIZE, /* actual size */
410 K0BASE);
411 /* start-sanitize-sky */
412 #else
413 /* the monitor */
414 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE - K1BASE, MONITOR_SIZE);
415 sim_do_command (sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
416 /* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
417 address_translation() */
418 sim_do_commandf (sd, "memory size 0x%lx", MEM_SIZE);
419 #endif
420 /* end-sanitize-sky */
421
422 device_init(sd);
423 }
424
425 /* start-sanitize-tx3904 */
426 #if (WITH_HW)
427 if (board != NULL
428 && (strcmp(board, BOARD_JMR3904) == 0 ||
429 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
430 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
431 {
432 /* match VIRTUAL memory layout of JMR-TX3904 board */
433
434 /* --- memory --- */
435
436 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
437 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
438 0x9FC00000,
439 4 * 1024 * 1024, /* 4 MB */
440 0xBFC00000);
441
442 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
443 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
444 0x80000000,
445 4 * 1024 * 1024, /* 4 MB */
446 0xA0000000);
447
448 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
449 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
450 0x88000000,
451 32 * 1024 * 1024, /* 32 MB */
452 0xA8000000);
453
454 /* --- simulated devices --- */
455 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
456 sim_hw_parse (sd, "/tx3904cpu");
457 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
458 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
459 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
460
461 /* -- device connections --- */
462 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
463 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
464 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
465 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
466
467 /* add PAL timer & I/O module */
468 if(! strcmp(board, BOARD_JMR3904_PAL))
469 {
470 /* the device */
471 sim_hw_parse (sd, "/pal@0xffff0000");
472 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
473
474 /* wire up interrupt ports to irc */
475 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
476 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
477 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
478 }
479
480 if(! strcmp(board, BOARD_JMR3904_DEBUG))
481 {
482 /* -- DEBUG: glue interrupt generators --- */
483 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
484 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
485 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
486 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
487 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
488 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
489 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
490 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
491 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
492 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
493 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
494 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
495 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
496 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
497 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
498 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
499 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
500 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
501 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
502 }
503
504 device_init(sd);
505 }
506 #endif
507 /* end-sanitize-tx3904 */
508
509
510 /* check for/establish the a reference program image */
511 if (sim_analyze_program (sd,
512 (STATE_PROG_ARGV (sd) != NULL
513 ? *STATE_PROG_ARGV (sd)
514 : NULL),
515 abfd) != SIM_RC_OK)
516 {
517 sim_module_uninstall (sd);
518 return 0;
519 }
520
521 /* Configure/verify the target byte order and other runtime
522 configuration options */
523 if (sim_config (sd) != SIM_RC_OK)
524 {
525 sim_module_uninstall (sd);
526 return 0;
527 }
528
529 if (sim_post_argv_init (sd) != SIM_RC_OK)
530 {
531 /* Uninstall the modules to avoid memory leaks,
532 file descriptor leaks, etc. */
533 sim_module_uninstall (sd);
534 return 0;
535 }
536
537 /* verify assumptions the simulator made about the host type system.
538 This macro does not return if there is a problem */
539 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
540 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
541
542 /* This is NASTY, in that we are assuming the size of specific
543 registers: */
544 {
545 int rn;
546 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
547 {
548 if (rn < 32)
549 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
550 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
551 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
552 else if ((rn >= 33) && (rn <= 37))
553 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
554 else if ((rn == SRIDX)
555 || (rn == FCR0IDX)
556 || (rn == FCR31IDX)
557 || ((rn >= 72) && (rn <= 89)))
558 cpu->register_widths[rn] = 32;
559 else
560 cpu->register_widths[rn] = 0;
561 }
562 /* start-sanitize-r5900 */
563
564 /* set the 5900 "upper" registers to 64 bits */
565 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
566 cpu->register_widths[rn] = 64;
567 /* end-sanitize-r5900 */
568
569 /* start-sanitize-sky */
570 #ifdef TARGET_SKY
571 /* Now the VU registers */
572 for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
573 cpu->register_widths[rn + NUM_CORE_REGS] = 16;
574 cpu->register_widths[rn + NUM_CORE_REGS + NUM_VU_REGS] = 16;
575 }
576
577 for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
578 cpu->register_widths[rn + NUM_CORE_REGS] = 32;
579 cpu->register_widths[rn + NUM_CORE_REGS + NUM_VU_REGS] = 32;
580 }
581
582 /* Finally the VIF registers */
583 for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
584 cpu->register_widths[rn + NUM_CORE_REGS] = 32;
585
586 cpu->cur_device = 0;
587 #endif
588 /* end-sanitize-sky */
589 }
590
591 #if defined(TRACE)
592 if (STATE & simTRACE)
593 open_trace(sd);
594 #endif /* TRACE */
595
596 /* Write an abort sequence into the TRAP (common) exception vector
597 addresses. This is to catch code executing a TRAP (et.al.)
598 instruction without installing a trap handler. */
599 {
600 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
601 HALT_INSTRUCTION /* BREAK */ };
602 H2T (halt[0]);
603 H2T (halt[1]);
604 sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
605 sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
606 }
607
608
609 /* Write the monitor trap address handlers into the monitor (eeprom)
610 address space. This can only be done once the target endianness
611 has been determined. */
612 {
613 unsigned loop;
614 /* Entry into the IDT monitor is via fixed address vectors, and
615 not using machine instructions. To avoid clashing with use of
616 the MIPS TRAP system, we place our own (simulator specific)
617 "undefined" instructions into the relevant vector slots. */
618 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
619 {
620 address_word vaddr = (MONITOR_BASE + loop);
621 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
622 H2T (insn);
623 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
624 }
625 /* The PMON monitor uses the same address space, but rather than
626 branching into it the address of a routine is loaded. We can
627 cheat for the moment, and direct the PMON routine to IDT style
628 instructions within the monitor space. This relies on the IDT
629 monitor not using the locations from 0xBFC00500 onwards as its
630 entry points.*/
631 for (loop = 0; (loop < 24); loop++)
632 {
633 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
634 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
635 switch (loop)
636 {
637 case 0: /* read */
638 value = 7;
639 break;
640 case 1: /* write */
641 value = 8;
642 break;
643 case 2: /* open */
644 value = 6;
645 break;
646 case 3: /* close */
647 value = 10;
648 break;
649 case 5: /* printf */
650 value = ((0x500 - 16) / 8); /* not an IDT reason code */
651 break;
652 case 8: /* cliexit */
653 value = 17;
654 break;
655 case 11: /* flush_cache */
656 value = 28;
657 break;
658 }
659 /* FIXME - should monitor_base be SIM_ADDR?? */
660 value = ((unsigned int)MONITOR_BASE + (value * 8));
661 H2T (value);
662 sim_write (sd, vaddr, (char *)&value, sizeof (value));
663
664 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
665 vaddr -= 0x300;
666 sim_write (sd, vaddr, (char *)&value, sizeof (value));
667 }
668 }
669
670 return sd;
671 }
672
673 #if defined(TRACE)
674 static void
675 open_trace(sd)
676 SIM_DESC sd;
677 {
678 tracefh = fopen(tracefile,"wb+");
679 if (tracefh == NULL)
680 {
681 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
682 tracefh = stderr;
683 }
684 }
685 #endif /* TRACE */
686
687 void
688 sim_close (sd, quitting)
689 SIM_DESC sd;
690 int quitting;
691 {
692 #ifdef DEBUG
693 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
694 #endif
695
696 /* start-sanitize-sky */
697 #ifdef TARGET_SKY
698 sky_command_options_close (sd);
699 #endif
700 /* end-sanitize-sky */
701
702
703 /* "quitting" is non-zero if we cannot hang on errors */
704
705 /* Ensure that any resources allocated through the callback
706 mechanism are released: */
707 sim_io_shutdown (sd);
708
709 #if defined(TRACE)
710 if (tracefh != NULL && tracefh != stderr)
711 fclose(tracefh);
712 tracefh = NULL;
713 #endif /* TRACE */
714
715 /* FIXME - free SD */
716
717 return;
718 }
719
720
721 int
722 sim_write (sd,addr,buffer,size)
723 SIM_DESC sd;
724 SIM_ADDR addr;
725 unsigned char *buffer;
726 int size;
727 {
728 int index;
729 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
730
731 /* Return the number of bytes written, or zero if error. */
732 #ifdef DEBUG
733 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
734 #endif
735
736 /* We use raw read and write routines, since we do not want to count
737 the GDB memory accesses in our statistics gathering. */
738
739 for (index = 0; index < size; index++)
740 {
741 address_word vaddr = (address_word)addr + index;
742 address_word paddr;
743 int cca;
744 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
745 break;
746 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
747 break;
748 }
749
750 return(index);
751 }
752
753 int
754 sim_read (sd,addr,buffer,size)
755 SIM_DESC sd;
756 SIM_ADDR addr;
757 unsigned char *buffer;
758 int size;
759 {
760 int index;
761 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
762
763 /* Return the number of bytes read, or zero if error. */
764 #ifdef DEBUG
765 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
766 #endif /* DEBUG */
767
768 for (index = 0; (index < size); index++)
769 {
770 address_word vaddr = (address_word)addr + index;
771 address_word paddr;
772 int cca;
773 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
774 break;
775 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
776 break;
777 }
778
779 return(index);
780 }
781
782 int
783 sim_store_register (sd,rn,memory,length)
784 SIM_DESC sd;
785 int rn;
786 unsigned char *memory;
787 int length;
788 {
789 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
790 /* NOTE: gdb (the client) stores registers in target byte order
791 while the simulator uses host byte order */
792 #ifdef DEBUG
793 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
794 #endif /* DEBUG */
795
796 /* Unfortunately this suffers from the same problem as the register
797 numbering one. We need to know what the width of each logical
798 register number is for the architecture being simulated. */
799
800 if (cpu->register_widths[rn] == 0)
801 {
802 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
803 return 0;
804 }
805
806 /* start-sanitize-r5900 */
807 if (rn >= 90 && rn < 90 + 32)
808 {
809 GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
810 return 8;
811 }
812 switch (rn)
813 {
814 case REGISTER_SA:
815 SA = T2H_8(*(unsigned64*)memory);
816 return 8;
817 case 122: /* FIXME */
818 LO1 = T2H_8(*(unsigned64*)memory);
819 return 8;
820 case 123: /* FIXME */
821 HI1 = T2H_8(*(unsigned64*)memory);
822 return 8;
823 }
824 /* end-sanitize-r5900 */
825
826 /* start-sanitize-sky */
827 #ifdef TARGET_SKY
828 if (rn >= NUM_CORE_REGS)
829 {
830 rn = rn - NUM_CORE_REGS;
831
832 if( rn < NUM_VU_REGS )
833 {
834 if (rn < NUM_VU_INTEGER_REGS)
835 return write_vu_int_reg (&(vu0_device.regs), rn, memory);
836 else if (rn >= FIRST_VEC_REG)
837 {
838 rn -= FIRST_VEC_REG;
839 return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
840 memory);
841 }
842 else switch (rn - NUM_VU_INTEGER_REGS)
843 {
844 case 0:
845 return write_vu_special_reg (&vu0_device, VU_REG_CIA,
846 memory);
847 case 1:
848 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
849 memory);
850 case 2: /* VU0 has no P register */
851 return 4;
852 case 3:
853 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
854 memory);
855 case 4:
856 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
857 memory);
858 default:
859 return write_vu_acc_reg (&(vu0_device.regs),
860 rn - (NUM_VU_INTEGER_REGS + 5),
861 memory);
862 }
863 }
864
865 rn = rn - NUM_VU_REGS;
866
867 if (rn < NUM_VU_REGS)
868 {
869 if (rn < NUM_VU_INTEGER_REGS)
870 return write_vu_int_reg (&(vu1_device.regs), rn, memory);
871 else if (rn >= FIRST_VEC_REG)
872 {
873 rn -= FIRST_VEC_REG;
874 return write_vu_vec_reg (&(vu1_device.regs),
875 rn >> 2, rn & 3, memory);
876 }
877 else switch (rn - NUM_VU_INTEGER_REGS)
878 {
879 case 0:
880 return write_vu_special_reg (&vu1_device, VU_REG_CIA,
881 memory);
882 case 1:
883 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
884 memory);
885 case 2:
886 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
887 memory);
888 case 3:
889 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
890 memory);
891 case 4:
892 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
893 memory);
894 default:
895 return write_vu_acc_reg (&(vu1_device.regs),
896 rn - (NUM_VU_INTEGER_REGS + 5),
897 memory);
898 }
899 }
900
901 rn -= NUM_VU_REGS; /* VIF0 registers are next */
902
903 if (rn < NUM_VIF_REGS)
904 {
905 if (rn < NUM_VIF_REGS-1)
906 return write_pke_reg (&pke0_device, rn, memory);
907 else
908 {
909 sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
910 return 0;
911 }
912 }
913
914 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
915
916 if (rn < NUM_VIF_REGS)
917 {
918 if (rn < NUM_VIF_REGS-1)
919 return write_pke_reg (&pke1_device, rn, memory);
920 else
921 {
922 sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
923 return 0;
924 }
925 }
926
927 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
928 return 0;
929 }
930 #endif
931 /* end-sanitize-sky */
932
933 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
934 {
935 if (cpu->register_widths[rn] == 32)
936 {
937 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
938 return 4;
939 }
940 else
941 {
942 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
943 return 8;
944 }
945 }
946
947 if (cpu->register_widths[rn] == 32)
948 {
949 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
950 return 4;
951 }
952 else
953 {
954 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
955 return 8;
956 }
957
958 return 0;
959 }
960
961 int
962 sim_fetch_register (sd,rn,memory,length)
963 SIM_DESC sd;
964 int rn;
965 unsigned char *memory;
966 int length;
967 {
968 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
969 /* NOTE: gdb (the client) stores registers in target byte order
970 while the simulator uses host byte order */
971 #ifdef DEBUG
972 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
973 #endif /* DEBUG */
974
975 if (cpu->register_widths[rn] == 0)
976 {
977 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
978 return 0;
979 }
980
981 /* start-sanitize-r5900 */
982 if (rn >= 90 && rn < 90 + 32)
983 {
984 *((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
985 return 8;
986 }
987 switch (rn)
988 {
989 case REGISTER_SA:
990 *((unsigned64*)memory) = H2T_8(SA);
991 return 8;
992 case 122: /* FIXME */
993 *((unsigned64*)memory) = H2T_8(LO1);
994 return 8;
995 case 123: /* FIXME */
996 *((unsigned64*)memory) = H2T_8(HI1);
997 return 8;
998 }
999 /* end-sanitize-r5900 */
1000
1001 /* start-sanitize-sky */
1002 #ifdef TARGET_SKY
1003 if (rn >= NUM_CORE_REGS)
1004 {
1005 rn = rn - NUM_CORE_REGS;
1006
1007 if (rn < NUM_VU_REGS)
1008 {
1009 if (rn < NUM_VU_INTEGER_REGS)
1010 return read_vu_int_reg (&(vu0_device.regs), rn, memory);
1011 else if (rn >= FIRST_VEC_REG)
1012 {
1013 rn -= FIRST_VEC_REG;
1014 return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
1015 memory);
1016 }
1017 else switch (rn - NUM_VU_INTEGER_REGS)
1018 {
1019 case 0:
1020 return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
1021 case 1:
1022 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
1023 memory);
1024 case 2: /* VU0 has no P register */
1025 *((int *) memory) = 0;
1026 return 4;
1027 case 3:
1028 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
1029 memory);
1030 case 4:
1031 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
1032 memory);
1033 default:
1034 return read_vu_acc_reg (&(vu0_device.regs),
1035 rn - (NUM_VU_INTEGER_REGS + 5),
1036 memory);
1037 }
1038 }
1039
1040 rn -= NUM_VU_REGS; /* VU1 registers are next */
1041
1042 if (rn < NUM_VU_REGS)
1043 {
1044 if (rn < NUM_VU_INTEGER_REGS)
1045 return read_vu_int_reg (&(vu1_device.regs), rn, memory);
1046 else if (rn >= FIRST_VEC_REG)
1047 {
1048 rn -= FIRST_VEC_REG;
1049 return read_vu_vec_reg (&(vu1_device.regs),
1050 rn >> 2, rn & 3, memory);
1051 }
1052 else switch (rn - NUM_VU_INTEGER_REGS)
1053 {
1054 case 0:
1055 return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
1056 case 1:
1057 return read_vu_misc_reg (&(vu1_device.regs),
1058 VU_REG_MR, memory);
1059 case 2:
1060 return read_vu_misc_reg (&(vu1_device.regs),
1061 VU_REG_MP, memory);
1062 case 3:
1063 return read_vu_misc_reg (&(vu1_device.regs),
1064 VU_REG_MI, memory);
1065 case 4:
1066 return read_vu_misc_reg (&(vu1_device.regs),
1067 VU_REG_MQ, memory);
1068 default:
1069 return read_vu_acc_reg (&(vu1_device.regs),
1070 rn - (NUM_VU_INTEGER_REGS + 5),
1071 memory);
1072 }
1073 }
1074
1075 rn -= NUM_VU_REGS; /* VIF0 registers are next */
1076
1077 if (rn < NUM_VIF_REGS)
1078 {
1079 if (rn < NUM_VIF_REGS-2)
1080 return read_pke_reg (&pke0_device, rn, memory);
1081 else if (rn == NUM_VIF_REGS-2)
1082 return read_pke_pc (&pke0_device, memory);
1083 else
1084 return read_pke_pcx (&pke0_device, memory);
1085 }
1086
1087 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
1088
1089 if (rn < NUM_VIF_REGS)
1090 {
1091 if (rn < NUM_VIF_REGS-2)
1092 return read_pke_reg (&pke1_device, rn, memory);
1093 else if (rn == NUM_VIF_REGS-2)
1094 return read_pke_pc (&pke1_device, memory);
1095 else
1096 return read_pke_pcx (&pke1_device, memory);
1097 }
1098
1099 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
1100 }
1101 #endif
1102 /* end-sanitize-sky */
1103
1104 /* Any floating point register */
1105 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
1106 {
1107 if (cpu->register_widths[rn] == 32)
1108 {
1109 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
1110 return 4;
1111 }
1112 else
1113 {
1114 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
1115 return 8;
1116 }
1117 }
1118
1119 if (cpu->register_widths[rn] == 32)
1120 {
1121 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1122 return 4;
1123 }
1124 else
1125 {
1126 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
1127 return 8;
1128 }
1129
1130 return 0;
1131 }
1132
1133
1134 SIM_RC
1135 sim_create_inferior (sd, abfd, argv,env)
1136 SIM_DESC sd;
1137 struct _bfd *abfd;
1138 char **argv;
1139 char **env;
1140 {
1141
1142 #ifdef DEBUG
1143 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1144 pr_addr(PC));
1145 #endif /* DEBUG */
1146
1147 ColdReset(sd);
1148
1149 if (abfd != NULL)
1150 {
1151 /* override PC value set by ColdReset () */
1152 int cpu_nr;
1153 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1154 {
1155 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1156 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1157 }
1158 }
1159
1160 #if 0 /* def DEBUG */
1161 if (argv || env)
1162 {
1163 /* We should really place the argv slot values into the argument
1164 registers, and onto the stack as required. However, this
1165 assumes that we have a stack defined, which is not
1166 necessarily true at the moment. */
1167 char **cptr;
1168 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1169 for (cptr = argv; (cptr && *cptr); cptr++)
1170 printf("DBG: arg \"%s\"\n",*cptr);
1171 }
1172 #endif /* DEBUG */
1173
1174 return SIM_RC_OK;
1175 }
1176
1177 void
1178 sim_do_command (sd,cmd)
1179 SIM_DESC sd;
1180 char *cmd;
1181 {
1182 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1183 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1184 cmd);
1185 }
1186
1187 /*---------------------------------------------------------------------------*/
1188 /*-- Private simulator support interface ------------------------------------*/
1189 /*---------------------------------------------------------------------------*/
1190
1191 /* Read a null terminated string from memory, return in a buffer */
1192 static char *
1193 fetch_str (sd, addr)
1194 SIM_DESC sd;
1195 address_word addr;
1196 {
1197 char *buf;
1198 int nr = 0;
1199 char null;
1200 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1201 nr++;
1202 buf = NZALLOC (char, nr + 1);
1203 sim_read (sd, addr, buf, nr);
1204 return buf;
1205 }
1206
1207 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1208 static void
1209 sim_monitor (SIM_DESC sd,
1210 sim_cpu *cpu,
1211 address_word cia,
1212 unsigned int reason)
1213 {
1214 #ifdef DEBUG
1215 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1216 #endif /* DEBUG */
1217
1218 /* The IDT monitor actually allows two instructions per vector
1219 slot. However, the simulator currently causes a trap on each
1220 individual instruction. We cheat, and lose the bottom bit. */
1221 reason >>= 1;
1222
1223 /* The following callback functions are available, however the
1224 monitor we are simulating does not make use of them: get_errno,
1225 isatty, lseek, rename, system, time and unlink */
1226 switch (reason)
1227 {
1228
1229 case 6: /* int open(char *path,int flags) */
1230 {
1231 char *path = fetch_str (sd, A0);
1232 V0 = sim_io_open (sd, path, (int)A1);
1233 zfree (path);
1234 break;
1235 }
1236
1237 case 7: /* int read(int file,char *ptr,int len) */
1238 {
1239 int fd = A0;
1240 int nr = A2;
1241 char *buf = zalloc (nr);
1242 V0 = sim_io_read (sd, fd, buf, nr);
1243 sim_write (sd, A1, buf, nr);
1244 zfree (buf);
1245 }
1246 break;
1247
1248 case 8: /* int write(int file,char *ptr,int len) */
1249 {
1250 int fd = A0;
1251 int nr = A2;
1252 char *buf = zalloc (nr);
1253 sim_read (sd, A1, buf, nr);
1254 V0 = sim_io_write (sd, fd, buf, nr);
1255 zfree (buf);
1256 break;
1257 }
1258
1259 case 10: /* int close(int file) */
1260 {
1261 V0 = sim_io_close (sd, (int)A0);
1262 break;
1263 }
1264
1265 case 2: /* Densan monitor: char inbyte(int waitflag) */
1266 {
1267 if (A0 == 0) /* waitflag == NOWAIT */
1268 V0 = (unsigned_word)-1;
1269 }
1270 /* Drop through to case 11 */
1271
1272 case 11: /* char inbyte(void) */
1273 {
1274 char tmp;
1275 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1276 {
1277 sim_io_error(sd,"Invalid return from character read");
1278 V0 = (unsigned_word)-1;
1279 }
1280 else
1281 V0 = (unsigned_word)tmp;
1282 break;
1283 }
1284
1285 case 3: /* Densan monitor: void co(char chr) */
1286 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1287 {
1288 char tmp = (char)(A0 & 0xFF);
1289 sim_io_write_stdout (sd, &tmp, sizeof(char));
1290 break;
1291 }
1292
1293 case 17: /* void _exit() */
1294 {
1295 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1296 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1297 (unsigned int)(A0 & 0xFFFFFFFF));
1298 break;
1299 }
1300
1301 case 28 : /* PMON flush_cache */
1302 break;
1303
1304 case 55: /* void get_mem_info(unsigned int *ptr) */
1305 /* in: A0 = pointer to three word memory location */
1306 /* out: [A0 + 0] = size */
1307 /* [A0 + 4] = instruction cache size */
1308 /* [A0 + 8] = data cache size */
1309 {
1310 unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
1311 unsigned_4 zero = 0;
1312 H2T (value);
1313 sim_write (sd, A0 + 0, (char *)&value, 4);
1314 sim_write (sd, A0 + 4, (char *)&zero, 4);
1315 sim_write (sd, A0 + 8, (char *)&zero, 4);
1316 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1317 break;
1318 }
1319
1320 case 158 : /* PMON printf */
1321 /* in: A0 = pointer to format string */
1322 /* A1 = optional argument 1 */
1323 /* A2 = optional argument 2 */
1324 /* A3 = optional argument 3 */
1325 /* out: void */
1326 /* The following is based on the PMON printf source */
1327 {
1328 address_word s = A0;
1329 char c;
1330 signed_word *ap = &A1; /* 1st argument */
1331 /* This isn't the quickest way, since we call the host print
1332 routine for every character almost. But it does avoid
1333 having to allocate and manage a temporary string buffer. */
1334 /* TODO: Include check that we only use three arguments (A1,
1335 A2 and A3) */
1336 while (sim_read (sd, s++, &c, 1) && c != '\0')
1337 {
1338 if (c == '%')
1339 {
1340 char tmp[40];
1341 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1342 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1343 while (sim_read (sd, s++, &c, 1) && c != '\0')
1344 {
1345 if (strchr ("dobxXulscefg%", c))
1346 break;
1347 else if (c == '-')
1348 fmt = FMT_LJUST;
1349 else if (c == '0')
1350 fmt = FMT_RJUST0;
1351 else if (c == '~')
1352 fmt = FMT_CENTER;
1353 else if (c == '*')
1354 {
1355 if (haddot)
1356 trunc = (int)*ap++;
1357 else
1358 width = (int)*ap++;
1359 }
1360 else if (c >= '1' && c <= '9')
1361 {
1362 address_word t = s;
1363 unsigned int n;
1364 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1365 tmp[s - t] = c;
1366 tmp[s - t] = '\0';
1367 n = (unsigned int)strtol(tmp,NULL,10);
1368 if (haddot)
1369 trunc = n;
1370 else
1371 width = n;
1372 s--;
1373 }
1374 else if (c == '.')
1375 haddot = 1;
1376 }
1377 switch (c)
1378 {
1379 case '%':
1380 sim_io_printf (sd, "%%");
1381 break;
1382 case 's':
1383 if ((int)*ap != 0)
1384 {
1385 address_word p = *ap++;
1386 char ch;
1387 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1388 sim_io_printf(sd, "%c", ch);
1389 }
1390 else
1391 sim_io_printf(sd,"(null)");
1392 break;
1393 case 'c':
1394 sim_io_printf (sd, "%c", (int)*ap++);
1395 break;
1396 default:
1397 if (c == 'l')
1398 {
1399 sim_read (sd, s++, &c, 1);
1400 if (c == 'l')
1401 {
1402 longlong = 1;
1403 sim_read (sd, s++, &c, 1);
1404 }
1405 }
1406 if (strchr ("dobxXu", c))
1407 {
1408 word64 lv = (word64) *ap++;
1409 if (c == 'b')
1410 sim_io_printf(sd,"<binary not supported>");
1411 else
1412 {
1413 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1414 if (longlong)
1415 sim_io_printf(sd, tmp, lv);
1416 else
1417 sim_io_printf(sd, tmp, (int)lv);
1418 }
1419 }
1420 else if (strchr ("eEfgG", c))
1421 {
1422 double dbl = *(double*)(ap++);
1423 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1424 sim_io_printf (sd, tmp, dbl);
1425 trunc = 0;
1426 }
1427 }
1428 }
1429 else
1430 sim_io_printf(sd, "%c", c);
1431 }
1432 break;
1433 }
1434
1435 default:
1436 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1437 reason, pr_addr(cia));
1438 break;
1439 }
1440 return;
1441 }
1442
1443 /* Store a word into memory. */
1444
1445 static void
1446 store_word (SIM_DESC sd,
1447 sim_cpu *cpu,
1448 address_word cia,
1449 uword64 vaddr,
1450 signed_word val)
1451 {
1452 address_word paddr;
1453 int uncached;
1454
1455 if ((vaddr & 3) != 0)
1456 SignalExceptionAddressStore ();
1457 else
1458 {
1459 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1460 isTARGET, isREAL))
1461 {
1462 const uword64 mask = 7;
1463 uword64 memval;
1464 unsigned int byte;
1465
1466 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1467 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1468 memval = ((uword64) val) << (8 * byte);
1469 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1470 isREAL);
1471 }
1472 }
1473 }
1474
1475 /* Load a word from memory. */
1476
1477 static signed_word
1478 load_word (SIM_DESC sd,
1479 sim_cpu *cpu,
1480 address_word cia,
1481 uword64 vaddr)
1482 {
1483 if ((vaddr & 3) != 0)
1484 SignalExceptionAddressLoad ();
1485 else
1486 {
1487 address_word paddr;
1488 int uncached;
1489
1490 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1491 isTARGET, isREAL))
1492 {
1493 const uword64 mask = 0x7;
1494 const unsigned int reverse = ReverseEndian ? 1 : 0;
1495 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1496 uword64 memval;
1497 unsigned int byte;
1498
1499 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1500 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1501 isDATA, isREAL);
1502 byte = (vaddr & mask) ^ (bigend << 2);
1503 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1504 }
1505 }
1506
1507 return 0;
1508 }
1509
1510 /* Simulate the mips16 entry and exit pseudo-instructions. These
1511 would normally be handled by the reserved instruction exception
1512 code, but for ease of simulation we just handle them directly. */
1513
1514 static void
1515 mips16_entry (SIM_DESC sd,
1516 sim_cpu *cpu,
1517 address_word cia,
1518 unsigned int insn)
1519 {
1520 int aregs, sregs, rreg;
1521
1522 #ifdef DEBUG
1523 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1524 #endif /* DEBUG */
1525
1526 aregs = (insn & 0x700) >> 8;
1527 sregs = (insn & 0x0c0) >> 6;
1528 rreg = (insn & 0x020) >> 5;
1529
1530 /* This should be checked by the caller. */
1531 if (sregs == 3)
1532 abort ();
1533
1534 if (aregs < 5)
1535 {
1536 int i;
1537 signed_word tsp;
1538
1539 /* This is the entry pseudo-instruction. */
1540
1541 for (i = 0; i < aregs; i++)
1542 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1543
1544 tsp = SP;
1545 SP -= 32;
1546
1547 if (rreg)
1548 {
1549 tsp -= 4;
1550 store_word (SD, CPU, cia, (uword64) tsp, RA);
1551 }
1552
1553 for (i = 0; i < sregs; i++)
1554 {
1555 tsp -= 4;
1556 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1557 }
1558 }
1559 else
1560 {
1561 int i;
1562 signed_word tsp;
1563
1564 /* This is the exit pseudo-instruction. */
1565
1566 tsp = SP + 32;
1567
1568 if (rreg)
1569 {
1570 tsp -= 4;
1571 RA = load_word (SD, CPU, cia, (uword64) tsp);
1572 }
1573
1574 for (i = 0; i < sregs; i++)
1575 {
1576 tsp -= 4;
1577 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1578 }
1579
1580 SP += 32;
1581
1582 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1583 {
1584 if (aregs == 5)
1585 {
1586 FGR[0] = WORD64LO (GPR[4]);
1587 FPR_STATE[0] = fmt_uninterpreted;
1588 }
1589 else if (aregs == 6)
1590 {
1591 FGR[0] = WORD64LO (GPR[5]);
1592 FGR[1] = WORD64LO (GPR[4]);
1593 FPR_STATE[0] = fmt_uninterpreted;
1594 FPR_STATE[1] = fmt_uninterpreted;
1595 }
1596 }
1597
1598 PC = RA;
1599 }
1600
1601 }
1602
1603 /*-- trace support ----------------------------------------------------------*/
1604
1605 /* The TRACE support is provided (if required) in the memory accessing
1606 routines. Since we are also providing the architecture specific
1607 features, the architecture simulation code can also deal with
1608 notifying the TRACE world of cache flushes, etc. Similarly we do
1609 not need to provide profiling support in the simulator engine,
1610 since we can sample in the instruction fetch control loop. By
1611 defining the TRACE manifest, we add tracing as a run-time
1612 option. */
1613
1614 #if defined(TRACE)
1615 /* Tracing by default produces "din" format (as required by
1616 dineroIII). Each line of such a trace file *MUST* have a din label
1617 and address field. The rest of the line is ignored, so comments can
1618 be included if desired. The first field is the label which must be
1619 one of the following values:
1620
1621 0 read data
1622 1 write data
1623 2 instruction fetch
1624 3 escape record (treated as unknown access type)
1625 4 escape record (causes cache flush)
1626
1627 The address field is a 32bit (lower-case) hexadecimal address
1628 value. The address should *NOT* be preceded by "0x".
1629
1630 The size of the memory transfer is not important when dealing with
1631 cache lines (as long as no more than a cache line can be
1632 transferred in a single operation :-), however more information
1633 could be given following the dineroIII requirement to allow more
1634 complete memory and cache simulators to provide better
1635 results. i.e. the University of Pisa has a cache simulator that can
1636 also take bus size and speed as (variable) inputs to calculate
1637 complete system performance (a much more useful ability when trying
1638 to construct an end product, rather than a processor). They
1639 currently have an ARM version of their tool called ChARM. */
1640
1641
1642 void
1643 dotrace (SIM_DESC sd,
1644 sim_cpu *cpu,
1645 FILE *tracefh,
1646 int type,
1647 SIM_ADDR address,
1648 int width,
1649 char *comment,...)
1650 {
1651 if (STATE & simTRACE) {
1652 va_list ap;
1653 fprintf(tracefh,"%d %s ; width %d ; ",
1654 type,
1655 pr_addr(address),
1656 width);
1657 va_start(ap,comment);
1658 vfprintf(tracefh,comment,ap);
1659 va_end(ap);
1660 fprintf(tracefh,"\n");
1661 }
1662 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1663 we may be generating 64bit ones, we should put the hi-32bits of the
1664 address into the comment field. */
1665
1666 /* TODO: Provide a buffer for the trace lines. We can then avoid
1667 performing writes until the buffer is filled, or the file is
1668 being closed. */
1669
1670 /* NOTE: We could consider adding a comment field to the "din" file
1671 produced using type 3 markers (unknown access). This would then
1672 allow information about the program that the "din" is for, and
1673 the MIPs world that was being simulated, to be placed into the
1674 trace file. */
1675
1676 return;
1677 }
1678 #endif /* TRACE */
1679
1680 /*---------------------------------------------------------------------------*/
1681 /*-- simulator engine -------------------------------------------------------*/
1682 /*---------------------------------------------------------------------------*/
1683
1684 static void
1685 ColdReset (SIM_DESC sd)
1686 {
1687 int cpu_nr;
1688 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1689 {
1690 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1691 /* RESET: Fixed PC address: */
1692 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1693 /* The reset vector address is in the unmapped, uncached memory space. */
1694
1695 SR &= ~(status_SR | status_TS | status_RP);
1696 SR |= (status_ERL | status_BEV);
1697
1698 /* Cheat and allow access to the complete register set immediately */
1699 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1700 && WITH_TARGET_WORD_BITSIZE == 64)
1701 SR |= status_FR; /* 64bit registers */
1702
1703 /* Ensure that any instructions with pending register updates are
1704 cleared: */
1705 PENDING_INVALIDATE();
1706
1707 /* Initialise the FPU registers to the unknown state */
1708 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1709 {
1710 int rn;
1711 for (rn = 0; (rn < 32); rn++)
1712 FPR_STATE[rn] = fmt_uninterpreted;
1713 }
1714
1715 }
1716 }
1717
1718 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1719 /* Signal an exception condition. This will result in an exception
1720 that aborts the instruction. The instruction operation pseudocode
1721 will never see a return from this function call. */
1722
1723 void
1724 signal_exception (SIM_DESC sd,
1725 sim_cpu *cpu,
1726 address_word cia,
1727 int exception,...)
1728 {
1729 /* int vector; */
1730
1731 #ifdef DEBUG
1732 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1733 #endif /* DEBUG */
1734
1735 /* Ensure that any active atomic read/modify/write operation will fail: */
1736 LLBIT = 0;
1737
1738 switch (exception) {
1739
1740 case DebugBreakPoint :
1741 if (! (Debug & Debug_DM))
1742 {
1743 if (INDELAYSLOT())
1744 {
1745 CANCELDELAYSLOT();
1746
1747 Debug |= Debug_DBD; /* signaled from within in delay slot */
1748 DEPC = cia - 4; /* reference the branch instruction */
1749 }
1750 else
1751 {
1752 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1753 DEPC = cia;
1754 }
1755
1756 Debug |= Debug_DM; /* in debugging mode */
1757 Debug |= Debug_DBp; /* raising a DBp exception */
1758 PC = 0xBFC00200;
1759 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1760 }
1761 break;
1762
1763 case ReservedInstruction :
1764 {
1765 va_list ap;
1766 unsigned int instruction;
1767 va_start(ap,exception);
1768 instruction = va_arg(ap,unsigned int);
1769 va_end(ap);
1770 /* Provide simple monitor support using ReservedInstruction
1771 exceptions. The following code simulates the fixed vector
1772 entry points into the IDT monitor by causing a simulator
1773 trap, performing the monitor operation, and returning to
1774 the address held in the $ra register (standard PCS return
1775 address). This means we only need to pre-load the vector
1776 space with suitable instruction values. For systems were
1777 actual trap instructions are used, we would not need to
1778 perform this magic. */
1779 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1780 {
1781 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1782 /* NOTE: This assumes that a branch-and-link style
1783 instruction was used to enter the vector (which is the
1784 case with the current IDT monitor). */
1785 sim_engine_restart (SD, CPU, NULL, RA);
1786 }
1787 /* Look for the mips16 entry and exit instructions, and
1788 simulate a handler for them. */
1789 else if ((cia & 1) != 0
1790 && (instruction & 0xf81f) == 0xe809
1791 && (instruction & 0x0c0) != 0x0c0)
1792 {
1793 mips16_entry (SD, CPU, cia, instruction);
1794 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1795 }
1796 /* else fall through to normal exception processing */
1797 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1798 }
1799
1800 default:
1801 /* Store exception code into current exception id variable (used
1802 by exit code): */
1803
1804 /* TODO: If not simulating exceptions then stop the simulator
1805 execution. At the moment we always stop the simulation. */
1806
1807 #ifdef SUBTARGET_R3900
1808 /* update interrupt-related registers */
1809
1810 /* insert exception code in bits 6:2 */
1811 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1812 /* shift IE/KU history bits left */
1813 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1814
1815 if (STATE & simDELAYSLOT)
1816 {
1817 STATE &= ~simDELAYSLOT;
1818 CAUSE |= cause_BD;
1819 EPC = (cia - 4); /* reference the branch instruction */
1820 }
1821 else
1822 EPC = cia;
1823
1824 if (SR & status_BEV)
1825 PC = (signed)0xBFC00000 + 0x180;
1826 else
1827 PC = (signed)0x80000000 + 0x080;
1828 #else
1829 /* See figure 5-17 for an outline of the code below */
1830 if (! (SR & status_EXL))
1831 {
1832 CAUSE = (exception << 2);
1833 if (STATE & simDELAYSLOT)
1834 {
1835 STATE &= ~simDELAYSLOT;
1836 CAUSE |= cause_BD;
1837 EPC = (cia - 4); /* reference the branch instruction */
1838 }
1839 else
1840 EPC = cia;
1841 /* FIXME: TLB et.al. */
1842 /* vector = 0x180; */
1843 }
1844 else
1845 {
1846 CAUSE = (exception << 2);
1847 /* vector = 0x180; */
1848 }
1849 SR |= status_EXL;
1850 /* Store exception code into current exception id variable (used
1851 by exit code): */
1852
1853 if (SR & status_BEV)
1854 PC = (signed)0xBFC00200 + 0x180;
1855 else
1856 PC = (signed)0x80000000 + 0x180;
1857 #endif
1858
1859 switch ((CAUSE >> 2) & 0x1F)
1860 {
1861 case Interrupt:
1862 /* Interrupts arrive during event processing, no need to
1863 restart */
1864 return;
1865
1866 case NMIReset:
1867 /* Ditto */
1868 #ifdef SUBTARGET_3900
1869 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1870 PC = (signed)0xBFC00000;
1871 #endif SUBTARGET_3900
1872 return;
1873
1874 case TLBModification:
1875 case TLBLoad:
1876 case TLBStore:
1877 case AddressLoad:
1878 case AddressStore:
1879 case InstructionFetch:
1880 case DataReference:
1881 /* The following is so that the simulator will continue from the
1882 exception address on breakpoint operations. */
1883 PC = EPC;
1884 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1885 sim_stopped, SIM_SIGBUS);
1886
1887 case ReservedInstruction:
1888 case CoProcessorUnusable:
1889 PC = EPC;
1890 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1891 sim_stopped, SIM_SIGILL);
1892
1893 case IntegerOverflow:
1894 case FPE:
1895 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1896 sim_stopped, SIM_SIGFPE);
1897
1898 case BreakPoint:
1899 case SystemCall:
1900 case Trap:
1901 sim_engine_restart (SD, CPU, NULL, PC);
1902 break;
1903
1904 case Watch:
1905 PC = EPC;
1906 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1907 sim_stopped, SIM_SIGTRAP);
1908
1909 default : /* Unknown internal exception */
1910 PC = EPC;
1911 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1912 sim_stopped, SIM_SIGABRT);
1913
1914 }
1915
1916 case SimulatorFault:
1917 {
1918 va_list ap;
1919 char *msg;
1920 va_start(ap,exception);
1921 msg = va_arg(ap,char *);
1922 va_end(ap);
1923 sim_engine_abort (SD, CPU, NULL_CIA,
1924 "FATAL: Simulator error \"%s\"\n",msg);
1925 }
1926 }
1927
1928 return;
1929 }
1930
1931 #if defined(WARN_RESULT)
1932 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1933 /* This function indicates that the result of the operation is
1934 undefined. However, this should not affect the instruction
1935 stream. All that is meant to happen is that the destination
1936 register is set to an undefined result. To keep the simulator
1937 simple, we just don't bother updating the destination register, so
1938 the overall result will be undefined. If desired we can stop the
1939 simulator by raising a pseudo-exception. */
1940 #define UndefinedResult() undefined_result (sd,cia)
1941 static void
1942 undefined_result(sd,cia)
1943 SIM_DESC sd;
1944 address_word cia;
1945 {
1946 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
1947 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1948 state |= simSTOP;
1949 #endif
1950 return;
1951 }
1952 #endif /* WARN_RESULT */
1953
1954 /*-- FPU support routines ---------------------------------------------------*/
1955
1956 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1957 formats conform to ANSI/IEEE Std 754-1985. */
1958 /* SINGLE precision floating:
1959 * seeeeeeeefffffffffffffffffffffff
1960 * s = 1bit = sign
1961 * e = 8bits = exponent
1962 * f = 23bits = fraction
1963 */
1964 /* SINGLE precision fixed:
1965 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1966 * s = 1bit = sign
1967 * i = 31bits = integer
1968 */
1969 /* DOUBLE precision floating:
1970 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1971 * s = 1bit = sign
1972 * e = 11bits = exponent
1973 * f = 52bits = fraction
1974 */
1975 /* DOUBLE precision fixed:
1976 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1977 * s = 1bit = sign
1978 * i = 63bits = integer
1979 */
1980
1981 /* Extract sign-bit: */
1982 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1983 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1984 /* Extract biased exponent: */
1985 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1986 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1987 /* Extract unbiased Exponent: */
1988 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1989 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1990 /* Extract complete fraction field: */
1991 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1992 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1993 /* Extract numbered fraction bit: */
1994 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1995 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1996
1997 /* Explicit QNaN values used when value required: */
1998 #define FPQNaN_SINGLE (0x7FBFFFFF)
1999 #define FPQNaN_WORD (0x7FFFFFFF)
2000 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2001 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2002
2003 /* Explicit Infinity values used when required: */
2004 #define FPINF_SINGLE (0x7F800000)
2005 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2006
2007 #if 1 /* def DEBUG */
2008 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2009 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2010 #endif /* DEBUG */
2011
2012 uword64
2013 value_fpr (SIM_DESC sd,
2014 sim_cpu *cpu,
2015 address_word cia,
2016 int fpr,
2017 FP_formats fmt)
2018 {
2019 uword64 value = 0;
2020 int err = 0;
2021
2022 /* Treat unused register values, as fixed-point 64bit values: */
2023 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
2024 #if 1
2025 /* If request to read data as "uninterpreted", then use the current
2026 encoding: */
2027 fmt = FPR_STATE[fpr];
2028 #else
2029 fmt = fmt_long;
2030 #endif
2031
2032 /* For values not yet accessed, set to the desired format: */
2033 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2034 FPR_STATE[fpr] = fmt;
2035 #ifdef DEBUG
2036 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2037 #endif /* DEBUG */
2038 }
2039 if (fmt != FPR_STATE[fpr]) {
2040 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2041 FPR_STATE[fpr] = fmt_unknown;
2042 }
2043
2044 if (FPR_STATE[fpr] == fmt_unknown) {
2045 /* Set QNaN value: */
2046 switch (fmt) {
2047 case fmt_single:
2048 value = FPQNaN_SINGLE;
2049 break;
2050
2051 case fmt_double:
2052 value = FPQNaN_DOUBLE;
2053 break;
2054
2055 case fmt_word:
2056 value = FPQNaN_WORD;
2057 break;
2058
2059 case fmt_long:
2060 value = FPQNaN_LONG;
2061 break;
2062
2063 default:
2064 err = -1;
2065 break;
2066 }
2067 } else if (SizeFGR() == 64) {
2068 switch (fmt) {
2069 case fmt_single:
2070 case fmt_word:
2071 value = (FGR[fpr] & 0xFFFFFFFF);
2072 break;
2073
2074 case fmt_uninterpreted:
2075 case fmt_double:
2076 case fmt_long:
2077 value = FGR[fpr];
2078 break;
2079
2080 default :
2081 err = -1;
2082 break;
2083 }
2084 } else {
2085 switch (fmt) {
2086 case fmt_single:
2087 case fmt_word:
2088 value = (FGR[fpr] & 0xFFFFFFFF);
2089 break;
2090
2091 case fmt_uninterpreted:
2092 case fmt_double:
2093 case fmt_long:
2094 if ((fpr & 1) == 0) { /* even registers only */
2095 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2096 } else {
2097 SignalException(ReservedInstruction,0);
2098 }
2099 break;
2100
2101 default :
2102 err = -1;
2103 break;
2104 }
2105 }
2106
2107 if (err)
2108 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2109
2110 #ifdef DEBUG
2111 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2112 #endif /* DEBUG */
2113
2114 return(value);
2115 }
2116
2117 void
2118 store_fpr (SIM_DESC sd,
2119 sim_cpu *cpu,
2120 address_word cia,
2121 int fpr,
2122 FP_formats fmt,
2123 uword64 value)
2124 {
2125 int err = 0;
2126
2127 #ifdef DEBUG
2128 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2129 #endif /* DEBUG */
2130
2131 if (SizeFGR() == 64) {
2132 switch (fmt) {
2133 case fmt_uninterpreted_32:
2134 fmt = fmt_uninterpreted;
2135 case fmt_single :
2136 case fmt_word :
2137 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2138 FPR_STATE[fpr] = fmt;
2139 break;
2140
2141 case fmt_uninterpreted_64:
2142 fmt = fmt_uninterpreted;
2143 case fmt_uninterpreted:
2144 case fmt_double :
2145 case fmt_long :
2146 FGR[fpr] = value;
2147 FPR_STATE[fpr] = fmt;
2148 break;
2149
2150 default :
2151 FPR_STATE[fpr] = fmt_unknown;
2152 err = -1;
2153 break;
2154 }
2155 } else {
2156 switch (fmt) {
2157 case fmt_uninterpreted_32:
2158 fmt = fmt_uninterpreted;
2159 case fmt_single :
2160 case fmt_word :
2161 FGR[fpr] = (value & 0xFFFFFFFF);
2162 FPR_STATE[fpr] = fmt;
2163 break;
2164
2165 case fmt_uninterpreted_64:
2166 fmt = fmt_uninterpreted;
2167 case fmt_uninterpreted:
2168 case fmt_double :
2169 case fmt_long :
2170 if ((fpr & 1) == 0) { /* even register number only */
2171 FGR[fpr+1] = (value >> 32);
2172 FGR[fpr] = (value & 0xFFFFFFFF);
2173 FPR_STATE[fpr + 1] = fmt;
2174 FPR_STATE[fpr] = fmt;
2175 } else {
2176 FPR_STATE[fpr] = fmt_unknown;
2177 FPR_STATE[fpr + 1] = fmt_unknown;
2178 SignalException(ReservedInstruction,0);
2179 }
2180 break;
2181
2182 default :
2183 FPR_STATE[fpr] = fmt_unknown;
2184 err = -1;
2185 break;
2186 }
2187 }
2188 #if defined(WARN_RESULT)
2189 else
2190 UndefinedResult();
2191 #endif /* WARN_RESULT */
2192
2193 if (err)
2194 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2195
2196 #ifdef DEBUG
2197 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2198 #endif /* DEBUG */
2199
2200 return;
2201 }
2202
2203 int
2204 NaN(op,fmt)
2205 uword64 op;
2206 FP_formats fmt;
2207 {
2208 int boolean = 0;
2209 switch (fmt) {
2210 case fmt_single:
2211 case fmt_word:
2212 {
2213 sim_fpu wop;
2214 sim_fpu_32to (&wop, op);
2215 boolean = sim_fpu_is_nan (&wop);
2216 break;
2217 }
2218 case fmt_double:
2219 case fmt_long:
2220 {
2221 sim_fpu wop;
2222 sim_fpu_64to (&wop, op);
2223 boolean = sim_fpu_is_nan (&wop);
2224 break;
2225 }
2226 default:
2227 fprintf (stderr, "Bad switch\n");
2228 abort ();
2229 }
2230
2231 #ifdef DEBUG
2232 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2233 #endif /* DEBUG */
2234
2235 return(boolean);
2236 }
2237
2238 int
2239 Infinity(op,fmt)
2240 uword64 op;
2241 FP_formats fmt;
2242 {
2243 int boolean = 0;
2244
2245 #ifdef DEBUG
2246 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2247 #endif /* DEBUG */
2248
2249 switch (fmt) {
2250 case fmt_single:
2251 {
2252 sim_fpu wop;
2253 sim_fpu_32to (&wop, op);
2254 boolean = sim_fpu_is_infinity (&wop);
2255 break;
2256 }
2257 case fmt_double:
2258 {
2259 sim_fpu wop;
2260 sim_fpu_64to (&wop, op);
2261 boolean = sim_fpu_is_infinity (&wop);
2262 break;
2263 }
2264 default:
2265 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2266 break;
2267 }
2268
2269 #ifdef DEBUG
2270 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2271 #endif /* DEBUG */
2272
2273 return(boolean);
2274 }
2275
2276 int
2277 Less(op1,op2,fmt)
2278 uword64 op1;
2279 uword64 op2;
2280 FP_formats fmt;
2281 {
2282 int boolean = 0;
2283
2284 /* Argument checking already performed by the FPCOMPARE code */
2285
2286 #ifdef DEBUG
2287 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2288 #endif /* DEBUG */
2289
2290 /* The format type should already have been checked: */
2291 switch (fmt) {
2292 case fmt_single:
2293 {
2294 sim_fpu wop1;
2295 sim_fpu wop2;
2296 sim_fpu_32to (&wop1, op1);
2297 sim_fpu_32to (&wop2, op2);
2298 boolean = sim_fpu_is_lt (&wop1, &wop2);
2299 break;
2300 }
2301 case fmt_double:
2302 {
2303 sim_fpu wop1;
2304 sim_fpu wop2;
2305 sim_fpu_64to (&wop1, op1);
2306 sim_fpu_64to (&wop2, op2);
2307 boolean = sim_fpu_is_lt (&wop1, &wop2);
2308 break;
2309 }
2310 default:
2311 fprintf (stderr, "Bad switch\n");
2312 abort ();
2313 }
2314
2315 #ifdef DEBUG
2316 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2317 #endif /* DEBUG */
2318
2319 return(boolean);
2320 }
2321
2322 int
2323 Equal(op1,op2,fmt)
2324 uword64 op1;
2325 uword64 op2;
2326 FP_formats fmt;
2327 {
2328 int boolean = 0;
2329
2330 /* Argument checking already performed by the FPCOMPARE code */
2331
2332 #ifdef DEBUG
2333 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2334 #endif /* DEBUG */
2335
2336 /* The format type should already have been checked: */
2337 switch (fmt) {
2338 case fmt_single:
2339 {
2340 sim_fpu wop1;
2341 sim_fpu wop2;
2342 sim_fpu_32to (&wop1, op1);
2343 sim_fpu_32to (&wop2, op2);
2344 boolean = sim_fpu_is_eq (&wop1, &wop2);
2345 break;
2346 }
2347 case fmt_double:
2348 {
2349 sim_fpu wop1;
2350 sim_fpu wop2;
2351 sim_fpu_64to (&wop1, op1);
2352 sim_fpu_64to (&wop2, op2);
2353 boolean = sim_fpu_is_eq (&wop1, &wop2);
2354 break;
2355 }
2356 default:
2357 fprintf (stderr, "Bad switch\n");
2358 abort ();
2359 }
2360
2361 #ifdef DEBUG
2362 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2363 #endif /* DEBUG */
2364
2365 return(boolean);
2366 }
2367
2368 uword64
2369 AbsoluteValue(op,fmt)
2370 uword64 op;
2371 FP_formats fmt;
2372 {
2373 uword64 result = 0;
2374
2375 #ifdef DEBUG
2376 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2377 #endif /* DEBUG */
2378
2379 /* The format type should already have been checked: */
2380 switch (fmt) {
2381 case fmt_single:
2382 {
2383 sim_fpu wop;
2384 unsigned32 ans;
2385 sim_fpu_32to (&wop, op);
2386 sim_fpu_abs (&wop, &wop);
2387 sim_fpu_to32 (&ans, &wop);
2388 result = ans;
2389 break;
2390 }
2391 case fmt_double:
2392 {
2393 sim_fpu wop;
2394 unsigned64 ans;
2395 sim_fpu_64to (&wop, op);
2396 sim_fpu_abs (&wop, &wop);
2397 sim_fpu_to64 (&ans, &wop);
2398 result = ans;
2399 break;
2400 }
2401 default:
2402 fprintf (stderr, "Bad switch\n");
2403 abort ();
2404 }
2405
2406 return(result);
2407 }
2408
2409 uword64
2410 Negate(op,fmt)
2411 uword64 op;
2412 FP_formats fmt;
2413 {
2414 uword64 result = 0;
2415
2416 #ifdef DEBUG
2417 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2418 #endif /* DEBUG */
2419
2420 /* The format type should already have been checked: */
2421 switch (fmt) {
2422 case fmt_single:
2423 {
2424 sim_fpu wop;
2425 unsigned32 ans;
2426 sim_fpu_32to (&wop, op);
2427 sim_fpu_neg (&wop, &wop);
2428 sim_fpu_to32 (&ans, &wop);
2429 result = ans;
2430 break;
2431 }
2432 case fmt_double:
2433 {
2434 sim_fpu wop;
2435 unsigned64 ans;
2436 sim_fpu_64to (&wop, op);
2437 sim_fpu_neg (&wop, &wop);
2438 sim_fpu_to64 (&ans, &wop);
2439 result = ans;
2440 break;
2441 }
2442 default:
2443 fprintf (stderr, "Bad switch\n");
2444 abort ();
2445 }
2446
2447 return(result);
2448 }
2449
2450 uword64
2451 Add(op1,op2,fmt)
2452 uword64 op1;
2453 uword64 op2;
2454 FP_formats fmt;
2455 {
2456 uword64 result = 0;
2457
2458 #ifdef DEBUG
2459 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2460 #endif /* DEBUG */
2461
2462 /* The registers must specify FPRs valid for operands of type
2463 "fmt". If they are not valid, the result is undefined. */
2464
2465 /* The format type should already have been checked: */
2466 switch (fmt) {
2467 case fmt_single:
2468 {
2469 sim_fpu wop1;
2470 sim_fpu wop2;
2471 sim_fpu ans;
2472 unsigned32 res;
2473 sim_fpu_32to (&wop1, op1);
2474 sim_fpu_32to (&wop2, op2);
2475 sim_fpu_add (&ans, &wop1, &wop2);
2476 sim_fpu_to32 (&res, &ans);
2477 result = res;
2478 break;
2479 }
2480 case fmt_double:
2481 {
2482 sim_fpu wop1;
2483 sim_fpu wop2;
2484 sim_fpu ans;
2485 unsigned64 res;
2486 sim_fpu_64to (&wop1, op1);
2487 sim_fpu_64to (&wop2, op2);
2488 sim_fpu_add (&ans, &wop1, &wop2);
2489 sim_fpu_to64 (&res, &ans);
2490 result = res;
2491 break;
2492 }
2493 default:
2494 fprintf (stderr, "Bad switch\n");
2495 abort ();
2496 }
2497
2498 #ifdef DEBUG
2499 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2500 #endif /* DEBUG */
2501
2502 return(result);
2503 }
2504
2505 uword64
2506 Sub(op1,op2,fmt)
2507 uword64 op1;
2508 uword64 op2;
2509 FP_formats fmt;
2510 {
2511 uword64 result = 0;
2512
2513 #ifdef DEBUG
2514 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2515 #endif /* DEBUG */
2516
2517 /* The registers must specify FPRs valid for operands of type
2518 "fmt". If they are not valid, the result is undefined. */
2519
2520 /* The format type should already have been checked: */
2521 switch (fmt) {
2522 case fmt_single:
2523 {
2524 sim_fpu wop1;
2525 sim_fpu wop2;
2526 sim_fpu ans;
2527 unsigned32 res;
2528 sim_fpu_32to (&wop1, op1);
2529 sim_fpu_32to (&wop2, op2);
2530 sim_fpu_sub (&ans, &wop1, &wop2);
2531 sim_fpu_to32 (&res, &ans);
2532 result = res;
2533 }
2534 break;
2535 case fmt_double:
2536 {
2537 sim_fpu wop1;
2538 sim_fpu wop2;
2539 sim_fpu ans;
2540 unsigned64 res;
2541 sim_fpu_64to (&wop1, op1);
2542 sim_fpu_64to (&wop2, op2);
2543 sim_fpu_sub (&ans, &wop1, &wop2);
2544 sim_fpu_to64 (&res, &ans);
2545 result = res;
2546 }
2547 break;
2548 default:
2549 fprintf (stderr, "Bad switch\n");
2550 abort ();
2551 }
2552
2553 #ifdef DEBUG
2554 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2555 #endif /* DEBUG */
2556
2557 return(result);
2558 }
2559
2560 uword64
2561 Multiply(op1,op2,fmt)
2562 uword64 op1;
2563 uword64 op2;
2564 FP_formats fmt;
2565 {
2566 uword64 result = 0;
2567
2568 #ifdef DEBUG
2569 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2570 #endif /* DEBUG */
2571
2572 /* The registers must specify FPRs valid for operands of type
2573 "fmt". If they are not valid, the result is undefined. */
2574
2575 /* The format type should already have been checked: */
2576 switch (fmt) {
2577 case fmt_single:
2578 {
2579 sim_fpu wop1;
2580 sim_fpu wop2;
2581 sim_fpu ans;
2582 unsigned32 res;
2583 sim_fpu_32to (&wop1, op1);
2584 sim_fpu_32to (&wop2, op2);
2585 sim_fpu_mul (&ans, &wop1, &wop2);
2586 sim_fpu_to32 (&res, &ans);
2587 result = res;
2588 break;
2589 }
2590 case fmt_double:
2591 {
2592 sim_fpu wop1;
2593 sim_fpu wop2;
2594 sim_fpu ans;
2595 unsigned64 res;
2596 sim_fpu_64to (&wop1, op1);
2597 sim_fpu_64to (&wop2, op2);
2598 sim_fpu_mul (&ans, &wop1, &wop2);
2599 sim_fpu_to64 (&res, &ans);
2600 result = res;
2601 break;
2602 }
2603 default:
2604 fprintf (stderr, "Bad switch\n");
2605 abort ();
2606 }
2607
2608 #ifdef DEBUG
2609 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2610 #endif /* DEBUG */
2611
2612 return(result);
2613 }
2614
2615 uword64
2616 Divide(op1,op2,fmt)
2617 uword64 op1;
2618 uword64 op2;
2619 FP_formats fmt;
2620 {
2621 uword64 result = 0;
2622
2623 #ifdef DEBUG
2624 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2625 #endif /* DEBUG */
2626
2627 /* The registers must specify FPRs valid for operands of type
2628 "fmt". If they are not valid, the result is undefined. */
2629
2630 /* The format type should already have been checked: */
2631 switch (fmt) {
2632 case fmt_single:
2633 {
2634 sim_fpu wop1;
2635 sim_fpu wop2;
2636 sim_fpu ans;
2637 unsigned32 res;
2638 sim_fpu_32to (&wop1, op1);
2639 sim_fpu_32to (&wop2, op2);
2640 sim_fpu_div (&ans, &wop1, &wop2);
2641 sim_fpu_to32 (&res, &ans);
2642 result = res;
2643 break;
2644 }
2645 case fmt_double:
2646 {
2647 sim_fpu wop1;
2648 sim_fpu wop2;
2649 sim_fpu ans;
2650 unsigned64 res;
2651 sim_fpu_64to (&wop1, op1);
2652 sim_fpu_64to (&wop2, op2);
2653 sim_fpu_div (&ans, &wop1, &wop2);
2654 sim_fpu_to64 (&res, &ans);
2655 result = res;
2656 break;
2657 }
2658 default:
2659 fprintf (stderr, "Bad switch\n");
2660 abort ();
2661 }
2662
2663 #ifdef DEBUG
2664 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2665 #endif /* DEBUG */
2666
2667 return(result);
2668 }
2669
2670 uword64 UNUSED
2671 Recip(op,fmt)
2672 uword64 op;
2673 FP_formats fmt;
2674 {
2675 uword64 result = 0;
2676
2677 #ifdef DEBUG
2678 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2679 #endif /* DEBUG */
2680
2681 /* The registers must specify FPRs valid for operands of type
2682 "fmt". If they are not valid, the result is undefined. */
2683
2684 /* The format type should already have been checked: */
2685 switch (fmt) {
2686 case fmt_single:
2687 {
2688 sim_fpu wop;
2689 sim_fpu ans;
2690 unsigned32 res;
2691 sim_fpu_32to (&wop, op);
2692 sim_fpu_inv (&ans, &wop);
2693 sim_fpu_to32 (&res, &ans);
2694 result = res;
2695 break;
2696 }
2697 case fmt_double:
2698 {
2699 sim_fpu wop;
2700 sim_fpu ans;
2701 unsigned64 res;
2702 sim_fpu_64to (&wop, op);
2703 sim_fpu_inv (&ans, &wop);
2704 sim_fpu_to64 (&res, &ans);
2705 result = res;
2706 break;
2707 }
2708 default:
2709 fprintf (stderr, "Bad switch\n");
2710 abort ();
2711 }
2712
2713 #ifdef DEBUG
2714 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2715 #endif /* DEBUG */
2716
2717 return(result);
2718 }
2719
2720 uword64
2721 SquareRoot(op,fmt)
2722 uword64 op;
2723 FP_formats fmt;
2724 {
2725 uword64 result = 0;
2726
2727 #ifdef DEBUG
2728 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2729 #endif /* DEBUG */
2730
2731 /* The registers must specify FPRs valid for operands of type
2732 "fmt". If they are not valid, the result is undefined. */
2733
2734 /* The format type should already have been checked: */
2735 switch (fmt) {
2736 case fmt_single:
2737 {
2738 sim_fpu wop;
2739 sim_fpu ans;
2740 unsigned32 res;
2741 sim_fpu_32to (&wop, op);
2742 sim_fpu_sqrt (&ans, &wop);
2743 sim_fpu_to32 (&res, &ans);
2744 result = res;
2745 break;
2746 }
2747 case fmt_double:
2748 {
2749 sim_fpu wop;
2750 sim_fpu ans;
2751 unsigned64 res;
2752 sim_fpu_64to (&wop, op);
2753 sim_fpu_sqrt (&ans, &wop);
2754 sim_fpu_to64 (&res, &ans);
2755 result = res;
2756 break;
2757 }
2758 default:
2759 fprintf (stderr, "Bad switch\n");
2760 abort ();
2761 }
2762
2763 #ifdef DEBUG
2764 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2765 #endif /* DEBUG */
2766
2767 return(result);
2768 }
2769
2770 #if 0
2771 uword64
2772 Max (uword64 op1,
2773 uword64 op2,
2774 FP_formats fmt)
2775 {
2776 int cmp;
2777 unsigned64 result;
2778
2779 #ifdef DEBUG
2780 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2781 #endif /* DEBUG */
2782
2783 /* The registers must specify FPRs valid for operands of type
2784 "fmt". If they are not valid, the result is undefined. */
2785
2786 /* The format type should already have been checked: */
2787 switch (fmt)
2788 {
2789 case fmt_single:
2790 {
2791 sim_fpu wop1;
2792 sim_fpu wop2;
2793 sim_fpu_32to (&wop1, op1);
2794 sim_fpu_32to (&wop2, op2);
2795 cmp = sim_fpu_cmp (&wop1, &wop2);
2796 break;
2797 }
2798 case fmt_double:
2799 {
2800 sim_fpu wop1;
2801 sim_fpu wop2;
2802 sim_fpu_64to (&wop1, op1);
2803 sim_fpu_64to (&wop2, op2);
2804 cmp = sim_fpu_cmp (&wop1, &wop2);
2805 break;
2806 }
2807 default:
2808 fprintf (stderr, "Bad switch\n");
2809 abort ();
2810 }
2811
2812 switch (cmp)
2813 {
2814 case SIM_FPU_IS_SNAN:
2815 case SIM_FPU_IS_QNAN:
2816 result = op1;
2817 case SIM_FPU_IS_NINF:
2818 case SIM_FPU_IS_NNUMBER:
2819 case SIM_FPU_IS_NDENORM:
2820 case SIM_FPU_IS_NZERO:
2821 result = op2; /* op1 - op2 < 0 */
2822 case SIM_FPU_IS_PINF:
2823 case SIM_FPU_IS_PNUMBER:
2824 case SIM_FPU_IS_PDENORM:
2825 case SIM_FPU_IS_PZERO:
2826 result = op1; /* op1 - op2 > 0 */
2827 default:
2828 fprintf (stderr, "Bad switch\n");
2829 abort ();
2830 }
2831
2832 #ifdef DEBUG
2833 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2834 #endif /* DEBUG */
2835
2836 return(result);
2837 }
2838 #endif
2839
2840 #if 0
2841 uword64
2842 Min (uword64 op1,
2843 uword64 op2,
2844 FP_formats fmt)
2845 {
2846 int cmp;
2847 unsigned64 result;
2848
2849 #ifdef DEBUG
2850 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2851 #endif /* DEBUG */
2852
2853 /* The registers must specify FPRs valid for operands of type
2854 "fmt". If they are not valid, the result is undefined. */
2855
2856 /* The format type should already have been checked: */
2857 switch (fmt)
2858 {
2859 case fmt_single:
2860 {
2861 sim_fpu wop1;
2862 sim_fpu wop2;
2863 sim_fpu_32to (&wop1, op1);
2864 sim_fpu_32to (&wop2, op2);
2865 cmp = sim_fpu_cmp (&wop1, &wop2);
2866 break;
2867 }
2868 case fmt_double:
2869 {
2870 sim_fpu wop1;
2871 sim_fpu wop2;
2872 sim_fpu_64to (&wop1, op1);
2873 sim_fpu_64to (&wop2, op2);
2874 cmp = sim_fpu_cmp (&wop1, &wop2);
2875 break;
2876 }
2877 default:
2878 fprintf (stderr, "Bad switch\n");
2879 abort ();
2880 }
2881
2882 switch (cmp)
2883 {
2884 case SIM_FPU_IS_SNAN:
2885 case SIM_FPU_IS_QNAN:
2886 result = op1;
2887 case SIM_FPU_IS_NINF:
2888 case SIM_FPU_IS_NNUMBER:
2889 case SIM_FPU_IS_NDENORM:
2890 case SIM_FPU_IS_NZERO:
2891 result = op1; /* op1 - op2 < 0 */
2892 case SIM_FPU_IS_PINF:
2893 case SIM_FPU_IS_PNUMBER:
2894 case SIM_FPU_IS_PDENORM:
2895 case SIM_FPU_IS_PZERO:
2896 result = op2; /* op1 - op2 > 0 */
2897 default:
2898 fprintf (stderr, "Bad switch\n");
2899 abort ();
2900 }
2901
2902 #ifdef DEBUG
2903 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2904 #endif /* DEBUG */
2905
2906 return(result);
2907 }
2908 #endif
2909
2910 uword64
2911 convert (SIM_DESC sd,
2912 sim_cpu *cpu,
2913 address_word cia,
2914 int rm,
2915 uword64 op,
2916 FP_formats from,
2917 FP_formats to)
2918 {
2919 sim_fpu wop;
2920 sim_fpu_round round;
2921 unsigned32 result32;
2922 unsigned64 result64;
2923
2924 #ifdef DEBUG
2925 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
2926 #endif /* DEBUG */
2927
2928 switch (rm)
2929 {
2930 case FP_RM_NEAREST:
2931 /* Round result to nearest representable value. When two
2932 representable values are equally near, round to the value
2933 that has a least significant bit of zero (i.e. is even). */
2934 round = sim_fpu_round_near;
2935 break;
2936 case FP_RM_TOZERO:
2937 /* Round result to the value closest to, and not greater in
2938 magnitude than, the result. */
2939 round = sim_fpu_round_zero;
2940 break;
2941 case FP_RM_TOPINF:
2942 /* Round result to the value closest to, and not less than,
2943 the result. */
2944 round = sim_fpu_round_up;
2945 break;
2946
2947 case FP_RM_TOMINF:
2948 /* Round result to the value closest to, and not greater than,
2949 the result. */
2950 round = sim_fpu_round_down;
2951 break;
2952 default:
2953 round = 0;
2954 fprintf (stderr, "Bad switch\n");
2955 abort ();
2956 }
2957
2958 /* Convert the input to sim_fpu internal format */
2959 switch (from)
2960 {
2961 case fmt_double:
2962 sim_fpu_64to (&wop, op);
2963 break;
2964 case fmt_single:
2965 sim_fpu_32to (&wop, op);
2966 break;
2967 case fmt_word:
2968 sim_fpu_i32to (&wop, op, round);
2969 break;
2970 case fmt_long:
2971 sim_fpu_i64to (&wop, op, round);
2972 break;
2973 default:
2974 fprintf (stderr, "Bad switch\n");
2975 abort ();
2976 }
2977
2978 /* Convert sim_fpu format into the output */
2979 /* The value WOP is converted to the destination format, rounding
2980 using mode RM. When the destination is a fixed-point format, then
2981 a source value of Infinity, NaN or one which would round to an
2982 integer outside the fixed point range then an IEEE Invalid
2983 Operation condition is raised. */
2984 switch (to)
2985 {
2986 case fmt_single:
2987 sim_fpu_round_32 (&wop, round, 0);
2988 sim_fpu_to32 (&result32, &wop);
2989 result64 = result32;
2990 break;
2991 case fmt_double:
2992 sim_fpu_round_64 (&wop, round, 0);
2993 sim_fpu_to64 (&result64, &wop);
2994 break;
2995 case fmt_word:
2996 sim_fpu_to32i (&result32, &wop, round);
2997 result64 = result32;
2998 break;
2999 case fmt_long:
3000 sim_fpu_to64i (&result64, &wop, round);
3001 break;
3002 default:
3003 result64 = 0;
3004 fprintf (stderr, "Bad switch\n");
3005 abort ();
3006 }
3007
3008 #ifdef DEBUG
3009 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
3010 #endif /* DEBUG */
3011
3012 return(result64);
3013 }
3014
3015
3016 /*-- co-processor support routines ------------------------------------------*/
3017
3018 static int UNUSED
3019 CoProcPresent(coproc_number)
3020 unsigned int coproc_number;
3021 {
3022 /* Return TRUE if simulator provides a model for the given co-processor number */
3023 return(0);
3024 }
3025
3026 void
3027 cop_lw (SIM_DESC sd,
3028 sim_cpu *cpu,
3029 address_word cia,
3030 int coproc_num,
3031 int coproc_reg,
3032 unsigned int memword)
3033 {
3034 switch (coproc_num)
3035 {
3036 case 1:
3037 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3038 {
3039 #ifdef DEBUG
3040 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
3041 #endif
3042 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
3043 FPR_STATE[coproc_reg] = fmt_uninterpreted;
3044 break;
3045 }
3046
3047 default:
3048 #if 0 /* this should be controlled by a configuration option */
3049 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
3050 #endif
3051 break;
3052 }
3053
3054 return;
3055 }
3056
3057 void
3058 cop_ld (SIM_DESC sd,
3059 sim_cpu *cpu,
3060 address_word cia,
3061 int coproc_num,
3062 int coproc_reg,
3063 uword64 memword)
3064 {
3065 switch (coproc_num) {
3066 case 1:
3067 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3068 {
3069 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
3070 break;
3071 }
3072
3073 default:
3074 #if 0 /* this message should be controlled by a configuration option */
3075 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
3076 #endif
3077 break;
3078 }
3079
3080 return;
3081 }
3082
3083
3084 /* start-sanitize-sky */
3085 #ifdef TARGET_SKY
3086 void
3087 cop_lq (SIM_DESC sd,
3088 sim_cpu *cpu,
3089 address_word cia,
3090 int coproc_num,
3091 int coproc_reg,
3092 unsigned128 memword)
3093 {
3094 switch (coproc_num)
3095 {
3096 case 2:
3097 {
3098 int i;
3099
3100 while(vu0_busy())
3101 vu0_issue(sd);
3102
3103 /* one word at a time, argh! */
3104 for(i=0; i<4; i++)
3105 {
3106 unsigned_4 value;
3107 value = H2T_4(*A4_16(& memword, 3-i));
3108 write_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3109 }
3110 }
3111 break;
3112
3113 default:
3114 sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3115 coproc_num,coproc_reg,pr_addr(cia));
3116 break;
3117 }
3118
3119 return;
3120 }
3121 #endif /* TARGET_SKY */
3122 /* end-sanitize-sky */
3123
3124
3125 unsigned int
3126 cop_sw (SIM_DESC sd,
3127 sim_cpu *cpu,
3128 address_word cia,
3129 int coproc_num,
3130 int coproc_reg)
3131 {
3132 unsigned int value = 0;
3133
3134 switch (coproc_num)
3135 {
3136 case 1:
3137 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3138 {
3139 FP_formats hold;
3140 hold = FPR_STATE[coproc_reg];
3141 FPR_STATE[coproc_reg] = fmt_word;
3142 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
3143 FPR_STATE[coproc_reg] = hold;
3144 break;
3145 }
3146
3147 default:
3148 #if 0 /* should be controlled by configuration option */
3149 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3150 #endif
3151 break;
3152 }
3153
3154 return(value);
3155 }
3156
3157 uword64
3158 cop_sd (SIM_DESC sd,
3159 sim_cpu *cpu,
3160 address_word cia,
3161 int coproc_num,
3162 int coproc_reg)
3163 {
3164 uword64 value = 0;
3165 switch (coproc_num)
3166 {
3167 case 1:
3168 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3169 {
3170 value = ValueFPR(coproc_reg,fmt_uninterpreted);
3171 break;
3172 }
3173
3174 default:
3175 #if 0 /* should be controlled by configuration option */
3176 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3177 #endif
3178 break;
3179 }
3180
3181 return(value);
3182 }
3183
3184
3185 /* start-sanitize-sky */
3186 #ifdef TARGET_SKY
3187 unsigned128
3188 cop_sq (SIM_DESC sd,
3189 sim_cpu *cpu,
3190 address_word cia,
3191 int coproc_num,
3192 int coproc_reg)
3193 {
3194 unsigned128 value = U16_8(0, 0);
3195 switch (coproc_num)
3196 {
3197 case 2:
3198 {
3199 unsigned_16 xyzw;
3200 int i;
3201
3202 while(vu0_busy())
3203 vu0_issue(sd);
3204
3205 /* one word at a time, argh! */
3206 for(i=0; i<4; i++)
3207 {
3208 unsigned_4 value;
3209 read_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3210 *A4_16(& xyzw, 3-i) = T2H_4(value);
3211 }
3212 return xyzw;
3213 }
3214 break;
3215
3216 default:
3217 sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3218 coproc_num,coproc_reg,pr_addr(cia));
3219 break;
3220 }
3221
3222 return(value);
3223 }
3224 #endif /* TARGET_SKY */
3225 /* end-sanitize-sky */
3226
3227
3228 void
3229 decode_coproc (SIM_DESC sd,
3230 sim_cpu *cpu,
3231 address_word cia,
3232 unsigned int instruction)
3233 {
3234 int coprocnum = ((instruction >> 26) & 3);
3235
3236 switch (coprocnum)
3237 {
3238 case 0: /* standard CPU control and cache registers */
3239 {
3240 int code = ((instruction >> 21) & 0x1F);
3241 int rt = ((instruction >> 16) & 0x1F);
3242 int rd = ((instruction >> 11) & 0x1F);
3243 int tail = instruction & 0x3ff;
3244 /* R4000 Users Manual (second edition) lists the following CP0
3245 instructions:
3246 CODE><-RT><RD-><--TAIL--->
3247 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3248 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3249 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3250 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3251 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3252 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3253 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3254 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3255 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3256 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3257 */
3258 if (((code == 0x00) || (code == 0x04)) && tail == 0)
3259 {
3260 /* M[TF]C0 - 32 bit word */
3261
3262 switch (rd) /* NOTEs: Standard CP0 registers */
3263 {
3264 /* 0 = Index R4000 VR4100 VR4300 */
3265 /* 1 = Random R4000 VR4100 VR4300 */
3266 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3267 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3268 /* 4 = Context R4000 VR4100 VR4300 */
3269 /* 5 = PageMask R4000 VR4100 VR4300 */
3270 /* 6 = Wired R4000 VR4100 VR4300 */
3271 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3272 /* 9 = Count R4000 VR4100 VR4300 */
3273 /* 10 = EntryHi R4000 VR4100 VR4300 */
3274 /* 11 = Compare R4000 VR4100 VR4300 */
3275 /* 12 = SR R4000 VR4100 VR4300 */
3276 #ifdef SUBTARGET_R3900
3277 case 3:
3278 /* ignore */
3279 break;
3280 /* 3 = Config R3900 */
3281
3282 case 7:
3283 /* ignore */
3284 break;
3285 /* 3 = Cache R3900 */
3286
3287 #endif /* SUBTARGET_R3900 */
3288 case 12:
3289 if (code == 0x00)
3290 GPR[rt] = SR;
3291 else
3292 SR = GPR[rt];
3293 break;
3294 /* 13 = Cause R4000 VR4100 VR4300 */
3295 case 13:
3296 if (code == 0x00)
3297 GPR[rt] = CAUSE;
3298 else
3299 CAUSE = GPR[rt];
3300 break;
3301 /* 14 = EPC R4000 VR4100 VR4300 */
3302 case 14:
3303 if (code == 0x00)
3304 GPR[rt] = (signed_word) (signed_address) EPC;
3305 else
3306 EPC = GPR[rt];
3307 break;
3308 /* 15 = PRId R4000 VR4100 VR4300 */
3309 #ifdef SUBTARGET_R3900
3310 /* 16 = Debug */
3311 case 16:
3312 if (code == 0x00)
3313 GPR[rt] = Debug;
3314 else
3315 Debug = GPR[rt];
3316 break;
3317 #else
3318 /* 16 = Config R4000 VR4100 VR4300 */
3319 case 16:
3320 if (code == 0x00)
3321 GPR[rt] = C0_CONFIG;
3322 else
3323 C0_CONFIG = GPR[rt];
3324 break;
3325 #endif
3326 #ifdef SUBTARGET_R3900
3327 /* 17 = Debug */
3328 case 17:
3329 if (code == 0x00)
3330 GPR[rt] = DEPC;
3331 else
3332 DEPC = GPR[rt];
3333 break;
3334 #else
3335 /* 17 = LLAddr R4000 VR4100 VR4300 */
3336 #endif
3337 /* 18 = WatchLo R4000 VR4100 VR4300 */
3338 /* 19 = WatchHi R4000 VR4100 VR4300 */
3339 /* 20 = XContext R4000 VR4100 VR4300 */
3340 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3341 /* 27 = CacheErr R4000 VR4100 */
3342 /* 28 = TagLo R4000 VR4100 VR4300 */
3343 /* 29 = TagHi R4000 VR4100 VR4300 */
3344 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3345 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3346 /* CPR[0,rd] = GPR[rt]; */
3347 default:
3348 if (code == 0x00)
3349 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
3350 else
3351 COP0_GPR[rd] = GPR[rt];
3352 #if 0
3353 if (code == 0x00)
3354 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3355 else
3356 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3357 #endif
3358 }
3359 }
3360 /* start-sanitize-r5900 */
3361 else if (((code == 0x00) || (code == 0x04)) && rd == 0x18 && tail > 0 && tail < NR_COP0_BP)
3362 /* Break-point registers */
3363 {
3364 if (code == 0x00)
3365 GPR[rt] = (signed_word) (signed32) COP0_BP[tail];
3366 else
3367 COP0_BP[tail] = GPR[rt];
3368 }
3369 else if (((code == 0x00) || (code == 0x04)) && rd == 0x19 && tail > 0 && tail < NR_COP0_P)
3370 /* Performance registers */
3371 {
3372 if (code == 0x00)
3373 GPR[rt] = (signed_word) (signed32) COP0_P[tail];
3374 else
3375 COP0_P[tail] = GPR[rt];
3376 }
3377 /* end-sanitize-r5900 */
3378 else if (code == 0x10 && (tail & 0x3f) == 0x18)
3379 {
3380 /* ERET */
3381 if (SR & status_ERL)
3382 {
3383 /* Oops, not yet available */
3384 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3385 PC = EPC;
3386 SR &= ~status_ERL;
3387 }
3388 else
3389 {
3390 PC = EPC;
3391 SR &= ~status_EXL;
3392 }
3393 }
3394 else if (code == 0x10 && (tail & 0x3f) == 0x10)
3395 {
3396 /* RFE */
3397 #ifdef SUBTARGET_R3900
3398 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3399
3400 /* shift IE/KU history bits right */
3401 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
3402
3403 /* TODO: CACHE register */
3404 #endif /* SUBTARGET_R3900 */
3405 }
3406 else if (code == 0x10 && (tail & 0x3f) == 0x1F)
3407 {
3408 /* DERET */
3409 Debug &= ~Debug_DM;
3410 DELAYSLOT();
3411 DSPC = DEPC;
3412 }
3413 else
3414 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3415 /* TODO: When executing an ERET or RFE instruction we should
3416 clear LLBIT, to ensure that any out-standing atomic
3417 read/modify/write sequence fails. */
3418 }
3419 break;
3420
3421 case 2: /* co-processor 2 */
3422 {
3423 int handle = 0;
3424
3425 /* start-sanitize-sky */
3426 #ifdef TARGET_SKY
3427 /* On the R5900, this refers to a "VU" vector co-processor. */
3428
3429 int i_25_21 = (instruction >> 21) & 0x1f;
3430 int i_20_16 = (instruction >> 16) & 0x1f;
3431 int i_20_6 = (instruction >> 6) & 0x7fff;
3432 int i_15_11 = (instruction >> 11) & 0x1f;
3433 int i_15_0 = instruction & 0xffff;
3434 int i_10_1 = (instruction >> 1) & 0x3ff;
3435 int i_10_0 = instruction & 0x7ff;
3436 int i_10_6 = (instruction >> 6) & 0x1f;
3437 int i_5_0 = instruction & 0x03f;
3438 int interlock = instruction & 0x01;
3439
3440 handle = 1;
3441
3442 /* test COP2 usability */
3443 if(! (SR & status_CU2))
3444 {
3445 SignalException(CoProcessorUnusable,instruction);
3446 /* NOTREACHED */
3447 }
3448
3449 /* BC2T/BC2F/BC2TL/BC2FL handled in r5900.igen */
3450
3451 else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
3452 (i_25_21 == 0x01)) /* QMFC2 */
3453 {
3454 int rt = i_20_16;
3455 int id = i_15_11;
3456
3457 /* interlock checking */
3458 /* POLICY: never busy in macro mode */
3459 while(vu0_busy() && interlock)
3460 vu0_issue(sd);
3461
3462 /* perform VU register access */
3463 if(i_25_21 == 0x01) /* QMFC2 */
3464 {
3465 unsigned_4 x,y,z,w;
3466
3467 /* one word at a time, argh! */
3468 read_vu_vec_reg(&(vu0_device.regs), id, 3, &w);
3469 read_vu_vec_reg(&(vu0_device.regs), id, 2, &z);
3470 read_vu_vec_reg(&(vu0_device.regs), id, 1, &y);
3471 read_vu_vec_reg(&(vu0_device.regs), id, 0, &x);
3472
3473 GPR[rt] = U8_4(T2H_4(y), T2H_4(x));
3474 GPR1[rt] = U8_4(T2H_4(w), T2H_4(z));
3475 }
3476 else /* CFC2 */
3477 {
3478 GPR[rt] = vu0_read_cop2_register(id);
3479 }
3480 }
3481 else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
3482 (i_25_21 == 0x05)) /* QMTC2 */
3483 {
3484 int rt = i_20_16;
3485 int id = i_15_11;
3486
3487 /* interlock checking: wait until M or E bits set */
3488 /* POLICY: never busy in macro mode */
3489 while(vu0_busy() && interlock)
3490 {
3491 if(vu0_micro_interlock_released())
3492 {
3493 vu0_micro_interlock_clear();
3494 break;
3495 }
3496
3497 vu0_issue(sd);
3498 }
3499
3500 /* perform VU register access */
3501 if(i_25_21 == 0x05) /* QMTC2 */
3502 {
3503 unsigned_4 x,y,z,w;
3504
3505 x = H2T_4(V4_8(GPR[rt], 1));
3506 y = H2T_4(V4_8(GPR[rt], 0));
3507 z = H2T_4(V4_8(GPR1[rt], 1));
3508 w = H2T_4(V4_8(GPR1[rt], 0));
3509
3510 /* one word at a time, argh! */
3511 write_vu_vec_reg(&(vu0_device.regs), id, 3, & w);
3512 write_vu_vec_reg(&(vu0_device.regs), id, 2, & z);
3513 write_vu_vec_reg(&(vu0_device.regs), id, 1, & y);
3514 write_vu_vec_reg(&(vu0_device.regs), id, 0, & x);
3515 }
3516 else /* CTC2 */
3517 {
3518 vu0_write_cop2_register(id, GPR[rt]);
3519 }
3520 }
3521 else if(i_10_0 == 0x3bf) /* VWAITQ */
3522 {
3523 while(vu0_q_busy())
3524 vu0_issue(sd);
3525 }
3526 else if(i_5_0 == 0x38) /* VCALLMS */
3527 {
3528 unsigned_4 data = H2T_2(i_20_6);
3529
3530 while(vu0_busy())
3531 vu0_issue(sd);
3532
3533 /* write to reserved CIA register to get VU0 moving */
3534 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3535
3536 ASSERT(vu0_busy());
3537 }
3538 else if(i_5_0 == 0x39) /* VCALLMSR */
3539 {
3540 unsigned_4 data;
3541
3542 while(vu0_busy())
3543 vu0_issue(sd);
3544
3545 read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
3546 /* write to reserved CIA register to get VU0 moving */
3547 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3548
3549 ASSERT(vu0_busy());
3550 }
3551 /* handle all remaining UPPER VU instructions in one block */
3552 else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
3553 (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
3554 {
3555 unsigned_4 vu_upper, vu_lower;
3556 vu_upper =
3557 0x00000000 | /* bits 31 .. 25 */
3558 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3559 vu_lower = 0x8000033c; /* NOP */
3560
3561 /* POLICY: never busy in macro mode */
3562 while(vu0_busy())
3563 vu0_issue(sd);
3564
3565 vu0_macro_issue(vu_upper, vu_lower);
3566
3567 /* POLICY: wait for completion of macro-instruction */
3568 while(vu0_busy())
3569 vu0_issue(sd);
3570 }
3571 /* handle all remaining LOWER VU instructions in one block */
3572 else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
3573 (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
3574 { /* N.B.: VWAITQ already covered by prior case */
3575 unsigned_4 vu_upper, vu_lower;
3576 vu_upper = 0x000002ff; /* NOP/NOP */
3577 vu_lower =
3578 0x80000000 | /* bits 31 .. 25 */
3579 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3580
3581 /* POLICY: never busy in macro mode */
3582 while(vu0_busy())
3583 vu0_issue(sd);
3584
3585 vu0_macro_issue(vu_upper, vu_lower);
3586
3587 /* POLICY: wait for completion of macro-instruction */
3588 while(vu0_busy())
3589 vu0_issue(sd);
3590 }
3591 /* ... no other COP2 instructions ... */
3592 else
3593 {
3594 SignalException(ReservedInstruction, instruction);
3595 /* NOTREACHED */
3596 }
3597
3598 #undef MY_INDEX
3599 #undef MY_PREFIX
3600 #undef MY_NAME
3601
3602 #endif /* TARGET_SKY */
3603 /* end-sanitize-sky */
3604
3605 if(! handle)
3606 {
3607 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3608 instruction,pr_addr(cia));
3609 }
3610 }
3611 break;
3612
3613 case 1: /* should not occur (FPU co-processor) */
3614 case 3: /* should not occur (FPU co-processor) */
3615 SignalException(ReservedInstruction,instruction);
3616 break;
3617 }
3618
3619 return;
3620 }
3621
3622
3623 /*-- instruction simulation -------------------------------------------------*/
3624
3625 /* When the IGEN simulator is being built, the function below is be
3626 replaced by a generated version. However, WITH_IGEN == 2 indicates
3627 that the fubction below should be compiled but under a different
3628 name (to allow backward compatibility) */
3629
3630 #if (WITH_IGEN != 1)
3631 #if (WITH_IGEN > 1)
3632 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3633 void
3634 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3635 #else
3636 void
3637 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3638 #endif
3639 SIM_DESC sd;
3640 int next_cpu_nr; /* ignore */
3641 int nr_cpus; /* ignore */
3642 int siggnal; /* ignore */
3643 {
3644 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
3645 #if !defined(FASTSIM)
3646 unsigned int pipeline_count = 1;
3647 #endif
3648
3649 #ifdef DEBUG
3650 if (STATE_MEMORY (sd) == NULL) {
3651 printf("DBG: simulate() entered with no memory\n");
3652 exit(1);
3653 }
3654 #endif /* DEBUG */
3655
3656 #if 0 /* Disabled to check that everything works OK */
3657 /* The VR4300 seems to sign-extend the PC on its first
3658 access. However, this may just be because it is currently
3659 configured in 32bit mode. However... */
3660 PC = SIGNEXTEND(PC,32);
3661 #endif
3662
3663 /* main controlling loop */
3664 while (1) {
3665 /* vaddr is slowly being replaced with cia - current instruction
3666 address */
3667 address_word cia = (uword64)PC;
3668 address_word vaddr = cia;
3669 address_word paddr;
3670 int cca;
3671 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3672
3673 #ifdef DEBUG
3674 {
3675 printf("DBG: state = 0x%08X :",state);
3676 if (state & simHALTEX) printf(" simHALTEX");
3677 if (state & simHALTIN) printf(" simHALTIN");
3678 printf("\n");
3679 }
3680 #endif /* DEBUG */
3681
3682 DSSTATE = (STATE & simDELAYSLOT);
3683 #ifdef DEBUG
3684 if (dsstate)
3685 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3686 #endif /* DEBUG */
3687
3688 /* Fetch the next instruction from the simulator memory: */
3689 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3690 if ((vaddr & 1) == 0) {
3691 /* Copy the action of the LW instruction */
3692 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3693 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3694 uword64 value;
3695 unsigned int byte;
3696 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3697 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3698 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3699 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3700 } else {
3701 /* Copy the action of the LH instruction */
3702 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3703 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3704 uword64 value;
3705 unsigned int byte;
3706 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3707 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3708 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3709 paddr & ~ (uword64) 1,
3710 vaddr, isINSTRUCTION, isREAL);
3711 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3712 instruction = ((value >> (8 * byte)) & 0xFFFF);
3713 }
3714 } else {
3715 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3716 exit(1);
3717 }
3718
3719 #ifdef DEBUG
3720 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3721 #endif /* DEBUG */
3722
3723 /* This is required by exception processing, to ensure that we can
3724 cope with exceptions in the delay slots of branches that may
3725 already have changed the PC. */
3726 if ((vaddr & 1) == 0)
3727 PC += 4; /* increment ready for the next fetch */
3728 else
3729 PC += 2;
3730 /* NOTE: If we perform a delay slot change to the PC, this
3731 increment is not requuired. However, it would make the
3732 simulator more complicated to try and avoid this small hit. */
3733
3734 /* Currently this code provides a simple model. For more
3735 complicated models we could perform exception status checks at
3736 this point, and set the simSTOP state as required. This could
3737 also include processing any hardware interrupts raised by any
3738 I/O model attached to the simulator context.
3739
3740 Support for "asynchronous" I/O events within the simulated world
3741 could be providing by managing a counter, and calling a I/O
3742 specific handler when a particular threshold is reached. On most
3743 architectures a decrement and check for zero operation is
3744 usually quicker than an increment and compare. However, the
3745 process of managing a known value decrement to zero, is higher
3746 than the cost of using an explicit value UINT_MAX into the
3747 future. Which system is used will depend on how complicated the
3748 I/O model is, and how much it is likely to affect the simulator
3749 bandwidth.
3750
3751 If events need to be scheduled further in the future than
3752 UINT_MAX event ticks, then the I/O model should just provide its
3753 own counter, triggered from the event system. */
3754
3755 /* MIPS pipeline ticks. To allow for future support where the
3756 pipeline hit of individual instructions is known, this control
3757 loop manages a "pipeline_count" variable. It is initialised to
3758 1 (one), and will only be changed by the simulator engine when
3759 executing an instruction. If the engine does not have access to
3760 pipeline cycle count information then all instructions will be
3761 treated as using a single cycle. NOTE: A standard system is not
3762 provided by the default simulator because different MIPS
3763 architectures have different cycle counts for the same
3764 instructions.
3765
3766 [NOTE: pipeline_count has been replaced the event queue] */
3767
3768 /* shuffle the floating point status pipeline state */
3769 ENGINE_ISSUE_PREFIX_HOOK();
3770
3771 /* NOTE: For multi-context simulation environments the "instruction"
3772 variable should be local to this routine. */
3773
3774 /* Shorthand accesses for engine. Note: If we wanted to use global
3775 variables (and a single-threaded simulator engine), then we can
3776 create the actual variables with these names. */
3777
3778 if (!(STATE & simSKIPNEXT)) {
3779 /* Include the simulator engine */
3780 #include "oengine.c"
3781 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3782 #error "Mismatch between run-time simulator code and simulation engine"
3783 #endif
3784 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3785 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3786 #endif
3787 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3788 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3789 #endif
3790
3791 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3792 should check for it being changed. It is better doing it here,
3793 than within the simulator, since it will help keep the simulator
3794 small. */
3795 if (ZERO != 0) {
3796 #if defined(WARN_ZERO)
3797 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3798 #endif /* WARN_ZERO */
3799 ZERO = 0; /* reset back to zero before next instruction */
3800 }
3801 } else /* simSKIPNEXT check */
3802 STATE &= ~simSKIPNEXT;
3803
3804 /* If the delay slot was active before the instruction is
3805 executed, then update the PC to its new value: */
3806 if (DSSTATE) {
3807 #ifdef DEBUG
3808 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3809 #endif /* DEBUG */
3810 PC = DSPC;
3811 CANCELDELAYSLOT();
3812 }
3813
3814 if (MIPSISA < 4)
3815 PENDING_TICK();
3816
3817 #if !defined(FASTSIM)
3818 if (sim_events_tickn (sd, pipeline_count))
3819 {
3820 /* cpu->cia = cia; */
3821 sim_events_process (sd);
3822 }
3823 #else
3824 if (sim_events_tick (sd))
3825 {
3826 /* cpu->cia = cia; */
3827 sim_events_process (sd);
3828 }
3829 #endif /* FASTSIM */
3830 }
3831 }
3832 #endif
3833
3834
3835 /* This code copied from gdb's utils.c. Would like to share this code,
3836 but don't know of a common place where both could get to it. */
3837
3838 /* Temporary storage using circular buffer */
3839 #define NUMCELLS 16
3840 #define CELLSIZE 32
3841 static char*
3842 get_cell()
3843 {
3844 static char buf[NUMCELLS][CELLSIZE];
3845 static int cell=0;
3846 if (++cell>=NUMCELLS) cell=0;
3847 return buf[cell];
3848 }
3849
3850 /* Print routines to handle variable size regs, etc */
3851
3852 /* Eliminate warning from compiler on 32-bit systems */
3853 static int thirty_two = 32;
3854
3855 char*
3856 pr_addr(addr)
3857 SIM_ADDR addr;
3858 {
3859 char *paddr_str=get_cell();
3860 switch (sizeof(addr))
3861 {
3862 case 8:
3863 sprintf(paddr_str,"%08lx%08lx",
3864 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3865 break;
3866 case 4:
3867 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3868 break;
3869 case 2:
3870 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3871 break;
3872 default:
3873 sprintf(paddr_str,"%x",addr);
3874 }
3875 return paddr_str;
3876 }
3877
3878 char*
3879 pr_uword64(addr)
3880 uword64 addr;
3881 {
3882 char *paddr_str=get_cell();
3883 sprintf(paddr_str,"%08lx%08lx",
3884 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3885 return paddr_str;
3886 }
3887
3888
3889
3890 /*---------------------------------------------------------------------------*/
3891 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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