2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 We only need to take account of the target endianness when moving data
23 between the simulator and the host. We do not need to worry about the
24 endianness of the host, since this sim code and GDB are executing in
27 The IDT monitor (found on the VR4300 board), seems to lie about
28 register contents. It seems to treat the registers as sign-extended
29 32-bit values. This cause *REAL* problems when single-stepping 64-bit
34 /* The TRACE and PROFILE manifests enable the provision of extra
35 features. If they are not defined then a simpler (quicker)
36 simulator is constructed without the required run-time checks,
38 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
52 #include "libiberty.h"
54 #include "remote-sim.h" /* GDB simulator interface */
55 #include "callback.h" /* GDB simulator callback interface */
57 #include "support.h" /* internal support manifests */
59 /* Get the simulator engine description, without including the code: */
64 /* The following reserved instruction value is used when a simulator
65 trap is required. NOTE: Care must be taken, since this value may be
66 used in later revisions of the MIPS ISA. */
67 #define RSVD_INSTRUCTION (0x7C000000)
68 #define RSVD_INSTRUCTION_AMASK (0x03FFFFFF)
70 /* NOTE: These numbers depend on the processor architecture being
73 #define TLBModification (1)
76 #define AddressLoad (4)
77 #define AddressStore (5)
78 #define InstructionFetch (6)
79 #define DataReference (7)
80 #define SystemCall (8)
81 #define BreakPoint (9)
82 #define ReservedInstruction (10)
83 #define CoProcessorUnusable (11)
84 #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
89 /* The following exception code is actually private to the simulator
90 world. It is *NOT* a processor feature, and is used to signal
91 run-time errors in the simulator. */
92 #define SimulatorFault (0xFFFFFFFF)
94 /* The following are generic to all versions of the MIPS architecture
96 /* Memory Access Types (for CCA): */
98 #define CachedNoncoherent (1)
99 #define CachedCoherent (2)
102 #define isINSTRUCTION (1 == 0) /* FALSE */
103 #define isDATA (1 == 1) /* TRUE */
105 #define isLOAD (1 == 0) /* FALSE */
106 #define isSTORE (1 == 1) /* TRUE */
108 #define isREAL (1 == 0) /* FALSE */
109 #define isRAW (1 == 1) /* TRUE */
111 #define isTARGET (1 == 0) /* FALSE */
112 #define isHOST (1 == 1) /* TRUE */
114 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
115 is the number of bytes minus 1. */
116 #define AccessLength_BYTE (0)
117 #define AccessLength_HALFWORD (1)
118 #define AccessLength_TRIPLEBYTE (2)
119 #define AccessLength_WORD (3)
120 #define AccessLength_QUINTIBYTE (4)
121 #define AccessLength_SEXTIBYTE (5)
122 #define AccessLength_SEPTIBYTE (6)
123 #define AccessLength_DOUBLEWORD (7)
126 /* FPU registers must be one of the following types. All other values
127 are reserved (and undefined). */
133 /* The following are well outside the normal acceptable format
134 range, and are used in the register status vector. */
135 fmt_unknown
= 0x10000000,
136 fmt_uninterpreted
= 0x20000000,
140 /* NOTE: We cannot avoid globals, since the GDB "sim_" interface does
141 not allow a private variable to be passed around. This means that
142 simulators under GDB can only be single-threaded. However, it would
143 be possible for the simulators to be multi-threaded if GDB allowed
144 for a private pointer to be maintained. i.e. a general "void **ptr"
145 variable that GDB passed around in the argument list to all of
146 sim_xxx() routines. It could be initialised to NULL by GDB, and
147 then updated by sim_open() and used by the other sim_xxx() support
148 functions. This would allow new features in the simulator world,
149 like storing a context - continuing execution to gather a result,
150 and then going back to the point where the context was saved and
151 changing some state before continuing. i.e. the ability to perform
152 UNDOs on simulations. It would also allow the simulation of
153 shared-memory multi-processor systems. */
155 static host_callback
*callback
= NULL
; /* handle onto the current callback structure */
157 /* The warning system should be improved, to allow more information to
158 be passed about the cause: */
159 #define WARNING(m) { callback->printf_filtered(callback,"SIM Warning: %s\n",(m)); }
161 /* This is nasty, since we have to rely on matching the register
162 numbers used by GDB. Unfortunately, depending on the MIPS target
163 GDB uses different register numbers. We cannot just include the
164 relevant "gdb/tm.h" link, since GDB may not be configured before
165 the sim world, and also the GDB header file requires too much other
167 /* TODO: Sort out a scheme for *KNOWING* the mapping between real
168 registers, and the numbers that GDB uses. At the moment due to the
169 order that the tools are built, we cannot rely on a configured GDB
170 world whilst constructing the simulator. This means we have to
171 assume the GDB register number mapping. */
172 #define LAST_EMBED_REGNUM (89)
174 /* To keep this default simulator simple, and fast, we use a direct
175 vector of registers. The internal simulator engine then uses
176 manifests to access the correct slot. */
177 ut_reg registers
[LAST_EMBED_REGNUM
+ 1];
178 int register_widths
[LAST_EMBED_REGNUM
+ 1];
180 #define GPR (®isters[0])
183 #define FGR (®isters[FGRIDX])
185 #define LO (registers[33])
186 #define HI (registers[34])
187 #define PC (registers[37])
188 #define CAUSE (registers[36])
190 #define SR (registers[SRIDX]) /* CPU status register */
192 #define FCR0 (registers[FCR0IDX]) /* really a 32bit register */
193 #define FCR31IDX (70)
194 #define FCR31 (registers[FCR31IDX]) /* really a 32bit register */
196 #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
198 /* The following are pseudonyms for standard registers */
199 #define ZERO (registers[0])
200 #define V0 (registers[2])
201 #define A0 (registers[4])
202 #define A1 (registers[5])
203 #define A2 (registers[6])
204 #define A3 (registers[7])
205 #define SP (registers[29])
206 #define RA (registers[31])
208 ut_reg EPC
= 0; /* Exception PC */
211 /* Keep the current format state for each register: */
212 FP_formats fpr_state
[32];
215 /* VR4300 CP0 configuration register: */
216 unsigned int CONFIG
= 0;
218 /* The following are internal simulator state variables: */
219 ut_reg IPC
= 0; /* internal Instruction PC */
220 ut_reg DSPC
= 0; /* delay-slot PC */
223 /* TODO : these should be the bitmasks for these bits within the
224 status register. At the moment the following are VR4300
226 #define status_KSU_mask (0x3) /* mask for KSU bits */
227 #define status_KSU_shift (3) /* shift for field */
228 #define ksu_kernel (0x0)
229 #define ksu_supervisor (0x1)
230 #define ksu_user (0x2)
231 #define ksu_unknown (0x3)
233 #define status_RE (1 << 25) /* Reverse Endian in user mode */
234 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
235 #define status_SR (1 << 20) /* soft reset or NMI */
236 #define status_BEV (1 << 22) /* Location of general exception vectors */
237 #define status_TS (1 << 21) /* TLB shutdown has occurred */
238 #define status_ERL (1 << 2) /* Error level */
239 #define status_RP (1 << 27) /* Reduced Power mode */
241 #define config_EP_mask (0xF)
242 #define config_EP_shift (27)
243 #define config_EP_D (0x0)
244 #define config_EP_DxxDxx (0x6)
246 #define config_BE (1 << 15)
248 #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
251 /* Macro to update FPSR condition-code field. This is complicated by
252 the fact that there is a hole in the index range of the bits within
253 the FCSR register. Also, the number of bits visible depends on the
254 MIPS ISA version being supported. */
255 #define SETFCC(cc,v) {\
256 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
257 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
259 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
261 /* This should be the COC1 value at the start of the preceding
263 #define PREVCOC1() ((state & simPCOC1) ? 1 : 0)
266 /* Standard FCRS bits: */
267 #define IR (0) /* Inexact Result */
268 #define UF (1) /* UnderFlow */
269 #define OF (2) /* OverFlow */
270 #define DZ (3) /* Division by Zero */
271 #define IO (4) /* Invalid Operation */
272 #define UO (5) /* Unimplemented Operation */
274 /* Get masks for individual flags: */
275 #if 1 /* SAFE version */
276 #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
277 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
278 #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
280 #define FP_FLAGS(b) (1 << ((b) + 2))
281 #define FP_ENABLE(b) (1 << ((b) + 7))
282 #define FP_CAUSE(b) (1 << ((b) + 12))
285 #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
287 #define FP_MASK_RM (0x3)
289 #define FP_RM_NEAREST (0) /* Round to nearest (Round) */
290 #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
291 #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
292 #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
293 #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
295 /* Slots for delayed register updates. For the moment we just have a
296 fixed number of slots (rather than a more generic, dynamic
297 system). This keeps the simulator fast. However, we only allow for
298 the register update to be delayed for a single instruction
300 #define PSLOTS (5) /* Maximum number of instruction cycles */
304 int pending_slot_count
[PSLOTS
];
305 int pending_slot_reg
[PSLOTS
];
306 ut_reg pending_slot_value
[PSLOTS
];
308 /* The following are not used for MIPS IV onwards: */
309 #define PENDING_FILL(r,v) {\
310 printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
311 if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\
312 callback->printf_filtered(callback,"SIM Warning: Attempt to over-write pending value\n");\
313 pending_slot_count[pending_in] = 2;\
314 pending_slot_reg[pending_in] = (r);\
315 pending_slot_value[pending_in] = (uword64)(v);\
316 printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));\
319 if (pending_in == PSLOTS)\
321 printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
325 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
326 read-write instructions. It is set when a linked load occurs. It is
327 tested and cleared by the conditional store. It is cleared (during
328 other CPU operations) when a store to the location would no longer
329 be atomic. In particular, it is cleared by exception return
334 /* The HIACCESS and LOACCESS counts are used to ensure that
335 corruptions caused by using the HI or LO register to close to a
336 following operation are spotted. */
338 /* If either of the preceding two instructions have accessed the HI or
339 LO registers, then the values they see should be
340 undefined. However, to keep the simulator world simple, we just let
341 them use the value read and raise a warning to notify the user: */
342 #define CHECKHILO(s) {\
343 if ((HIACCESS != 0) || (LOACCESS != 0))\
344 callback->printf_filtered(callback,"SIM Warning: %s over-writing HI and LO registers values\n",(s));\
345 /* Set the access counts, since we are about\
346 to update the HI and LO registers: */\
347 HIACCESS = LOACCESS = 3; /* 3rd instruction will be safe */\
350 /* NOTE: We keep the following status flags as bit values (1 for true,
351 0 for false). This allows them to be used in binary boolean
352 operations without worrying about what exactly the non-zero true
356 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
359 /* Hardware configuration. Affects endianness of LoadMemory and
360 StoreMemory and the endianness of Kernel and Supervisor mode
361 execution. The value is 0 for little-endian; 1 for big-endian. */
362 #define BigEndianMem ((CONFIG & config_BE) ? 1 : 0)
363 /* NOTE: Problems will occur if the simulator memory model does not
364 match the host program expectation. i.e. if the host is writing
365 big-endian values to a little-endian memory model. */
368 /* This mode is selected if in User mode with the RE bit being set in
369 SR (Status Register). It reverses the endianness of load and store
371 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
374 /* The endianness for load and store instructions (0=little;1=big). In
375 User mode this endianness may be switched by setting the state_RE
376 bit in the SR register. Thus, BigEndianCPU may be computed as
377 (BigEndienMem EOR ReverseEndian). */
378 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
380 #if !defined(FASTSIM) || defined(PROFILE)
381 /* At the moment these values will be the same, since we do not have
382 access to the pipeline cycle count information from the simulator
384 unsigned int instruction_fetches
= 0;
385 unsigned int pipeline_ticks
= 0;
388 /* Flags in the "state" variable: */
389 #define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */
390 #define simSTEP (1 << 1) /* 0 = run; 1 = single-step */
391 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
392 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
393 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
394 #define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */
395 #define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */
396 /* Whilst simSTOP is not set, the simulator control loop should just
397 keep simulating instructions. The simSTEP flag is used to force
398 single-step execution. */
399 #define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */
400 #define simPCOC0 (1 << 17) /* COC[1] from current */
401 #define simPCOC1 (1 << 18) /* COC[1] from previous */
402 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
403 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
404 #define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
405 #define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
407 unsigned int state
= (0 | simBE
); /* big-endian simulator by default */
408 unsigned int rcexit
= 0; /* _exit() reason code holder */
410 #define DELAYSLOT() {\
411 if (state & simDELAYSLOT) callback->printf_filtered(callback,"SIM Warning: Delay slot already activated (branch in delay slot?)\n");\
412 state |= simDELAYSLOT;\
416 state &= ~simDELAYSLOT;\
417 state |= simSKIPNEXT;\
420 /* Very simple memory model to start with: */
421 unsigned char *membank
= NULL
;
422 ut_reg membank_base
= 0xA0000000;
423 unsigned membank_size
= (1 << 20); /* (16 << 20); */ /* power-of-2 */
425 /* Simple run-time monitor support */
426 unsigned char *monitor
= NULL
;
427 ut_reg monitor_base
= 0xBFC00000;
428 unsigned monitor_size
= (1 << 11); /* power-of-2 */
431 char *tracefile
= "trace.din"; /* default filename for trace log */
432 FILE *tracefh
= NULL
;
436 unsigned profile_frequency
= 256;
437 unsigned profile_nsamples
= (128 << 10);
438 unsigned short *profile_hist
= NULL
;
439 ut_reg profile_minpc
;
440 ut_reg profile_maxpc
;
441 int profile_shift
= 0; /* address shift amount */
444 /*---------------------------------------------------------------------------*/
445 /*-- GDB simulator interface ------------------------------------------------*/
446 /*---------------------------------------------------------------------------*/
448 static void dotrace
PARAMS((FILE *tracefh
,int type
,unsigned int address
,int width
,char *comment
,...));
449 extern void sim_error
PARAMS((char *fmt
,...));
450 static void ColdReset
PARAMS((void));
451 static int AddressTranslation
PARAMS((uword64 vAddr
,int IorD
,int LorS
,uword64
*pAddr
,int *CCA
,int host
,int raw
));
452 static void StoreMemory
PARAMS((int CCA
,int AccessLength
,uword64 MemElem
,uword64 pAddr
,uword64 vAddr
,int raw
));
453 static uword64 LoadMemory
PARAMS((int CCA
,int AccessLength
,uword64 pAddr
,uword64 vAddr
,int IorD
,int raw
));
454 static void SignalException
PARAMS((int exception
,...));
455 static void simulate
PARAMS((void));
456 static long getnum(char *value
);
457 extern void sim_size(unsigned int newsize
);
458 extern void sim_set_profile(int frequency
);
459 static unsigned int power2(unsigned int value
);
465 if (callback
== NULL
) {
466 fprintf(stderr
,"SIM Error: sim_open() called without callbacks attached\n");
470 /* The following ensures that the standard file handles for stdin,
471 stdout and stderr are initialised: */
472 callback
->init(callback
);
476 if (state
& simEXCEPTION
) {
477 fprintf(stderr
,"This simulator is not suitable for this host configuration\n");
483 if (*((char *)&data
) != 0x12)
484 state
|= simHOSTBE
; /* big-endian host */
488 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
489 and DOUBLE binary formats. This is a bit nasty, requiring that we
490 trust the explicit manifests held in the source: */
495 if (((float)4.01102924346923828125 != *(float *)s
) || ((double)523.2939453125 != *(double *)s
)) {
496 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
502 /* This is NASTY, in that we are assuming the size of specific
506 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
508 register_widths
[rn
] = GPRLEN
;
509 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
510 register_widths
[rn
] = GPRLEN
;
511 else if ((rn
>= 33) && (rn
<= 37))
512 register_widths
[rn
] = GPRLEN
;
513 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
514 register_widths
[rn
] = 32;
516 register_widths
[rn
] = 0;
520 /* It would be good if we could select particular named MIPS
521 architecture simulators. However, having a pre-built, fixed
522 engine would mean including multiple engines. If the simulator is
523 changed to a run-time conditional version, then the ability to
524 select a particular architecture would be straightforward. */
530 static struct option cmdline
[] = {
533 {"profile", 0,0,'p'},
536 {"tracefile",1,0,'z'},
537 {"frequency",1,0,'y'},
538 {"samples", 1,0,'x'},
542 /* Unfortunately, getopt_long() is designed to be used with
543 vectors, where the first option is normally program name (and
544 ignored). We cheat by creating a dummy first argument, so that
545 we can use the standard argument processing. */
546 #define DUMMYARG "simulator "
547 cline
= (char *)malloc(strlen(args
) + strlen(DUMMYARG
) + 1);
549 fprintf(stderr
,"Failed to allocate memory for command line buffer\n");
552 sprintf(cline
,"%s%s",DUMMYARG
,args
);
553 argv
= buildargv(cline
);
554 for (argc
= 0; argv
[argc
]; argc
++);
556 /* Unfortunately, getopt_long() assumes that it is ignoring the
557 first argument (normally the program name). This means it
558 ignores the first option on our "args" line. */
559 optind
= 0; /* Force reset of argument processing */
561 int option_index
= 0;
563 c
= getopt_long(argc
,argv
,"hn:s:tp",cmdline
,&option_index
);
569 callback
->printf_filtered(callback
,"Usage:\n\t\
570 target sim [-h] [--name=<model>] [--size=<amount>]");
572 callback
->printf_filtered(callback
," [-t [--tracefile=<name>]]");
575 callback
->printf_filtered(callback
," [-p [--frequency=<count>] [--samples=<count>]]");
577 callback
->printf_filtered(callback
,"\n");
581 callback
->printf_filtered(callback
,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg
);
585 membank_size
= (unsigned)getnum(optarg
);
590 /* Eventually the simTRACE flag could be treated as a toggle, to
591 allow external control of the program points being traced
592 (i.e. only from main onwards, excluding the run-time setup,
597 Simulator constructed without tracing support (for performance).\n\
598 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
604 if (optarg
!= NULL
) {
606 tmp
= (char *)malloc(strlen(optarg
) + 1);
608 callback
->printf_filtered(callback
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
612 callback
->printf_filtered(callback
,"Placing trace information into file \"%s\"\n",tracefile
);
623 Simulator constructed without profiling support (for performance).\n\
624 Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
625 #endif /* !PROFILE */
630 profile_nsamples
= (unsigned)getnum(optarg
);
636 sim_set_profile((int)getnum(optarg
));
641 callback
->printf_filtered(callback
,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c
);
648 callback
->printf_filtered(callback
,"Warning: Ignoring spurious non-option arguments ");
649 while (optind
< argc
)
650 callback
->printf_filtered(callback
,"\"%s\" ",argv
[optind
++]);
651 callback
->printf_filtered(callback
,"\n");
657 /* If the host has "mmap" available we could use it to provide a
658 very large virtual address space for the simulator, since memory
659 would only be allocated within the "mmap" space as it is
660 accessed. This can also be linked to the architecture specific
661 support, required to simulate the MMU. */
662 sim_size(membank_size
);
663 /* NOTE: The above will also have enabled any profiling state */
666 /* If we were providing a more complete I/O, co-processor or memory
667 simulation, we should perform any "device" initialisation at this
668 point. This can include pre-loading memory areas with particular
669 patterns (e.g. simulating ROM monitors). */
671 /* We can start writing to the memory, now that the processor has
673 monitor
= (unsigned char *)calloc(1,monitor_size
);
675 fprintf(stderr
,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size
);
678 /* TODO: Provide support for PMON monitor */
679 /* Entry into the IDT monitor is via fixed address vectors, and
680 not using machine instructions. To avoid clashing with use of
681 the MIPS TRAP system, we place our own (simulator specific)
682 "undefined" instructions into the relevant vector slots. */
683 for (loop
= 0; (loop
< monitor_size
); loop
+= 4) {
684 uword64 vaddr
= (monitor_base
+ loop
);
687 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
))
688 StoreMemory(cca
,AccessLength_WORD
,(RSVD_INSTRUCTION
| ((loop
>> 2) & RSVD_INSTRUCTION_AMASK
)),paddr
,vaddr
,isRAW
);
693 if (state
& simTRACE
) {
694 tracefh
= fopen(tracefile
,"wb+");
695 if (tracefh
== NULL
) {
696 callback
->printf_filtered(callback
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
705 /* For the profile writing, we write the data in the host
706 endianness. This unfortunately means we are assuming that the
707 profile file we create is processed on the same host executing the
708 simulator. The gmon.out file format should either have an explicit
709 endianness, or a method of encoding the endianness in the file
719 if (state
& simHOSTBE
) {
720 buff
[3] = ((val
>> 0) & 0xFF);
721 buff
[2] = ((val
>> 8) & 0xFF);
722 buff
[1] = ((val
>> 16) & 0xFF);
723 buff
[0] = ((val
>> 24) & 0xFF);
725 buff
[0] = ((val
>> 0) & 0xFF);
726 buff
[1] = ((val
>> 8) & 0xFF);
727 buff
[2] = ((val
>> 16) & 0xFF);
728 buff
[3] = ((val
>> 24) & 0xFF);
730 if (fwrite(buff
,4,1,fh
) != 1) {
731 callback
->printf_filtered(callback
,"Failed to write 4bytes to the profile file\n");
744 if (state
& simHOSTBE
) {
745 buff
[1] = ((val
>> 0) & 0xFF);
746 buff
[0] = ((val
>> 8) & 0xFF);
748 buff
[0] = ((val
>> 0) & 0xFF);
749 buff
[1] = ((val
>> 8) & 0xFF);
751 if (fwrite(buff
,2,1,fh
) != 1) {
752 callback
->printf_filtered(callback
,"Failed to write 2bytes to the profile file\n");
763 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
766 /* Cannot assume sim_kill() has been called */
767 /* "quitting" is non-zero if we cannot hang on errors */
769 /* Ensure that any resources allocated through the callback
770 mechanism are released: */
771 callback
->shutdown(callback
);
774 if ((state
& simPROFILE
) && (profile_hist
!= NULL
)) {
775 unsigned short *p
= profile_hist
;
776 FILE *pf
= fopen("gmon.out","wb");
780 callback
->printf_filtered(callback
,"Failed to open \"gmon.out\" profile file\n");
784 printf("DBG: minpc = 0x%08X\n",(unsigned int)profile_minpc
);
785 printf("DBG: maxpc = 0x%08X\n",(unsigned int)profile_maxpc
);
787 ok
= writeout32(pf
,(unsigned int)profile_minpc
);
789 ok
= writeout32(pf
,(unsigned int)profile_maxpc
);
791 ok
= writeout32(pf
,(profile_nsamples
* 2) + 12); /* size of sample buffer (+ header) */
793 printf("DBG: nsamples = %d (size = 0x%08X)\n",profile_nsamples
,((profile_nsamples
* 2) + 12));
795 for (loop
= 0; (ok
&& (loop
< profile_nsamples
)); loop
++) {
796 ok
= writeout16(pf
,profile_hist
[loop
]);
806 state
&= ~simPROFILE
;
811 if (tracefh
!= stderr
)
824 sim_resume (step
,signal
)
828 printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step
,signal
,membank
);
832 state
|= simSTEP
; /* execute only a single instruction */
834 state
&= ~(simSTOP
| simSTEP
); /* execute until event */
836 state
|= (simHALTEX
| simHALTIN
); /* treat interrupt event as exception */
838 /* Start executing instructions from the current state (set
839 explicitly by register updates, or by sim_create_inferior): */
846 sim_write (addr
,buffer
,size
)
848 unsigned char *buffer
;
852 uword64 vaddr
= (uword64
)addr
;
854 /* Return the number of bytes written, or zero if error. */
856 callback
->printf_filtered(callback
,"sim_write(0x%08X%08X,buffer,%d);\n",WORD64HI(addr
),WORD64LO(addr
),size
);
859 /* We provide raw read and write routines, since we do not want to
860 count the GDB memory accesses in our statistics gathering. */
862 /* There is a lot of code duplication in the individual blocks
863 below, but the variables are declared locally to a block to give
864 the optimiser the best chance of improving the code. We have to
865 perform slow byte reads from the host memory, to ensure that we
866 get the data into the correct endianness for the (simulated)
867 target memory world. */
869 /* Mask count to get odd byte, odd halfword, and odd word out of the
870 way. We can then perform doubleword transfers to and from the
871 simulator memory for optimum performance. */
872 if (index
&& (index
& 1)) {
875 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
876 uword64 value
= ((uword64
)(*buffer
++));
877 StoreMemory(cca
,AccessLength_BYTE
,value
,paddr
,vaddr
,isRAW
);
880 index
&= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
882 if (index
&& (index
& 2)) {
885 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
887 /* We need to perform the following magic to ensure that that
888 bytes are written into same byte positions in the target memory
889 world, regardless of the endianness of the host. */
891 value
= ((uword64
)(*buffer
++) << 8);
892 value
|= ((uword64
)(*buffer
++) << 0);
894 value
= ((uword64
)(*buffer
++) << 0);
895 value
|= ((uword64
)(*buffer
++) << 8);
897 StoreMemory(cca
,AccessLength_HALFWORD
,value
,paddr
,vaddr
,isRAW
);
902 if (index
&& (index
& 4)) {
905 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
908 value
= ((uword64
)(*buffer
++) << 24);
909 value
|= ((uword64
)(*buffer
++) << 16);
910 value
|= ((uword64
)(*buffer
++) << 8);
911 value
|= ((uword64
)(*buffer
++) << 0);
913 value
= ((uword64
)(*buffer
++) << 0);
914 value
|= ((uword64
)(*buffer
++) << 8);
915 value
|= ((uword64
)(*buffer
++) << 16);
916 value
|= ((uword64
)(*buffer
++) << 24);
918 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
923 for (;index
; index
-= 8) {
926 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isRAW
)) {
929 value
= ((uword64
)(*buffer
++) << 56);
930 value
|= ((uword64
)(*buffer
++) << 48);
931 value
|= ((uword64
)(*buffer
++) << 40);
932 value
|= ((uword64
)(*buffer
++) << 32);
933 value
|= ((uword64
)(*buffer
++) << 24);
934 value
|= ((uword64
)(*buffer
++) << 16);
935 value
|= ((uword64
)(*buffer
++) << 8);
936 value
|= ((uword64
)(*buffer
++) << 0);
938 value
= ((uword64
)(*buffer
++) << 0);
939 value
|= ((uword64
)(*buffer
++) << 8);
940 value
|= ((uword64
)(*buffer
++) << 16);
941 value
|= ((uword64
)(*buffer
++) << 24);
942 value
|= ((uword64
)(*buffer
++) << 32);
943 value
|= ((uword64
)(*buffer
++) << 40);
944 value
|= ((uword64
)(*buffer
++) << 48);
945 value
|= ((uword64
)(*buffer
++) << 56);
947 StoreMemory(cca
,AccessLength_DOUBLEWORD
,value
,paddr
,vaddr
,isRAW
);
956 sim_read (addr
,buffer
,size
)
958 unsigned char *buffer
;
963 /* Return the number of bytes read, or zero if error. */
965 callback
->printf_filtered(callback
,"sim_read(0x%08X%08X,buffer,%d);\n",WORD64HI(addr
),WORD64LO(addr
),size
);
968 /* TODO: Perform same optimisation as the sim_write() code
969 above. NOTE: This will require a bit more work since we will need
970 to ensure that the source physical address is doubleword aligned
971 before, and then deal with trailing bytes. */
972 for (index
= 0; (index
< size
); index
++) {
973 uword64 vaddr
,paddr
,value
;
975 vaddr
= (uword64
)addr
+ index
;
976 if (AddressTranslation(vaddr
,isDATA
,isLOAD
,&paddr
,&cca
,isTARGET
,isRAW
)) {
977 value
= LoadMemory(cca
,AccessLength_BYTE
,paddr
,vaddr
,isDATA
,isRAW
);
978 buffer
[index
] = (unsigned char)(value
&0xFF);
987 sim_store_register (rn
,memory
)
989 unsigned char *memory
;
992 callback
->printf_filtered(callback
,"sim_store_register(%d,*memory=0x%08X%08X);\n",rn
,*((unsigned int *)memory
),*((unsigned int *)(memory
+ 4)));
995 /* Unfortunately this suffers from the same problem as the register
996 numbering one. We need to know what the width of each logical
997 register number is for the architecture being simulated. */
998 if (register_widths
[rn
] == 0)
999 callback
->printf_filtered(callback
,"Warning: Invalid register width for %d (register store ignored)\n",rn
);
1001 if (register_widths
[rn
] == 32)
1002 registers
[rn
] = *((unsigned int *)memory
);
1004 registers
[rn
] = *((uword64
*)memory
);
1011 sim_fetch_register (rn
,memory
)
1013 unsigned char *memory
;
1016 callback
->printf_filtered(callback
,"sim_fetch_register(%d=0x%08X%08X,mem) : place simulator registers into memory\n",rn
,WORD64HI(registers
[rn
]),WORD64LO(registers
[rn
]));
1019 if (register_widths
[rn
] == 0)
1020 callback
->printf_filtered(callback
,"Warning: Invalid register width for %d (register fetch ignored)\n",rn
);
1022 if (register_widths
[rn
] == 32)
1023 *((unsigned int *)memory
) = (registers
[rn
] & 0xFFFFFFFF);
1024 else /* 64bit register */
1025 *((uword64
*)memory
) = registers
[rn
];
1031 sim_stop_reason (reason
,sigrc
)
1032 enum sim_stop
*reason
;
1035 /* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so
1036 sim_exited *sigrc = argument to exit()
1037 sim_stopped *sigrc = exception number
1038 sim_signalled *sigrc = signal number
1040 if (state
& simEXCEPTION
) {
1041 /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers,
1042 and not the MIPS specific exception codes. */
1044 /* For some reason, sending GDB a sim_signalled reason cause it to
1046 *reason
= sim_stopped
;
1048 *reason
= sim_signalled
;
1050 switch ((CAUSE
>> 2) & 0x1F) {
1052 *sigrc
= SIGINT
; /* wrong type of interrupt, but it will do for the moment */
1055 case TLBModification
:
1060 case InstructionFetch
:
1065 case ReservedInstruction
:
1066 case CoProcessorUnusable
:
1070 case IntegerOverflow
:
1082 default : /* Unknown internal exception */
1086 } else if (state
& simEXIT
) {
1087 printf("DBG: simEXIT (%d)\n",rcexit
);
1088 *reason
= sim_exited
;
1090 } else { /* assume single-stepping */
1091 *reason
= sim_stopped
;
1094 state
&= ~(simEXCEPTION
| simEXIT
);
1102 /* Accessed from the GDB "info files" command: */
1104 callback
->printf_filtered(callback
,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT
? 64 : 32));
1106 callback
->printf_filtered(callback
,"%s endian memory model\n",(BigEndianMem
? "Big" : "Little"));
1108 callback
->printf_filtered(callback
,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size
,WORD64HI(membank_base
),WORD64LO(membank_base
));
1110 #if !defined(FASTSIM)
1111 callback
->printf_filtered(callback
,"Instruction fetches = %d\n",instruction_fetches
);
1112 callback
->printf_filtered(callback
,"Pipeline ticks = %d\n",pipeline_ticks
);
1113 /* It would be a useful feature, if when performing multi-cycle
1114 simulations (rather than single-stepping) we keep the start and
1115 end times of the execution, so that we can give a performance
1116 figure for the simulator. */
1117 #endif /* !FASTSIM */
1119 /* print information pertaining to MIPS ISA and architecture being simulated */
1120 /* things that may be interesting */
1121 /* instructions executed - if available */
1122 /* cycles executed - if available */
1123 /* pipeline stalls - if available */
1124 /* virtual time taken */
1125 /* profiling size */
1126 /* profiling frequency */
1134 sim_load (prog
,from_tty
)
1138 /* Return non-zero if the caller should handle the load. Zero if
1139 we have loaded the image. */
1144 sim_create_inferior (start_address
,argv
,env
)
1145 SIM_ADDR start_address
;
1150 printf("DBG: sim_create_inferior entered: start_address = 0x%08X\n",start_address
);
1153 /* Prepare to execute the program to be simulated */
1154 /* argv and env are NULL terminated lists of pointers */
1157 PC
= (uword64
)start_address
;
1159 /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
1160 PC
= SIGNEXTEND(start_address
,32);
1162 /* NOTE: GDB normally sets the PC explicitly. However, this call is
1163 used by other clients of the simulator. */
1166 callback
->printf_filtered(callback
,"sim_create_inferior() : passed arguments ignored\n");
1167 #if 1 /* def DEBUG */
1170 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
1171 printf("DBG: arg \"%s\"\n",*cptr
);
1174 /* We should really place the argv slot values into the argument
1175 registers, and onto the stack as required. However, this
1176 assumes that we have a stack defined, which is not necessarily
1177 true at the moment. */
1187 /* This routine should be for terminating any existing simulation
1188 thread. Since we are single-threaded only at the moment, this is
1189 not an issue. It should *NOT* be used to terminate the
1191 #else /* do *NOT* call sim_close */
1192 sim_close(1); /* Do not hang on errors */
1193 /* This would also be the point where any memory mapped areas used
1194 by the simulator should be released. */
1200 sim_get_quit_code ()
1202 /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as
1203 the function return value. However, it may be more correct for
1204 this to return the argument to the exit() function (if
1210 sim_set_callbacks (p
)
1217 typedef enum {e_terminate
,e_help
,e_setmemsize
,e_reset
} e_cmds
;
1219 static struct t_sim_command
{
1223 } sim_commands
[] = {
1224 {e_help
, "help", ": Show MIPS simulator private commands"},
1225 {e_setmemsize
,"set-memory-size","<n> : Specify amount of memory simulated"},
1226 {e_reset
, "reset-system", ": Reset the simulated processor"},
1231 sim_do_command (cmd
)
1234 struct t_sim_command
*cptr
;
1236 if (!(cmd
&& *cmd
!= '\0'))
1239 /* NOTE: Accessed from the GDB "sim" commmand: */
1240 for (cptr
= sim_commands
; cptr
&& cptr
->name
; cptr
++)
1241 if (strncmp(cmd
,cptr
->name
,strlen(cptr
->name
)) == 0) {
1242 cmd
+= strlen(cptr
->name
);
1244 case e_help
: /* no arguments */
1245 { /* no arguments */
1246 struct t_sim_command
*lptr
;
1247 callback
->printf_filtered(callback
,"List of MIPS simulator commands:\n");
1248 for (lptr
= sim_commands
; lptr
->name
; lptr
++)
1249 callback
->printf_filtered(callback
,"%s %s\n",lptr
->name
,lptr
->help
);
1253 case e_setmemsize
: /* memory size argument */
1255 unsigned int newsize
= (unsigned int)getnum(cmd
);
1260 case e_reset
: /* no arguments */
1262 /* NOTE: See the comments in sim_open() relating to device
1267 callback
->printf_filtered(callback
,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd
,cptr
->id
);
1274 callback
->printf_filtered(callback
,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd
);
1279 /*---------------------------------------------------------------------------*/
1280 /* NOTE: The following routines do not seem to be used by GDB at the
1281 moment. However, they may be useful to the standalone simulator
1285 /* The profiling format is described in the "gmon_out.h" header file */
1290 #if defined(PROFILE)
1291 profile_frequency
= n
;
1292 state
|= simPROFILE
;
1293 #endif /* PROFILE */
1298 sim_set_profile_size (n
)
1301 #if defined(PROFILE)
1302 if (state
& simPROFILE
) {
1305 /* Since we KNOW that the memory banks are a power-of-2 in size: */
1306 profile_nsamples
= power2(n
);
1307 profile_minpc
= membank_base
;
1308 profile_maxpc
= (membank_base
+ membank_size
);
1310 /* Just in-case we are sampling every address: NOTE: The shift
1311 right of 2 is because we only have word-aligned PC addresses. */
1312 if (profile_nsamples
> (membank_size
>> 2))
1313 profile_nsamples
= (membank_size
>> 2);
1315 /* Since we are dealing with power-of-2 values: */
1316 profile_shift
= (((membank_size
>> 2) / profile_nsamples
) - 1);
1318 bsize
= (profile_nsamples
* sizeof(unsigned short));
1319 if (profile_hist
== NULL
)
1320 profile_hist
= (unsigned short *)calloc(64,(bsize
/ 64));
1322 profile_hist
= (unsigned short *)realloc(profile_hist
,bsize
);
1323 if (profile_hist
== NULL
) {
1324 callback
->printf_filtered(callback
,"Failed to allocate VM for profiling buffer (0x%08X bytes)\n",bsize
);
1325 state
&= ~simPROFILE
;
1328 #endif /* PROFILE */
1335 unsigned int newsize
;
1338 /* Used by "run", and internally, to set the simulated memory size */
1339 newsize
= power2(newsize
);
1340 if (membank
== NULL
)
1341 new = (char *)calloc(64,(membank_size
/ 64));
1343 new = (char *)realloc(membank
,newsize
);
1345 if (membank
== NULL
)
1346 callback
->printf_filtered(callback
,"Not enough VM for simulation memory of 0x%08X bytes\n",membank_size
);
1348 callback
->printf_filtered(callback
,"Failed to resize memory (still 0x%08X bytes)\n",membank_size
);
1350 membank_size
= (unsigned)newsize
;
1352 callback
->printf_filtered(callback
,"Memory size now 0x%08X bytes\n",membank_size
);
1353 #if defined(PROFILE)
1354 /* Ensure that we sample across the new memory range */
1355 sim_set_profile_size(profile_nsamples
);
1356 #endif /* PROFILE */
1365 /* This routine is called by the "run" program, when detailed
1366 execution information is required. Rather than executing a single
1367 instruction, and looping around externally... we just start
1368 simulating, returning TRUE when the simulator stops (for whatever
1372 /* Ensure tracing is enabled, if available */
1373 if (tracefh
!= NULL
)
1377 state
&= ~(simSTOP
| simSTEP
); /* execute until event */
1378 state
|= (simHALTEX
| simHALTIN
); /* treat interrupt event as exception */
1379 /* Start executing instructions from the current state (set
1380 explicitly by register updates, or by sim_create_inferior): */
1386 /*---------------------------------------------------------------------------*/
1387 /*-- Private simulator support interface ------------------------------------*/
1388 /*---------------------------------------------------------------------------*/
1390 /* Simple monitor interface (currently setup for the IDT monitor) */
1393 unsigned int reason
;
1395 /* The IDT monitor actually allows two instructions per vector
1396 slot. However, the simulator currently causes a trap on each
1397 individual instruction. We cheat, and lose the bottom bit. */
1400 /* The following callback functions are available, however the
1401 monitor we are simulating does not make use of them: get_errno,
1402 isatty, lseek, rename, system, time and unlink */
1404 case 6: /* int open(char *path,int flags) */
1409 if (AddressTranslation(A0
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1410 V0
= callback
->open(callback
,(char *)((int)paddr
),(int)A1
);
1412 callback
->printf_filtered(callback
,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
1416 case 7: /* int read(int file,char *ptr,int len) */
1421 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1422 V0
= callback
->read(callback
,(int)A0
,(char *)((int)paddr
),(int)A2
);
1424 callback
->printf_filtered(callback
,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
1428 case 8: /* int write(int file,char *ptr,int len) */
1433 if (AddressTranslation(A1
,isDATA
,isLOAD
,&paddr
,&cca
,isHOST
,isREAL
))
1434 V0
= callback
->write(callback
,(int)A0
,(const char *)((int)paddr
),(int)A2
);
1436 callback
->printf_filtered(callback
,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
1440 case 10: /* int close(int file) */
1441 V0
= callback
->close(callback
,(int)A0
);
1444 case 11: /* char inbyte(void) */
1447 if (callback
->read_stdin(callback
,&tmp
,sizeof(char)) != sizeof(char)) {
1448 callback
->printf_filtered(callback
,"WARNING: Invalid return from character read\n");
1456 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1458 char tmp
= (char)(A0
& 0xFF);
1459 callback
->write_stdout(callback
,&tmp
,sizeof(char));
1463 case 17: /* void _exit() */
1464 callback
->printf_filtered(callback
,"sim_monitor(17): _exit(int reason) to be coded\n");
1465 state
|= (simSTOP
| simEXIT
); /* stop executing code */
1466 rcexit
= (unsigned int)(A0
& 0xFFFFFFFF);
1469 case 55: /* void get_mem_info(unsigned int *ptr) */
1470 /* in: A0 = pointer to three word memory location */
1471 /* out: [A0 + 0] = size */
1472 /* [A0 + 4] = instruction cache size */
1473 /* [A0 + 8] = data cache size */
1476 uword64 paddr
, value
;
1480 /* NOTE: We use RAW memory writes here, but since we are not
1481 gathering statistics for the monitor calls we are simulating,
1482 it is not an issue. */
1485 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1486 value
= (uword64
)membank_size
;
1487 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
1488 /* We re-do the address translations, in-case the block
1489 overlaps a memory boundary: */
1491 vaddr
+= (AccessLength_WORD
+ 1);
1492 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
)) {
1493 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
1494 vaddr
+= (AccessLength_WORD
+ 1);
1495 if (AddressTranslation(vaddr
,isDATA
,isSTORE
,&paddr
,&cca
,isTARGET
,isREAL
))
1496 StoreMemory(cca
,AccessLength_WORD
,value
,paddr
,vaddr
,isRAW
);
1505 callback
->printf_filtered(callback
,"WARNING: Invalid pointer passed into monitor call\n");
1510 callback
->printf_filtered(callback
,"TODO: sim_monitor(%d) : PC = 0x%08X%08X\n",reason
,WORD64HI(IPC
),WORD64LO(IPC
));
1511 callback
->printf_filtered(callback
,"(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)\n",WORD64HI(A0
),WORD64LO(A0
),WORD64HI(A1
),WORD64LO(A1
),WORD64HI(A2
),WORD64LO(A2
),WORD64HI(A3
),WORD64LO(A3
));
1523 callback
->printf_filtered(callback
,"SIM Error: ");
1524 callback
->printf_filtered(callback
,fmt
,ap
);
1526 SignalException(SimulatorFault
,"");
1536 /* Round *UP* to the nearest power-of-2 if not already one */
1537 if (value
!= (value
& ~(value
- 1))) {
1538 for (tmp
= value
, loop
= 0; (tmp
!= 0); loop
++)
1540 value
= (1 << loop
);
1553 num
= strtol(value
,&end
,10);
1555 callback
->printf_filtered(callback
,"Warning: Invalid number \"%s\" ignored, using zero\n",value
);
1557 if (*end
&& ((tolower(*end
) == 'k') || (tolower(*end
) == 'm'))) {
1558 if (tolower(*end
) == 'k')
1565 callback
->printf_filtered(callback
,"Warning: Spurious characters \"%s\" at end of number ignored\n",end
);
1571 /*-- trace support ----------------------------------------------------------*/
1573 /* The TRACE support is provided (if required) in the memory accessing
1574 routines. Since we are also providing the architecture specific
1575 features, the architecture simulation code can also deal with
1576 notifying the TRACE world of cache flushes, etc. Similarly we do
1577 not need to provide profiling support in the simulator engine,
1578 since we can sample in the instruction fetch control loop. By
1579 defining the TRACE manifest, we add tracing as a run-time
1583 /* Tracing by default produces "din" format (as required by
1584 dineroIII). Each line of such a trace file *MUST* have a din label
1585 and address field. The rest of the line is ignored, so comments can
1586 be included if desired. The first field is the label which must be
1587 one of the following values:
1592 3 escape record (treated as unknown access type)
1593 4 escape record (causes cache flush)
1595 The address field is a 32bit (lower-case) hexadecimal address
1596 value. The address should *NOT* be preceded by "0x".
1598 The size of the memory transfer is not important when dealing with
1599 cache lines (as long as no more than a cache line can be
1600 transferred in a single operation :-), however more information
1601 could be given following the dineroIII requirement to allow more
1602 complete memory and cache simulators to provide better
1603 results. i.e. the University of Pisa has a cache simulator that can
1604 also take bus size and speed as (variable) inputs to calculate
1605 complete system performance (a much more useful ability when trying
1606 to construct an end product, rather than a processor). They
1607 currently have an ARM version of their tool called ChARM. */
1610 void dotrace(tracefh
,type
,address
,width
,comment
)
1613 unsigned int address
;
1617 if (state
& simTRACE
) {
1619 fprintf(tracefh
,"%d %08x ; width %d ; ",type
,address
,width
);
1620 va_start(ap
,comment
);
1621 fprintf(tracefh
,comment
,ap
);
1623 fprintf(tracefh
,"\n");
1625 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1626 we may be generating 64bit ones, we should put the hi-32bits of the
1627 address into the comment field. */
1629 /* TODO: Provide a buffer for the trace lines. We can then avoid
1630 performing writes until the buffer is filled, or the file is
1633 /* NOTE: We could consider adding a comment field to the "din" file
1634 produced using type 3 markers (unknown access). This would then
1635 allow information about the program that the "din" is for, and
1636 the MIPs world that was being simulated, to be placed into the
1643 /*---------------------------------------------------------------------------*/
1644 /*-- simulator engine -------------------------------------------------------*/
1645 /*---------------------------------------------------------------------------*/
1650 /* RESET: Fixed PC address: */
1651 PC
= (((uword64
)0xFFFFFFFF<<32) | 0xBFC00000);
1652 /* The reset vector address is in the unmapped, uncached memory space. */
1654 SR
&= ~(status_SR
| status_TS
| status_RP
);
1655 SR
|= (status_ERL
| status_BEV
);
1656 /* VR4300 starts in Big-Endian mode */
1657 CONFIG
&= ~(config_EP_mask
<< config_EP_shift
);
1658 CONFIG
|= ((config_EP_D
<< config_EP_shift
) | config_BE
);
1659 /* TODO: The VR4300 CONFIG register is not modelled fully at the moment */
1661 #if defined(HASFPU) && (GPRLEN == (64))
1662 /* Cheat and allow access to the complete register set immediately: */
1663 SR
|= status_FR
; /* 64bit registers */
1664 #endif /* HASFPU and 64bit FP registers */
1666 /* Ensure that any instructions with pending register updates are
1670 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1671 pending_slot_reg
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1672 pending_in
= pending_out
= pending_total
= 0;
1676 /* Initialise the FPU registers to the unknown state */
1679 for (rn
= 0; (rn
< 32); rn
++)
1680 fpr_state
[rn
] = fmt_uninterpreted
;
1687 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1688 /* Translate a virtual address to a physical address and cache
1689 coherence algorithm describing the mechanism used to resolve the
1690 memory reference. Given the virtual address vAddr, and whether the
1691 reference is to Instructions ot Data (IorD), find the corresponding
1692 physical address (pAddr) and the cache coherence algorithm (CCA)
1693 used to resolve the reference. If the virtual address is in one of
1694 the unmapped address spaces the physical address and the CCA are
1695 determined directly by the virtual address. If the virtual address
1696 is in one of the mapped address spaces then the TLB is used to
1697 determine the physical address and access type; if the required
1698 translation is not present in the TLB or the desired access is not
1699 permitted the function fails and an exception is taken.
1701 NOTE: This function is extended to return an exception state. This,
1702 along with the exception generation is used to notify whether a
1703 valid address translation occured */
1706 AddressTranslation(vAddr
,IorD
,LorS
,pAddr
,CCA
,host
,raw
)
1715 int res
= -1; /* TRUE : Assume good return */
1718 callback
->printf_filtered(callback
,"AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr
),WORD64LO(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1721 /* Check that the address is valid for this memory model */
1723 /* For a simple (flat) memory model, we simply pass virtual
1724 addressess through (mostly) unchanged. */
1725 vAddr
&= 0xFFFFFFFF;
1726 *pAddr
= vAddr
; /* default for isTARGET */
1727 *CCA
= Uncached
; /* not used for isHOST */
1729 /* NOTE: This is a duplicate of the code that appears in the
1730 LoadMemory and StoreMemory functions. They should be merged into
1731 a single function (that can be in-lined if required). */
1732 if ((vAddr
>= membank_base
) && (vAddr
< (membank_base
+ membank_size
))) {
1734 *pAddr
= (int)&membank
[((unsigned int)(vAddr
- membank_base
) & (membank_size
- 1))];
1735 } else if ((vAddr
>= monitor_base
) && (vAddr
< (monitor_base
+ monitor_size
))) {
1737 *pAddr
= (int)&monitor
[((unsigned int)(vAddr
- monitor_base
) & (monitor_size
- 1))];
1739 #if 1 /* def DEBUG */
1740 callback
->printf_filtered(callback
,"Failed: AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr
),WORD64LO(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "isSTORE" : "isLOAD"));
1742 res
= 0; /* AddressTranslation has failed */
1744 if (!raw
) /* only generate exceptions on real memory transfers */
1745 SignalException((LorS
== isSTORE
) ? AddressStore
: AddressLoad
);
1747 callback
->printf_filtered(callback
,"AddressTranslation for %s %s from 0x%08X%08X failed\n",(IorD
? "data" : "instruction"),(LorS
? "store" : "load"),WORD64HI(vAddr
),WORD64LO(vAddr
));
1753 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1754 /* Prefetch data from memory. Prefetch is an advisory instruction for
1755 which an implementation specific action is taken. The action taken
1756 may increase performance, but must not change the meaning of the
1757 program, or alter architecturally-visible state. */
1759 Prefetch(CCA
,pAddr
,vAddr
,DATA
,hint
)
1767 callback
->printf_filtered(callback
,"Prefetch(%d,0x%08X%08X,0x%08X%08X,%d,%d);\n",CCA
,WORD64HI(pAddr
),WORD64LO(pAddr
),WORD64HI(vAddr
),WORD64LO(vAddr
),DATA
,hint
);
1770 /* For our simple memory model we do nothing */
1774 /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1775 /* Load a value from memory. Use the cache and main memory as
1776 specified in the Cache Coherence Algorithm (CCA) and the sort of
1777 access (IorD) to find the contents of AccessLength memory bytes
1778 starting at physical location pAddr. The data is returned in the
1779 fixed width naturally-aligned memory element (MemElem). The
1780 low-order two (or three) bits of the address and the AccessLength
1781 indicate which of the bytes within MemElem needs to be given to the
1782 processor. If the memory access type of the reference is uncached
1783 then only the referenced bytes are read from memory and valid
1784 within the memory element. If the access type is cached, and the
1785 data is not present in cache, an implementation specific size and
1786 alignment block of memory is read and loaded into the cache to
1787 satisfy a load reference. At a minimum, the block is the entire
1790 LoadMemory(CCA
,AccessLength
,pAddr
,vAddr
,IorD
,raw
)
1801 if (membank
== NULL
)
1802 callback
->printf_filtered(callback
,"DBG: LoadMemory(%d,%d,0x%08X%08X,0x%08X%08X,%s,%s)\n",CCA
,AccessLength
,WORD64HI(pAddr
),WORD64LO(pAddr
),WORD64HI(vAddr
),WORD64LO(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(raw
? "isRAW" : "isREAL"));
1805 #if defined(WARN_MEM)
1806 if (CCA
!= uncached
)
1807 callback
->printf_filtered(callback
,"SIM Warning: LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1809 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
) {
1810 /* In reality this should be a Bus Error */
1811 sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength
,WORD64HI(pAddr
),WORD64LO(pAddr
));
1813 #endif /* WARN_MEM */
1815 /* Decide which physical memory locations are being dealt with. At
1816 this point we should be able to split the pAddr bits into the
1817 relevant address map being simulated. If the "raw" variable is
1818 set, the memory read being performed should *NOT* update any I/O
1819 state or affect the CPU state. This also includes avoiding
1820 affecting statistics gathering. */
1822 /* If instruction fetch then we need to check that the two lo-order
1823 bits are zero, otherwise raise a InstructionFetch exception: */
1824 if ((IorD
== isINSTRUCTION
) && ((pAddr
& 0x3) != 0))
1825 SignalException(InstructionFetch
);
1828 unsigned char *mem
= NULL
;
1832 dotrace(tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1835 /* NOTE: Quicker methods of decoding the address space can be used
1836 when a real memory map is being simulated (i.e. using hi-order
1837 address bits to select device). */
1838 if ((pAddr
>= membank_base
) && (pAddr
< (membank_base
+ membank_size
))) {
1839 index
= ((unsigned int)(pAddr
- membank_base
) & (membank_size
- 1));
1841 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
1842 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
1846 sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr
),WORD64LO(pAddr
));
1848 /* If we obtained the endianness of the host, and it is the same
1849 as the target memory system we can optimise the memory
1850 accesses. However, without that information we must perform
1851 slow transfer, and hope that the compiler optimisation will
1852 merge successive loads. */
1853 value
= 0; /* no data loaded yet */
1855 /* In reality we should always be loading a doubleword value (or
1856 word value in 32bit memory worlds). The external code then
1857 extracts the required bytes. However, to keep performance
1858 high we only load the required bytes into the relevant
1861 switch (AccessLength
) { /* big-endian memory */
1862 case AccessLength_DOUBLEWORD
:
1863 value
|= ((uword64
)mem
[index
++] << 56);
1864 case AccessLength_SEPTIBYTE
:
1865 value
|= ((uword64
)mem
[index
++] << 48);
1866 case AccessLength_SEXTIBYTE
:
1867 value
|= ((uword64
)mem
[index
++] << 40);
1868 case AccessLength_QUINTIBYTE
:
1869 value
|= ((uword64
)mem
[index
++] << 32);
1870 case AccessLength_WORD
:
1871 value
|= ((unsigned int)mem
[index
++] << 24);
1872 case AccessLength_TRIPLEBYTE
:
1873 value
|= ((unsigned int)mem
[index
++] << 16);
1874 case AccessLength_HALFWORD
:
1875 value
|= ((unsigned int)mem
[index
++] << 8);
1876 case AccessLength_BYTE
:
1877 value
|= mem
[index
];
1881 index
+= (AccessLength
+ 1);
1882 switch (AccessLength
) { /* little-endian memory */
1883 case AccessLength_DOUBLEWORD
:
1884 value
|= ((uword64
)mem
[--index
] << 56);
1885 case AccessLength_SEPTIBYTE
:
1886 value
|= ((uword64
)mem
[--index
] << 48);
1887 case AccessLength_SEXTIBYTE
:
1888 value
|= ((uword64
)mem
[--index
] << 40);
1889 case AccessLength_QUINTIBYTE
:
1890 value
|= ((uword64
)mem
[--index
] << 32);
1891 case AccessLength_WORD
:
1892 value
|= ((uword64
)mem
[--index
] << 24);
1893 case AccessLength_TRIPLEBYTE
:
1894 value
|= ((uword64
)mem
[--index
] << 16);
1895 case AccessLength_HALFWORD
:
1896 value
|= ((uword64
)mem
[--index
] << 8);
1897 case AccessLength_BYTE
:
1898 value
|= ((uword64
)mem
[--index
] << 0);
1904 printf("DBG: LoadMemory() : (offset %d) : value = 0x%08X%08X\n",(int)(pAddr
& LOADDRMASK
),WORD64HI(value
),WORD64LO(value
));
1907 /* TODO: We could try and avoid the shifts when dealing with raw
1908 memory accesses. This would mean updating the LoadMemory and
1909 StoreMemory routines to avoid shifting the data before
1910 returning or using it. */
1911 if (!raw
) { /* do nothing for raw accessess */
1913 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1914 else /* little-endian only needs to be shifted up to the correct byte offset */
1915 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1919 printf("DBG: LoadMemory() : shifted value = 0x%08X%08X\n",WORD64HI(value
),WORD64LO(value
));
1927 /* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1928 /* Store a value to memory. The specified data is stored into the
1929 physical location pAddr using the memory hierarchy (data caches and
1930 main memory) as specified by the Cache Coherence Algorithm
1931 (CCA). The MemElem contains the data for an aligned, fixed-width
1932 memory element (word for 32-bit processors, doubleword for 64-bit
1933 processors), though only the bytes that will actually be stored to
1934 memory need to be valid. The low-order two (or three) bits of pAddr
1935 and the AccessLength field indicates which of the bytes within the
1936 MemElem data should actually be stored; only these bytes in memory
1939 StoreMemory(CCA
,AccessLength
,MemElem
,pAddr
,vAddr
,raw
)
1948 callback
->printf_filtered(callback
,"DBG: StoreMemory(%d,%d,0x%08X%08X,0x%08X%08X,0x%08X%08X,%s)\n",CCA
,AccessLength
,WORD64HI(MemElem
),WORD64LO(MemElem
),WORD64HI(pAddr
),WORD64LO(pAddr
),WORD64HI(vAddr
),WORD64LO(vAddr
),(raw
? "isRAW" : "isREAL"));
1951 #if defined(WARN_MEM)
1952 if (CCA
!= uncached
)
1953 callback
->printf_filtered(callback
,"SIM Warning: StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1955 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1956 sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength
,WORD64HI(pAddr
),WORD64LO(pAddr
));
1957 #endif /* WARN_MEM */
1961 dotrace(tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1964 /* See the comments in the LoadMemory routine about optimising
1965 memory accesses. Also if we wanted to make the simulator smaller,
1966 we could merge a lot of this code with the LoadMemory
1967 routine. However, this would slow the simulator down with
1968 run-time conditionals. */
1971 unsigned char *mem
= NULL
;
1973 if ((pAddr
>= membank_base
) && (pAddr
< (membank_base
+ membank_size
))) {
1974 index
= ((unsigned int)(pAddr
- membank_base
) & (membank_size
- 1));
1976 } else if ((pAddr
>= monitor_base
) && (pAddr
< (monitor_base
+ monitor_size
))) {
1977 index
= ((unsigned int)(pAddr
- monitor_base
) & (monitor_size
- 1));
1982 sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr
),WORD64LO(pAddr
));
1987 printf("DBG: StoreMemory: offset = %d MemElem = 0x%08X%08X\n",(unsigned int)(pAddr
& LOADDRMASK
),WORD64HI(MemElem
),WORD64LO(MemElem
));
1992 shift
= ((7 - AccessLength
) * 8);
1993 else /* real memory access */
1994 shift
= ((pAddr
& LOADDRMASK
) * 8);
1997 /* no need to shift raw little-endian data */
1999 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
2003 printf("DBG: StoreMemory: shift = %d MemElem = 0x%08X%08X\n",shift
,WORD64HI(MemElem
),WORD64LO(MemElem
));
2007 switch (AccessLength
) { /* big-endian memory */
2008 case AccessLength_DOUBLEWORD
:
2009 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2011 case AccessLength_SEPTIBYTE
:
2012 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2014 case AccessLength_SEXTIBYTE
:
2015 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2017 case AccessLength_QUINTIBYTE
:
2018 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2020 case AccessLength_WORD
:
2021 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2023 case AccessLength_TRIPLEBYTE
:
2024 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2026 case AccessLength_HALFWORD
:
2027 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2029 case AccessLength_BYTE
:
2030 mem
[index
++] = (unsigned char)(MemElem
>> 56);
2034 index
+= (AccessLength
+ 1);
2035 switch (AccessLength
) { /* little-endian memory */
2036 case AccessLength_DOUBLEWORD
:
2037 mem
[--index
] = (unsigned char)(MemElem
>> 56);
2038 case AccessLength_SEPTIBYTE
:
2039 mem
[--index
] = (unsigned char)(MemElem
>> 48);
2040 case AccessLength_SEXTIBYTE
:
2041 mem
[--index
] = (unsigned char)(MemElem
>> 40);
2042 case AccessLength_QUINTIBYTE
:
2043 mem
[--index
] = (unsigned char)(MemElem
>> 32);
2044 case AccessLength_WORD
:
2045 mem
[--index
] = (unsigned char)(MemElem
>> 24);
2046 case AccessLength_TRIPLEBYTE
:
2047 mem
[--index
] = (unsigned char)(MemElem
>> 16);
2048 case AccessLength_HALFWORD
:
2049 mem
[--index
] = (unsigned char)(MemElem
>> 8);
2050 case AccessLength_BYTE
:
2051 mem
[--index
] = (unsigned char)(MemElem
>> 0);
2061 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2062 /* Order loads and stores to synchronise shared memory. Perform the
2063 action necessary to make the effects of groups of synchronizable
2064 loads and stores indicated by stype occur in the same order for all
2067 SyncOperation(stype
)
2071 callback
->printf_filtered(callback
,"SyncOperation(%d) : TODO\n",stype
);
2076 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2077 /* Signal an exception condition. This will result in an exception
2078 that aborts the instruction. The instruction operation pseudocode
2079 will never see a return from this function call. */
2081 SignalException(exception
)
2084 /* Ensure that any active atomic read/modify/write operation will fail: */
2087 switch (exception
) {
2088 /* TODO: For testing purposes I have been ignoring TRAPs. In
2089 reality we should either simulate them, or allow the user to
2090 ignore them at run-time. */
2092 callback
->printf_filtered(callback
,"Ignoring instruction TRAP (PC 0x%08X%08X)\n",WORD64HI(IPC
),WORD64LO(IPC
));
2095 case ReservedInstruction
:
2098 unsigned int instruction
;
2099 va_start(ap
,exception
);
2100 instruction
= va_arg(ap
,unsigned int);
2102 /* Provide simple monitor support using ReservedInstruction
2103 exceptions. The following code simulates the fixed vector
2104 entry points into the IDT monitor by causing a simulator
2105 trap, performing the monitor operation, and returning to
2106 the address held in the $ra register (standard PCS return
2107 address). This means we only need to pre-load the vector
2108 space with suitable instruction values. For systems were
2109 actual trap instructions are used, we would not need to
2110 perform this magic. */
2111 if ((instruction
& ~RSVD_INSTRUCTION_AMASK
) == RSVD_INSTRUCTION
) {
2112 sim_monitor(instruction
& RSVD_INSTRUCTION_AMASK
);
2113 PC
= RA
; /* simulate the return from the vector entry */
2114 /* NOTE: This assumes that a branch-and-link style
2115 instruction was used to enter the vector (which is the
2116 case with the current IDT monitor). */
2117 break; /* out of the switch statement */
2118 } /* else fall through to normal exception processing */
2119 callback
->printf_filtered(callback
,"DBG: ReservedInstruction 0x%08X at IPC = 0x%08X%08X\n",instruction
,WORD64HI(IPC
),WORD64LO(IPC
));
2123 #if 1 /* def DEBUG */
2124 callback
->printf_filtered(callback
,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception
,WORD64HI(IPC
),WORD64LO(IPC
));
2126 /* Store exception code into current exception id variable (used
2129 /* TODO: If not simulating exceptions then stop the simulator
2130 execution. At the moment we always stop the simulation. */
2131 state
|= (simSTOP
| simEXCEPTION
);
2132 CAUSE
= (exception
<< 2);
2133 if (state
& simDELAYSLOT
) {
2135 EPC
= (IPC
- 4); /* reference the branch instruction */
2138 /* The following is so that the simulator will continue from the
2139 exception address on breakpoint operations. */
2143 case SimulatorFault
:
2147 va_start(ap
,exception
);
2148 msg
= va_arg(ap
,char *);
2149 fprintf(stderr
,"FATAL: Simulator error \"%s\"\n",msg
);
2158 #if defined(WARN_RESULT)
2159 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2160 /* This function indicates that the result of the operation is
2161 undefined. However, this should not affect the instruction
2162 stream. All that is meant to happen is that the destination
2163 register is set to an undefined result. To keep the simulator
2164 simple, we just don't bother updating the destination register, so
2165 the overall result will be undefined. If desired we can stop the
2166 simulator by raising a pseudo-exception. */
2170 callback
->printf_filtered(callback
,"UndefinedResult: IPC = 0x%08X%08X\n",WORD64HI(IPC
),WORD64LO(IPC
));
2171 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2176 #endif /* WARN_RESULT */
2179 CacheOp(op
,pAddr
,vAddr
,instruction
)
2183 unsigned int instruction
;
2185 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2186 enable bit in the Status Register is clear - a coprocessor
2187 unusable exception is taken. */
2188 callback
->printf_filtered(callback
,"TODO: Cache availability checking (PC = 0x%08X%08X)\n",WORD64HI(IPC
),WORD64LO(IPC
));
2191 case 0: /* instruction cache */
2193 case 0: /* Index Invalidate */
2194 case 1: /* Index Load Tag */
2195 case 2: /* Index Store Tag */
2196 case 4: /* Hit Invalidate */
2198 case 6: /* Hit Writeback */
2199 callback
->printf_filtered(callback
,"SIM Warning: Instruction CACHE operation %d to be coded\n",(op
>> 2));
2203 SignalException(ReservedInstruction
,instruction
);
2208 case 1: /* data cache */
2210 case 0: /* Index Writeback Invalidate */
2211 case 1: /* Index Load Tag */
2212 case 2: /* Index Store Tag */
2213 case 3: /* Create Dirty */
2214 case 4: /* Hit Invalidate */
2215 case 5: /* Hit Writeback Invalidate */
2216 case 6: /* Hit Writeback */
2217 callback
->printf_filtered(callback
,"SIM Warning: Data CACHE operation %d to be coded\n",(op
>> 2));
2221 SignalException(ReservedInstruction
,instruction
);
2226 default: /* unrecognised cache ID */
2227 SignalException(ReservedInstruction
,instruction
);
2234 /*-- FPU support routines ---------------------------------------------------*/
2236 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
2239 #define SizeFGR() (GPRLEN)
2241 /* They depend on the CPU being simulated */
2242 #define SizeFGR() ((PROCESSOR_64BIT && ((SR & status_FR) == 1)) ? 64 : 32)
2245 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2246 formats conform to ANSI/IEEE Std 754-1985. */
2247 /* SINGLE precision floating:
2248 * seeeeeeeefffffffffffffffffffffff
2250 * e = 8bits = exponent
2251 * f = 23bits = fraction
2253 /* SINGLE precision fixed:
2254 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2256 * i = 31bits = integer
2258 /* DOUBLE precision floating:
2259 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2261 * e = 11bits = exponent
2262 * f = 52bits = fraction
2264 /* DOUBLE precision fixed:
2265 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2267 * i = 63bits = integer
2270 /* Extract sign-bit: */
2271 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2272 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2273 /* Extract biased exponent: */
2274 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2275 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2276 /* Extract unbiased Exponent: */
2277 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2278 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2279 /* Extract complete fraction field: */
2280 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2281 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2282 /* Extract numbered fraction bit: */
2283 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2284 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2286 /* Explicit QNaN values used when value required: */
2287 #define FPQNaN_SINGLE (0x7FBFFFFF)
2288 #define FPQNaN_WORD (0x7FFFFFFF)
2289 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2290 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2292 /* Explicit Infinity values used when required: */
2293 #define FPINF_SINGLE (0x7F800000)
2294 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2296 #if 1 /* def DEBUG */
2297 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2298 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2309 /* Treat unused register values, as fixed-point 64bit values: */
2310 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2312 /* If request to read data as "uninterpreted", then use the current
2314 fmt
= fpr_state
[fpr
];
2319 /* For values not yet accessed, set to the desired format: */
2320 if (fpr_state
[fpr
] == fmt_uninterpreted
) {
2321 fpr_state
[fpr
] = fmt
;
2323 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2326 if (fmt
!= fpr_state
[fpr
]) {
2327 callback
->printf_filtered(callback
,"Warning: FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)\n",fpr
,DOFMT(fpr_state
[fpr
]),DOFMT(fmt
),WORD64HI(IPC
),WORD64LO(IPC
));
2328 fpr_state
[fpr
] = fmt_unknown
;
2331 if (fpr_state
[fpr
] == fmt_unknown
) {
2332 /* Set QNaN value: */
2335 value
= FPQNaN_SINGLE
;
2339 value
= FPQNaN_DOUBLE
;
2343 value
= FPQNaN_WORD
;
2347 value
= FPQNaN_LONG
;
2354 } else if (SizeFGR() == 64) {
2358 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2361 case fmt_uninterpreted
:
2371 } else if ((fpr
& 1) == 0) { /* even registers only */
2375 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2378 case fmt_uninterpreted
:
2381 value
= ((FGR
[fpr
+1] << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2391 SignalException(SimulatorFault
,"Unrecognised FP format in ValueFPR()");
2394 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),WORD64HI(value
),WORD64LO(value
),WORD64HI(IPC
),WORD64LO(IPC
),SizeFGR());
2401 StoreFPR(fpr
,fmt
,value
)
2409 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),WORD64HI(value
),WORD64LO(value
),WORD64HI(IPC
),WORD64LO(IPC
),SizeFGR());
2412 if (SizeFGR() == 64) {
2416 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2417 fpr_state
[fpr
] = fmt
;
2420 case fmt_uninterpreted
:
2424 fpr_state
[fpr
] = fmt
;
2428 fpr_state
[fpr
] = fmt_unknown
;
2432 } else if ((fpr
& 1) == 0) { /* even register number only */
2436 FGR
[fpr
+1] = 0xDEADC0DE;
2437 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2438 fpr_state
[fpr
+ 1] = fmt
;
2439 fpr_state
[fpr
] = fmt
;
2442 case fmt_uninterpreted
:
2445 FGR
[fpr
+1] = (value
>> 32);
2446 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2447 fpr_state
[fpr
+ 1] = fmt
;
2448 fpr_state
[fpr
] = fmt
;
2452 fpr_state
[fpr
] = fmt_unknown
;
2457 #if defined(WARN_RESULT)
2460 #endif /* WARN_RESULT */
2463 SignalException(SimulatorFault
,"Unrecognised FP format in StoreFPR()");
2466 printf("DBG: StoreFPR: fpr[%d] = 0x%08X%08X (format %s)\n",fpr
,WORD64HI(FGR
[fpr
]),WORD64LO(FGR
[fpr
]),DOFMT(fmt
));
2479 /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
2480 know that the exponent field is biased... we we cheat and avoid
2481 removing the bias value. */
2484 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) != 0));
2485 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2486 dealing with a SNaN or QNaN */
2489 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) != 0));
2490 /* We could use "FP_S_fb(1,op)" to ascertain whether we are
2491 dealing with a SNaN or QNaN */
2494 boolean
= (op
== FPQNaN_WORD
);
2497 boolean
= (op
== FPQNaN_LONG
);
2502 printf("DBG: NaN: returning %d for 0x%08X%08X (format = %s)\n",boolean
,WORD64HI(op
),WORD64LO(op
),DOFMT(fmt
));
2516 printf("DBG: Infinity: format %s 0x%08X%08X (PC = 0x%08X%08X)\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
),WORD64HI(IPC
),WORD64LO(IPC
));
2519 /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
2520 know that the exponent field is biased... we we cheat and avoid
2521 removing the bias value. */
2524 boolean
= ((FP_S_be(op
) == 0xFF) && (FP_S_f(op
) == 0));
2527 boolean
= ((FP_D_be(op
) == 0x7FF) && (FP_D_f(op
) == 0));
2530 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2535 printf("DBG: Infinity: returning %d for 0x%08X%08X (format = %s)\n",boolean
,WORD64HI(op
),WORD64LO(op
),DOFMT(fmt
));
2549 /* Argument checking already performed by the FPCOMPARE code */
2552 printf("DBG: Less: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
2555 /* The format type should already have been checked: */
2559 unsigned int wop1
= (unsigned int)op1
;
2560 unsigned int wop2
= (unsigned int)op2
;
2561 boolean
= (*(float *)&wop1
< *(float *)&wop2
);
2565 boolean
= (*(double *)&op1
< *(double *)&op2
);
2570 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2584 /* Argument checking already performed by the FPCOMPARE code */
2587 printf("DBG: Equal: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
2590 /* The format type should already have been checked: */
2593 boolean
= ((op1
& 0xFFFFFFFF) == (op2
& 0xFFFFFFFF));
2596 boolean
= (op1
== op2
);
2601 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2615 printf("DBG: Negate: %s: op = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
));
2618 /* The format type should already have been checked: */
2622 unsigned int wop
= (unsigned int)op
;
2623 float tmp
= ((float)0.0 - *(float *)&wop
);
2624 result
= (uword64
)*(unsigned int *)&tmp
;
2629 double tmp
= ((double)0.0 - *(double *)&op
);
2630 result
= *(uword64
*)&tmp
;
2647 printf("DBG: Add: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
2650 /* The registers must specify FPRs valid for operands of type
2651 "fmt". If they are not valid, the result is undefined. */
2653 /* The format type should already have been checked: */
2657 unsigned int wop1
= (unsigned int)op1
;
2658 unsigned int wop2
= (unsigned int)op2
;
2659 float tmp
= (*(float *)&wop1
+ *(float *)&wop2
);
2660 result
= (uword64
)*(unsigned int *)&tmp
;
2665 double tmp
= (*(double *)&op1
+ *(double *)&op2
);
2666 result
= *(uword64
*)&tmp
;
2672 printf("DBG: Add: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
2687 printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64H(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
2690 /* The registers must specify FPRs valid for operands of type
2691 "fmt". If they are not valid, the result is undefined. */
2693 /* The format type should already have been checked: */
2697 unsigned int wop1
= (unsigned int)op1
;
2698 unsigned int wop2
= (unsigned int)op2
;
2699 float tmp
= (*(float *)&wop1
- *(float *)&wop2
);
2700 result
= (uword64
)*(unsigned int *)&tmp
;
2705 double tmp
= (*(double *)&op1
- *(double *)&op2
);
2706 result
= *(uword64
*)&tmp
;
2712 printf("DBG: Sub: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
2719 Multiply(op1
,op2
,fmt
)
2727 printf("DBG: Multiply: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
2730 /* The registers must specify FPRs valid for operands of type
2731 "fmt". If they are not valid, the result is undefined. */
2733 /* The format type should already have been checked: */
2737 unsigned int wop1
= (unsigned int)op1
;
2738 unsigned int wop2
= (unsigned int)op2
;
2739 float tmp
= (*(float *)&wop1
* *(float *)&wop2
);
2740 result
= (uword64
)*(unsigned int *)&tmp
;
2745 double tmp
= (*(double *)&op1
* *(double *)&op2
);
2746 result
= *(uword64
*)&tmp
;
2752 printf("DBG: Multiply: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
2767 printf("DBG: Divide: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op1
),WORD64LO(op1
),WORD64HI(op2
),WORD64LO(op2
));
2770 /* The registers must specify FPRs valid for operands of type
2771 "fmt". If they are not valid, the result is undefined. */
2773 /* The format type should already have been checked: */
2777 unsigned int wop1
= (unsigned int)op1
;
2778 unsigned int wop2
= (unsigned int)op2
;
2779 float tmp
= (*(float *)&wop1
/ *(float *)&wop2
);
2780 result
= (uword64
)*(unsigned int *)&tmp
;
2785 double tmp
= (*(double *)&op1
/ *(double *)&op2
);
2786 result
= *(uword64
*)&tmp
;
2792 printf("DBG: Divide: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
2806 printf("DBG: Recip: %s: op = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
));
2809 /* The registers must specify FPRs valid for operands of type
2810 "fmt". If they are not valid, the result is undefined. */
2812 /* The format type should already have been checked: */
2816 unsigned int wop
= (unsigned int)op
;
2817 float tmp
= ((float)1.0 / *(float *)&wop
);
2818 result
= (uword64
)*(unsigned int *)&tmp
;
2823 double tmp
= ((double)1.0 / *(double *)&op
);
2824 result
= *(uword64
*)&tmp
;
2830 printf("DBG: Recip: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
2844 printf("DBG: SquareRoot: %s: op = 0x%08X%08X\n",DOFMT(fmt
),WORD64HI(op
),WORD64LO(op
));
2847 /* The registers must specify FPRs valid for operands of type
2848 "fmt". If they are not valid, the result is undefined. */
2850 /* The format type should already have been checked: */
2854 unsigned int wop
= (unsigned int)op
;
2855 float tmp
= ((float)sqrt((double)*(float *)&wop
));
2856 result
= (uword64
)*(unsigned int *)&tmp
;
2861 double tmp
= (sqrt(*(double *)&op
));
2862 result
= *(uword64
*)&tmp
;
2868 printf("DBG: SquareRoot: returning 0x%08X%08X (format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(fmt
));
2875 Convert(rm
,op
,from
,to
)
2884 printf("DBG: Convert: mode %s : op 0x%08X%08X : from %s : to %s : (PC = 0x%08X%08X)\n",RMMODE(rm
),WORD64HI(op
),WORD64LO(op
),DOFMT(from
),DOFMT(to
),WORD64HI(IPC
),WORD64LO(IPC
));
2887 /* The value "op" is converted to the destination format, rounding
2888 using mode "rm". When the destination is a fixed-point format,
2889 then a source value of Infinity, NaN or one which would round to
2890 an integer outside the fixed point range then an IEEE Invalid
2891 Operation condition is raised. */
2898 tmp
= (float)(*(double *)&op
);
2902 tmp
= (float)((int)(op
& 0xFFFFFFFF));
2906 tmp
= (float)((int)op
);
2912 /* Round result to nearest representable value. When two
2913 representable values are equally near, round to the value
2914 that has a least significant bit of zero (i.e. is even). */
2915 tmp
= (float)anint((double)tmp
);
2919 /* Round result to the value closest to, and not greater in
2920 magnitude than, the result. */
2921 tmp
= (float)aint((double)tmp
);
2925 /* Round result to the value closest to, and not less than,
2927 tmp
= (float)ceil((double)tmp
);
2931 /* Round result to the value closest to, and not greater than,
2933 tmp
= (float)floor((double)tmp
);
2936 result
= (uword64
)*(unsigned int *)&tmp
;
2947 unsigned int wop
= (unsigned int)op
;
2948 tmp
= (double)(*(float *)&wop
);
2953 tmp
= (double)((word64
)SIGNEXTEND((op
& 0xFFFFFFFF),32));
2957 tmp
= (double)((word64
)op
);
2963 tmp
= anint(*(double *)&tmp
);
2967 tmp
= aint(*(double *)&tmp
);
2971 tmp
= ceil(*(double *)&tmp
);
2975 tmp
= floor(*(double *)&tmp
);
2978 result
= *(uword64
*)&tmp
;
2984 if (Infinity(op
,from
) || NaN(op
,from
) || (1 == 0/*TODO: check range */)) {
2985 printf("DBG: TODO: update FCSR\n");
2986 SignalException(FPE
);
2988 if (to
== fmt_word
) {
2993 unsigned int wop
= (unsigned int)op
;
2994 tmp
= (unsigned int)*((float *)&wop
);
2998 tmp
= (unsigned int)*((double *)&op
);
3000 printf("DBG: from double %.30f (0x%08X%08X) to word: 0x%08X\n",*((double *)&op
),WORD64HI(op
),WORD64LO(op
),tmp
);
3004 result
= (uword64
)tmp
;
3005 } else { /* fmt_long */
3009 unsigned int wop
= (unsigned int)op
;
3010 result
= (uword64
)*((float *)&wop
);
3014 result
= (uword64
)*((double *)&op
);
3023 printf("DBG: Convert: returning 0x%08X%08X (to format = %s)\n",WORD64HI(result
),WORD64LO(result
),DOFMT(to
));
3030 /*-- co-processor support routines ------------------------------------------*/
3033 CoProcPresent(coproc_number
)
3034 unsigned int coproc_number
;
3036 /* Return TRUE if simulator provides a model for the given co-processor number */
3041 COP_LW(coproc_num
,coproc_reg
,memword
)
3042 int coproc_num
, coproc_reg
;
3043 unsigned int memword
;
3045 switch (coproc_num
) {
3049 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%08X%08X\n",memword
,WORD64HI(memword
),WORD64LO(memword
));
3051 StoreFPR(coproc_reg
,fmt_uninterpreted
,(uword64
)memword
);
3056 callback
->printf_filtered(callback
,"COP_LW(%d,%d,0x%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,WORD64HI(IPC
),WORD64LO(IPC
));
3064 COP_LD(coproc_num
,coproc_reg
,memword
)
3065 int coproc_num
, coproc_reg
;
3068 switch (coproc_num
) {
3071 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3076 callback
->printf_filtered(callback
,"COP_LD(%d,%d,0x%08X%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,WORD64HI(memword
),WORD64LO(memword
),WORD64HI(IPC
),WORD64LO(IPC
));
3084 COP_SW(coproc_num
,coproc_reg
)
3085 int coproc_num
, coproc_reg
;
3087 unsigned int value
= 0;
3088 switch (coproc_num
) {
3092 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3095 value
= (unsigned int)ValueFPR(coproc_reg
,fpr_state
[coproc_reg
]);
3098 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(fpr_state
[coproc_reg
]));
3100 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
3107 callback
->printf_filtered(callback
,"COP_SW(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,WORD64HI(IPC
),WORD64LO(IPC
));
3115 COP_SD(coproc_num
,coproc_reg
)
3116 int coproc_num
, coproc_reg
;
3119 switch (coproc_num
) {
3123 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3126 value
= ValueFPR(coproc_reg
,fpr_state
[coproc_reg
]);
3129 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(fpr_state
[coproc_reg
]));
3131 value
= ValueFPR(coproc_reg
,fmt_double
);
3138 callback
->printf_filtered(callback
,"COP_SD(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num
,coproc_reg
,WORD64HI(IPC
),WORD64LO(IPC
));
3146 decode_coproc(instruction
)
3147 unsigned int instruction
;
3149 int coprocnum
= ((instruction
>> 26) & 3);
3151 switch (coprocnum
) {
3152 case 0: /* standard CPU control and cache registers */
3155 Standard CP0 registers
3156 0 = Index R4000 VR4100 VR4300
3157 1 = Random R4000 VR4100 VR4300
3158 2 = EntryLo0 R4000 VR4100 VR4300
3159 3 = EntryLo1 R4000 VR4100 VR4300
3160 4 = Context R4000 VR4100 VR4300
3161 5 = PageMask R4000 VR4100 VR4300
3162 6 = Wired R4000 VR4100 VR4300
3163 8 = BadVAddr R4000 VR4100 VR4300
3164 9 = Count R4000 VR4100 VR4300
3165 10 = EntryHi R4000 VR4100 VR4300
3166 11 = Compare R4000 VR4100 VR4300
3167 12 = SR R4000 VR4100 VR4300
3168 13 = Cause R4000 VR4100 VR4300
3169 14 = EPC R4000 VR4100 VR4300
3170 15 = PRId R4000 VR4100 VR4300
3171 16 = Config R4000 VR4100 VR4300
3172 17 = LLAddr R4000 VR4100 VR4300
3173 18 = WatchLo R4000 VR4100 VR4300
3174 19 = WatchHi R4000 VR4100 VR4300
3175 20 = XContext R4000 VR4100 VR4300
3176 26 = PErr or ECC R4000 VR4100 VR4300
3177 27 = CacheErr R4000 VR4100
3178 28 = TagLo R4000 VR4100 VR4300
3179 29 = TagHi R4000 VR4100 VR4300
3180 30 = ErrorEPC R4000 VR4100 VR4300
3182 int code
= ((instruction
>> 21) & 0x1F);
3183 /* R4000 Users Manual (second edition) lists the following CP0
3185 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3186 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3187 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3188 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3189 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3190 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3191 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3192 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3193 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3194 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3196 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0)) {
3197 int rt
= ((instruction
>> 16) & 0x1F);
3198 int rd
= ((instruction
>> 11) & 0x1F);
3199 if (code
== 0x00) { /* MF : move from */
3200 callback
->printf_filtered(callback
,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt
,rd
);
3201 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3202 } else { /* MT : move to */
3203 /* CPR[0,rd] = GPR[rt]; */
3204 callback
->printf_filtered(callback
,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt
,rd
);
3207 callback
->printf_filtered(callback
,"Warning: Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction
,WORD64HI(IPC
),WORD64LO(IPC
));
3208 /* TODO: When executing an ERET or RFE instruction we should
3209 clear LLBIT, to ensure that any out-standing atomic
3210 read/modify/write sequence fails. */
3214 case 2: /* undefined co-processor */
3215 callback
->printf_filtered(callback
,"Warning: COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction
,WORD64HI(IPC
),WORD64LO(IPC
));
3218 case 1: /* should not occur (FPU co-processor) */
3219 case 3: /* should not occur (FPU co-processor) */
3220 SignalException(ReservedInstruction
,instruction
);
3227 /*-- instruction simulation -------------------------------------------------*/
3232 unsigned int pipeline_count
= 1;
3235 if (membank
== NULL
) {
3236 printf("DBG: simulate() entered with no memory\n");
3241 #if 0 /* Disabled to check that everything works OK */
3242 /* The VR4300 seems to sign-extend the PC on its first
3243 access. However, this may just be because it is currently
3244 configured in 32bit mode. However... */
3245 PC
= SIGNEXTEND(PC
,32);
3248 /* main controlling loop */
3250 /* Fetch the next instruction from the simulator memory: */
3251 uword64 vaddr
= (uword64
)PC
;
3254 unsigned int instruction
;
3255 int dsstate
= (state
& simDELAYSLOT
);
3259 printf("DBG: state = 0x%08X :",state
);
3260 if (state
& simSTOP
) printf(" simSTOP");
3261 if (state
& simSTEP
) printf(" simSTEP");
3262 if (state
& simHALTEX
) printf(" simHALTEX");
3263 if (state
& simHALTIN
) printf(" simHALTIN");
3264 if (state
& simBE
) printf(" simBE");
3270 callback
->printf_filtered(callback
,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC
),WORD64LO(DSPC
));
3273 if (AddressTranslation(PC
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) { /* Copy the action of the LW instruction */
3274 unsigned int reverse
= (ReverseEndian
? 1 : 0);
3275 unsigned int bigend
= (BigEndianCPU
? 1 : 0);
3278 paddr
= ((paddr
& ~0x7) | ((paddr
& 0x7) ^ (reverse
<< 2)));
3279 value
= LoadMemory(cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3280 byte
= ((vaddr
& 0x7) ^ (bigend
<< 2));
3281 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3283 fprintf(stderr
,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC
),WORD64LO(PC
));
3288 callback
->printf_filtered(callback
,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction
,WORD64HI(PC
),WORD64LO(PC
));
3291 #if !defined(FASTSIM) || defined(PROFILE)
3292 instruction_fetches
++;
3293 #if defined(PROFILE)
3294 if ((state
& simPROFILE
) && ((instruction_fetches
% profile_frequency
) == 0) && profile_hist
) {
3295 int n
= ((unsigned int)(PC
- profile_minpc
) >> (profile_shift
+ 2));
3296 if (n
< profile_nsamples
) {
3297 /* NOTE: The counts for the profiling bins are only 16bits wide */
3298 if (profile_hist
[n
] != USHRT_MAX
)
3299 (profile_hist
[n
])++;
3302 #endif /* PROFILE */
3303 #endif /* !FASTSIM && PROFILE */
3305 IPC
= PC
; /* copy PC for this instruction */
3306 /* This is required by exception processing, to ensure that we can
3307 cope with exceptions in the delay slots of branches that may
3308 already have changed the PC. */
3309 PC
+= 4; /* increment ready for the next fetch */
3310 /* NOTE: If we perform a delay slot change to the PC, this
3311 increment is not requuired. However, it would make the
3312 simulator more complicated to try and avoid this small hit. */
3314 /* Currently this code provides a simple model. For more
3315 complicated models we could perform exception status checks at
3316 this point, and set the simSTOP state as required. This could
3317 also include processing any hardware interrupts raised by any
3318 I/O model attached to the simulator context.
3320 Support for "asynchronous" I/O events within the simulated world
3321 could be providing by managing a counter, and calling a I/O
3322 specific handler when a particular threshold is reached. On most
3323 architectures a decrement and check for zero operation is
3324 usually quicker than an increment and compare. However, the
3325 process of managing a known value decrement to zero, is higher
3326 than the cost of using an explicit value UINT_MAX into the
3327 future. Which system is used will depend on how complicated the
3328 I/O model is, and how much it is likely to affect the simulator
3331 If events need to be scheduled further in the future than
3332 UINT_MAX event ticks, then the I/O model should just provide its
3333 own counter, triggered from the event system. */
3335 /* MIPS pipeline ticks. To allow for future support where the
3336 pipeline hit of individual instructions is known, this control
3337 loop manages a "pipeline_count" variable. It is initialised to
3338 1 (one), and will only be changed by the simulator engine when
3339 executing an instruction. If the engine does not have access to
3340 pipeline cycle count information then all instructions will be
3341 treated as using a single cycle. NOTE: A standard system is not
3342 provided by the default simulator because different MIPS
3343 architectures have different cycle counts for the same
3347 /* Set previous flag, depending on current: */
3348 if (state
& simPCOC0
)
3352 /* and update the current value: */
3359 /* NOTE: For multi-context simulation environments the "instruction"
3360 variable should be local to this routine. */
3362 /* Shorthand accesses for engine. Note: If we wanted to use global
3363 variables (and a single-threaded simulator engine), then we can
3364 create the actual variables with these names. */
3366 if (!(state
& simSKIPNEXT
)) {
3367 /* Include the simulator engine */
3369 #if ((GPRLEN == 64) && !defined(PROCESSOR_64BIT)) || ((GPRLEN == 32) && defined(PROCESSOR_64BIT))
3370 #error "Mismatch between run-time simulator code and simulation engine"
3373 #if defined(WARN_LOHI)
3374 /* Decrement the HI/LO validity ticks */
3379 #endif /* WARN_LOHI */
3381 #if defined(WARN_ZERO)
3382 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3383 should check for it being changed. It is better doing it here,
3384 than within the simulator, since it will help keep the simulator
3387 callback
->printf_filtered(callback
,"SIM Warning: The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X)\nSIM Warning: Resetting back to zero\n",WORD64HI(ZERO
),WORD64LO(ZERO
),WORD64HI(IPC
),WORD64LO(IPC
));
3388 ZERO
= 0; /* reset back to zero before next instruction */
3390 #endif /* WARN_ZERO */
3391 } else /* simSKIPNEXT check */
3392 state
&= ~simSKIPNEXT
;
3394 /* If the delay slot was active before the instruction is
3395 executed, then update the PC to its new value: */
3398 printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC
),WORD64LO(DSPC
));
3401 state
&= ~simDELAYSLOT
;
3404 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3405 /* Deal with pending register updates: */
3407 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3409 if (pending_out
!= pending_in
) {
3411 int index
= pending_out
;
3412 int total
= pending_total
;
3413 if (pending_total
== 0) {
3414 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3417 for (loop
= 0; (loop
< total
); loop
++) {
3419 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3421 if (pending_slot_reg
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3423 printf("pending_slot_count[%d] = %d\n",index
,pending_slot_count
[index
]);
3425 if (--(pending_slot_count
[index
]) == 0) {
3427 printf("pending_slot_reg[%d] = %d\n",index
,pending_slot_reg
[index
]);
3428 printf("pending_slot_value[%d] = 0x%08X%08X\n",index
,WORD64HI(pending_slot_value
[index
]),WORD64LO(pending_slot_value
[index
]));
3430 if (pending_slot_reg
[index
] == COCIDX
) {
3431 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3433 registers
[pending_slot_reg
[index
]] = pending_slot_value
[index
];
3435 /* The only time we have PENDING updates to FPU
3436 registers, is when performing binary transfers. This
3437 means we should update the register type field. */
3438 if ((pending_slot_reg
[index
] >= FGRIDX
) && (pending_slot_reg
[index
] < (FGRIDX
+ 32)))
3439 fpr_state
[pending_slot_reg
[index
]] = fmt_uninterpreted
;
3443 printf("registers[%d] = 0x%08X%08X\n",pending_slot_reg
[index
],WORD64HI(registers
[pending_slot_reg
[index
]]),WORD64LO(registers
[pending_slot_reg
[index
]]));
3445 pending_slot_reg
[index
] = (LAST_EMBED_REGNUM
+ 1);
3447 if (pending_out
== PSLOTS
)
3453 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3456 if (index
== PSLOTS
)
3461 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3465 #if !defined(FASTSIM)
3466 pipeline_ticks
+= pipeline_count
;
3467 #endif /* FASTSIM */
3469 if (state
& simSTEP
)
3471 } while (!(state
& simSTOP
));
3474 if (membank
== NULL
) {
3475 printf("DBG: simulate() LEAVING with no memory\n");
3483 /*---------------------------------------------------------------------------*/
3484 /*> EOF interp.c <*/